Added TWO_STAGE_SHIFT parameter
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@ -158,6 +158,13 @@ latches the value internally.
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This parameter is only available for the `picorv32` core. In the
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This parameter is only available for the `picorv32` core. In the
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`picorv32_axi` core this is implicitly set to 0.
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`picorv32_axi` core this is implicitly set to 0.
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#### TWO_STAGE_SHIFT (default = 1)
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By default shift operations are performed in two stages: first shift in units
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of 4 bits and then shift in units of 1 bit. This speeds up shift operations,
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but adds additional hardware. Set this parameter to 0 to disable the two-stage
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shift to further reduce the size of the core.
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#### CATCH_MISALIGN (default = 1)
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#### CATCH_MISALIGN (default = 1)
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Set this to 0 to disable the circuitry for catching misaligned memory
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Set this to 0 to disable the circuitry for catching misaligned memory
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@ -36,6 +36,7 @@ module picorv32 #(
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_PCPI = 0,
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@ -885,7 +886,7 @@ module picorv32 #(
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reg_out <= reg_op1;
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reg_out <= reg_op1;
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mem_do_rinst <= mem_do_prefetch;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_fetch;
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end else if (reg_sh >= 4) begin
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end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
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(* parallel_case, full_case *)
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(* parallel_case, full_case *)
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case (1'b1)
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case (1'b1)
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instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
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instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
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@ -1136,6 +1137,7 @@ module picorv32_axi #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_PCPI = 0,
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@ -1230,6 +1232,7 @@ module picorv32_axi #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
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.CATCH_MISALIGN (CATCH_MISALIGN ),
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.CATCH_MISALIGN (CATCH_MISALIGN ),
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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