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Improvements in dhrystone "make timing"

This commit is contained in:
Clifford Wolf 2016-04-14 00:48:58 +02:00
parent 63c28e4389
commit c2c3978db2
2 changed files with 7 additions and 4 deletions
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7
dhrystone/Makefile
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@ -6,9 +6,12 @@ TOOLCHAIN_PREFIX = riscv32-unknown-elf-
test: testbench.exe dhry.hex test: testbench.exe dhry.hex
vvp -N testbench.exe vvp -N testbench.exe
timing: timing.exe dhry.hex timing: timing.txt
grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
gawk '{printf("%03d-%-7s %2d %-8s (%d)\n",$$3,$$2,$$3,$$2,$$1);}' | sort | cut -c13-
timing.txt: timing.exe dhry.hex
vvp -N timing.exe > timing.txt vvp -N timing.exe > timing.txt
grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | sort -k3 -n
testbench.exe: testbench.v ../picorv32.v testbench.exe: testbench.v ../picorv32.v
iverilog -o testbench.exe testbench.v ../picorv32.v iverilog -o testbench.exe testbench.v ../picorv32.v

4
dhrystone/testbench.v
View File

@ -92,8 +92,8 @@ module testbench;
$finish; $finish;
end end
always @(posedge clk) begin always @(posedge clk) begin
if (uut.decoder_trigger_q && !uut.decoder_pseudo_trigger_q) if (uut.dbg_next)
$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "x", uut.count_cycle); $display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "pcpi", uut.count_cycle);
end end
`endif `endif
endmodule endmodule