Improved AXI tests
This commit is contained in:
Clifford Wolf
parent
f9ae73066b
commit
c55d537401
7
Makefile
7
Makefile
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@ -4,10 +4,17 @@ TEST_OBJS=$(addsuffix .o,$(basename $(wildcard tests/*.S)))
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test: testbench.exe firmware/firmware.hex
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vvp -N testbench.exe
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test_axi: testbench_axi.exe firmware/firmware.hex
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vvp -N testbench_axi.exe
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testbench.exe: testbench.v picorv32.v
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iverilog -o testbench.exe testbench.v picorv32.v
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chmod -x testbench.exe
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testbench_axi.exe: testbench.v picorv32.v
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iverilog -o testbench_axi.exe -DAXI_TEST testbench.v picorv32.v
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chmod -x testbench_axi.exe
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firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
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python3 firmware/makehex.py $< > $@
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156
testbench.v
156
testbench.v
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@ -1,6 +1,6 @@
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`timescale 1 ns / 1 ps
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// `define VERBOSE
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// `define RANDOM_AXI_DELAYS
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// `define AXI_TEST
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module testbench;
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@ -75,12 +75,13 @@ module testbench;
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endtask
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reg [2:0] fast_axi_transaction = ~0;
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reg [4:0] async_axi_transaction = ~0;
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reg [4:0] delay_axi_transaction = 0;
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`ifdef RANDOM_AXI_DELAYS
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`ifdef AXI_TEST
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always @(posedge clk) begin
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xorshift64_next;
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{fast_axi_transaction, delay_axi_transaction} <= xorshift64_state;
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{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
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end
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`endif
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@ -98,6 +99,80 @@ module testbench;
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reg [ 3:0] latched_wstrb;
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reg latched_rinsn;
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task handle_axi_arvalid; begin
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mem_axi_arready <= 1;
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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fast_raddr <= 1;
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end endtask
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task handle_axi_awvalid; begin
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mem_axi_awready <= 1;
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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fast_waddr <= 1;
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end endtask
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task handle_axi_wvalid; begin
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mem_axi_wready <= 1;
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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fast_wdata <= 1;
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end endtask
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task handle_axi_rvalid; begin
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`ifdef VERBOSE
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$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
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`endif
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if (latched_raddr < 64*1024) begin
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mem_axi_rdata <= memory[latched_raddr >> 2];
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mem_axi_rvalid <= 1;
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latched_raddr_en = 0;
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end else begin
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$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
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$finish;
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end
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end endtask
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task handle_axi_bvalid; begin
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`ifdef VERBOSE
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
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`endif
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if (latched_waddr < 64*1024) begin
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if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
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if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
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if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
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if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
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end else
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if (latched_waddr == 32'h1000_0000) begin
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`ifdef VERBOSE
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if (32 <= latched_wdata && latched_wdata < 128)
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$display("OUT: '%c'", latched_wdata);
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else
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$display("OUT: %3d", latched_wdata);
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`else
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$write("%c", latched_wdata);
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$fflush();
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`endif
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end else begin
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$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
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$finish;
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end
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mem_axi_bvalid <= 1;
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latched_waddr_en = 0;
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latched_wdata_en = 0;
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end endtask
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always @(negedge clk) begin
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid;
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid;
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if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid;
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end
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always @(posedge clk) begin
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mem_axi_arready <= 0;
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mem_axi_awready <= 0;
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@ -132,77 +207,12 @@ module testbench;
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latched_wdata_en = 1;
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end
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) begin
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mem_axi_arready <= 1;
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if (fast_axi_transaction[0]) begin
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fast_raddr <= 1;
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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end
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end
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid;
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) begin
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mem_axi_awready <= 1;
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if (fast_axi_transaction[1]) begin
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fast_waddr <= 1;
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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end
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end
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) begin
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mem_axi_wready <= 1;
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if (fast_axi_transaction[2]) begin
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fast_wdata <= 1;
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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end
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end
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if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) begin
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`ifdef VERBOSE
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$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
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`endif
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if (latched_raddr < 64*1024) begin
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mem_axi_rdata <= memory[latched_raddr >> 2];
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mem_axi_rvalid <= 1;
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latched_raddr_en = 0;
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end else begin
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$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
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$finish;
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end
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end
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) begin
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`ifdef VERBOSE
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
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`endif
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if (latched_waddr < 64*1024) begin
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if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
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if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
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if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
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if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
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end else
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if (latched_waddr == 32'h1000_0000) begin
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`ifdef VERBOSE
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if (32 <= latched_wdata && latched_wdata < 128)
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$display("OUT: '%c'", latched_wdata);
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else
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$display("OUT: %3d", latched_wdata);
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`else
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$write("%c", latched_wdata);
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$fflush();
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`endif
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end else begin
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$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
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$finish;
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end
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mem_axi_bvalid <= 1;
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latched_waddr_en = 0;
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latched_wdata_en = 0;
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end
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if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
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end
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initial begin
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