Moved cpuregs read/write to extra always blocks
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Clifford Wolf
parent
82d837bf96
commit
c9519df01b
124
picorv32.v
124
picorv32.v
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@ -1063,9 +1063,6 @@ module picorv32 #(
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if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
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end
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reg cpuregs_write;
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reg [31:0] cpuregs_wrdata;
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reg set_mem_do_rinst;
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reg set_mem_do_rdata;
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reg set_mem_do_wdata;
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@ -1166,14 +1163,62 @@ module picorv32 #(
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clear_prefetched_high_word = COMPRESSED_ISA;
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end
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reg cpuregs_write;
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reg [31:0] cpuregs_wrdata;
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reg [31:0] cpuregs_rs1;
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reg [31:0] cpuregs_rs2;
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reg [regindex_bits-1:0] decoded_rs;
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always @* begin
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cpuregs_write = 0;
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cpuregs_wrdata = 'bx;
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if (cpu_state == cpu_state_fetch) begin
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(* parallel_case *)
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case (1'b1)
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latched_branch: begin
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cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
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cpuregs_write = 1;
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end
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latched_store && !latched_branch: begin
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cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
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cpuregs_write = 1;
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end
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ENABLE_IRQ && irq_state[0]: begin
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cpuregs_wrdata = reg_next_pc | latched_compr;
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cpuregs_write = 1;
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end
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ENABLE_IRQ && irq_state[1]: begin
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cpuregs_wrdata = irq_pending & ~irq_mask;
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cpuregs_write = 1;
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end
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endcase
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end
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end
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always @(posedge clk) begin
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if (cpuregs_write)
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cpuregs[latched_rd] <= cpuregs_wrdata;
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end
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always @* begin
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decoded_rs = 'bx;
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if (ENABLE_REGS_DUALPORT) begin
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cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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end else begin
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decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
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cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
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cpuregs_rs2 = cpuregs_rs1;
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end
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end
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assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
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always @(posedge clk) begin
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trap <= 0;
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reg_sh <= 'bx;
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reg_out <= 'bx;
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cpuregs_write = 0;
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cpuregs_wrdata = 'bx;
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set_mem_do_rinst = 0;
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set_mem_do_rdata = 0;
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set_mem_do_wdata = 0;
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@ -1269,32 +1314,21 @@ module picorv32 #(
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latched_branch: begin
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current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) : reg_next_pc;
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
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cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
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cpuregs_write = 1;
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end
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latched_store && !latched_branch: begin
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`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
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cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
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cpuregs_write = 1;
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end
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ENABLE_IRQ && irq_state[0]: begin
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cpuregs_wrdata = current_pc | latched_compr;
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cpuregs_write = 1;
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current_pc = PROGADDR_IRQ;
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irq_active <= 1;
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mem_do_rinst <= 1;
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end
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ENABLE_IRQ && irq_state[1]: begin
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eoi <= irq_pending & ~irq_mask;
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cpuregs_wrdata = irq_pending & ~irq_mask;
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cpuregs_write = 1;
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next_irq_pending = next_irq_pending & irq_mask;
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end
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endcase
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if (cpuregs_write)
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cpuregs[latched_rd] <= cpuregs_wrdata;
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if (ENABLE_TRACE && latched_trace) begin
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latched_trace <= 0;
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trace_valid <= 1;
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@ -1365,13 +1399,13 @@ module picorv32 #(
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case (1'b1)
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(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
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if (WITH_PCPI) begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_op1 <= cpuregs_rs1;
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if (ENABLE_REGS_DUALPORT) begin
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pcpi_valid <= 1;
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
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reg_sh <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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if (pcpi_int_ready) begin
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mem_do_rinst <= 1;
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pcpi_valid <= 0;
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@ -1425,14 +1459,14 @@ module picorv32 #(
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cpu_state <= cpu_state_exec;
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end
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ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_out <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_out <= cpuregs_rs1;
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latched_store <= 1;
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cpu_state <= cpu_state_fetch;
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end
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ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_out <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_out <= cpuregs_rs1;
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latched_rd <= latched_rd | irqregs_offset;
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latched_store <= 1;
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cpu_state <= cpu_state_fetch;
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@ -1442,39 +1476,39 @@ module picorv32 #(
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irq_active <= 0;
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latched_branch <= 1;
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latched_store <= 1;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_out <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_out <= cpuregs_rs1;
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cpu_state <= cpu_state_fetch;
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end
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ENABLE_IRQ && instr_maskirq: begin
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latched_store <= 1;
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reg_out <= irq_mask;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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irq_mask <= cpuregs_rs1 | MASKED_IRQ;
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cpu_state <= cpu_state_fetch;
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end
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ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
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latched_store <= 1;
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reg_out <= timer;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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timer <= cpuregs_rs1;
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cpu_state <= cpu_state_fetch;
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end
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is_lb_lh_lw_lbu_lhu: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_op1 <= cpuregs_rs1;
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cpu_state <= cpu_state_ldmem;
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mem_do_rinst <= 1;
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end
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is_slli_srli_srai && !BARREL_SHIFTER: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_op1 <= cpuregs_rs1;
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reg_sh <= decoded_rs2;
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cpu_state <= cpu_state_shift;
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end
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is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_op1 <= cpuregs_rs1;
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reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
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if (TWO_CYCLE_ALU)
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alu_wait <= 1;
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@ -1483,12 +1517,12 @@ module picorv32 #(
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cpu_state <= cpu_state_exec;
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end
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default: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_op1 <= cpuregs_rs1;
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if (ENABLE_REGS_DUALPORT) begin
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
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reg_sh <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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(* parallel_case *)
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case (1'b1)
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is_sb_sh_sw: begin
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@ -1514,9 +1548,9 @@ module picorv32 #(
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end
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cpu_state_ld_rs2: begin
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
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reg_sh <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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(* parallel_case *)
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case (1'b1)
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