From c9de8001fe8ca4d4af260b3aef378805759e3583 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Wed, 7 Jun 2017 08:05:19 -0700 Subject: [PATCH] Remove some trailing whitespace --- dhrystone/syscalls.c | 2 +- picorv32.v | 2 +- scripts/csmith/syscalls.c | 2 +- scripts/cxxdemo/syscalls.c | 2 +- scripts/quartus/tabtest.sh | 4 ++-- scripts/smtbmc/opcode.v | 2 +- scripts/tomthumbtg/run.sh | 2 +- scripts/yosys-cmp/lse.sh | 2 +- tests/srli.S | 4 ++-- 9 files changed, 11 insertions(+), 11 deletions(-) diff --git a/dhrystone/syscalls.c b/dhrystone/syscalls.c index cdf872f..b23f605 100644 --- a/dhrystone/syscalls.c +++ b/dhrystone/syscalls.c @@ -62,7 +62,7 @@ ssize_t write(int file, const void *ptr, size_t len) return len; } -int close(int file) +int close(int file) { // close is called before _exit() return 0; diff --git a/picorv32.v b/picorv32.v index ff14786..eb642d0 100644 --- a/picorv32.v +++ b/picorv32.v @@ -654,7 +654,7 @@ module picorv32 #( instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; - + wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; diff --git a/scripts/csmith/syscalls.c b/scripts/csmith/syscalls.c index cdf872f..b23f605 100644 --- a/scripts/csmith/syscalls.c +++ b/scripts/csmith/syscalls.c @@ -62,7 +62,7 @@ ssize_t write(int file, const void *ptr, size_t len) return len; } -int close(int file) +int close(int file) { // close is called before _exit() return 0; diff --git a/scripts/cxxdemo/syscalls.c b/scripts/cxxdemo/syscalls.c index cdf872f..b23f605 100644 --- a/scripts/cxxdemo/syscalls.c +++ b/scripts/cxxdemo/syscalls.c @@ -62,7 +62,7 @@ ssize_t write(int file, const void *ptr, size_t len) return len; } -int close(int file) +int close(int file) { // close is called before _exit() return 0; diff --git a/scripts/quartus/tabtest.sh b/scripts/quartus/tabtest.sh index d731f76..2fd1b40 100644 --- a/scripts/quartus/tabtest.sh +++ b/scripts/quartus/tabtest.sh @@ -37,7 +37,7 @@ set_global_assignment -name SDC_FILE test_${1}.sdc EOT echo "Running tab_${ip}_${dev}_${grade}/test_${1}.." - + if ! $QUARTUS_BIN/quartus_map test_${1}; then exit 1 fi @@ -47,7 +47,7 @@ set_global_assignment -name SDC_FILE test_${1}.sdc if ! $QUARTUS_BIN/quartus_sta test_${1} -c test_${1}; then exit 1 fi - + cp output_files/test_${1}.sta.summary test_${1}.txt } diff --git a/scripts/smtbmc/opcode.v b/scripts/smtbmc/opcode.v index 4c3792d..7a13bd2 100644 --- a/scripts/smtbmc/opcode.v +++ b/scripts/smtbmc/opcode.v @@ -86,7 +86,7 @@ function opcode_sys; if (opcode[31:20] == 12'hC81 && opcode[19:12] == 3'b010 && opcode[6:0] == 7'b1110011) opcode_sys = 1; // RDTIMEH if (opcode[31:20] == 12'hC82 && opcode[19:12] == 3'b010 && opcode[6:0] == 7'b1110011) opcode_sys = 1; // RDINSTRETH end - + endfunction function opcode_valid; diff --git a/scripts/tomthumbtg/run.sh b/scripts/tomthumbtg/run.sh index dcce6bd..63a6935 100644 --- a/scripts/tomthumbtg/run.sh +++ b/scripts/tomthumbtg/run.sh @@ -9,7 +9,7 @@ if [ ! -f testgen.tgz ]; then fi rm -rf tests testgen/ -tar xvzf testgen.tgz +tar xvzf testgen.tgz iverilog -o testbench_a -s testbench testbench.v ../../picorv32.v -DTWO_STAGE_SHIFT=0 -DBARREL_SHIFTER=0 -DTWO_CYCLE_COMPARE=0 -DTWO_CYCLE_ALU=0 iverilog -o testbench_b -s testbench testbench.v ../../picorv32.v -DTWO_STAGE_SHIFT=1 -DBARREL_SHIFTER=0 -DTWO_CYCLE_COMPARE=0 -DTWO_CYCLE_ALU=0 diff --git a/scripts/yosys-cmp/lse.sh b/scripts/yosys-cmp/lse.sh index cfbb04c..a802c67 100644 --- a/scripts/yosys-cmp/lse.sh +++ b/scripts/yosys-cmp/lse.sh @@ -29,7 +29,7 @@ cat > lse.prj << EOT -fsm_encoding_style Auto -use_io_insertion 1 -use_io_reg auto --ifd +-ifd -resolve_mixed_drivers 0 -RWCheckOnRam 0 -fix_gated_clocks 1 diff --git a/tests/srli.S b/tests/srli.S index c2797cd..be56dc3 100644 --- a/tests/srli.S +++ b/tests/srli.S @@ -48,11 +48,11 @@ RVTEST_CODE_BEGIN TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - + TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - + TEST_IMM_ZEROSRC1( 28, srli, 0, 31 ); TEST_IMM_ZERODEST( 29, srli, 33, 20 );