diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys
index b64e7e1..ded89d9 100644
--- a/scripts/yosys/synth_sim.ys
+++ b/scripts/yosys/synth_sim.ys
@@ -1,7 +1,8 @@
 # yosys synthesis script for post-synthesis simulation (make test_synth)
 
 read_verilog picorv32.v
-chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
+chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
+        -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
 hierarchy -top picorv32_axi
 synth
 write_verilog synth.v