Improve spiflash testbench and firmware

spiflash/firmware.s

@@ -1,8 +1,56 @@
-start:
+# write RAM code (a sequence of nops followed by ret)
-      li      x1,0xc0000000
+li      x5,0x00000013   # nop
-      sw      x0,0(x0)
+sw      x5,4(x0)
-loop: lw      x2,0(x0)
+sw      x5,8(x0)
-      addi    x2,x2,1
+sw      x5,12(x0)
-      sw      x2,0(x1)
+sw      x5,16(x0)
-      sw      x2,0(x0)
+sw      x5,20(x0)
-      j       loop
+sw      x5,24(x0)
+sw      x5,28(x0)
+sw      x5,32(x0)
+sw      x5,36(x0)
+sw      x5,40(x0)
+sw      x5,44(x0)
+sw      x5,48(x0)
+sw      x5,52(x0)
+sw      x5,56(x0)
+sw      x5,60(x0)
+sw      x5,64(x0)
+sw      x5,68(x0)
+sw      x5,72(x0)
+sw      x5,76(x0)
+li      x5,0x00008067   # ret
+sw      x5,80(x0)
+
+# setup gpio address in x5
+li      x5,0xc0000000
+sw      x0,0(x5)
+
+# initial entry point into RAM code
+li      x3,4
+
+# initialize RAM counter
+sw      x0,0(x0)
+
+# start of loop. remember this address
+auipc   x4,0
+
+# execute RAM code, come back here
+jalr    x3
+
+# load counter and increment
+lw      x6,0(x0)
+addi    x6,x6,1
+
+# store counter and update gpios
+sw      x6,0(x5)
+sw      x6,0(x0)
+
+# calculate new entry point into RAM code
+slli    x3,x6,2
+andi    x3,x3,63
+addi    x3,x3,4
+
+# execute RAM code, come back to start of loop
+mv      x1,x4
+jr      x3

spiflash/spiflash.v

@@ -4,7 +4,7 @@ module spiflash (
 	input      spi_mosi,
 	input      spi_sclk
 );
-	localparam verbose = 1;
+	localparam verbose = 0;
 	
 	reg [7:0] buffer;
 	integer bitcount = 0;
@@ -29,12 +29,7 @@ module spiflash (
 
 	task spi_action;
 		begin
-			if (verbose) begin
+			spi_in = buffer;
-				if (bytecount == 1)
-					$write("<SPI>");
-				$write("<SPI:%02x", buffer);
-				spi_in = buffer;
-			end
 
 			if (bytecount == 1) begin
 				spi_cmd = buffer;
@@ -60,12 +55,15 @@ module spiflash (
 				end
 			end
 
+			spi_out = buffer;
+			spi_io_vld = 1;
+
 			if (verbose) begin
-				$write(":%02x>", buffer);
+				if (bytecount == 1)
-				spi_out = buffer;
+					$write("<SPI-START>");
-				spi_io_vld = 1;
+				$write("<SPI:%02x:%02x>", spi_in, spi_out);
-				$fflush;
 			end
+
 		end
 	endtask
 

spiflash/testbench.v

@@ -5,9 +5,10 @@ module testbench;
 	initial begin
 		$dumpfile("testbench.vcd");
 		$dumpvars(0, testbench);
-		repeat (10000) @(posedge clk);
+		repeat (100000) @(posedge clk);
-		$display("<END>");
+		$display("");
-		$finish;
+		$display("[TIMEOUT]");
+		$stop;
 	end
 
 	wire [31:0] gpio_i = 0;
@@ -18,6 +19,17 @@ module testbench;
 	wire spi_mosi;
 	wire spi_miso;
 
+	always @(gpio_o) begin
+		$write("<GPIO:%02x>", gpio_o[7:0]);
+		if (gpio_o == 63) begin
+			$display("[OK]");
+			$finish;
+		end
+		if (gpio_o % 8 == 7) begin
+			$display("");
+		end
+	end
+
 	top uut (
 		.clk     (clk     ),
 		.gpio_i  (gpio_i  ),