colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update README.md

This commit is contained in:
Clifford Wolf 2019-08-09 09:23:17 +02:00 committed by GitHub
parent e6779ba52b
commit d124abbacd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -92,7 +92,7 @@ This Verilog file contains the following Verilog modules:
| `picorv32_axi` | The version of the CPU with AXI4-Lite interface | | `picorv32_axi` | The version of the CPU with AXI4-Lite interface |
| `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite | | `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite |
| `picorv32_wb` | The version of the CPU with Wishbone Master interface | | `picorv32_wb` | The version of the CPU with Wishbone Master interface |
| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions | | `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU\|U]]` instructions |
| `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier | | `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier |
| `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions | | `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions |