Added next gen yosys-smtbmc verification scripts
This commit is contained in:
Clifford Wolf
parent
98d248d2c2
commit
d1d3c3c5e1
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@ -1145,6 +1145,9 @@ module picorv32 #(
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if (ENABLE_COUNTERS) begin
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count_cycle <= resetn ? count_cycle + 1 : 0;
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if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
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end else begin
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count_cycle <= 'bx;
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count_instr <= 'bx;
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end
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next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
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@ -1667,11 +1670,11 @@ module picorv32 #(
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reg [4:0] last_mem_ready;
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always @(posedge clk)
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last_mem_ready <= {last_mem_ready, mem_ready};
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assume property (|last_mem_ready);
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restrict property (|last_mem_ready);
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reg ok;
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always @* begin
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assume (resetn == |cycle);
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restrict (resetn == |cycle);
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if (cycle) begin
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// instruction fetches are read-only
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if (mem_valid && mem_instr)
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@ -0,0 +1,3 @@
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tracecmp.smt2
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tracecmp.vcd
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tracecmp.yslog
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@ -0,0 +1,71 @@
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[*]
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[*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI
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[*] Fri Aug 26 15:42:37 2016
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[*]
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[dumpfile] "/home/clifford/Work/picorv32/scripts/smtbmc/tracecmp.vcd"
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[dumpfile_mtime] "Fri Aug 26 15:33:18 2016"
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[dumpfile_size] 80106
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[savefile] "/home/clifford/Work/picorv32/scripts/smtbmc/tracecmp.gtkw"
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[timestart] 0
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[size] 1216 863
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[pos] -1 -1
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*-2.860312 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] testbench.
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[sst_width] 241
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[signals_width] 337
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[sst_expanded] 1
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[sst_vpaned_height] 252
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@28
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smt_clock
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testbench.resetn
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testbench.trap_0
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testbench.trap_1
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@200
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-
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-Trace CMP
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@28
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testbench.trace_valid_0
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testbench.trace_valid_1
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@22
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testbench.trace_data_0[35:0]
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testbench.trace_data_1[35:0]
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@420
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testbench.trace_balance[7:0]
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@200
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-
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-CPU #0
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@28
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testbench.mem_valid_0
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testbench.mem_ready_0
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testbench.mem_instr_0
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@22
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testbench.mem_addr_0[31:0]
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testbench.mem_rdata_0[31:0]
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testbench.mem_wdata_0[31:0]
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@28
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testbench.mem_wstrb_0[3:0]
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@22
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testbench.cpu_0.cpu_state[7:0]
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@28
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testbench.cpu_0.mem_state[1:0]
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@200
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-
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-CPU #1
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@28
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testbench.mem_valid_1
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testbench.mem_ready_1
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testbench.mem_instr_1
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@22
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testbench.mem_addr_1[31:0]
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testbench.mem_rdata_1[31:0]
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testbench.mem_wdata_1[31:0]
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@28
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testbench.mem_wstrb_1[3:0]
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@22
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testbench.cpu_1.cpu_state[7:0]
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@28
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testbench.cpu_1.mem_state[1:0]
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@200
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-
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[pattern_trace] 1
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[pattern_trace] 0
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@ -0,0 +1,12 @@
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#!/bin/bash
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set -ex
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yosys -ql tracecmp.yslog \
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-p 'read_verilog -formal -norestrict -assume-asserts ../../picorv32.v' \
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-p 'read_verilog -formal tracecmp.v' \
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-p 'prep -top testbench -nordff' \
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-p 'write_smt2 -mem -bv -wires tracecmp.smt2'
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yosys-smtbmc -s yices --smtc tracecmp.smtc --dump-vcd tracecmp.vcd tracecmp.smt2
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@ -0,0 +1,12 @@
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initial
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assume (= [mem_0] [mem_1])
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assume (= [cpu_0.cpuregs] [cpu_1.cpuregs])
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assume (= [trace_data_0] [trace_data_1])
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always
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assume (=> (not [mem_valid_0]) (not [mem_ready_0]))
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assume (=> (not [mem_valid_1]) (not [mem_ready_1]))
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# assume (= [mem_ready_0] [mem_ready_1])
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always -1
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assert (=> (= [trace_balance] #x00) (= [trace_data_0] [trace_data_1]))
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@ -0,0 +1,109 @@
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module testbench(input clk, mem_ready_0, mem_ready_1);
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// set this to 1 to test generation of counter examples
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localparam ENABLE_COUNTERS = 0;
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reg resetn = 0;
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always @(posedge clk) resetn <= 1;
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(* keep *) wire trap_0, trace_valid_0, mem_valid_0, mem_instr_0;
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(* keep *) wire [3:0] mem_wstrb_0;
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(* keep *) wire [31:0] mem_addr_0, mem_wdata_0, mem_rdata_0;
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(* keep *) wire [35:0] trace_data_0;
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(* keep *) wire trap_1, trace_valid_1, mem_valid_1, mem_instr_1;
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(* keep *) wire [3:0] mem_wstrb_1;
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(* keep *) wire [31:0] mem_addr_1, mem_wdata_1, mem_rdata_1;
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(* keep *) wire [35:0] trace_data_1;
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reg [31:0] mem_0 [0:2**30-1];
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reg [31:0] mem_1 [0:2**30-1];
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assign mem_rdata_0 = mem_0[mem_addr_0 >> 2];
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assign mem_rdata_1 = mem_1[mem_addr_1 >> 2];
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always @(posedge clk) begin
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if (resetn && mem_valid_0 && mem_ready_0) begin
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if (mem_wstrb_0[3]) mem_0[mem_addr_0 >> 2][31:24] <= mem_wdata_0[31:24];
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if (mem_wstrb_0[2]) mem_0[mem_addr_0 >> 2][23:16] <= mem_wdata_0[23:16];
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if (mem_wstrb_0[1]) mem_0[mem_addr_0 >> 2][15: 8] <= mem_wdata_0[15: 8];
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if (mem_wstrb_0[0]) mem_0[mem_addr_0 >> 2][ 7: 0] <= mem_wdata_0[ 7: 0];
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end
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if (resetn && mem_valid_1 && mem_ready_1) begin
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if (mem_wstrb_1[3]) mem_1[mem_addr_1 >> 2][31:24] <= mem_wdata_1[31:24];
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if (mem_wstrb_1[2]) mem_1[mem_addr_1 >> 2][23:16] <= mem_wdata_1[23:16];
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if (mem_wstrb_1[1]) mem_1[mem_addr_1 >> 2][15: 8] <= mem_wdata_1[15: 8];
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if (mem_wstrb_1[0]) mem_1[mem_addr_1 >> 2][ 7: 0] <= mem_wdata_1[ 7: 0];
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end
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end
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(* keep *) reg [7:0] trace_balance;
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reg [7:0] trace_balance_q;
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always @* begin
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trace_balance = trace_balance_q;
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if (trace_valid_0) trace_balance = trace_balance + 1;
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if (trace_valid_1) trace_balance = trace_balance - 1;
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end
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always @(posedge clk) begin
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trace_balance_q <= resetn ? trace_balance : 0;
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end
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picorv32 #(
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// do not change this settings
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.ENABLE_TRACE(1),
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// change this settings as you like
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.ENABLE_REGS_DUALPORT(1),
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.TWO_STAGE_SHIFT(1),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.ENABLE_MUL(0),
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.ENABLE_DIV(0)
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) cpu_0 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap_0 ),
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.mem_valid (mem_valid_0 ),
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.mem_instr (mem_instr_0 ),
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.mem_ready (mem_ready_0 ),
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.mem_addr (mem_addr_0 ),
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.mem_wdata (mem_wdata_0 ),
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.mem_wstrb (mem_wstrb_0 ),
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.mem_rdata (mem_rdata_0 ),
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.trace_valid (trace_valid_0),
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.trace_data (trace_data_0 )
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);
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picorv32 #(
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// do not change this settings
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.ENABLE_TRACE(1),
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// change this settings as you like
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.ENABLE_REGS_DUALPORT(1),
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.TWO_STAGE_SHIFT(1),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.ENABLE_MUL(0),
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.ENABLE_DIV(0)
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) cpu_1 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap_1 ),
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.mem_valid (mem_valid_1 ),
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.mem_instr (mem_instr_1 ),
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.mem_ready (mem_ready_1 ),
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.mem_addr (mem_addr_1 ),
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.mem_wdata (mem_wdata_1 ),
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.mem_wstrb (mem_wstrb_1 ),
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.mem_rdata (mem_rdata_1 ),
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.trace_valid (trace_valid_1),
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.trace_data (trace_data_1 )
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);
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endmodule
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