picosoc: increase available memory by using SPRAM instead of BRAM for the Icebreaker example

This commit is contained in:
Steffen Vogel 2019-02-11 23:13:05 +01:00
parent 9b70921103
commit d21937bafc
5 changed files with 118 additions and 6 deletions

View File

@ -50,10 +50,10 @@ icebsim: icebreaker_tb.vvp icebreaker_fw.hex
icebsynsim: icebreaker_syn_tb.vvp icebreaker_fw.hex
vvp -N $< +firmware=icebreaker_fw.hex
icebreaker.json: icebreaker.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
icebreaker.json: icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
yosys -ql icebreaker.log -p 'synth_ice40 -top icebreaker -json icebreaker.json' $^
icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v

91
picosoc/ice40up5k_spram.v Normal file
View File

@ -0,0 +1,91 @@
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module ice40up5k_spram #(
// We current always use the whole SPRAM (128 kB)
parameter integer WORDS = 32768
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
wire cs_0, cs_1;
wire [31:0] rdata_0, rdata_1;
assign cs_0 = !addr[14];
assign cs_1 = addr[14];
assign rdata = addr[14] ? rdata_1 : rdata_0;
SB_SPRAM256KA ram00 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[15:0]),
.MASKWREN({wen[1], wen[1], wen[0], wen[0]}),
.WREN(wen[1]|wen[0]),
.CHIPSELECT(cs_0),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_0[15:0])
);
SB_SPRAM256KA ram01 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[31:16]),
.MASKWREN({wen[3], wen[3], wen[2], wen[2]}),
.WREN(wen[3]|wen[2]),
.CHIPSELECT(cs_0),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_0[31:16])
);
SB_SPRAM256KA ram10 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[15:0]),
.MASKWREN({wen[1], wen[1], wen[0], wen[0]}),
.WREN(wen[1]|wen[0]),
.CHIPSELECT(cs_1),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_1[15:0])
);
SB_SPRAM256KA ram11 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[31:16]),
.MASKWREN({wen[3], wen[3], wen[2], wen[2]}),
.WREN(wen[3]|wen[2]),
.CHIPSELECT(cs_1),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_1[31:16])
);
endmodule

View File

@ -17,6 +17,12 @@
*
*/
`ifdef PICOSOC_V
`error "icebreaker.v must be read before icebreaker.v!"
`endif
`define PICOSOC_MEM ice40up5k_spram
module icebreaker (
input clk,
@ -100,7 +106,8 @@ module icebreaker (
picosoc #(
.BARREL_SHIFTER(0),
.ENABLE_MULDIV(0)
.ENABLE_MULDIV(0),
.MEM_WORDS(32768)
) soc (
.clk (clk ),
.resetn (resetn ),

View File

@ -14,10 +14,14 @@ filesets:
targets:
default:
filesets : [picosoc]
parameters : [PICORV32_REGS]
parameters : [PICORV32_REGS, PICOSOC_MEM]
parameters:
PICORV32_REGS:
datatype : str
default : picosoc_regs
paramtype : vlogdefine
PICOSOC_MEM:
datatype : str
default : picosoc_mem
paramtype : vlogdefine

View File

@ -25,6 +25,14 @@
`define PICORV32_REGS picosoc_regs
`endif
`ifndef PICOSOC_MEM
`define PICOSOC_MEM picosoc_mem
`endif
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICOSOC_V
module picosoc (
input clk,
input resetn,
@ -197,7 +205,9 @@ module picosoc (
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
picosoc_mem #(.WORDS(MEM_WORDS)) memory (
`PICOSOC_MEM #(
.WORDS(MEM_WORDS)
) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),