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format testbench.

This commit is contained in:
colin.liang 2023-01-10 15:44:16 +08:00
parent 42e498aa28
commit d4ce161c1c
1 changed files with 216 additions and 220 deletions
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86
testbench_wb.v
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@ -35,8 +35,7 @@ module testbench #(
repeat (10) @(posedge clk); repeat (10) @(posedge clk);
while (!trap) begin while (!trap) begin
@(posedge clk); @(posedge clk);
if (trace_valid) if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
$fwrite(trace_file, "%x\n", trace_data);
end end
$fclose(trace_file); $fclose(trace_file);
$display("Finished writing testbench.trace."); $display("Finished writing testbench.trace.");
@ -44,7 +43,7 @@ module testbench #(
end end
picorv32_wrapper #( picorv32_wrapper #(
.VERBOSE (VERBOSE) .VERBOSE(VERBOSE)
) top ( ) top (
.wb_clk(clk), .wb_clk(clk),
.wb_rst(resetn), .wb_rst(resetn),
@ -86,13 +85,12 @@ module picorv32_wrapper #(
wire [31:0] wb_s2m_dat; wire [31:0] wb_s2m_dat;
wire wb_s2m_ack; wire wb_s2m_ack;
picorv32_wb #( picorv32_wb #() uut (
) uut ( .trap(trap),
.trap (trap),
.exit(exit), .exit(exit),
.irq (irq), .irq(irq),
.trace_valid (trace_valid), .trace_valid(trace_valid),
.trace_data (trace_data), .trace_data(trace_data),
.mem_instr(mem_instr), .mem_instr(mem_instr),
.wb_clk_i(wb_clk), .wb_clk_i(wb_clk),
@ -101,8 +99,7 @@ module picorv32_wrapper #(
reg [1023:0] firmware_file; reg [1023:0] firmware_file;
initial begin initial begin
if (!$value$plusargs("firmware=%s", firmware_file)) if (!$value$plusargs("firmware=%s", firmware_file)) firmware_file = "firmware/firmware.hex";
firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, uut.memory); $readmemh(firmware_file, uut.memory);
end end
@ -119,8 +116,7 @@ module picorv32_wrapper #(
$finish; $finish;
end else begin end else begin
$display("ERROR!"); $display("ERROR!");
if ($test$plusargs("noerror")) if ($test$plusargs("noerror")) $finish;
$finish;
$stop; $stop;
end end
end end
@ -133,7 +129,8 @@ endmodule
* picorv32_wb * picorv32_wb
***************************************************************/ ***************************************************************/
module picorv32_wb #() ( module picorv32_wb #(
) (
output trap, output trap,
output reg exit, output reg exit,
@ -181,7 +178,7 @@ endmodule
wire mem_la_write; wire mem_la_write;
wire [31:0] mem_la_addr; wire [31:0] mem_la_addr;
wire [31:0] mem_la_wdata; wire [31:0] mem_la_wdata;
wire [3:0] mem_la_wstrb; wire [ 3:0] mem_la_wstrb;
wire clk; wire clk;
@ -212,46 +209,46 @@ endmodule
.ENABLE_IRQ_TIMER(1), .ENABLE_IRQ_TIMER(1),
.ENABLE_TRACE(1), .ENABLE_TRACE(1),
.REGS_INIT_ZERO(0), .REGS_INIT_ZERO(0),
.MASKED_IRQ(32'h 0000_0000), .MASKED_IRQ(32'h0000_0000),
.LATCHED_IRQ(32'h ffff_ffff), .LATCHED_IRQ(32'hffff_ffff),
.PROGADDR_RESET(32'h 0000_0000), .PROGADDR_RESET(32'h0000_0000),
.PROGADDR_IRQ(32'h 0000_0010), .PROGADDR_IRQ(32'h0000_0010),
.STACKADDR(32'h ffff_ffff) .STACKADDR(32'hffff_ffff)
) picorv32_core ( ) picorv32_core (
.clk (clk ), .clk (clk),
.resetn (resetn), .resetn(resetn),
.trap (trap ), .trap (trap),
.mem_valid (mem_valid ), .mem_valid (mem_valid),
.mem_instr (mem_instr ), .mem_instr (mem_instr),
.mem_ready (mem_ready ), .mem_ready (mem_ready),
.mem_addr (mem_addr ), .mem_addr (mem_addr),
.mem_wdata (mem_wdata ), .mem_wdata (mem_wdata),
.mem_wstrb (mem_wstrb ), .mem_wstrb (mem_wstrb),
.mem_rdata (mem_rdata ), .mem_rdata (mem_rdata),
.mem_la_read (mem_la_read ), .mem_la_read (mem_la_read),
.mem_la_write(mem_la_write), .mem_la_write(mem_la_write),
.mem_la_addr (mem_la_addr ), .mem_la_addr (mem_la_addr),
.mem_la_wdata(mem_la_wdata), .mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb), .mem_la_wstrb(mem_la_wstrb),
.irq(irq), .irq (irq),
.eoi(eoi), .eoi (eoi),
.trace_valid(trace_valid), .trace_valid(trace_valid),
.trace_data (trace_data) .trace_data (trace_data)
); );
reg [7:0] memory [0:256*1024-1]; reg [7:0] memory[0:256*1024-1];
assign mem_ready = 1; assign mem_ready = 1;
always @(posedge clk) begin always @(posedge clk) begin
mem_rdata[ 7: 0] <= mem_la_read ? memory[mem_la_addr + 0] : 'bx; mem_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
mem_rdata[15: 8] <= mem_la_read ? memory[mem_la_addr + 1] : 'bx; mem_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr + 2] : 'bx; mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr + 3] : 'bx; mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
if (mem_la_write) begin if (mem_la_write) begin
case (mem_la_addr) case (mem_la_addr)
32'h1000_0000: begin 32'h1000_0000: begin
@ -261,14 +258,13 @@ endmodule
`endif `endif
end end
32'h2000_0000: begin 32'h2000_0000: begin
if (mem_la_wdata[31:0] == 123456789) if (mem_la_wdata[31:0] == 123456789) exit = 1;
exit = 1;
end end
default: begin default: begin
if (mem_la_wstrb[0]) memory[mem_la_addr + 0] <= mem_la_wdata[ 7: 0]; if (mem_la_wstrb[0]) memory[mem_la_addr+0] <= mem_la_wdata[7:0];
if (mem_la_wstrb[1]) memory[mem_la_addr + 1] <= mem_la_wdata[15: 8]; if (mem_la_wstrb[1]) memory[mem_la_addr+1] <= mem_la_wdata[15:8];
if (mem_la_wstrb[2]) memory[mem_la_addr + 2] <= mem_la_wdata[23:16]; if (mem_la_wstrb[2]) memory[mem_la_addr+2] <= mem_la_wdata[23:16];
if (mem_la_wstrb[3]) memory[mem_la_addr + 3] <= mem_la_wdata[31:24]; if (mem_la_wstrb[3]) memory[mem_la_addr+3] <= mem_la_wdata[31:24];
end end
endcase endcase
end end