format testbench.
This commit is contained in:
colin.liang
parent
42e498aa28
commit
d4ce161c1c
436
testbench_wb.v
436
testbench_wb.v
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@ -2,129 +2,125 @@
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`ifndef VERILATOR
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`ifndef VERILATOR
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module testbench #(
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module testbench #(
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parameter VERBOSE = 0
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parameter VERBOSE = 0
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);
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);
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reg clk = 1;
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reg clk = 1;
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reg resetn = 1;
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reg resetn = 1;
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wire trap;
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wire trap;
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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initial begin
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initial begin
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repeat (100) @(posedge clk);
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repeat (100) @(posedge clk);
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resetn <= 0;
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resetn <= 0;
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end
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end
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initial begin
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initial begin
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if ($test$plusargs("vcd")) begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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$dumpvars(0, testbench);
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end
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end
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repeat (1000000) @(posedge clk);
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repeat (1000000) @(posedge clk);
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$display("TIMEOUT");
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$display("TIMEOUT");
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$finish;
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$finish;
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end
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end
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wire trace_valid;
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wire trace_valid;
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wire [35:0] trace_data;
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wire [35:0] trace_data;
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integer trace_file;
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integer trace_file;
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initial begin
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initial begin
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if ($test$plusargs("trace")) begin
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if ($test$plusargs("trace")) begin
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trace_file = $fopen("testbench.trace", "w");
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trace_file = $fopen("testbench.trace", "w");
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repeat (10) @(posedge clk);
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repeat (10) @(posedge clk);
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while (!trap) begin
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while (!trap) begin
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@(posedge clk);
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@(posedge clk);
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if (trace_valid)
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if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
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$fwrite(trace_file, "%x\n", trace_data);
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end
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end
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$fclose(trace_file);
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$fclose(trace_file);
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$display("Finished writing testbench.trace.");
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$display("Finished writing testbench.trace.");
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end
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end
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end
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end
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picorv32_wrapper #(
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picorv32_wrapper #(
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.VERBOSE (VERBOSE)
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.VERBOSE(VERBOSE)
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) top (
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) top (
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.wb_clk(clk),
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.wb_clk(clk),
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.wb_rst(resetn),
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.wb_rst(resetn),
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.trap(trap),
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.trap(trap),
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.trace_valid(trace_valid),
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.trace_valid(trace_valid),
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.trace_data(trace_data)
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.trace_data(trace_data)
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);
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);
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endmodule
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endmodule
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`endif
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`endif
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module picorv32_wrapper #(
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module picorv32_wrapper #(
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parameter VERBOSE = 0
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parameter VERBOSE = 0
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) (
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) (
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input wb_clk,
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input wb_clk,
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input wb_rst,
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input wb_rst,
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output trap,
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output trap,
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output trace_valid,
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output trace_valid,
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output [35:0] trace_data
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output [35:0] trace_data
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);
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);
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wire exit;
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wire exit;
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reg [31:0] irq = 0;
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reg [31:0] irq = 0;
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wire mem_instr;
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wire mem_instr;
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reg [15:0] count_cycle = 0;
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reg [15:0] count_cycle = 0;
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always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
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always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
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always @* begin
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always @* begin
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irq = 0;
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irq = 0;
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irq[4] = &count_cycle[12:0];
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irq[4] = &count_cycle[12:0];
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irq[5] = &count_cycle[15:0];
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irq[5] = &count_cycle[15:0];
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end
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end
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wire [31:0] wb_m2s_adr;
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wire [31:0] wb_m2s_adr;
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wire [31:0] wb_m2s_dat;
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wire [31:0] wb_m2s_dat;
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wire [3:0] wb_m2s_sel;
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wire [3:0] wb_m2s_sel;
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wire wb_m2s_we;
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wire wb_m2s_we;
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wire wb_m2s_cyc;
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wire wb_m2s_cyc;
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wire wb_m2s_stb;
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wire wb_m2s_stb;
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wire [31:0] wb_s2m_dat;
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wire [31:0] wb_s2m_dat;
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wire wb_s2m_ack;
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wire wb_s2m_ack;
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picorv32_wb #(
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picorv32_wb #() uut (
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) uut (
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.trap(trap),
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.trap (trap),
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.exit(exit),
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.exit(exit),
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.irq(irq),
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.irq (irq),
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.trace_valid(trace_valid),
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.trace_valid (trace_valid),
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.trace_data(trace_data),
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.trace_data (trace_data),
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.mem_instr(mem_instr),
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.mem_instr(mem_instr),
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.wb_clk_i(wb_clk),
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.wb_clk_i(wb_clk),
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.wb_rst_i(wb_rst),
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.wb_rst_i(wb_rst),
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);
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);
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reg [1023:0] firmware_file;
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reg [1023:0] firmware_file;
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initial begin
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initial begin
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if (!$value$plusargs("firmware=%s", firmware_file))
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if (!$value$plusargs("firmware=%s", firmware_file)) firmware_file = "firmware/firmware.hex";
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firmware_file = "firmware/firmware.hex";
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$readmemh(firmware_file, uut.memory);
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$readmemh(firmware_file, uut.memory);
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end
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end
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integer cycle_counter;
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integer cycle_counter;
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always @(posedge wb_clk) begin
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always @(posedge wb_clk) begin
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cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
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cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
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if (!wb_rst && trap) begin
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if (!wb_rst && trap) begin
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`ifndef VERILATOR
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`ifndef VERILATOR
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repeat (10) @(posedge wb_clk);
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repeat (10) @(posedge wb_clk);
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`endif
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`endif
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$display("TRAP after %1d clock cycles", cycle_counter);
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$display("TRAP after %1d clock cycles", cycle_counter);
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if (exit) begin
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if (exit) begin
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$display("ALL TESTS PASSED.");
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$display("ALL TESTS PASSED.");
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$finish;
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$finish;
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end else begin
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end else begin
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$display("ERROR!");
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$display("ERROR!");
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if ($test$plusargs("noerror"))
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if ($test$plusargs("noerror")) $finish;
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$finish;
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$stop;
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$stop;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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@ -133,144 +129,144 @@ endmodule
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* picorv32_wb
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* picorv32_wb
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***************************************************************/
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***************************************************************/
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module picorv32_wb #() (
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module picorv32_wb #(
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output trap,
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) (
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output reg exit,
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output trap,
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output reg exit,
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// Wishbone interfaces
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// Wishbone interfaces
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input wb_rst_i,
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input wb_rst_i,
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input wb_clk_i,
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input wb_clk_i,
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output reg [31:0] wbm_adr_o,
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output reg [31:0] wbm_adr_o,
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output reg [31:0] wbm_dat_o,
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output reg [31:0] wbm_dat_o,
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input [31:0] wbm_dat_i,
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input [31:0] wbm_dat_i,
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output reg wbm_we_o,
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output reg wbm_we_o,
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output reg [3:0] wbm_sel_o,
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output reg [3:0] wbm_sel_o,
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output reg wbm_stb_o,
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output reg wbm_stb_o,
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input wbm_ack_i,
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input wbm_ack_i,
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output reg wbm_cyc_o,
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output reg wbm_cyc_o,
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// Pico Co-Processor Interface (PCPI)
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// Pico Co-Processor Interface (PCPI)
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output pcpi_valid,
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output pcpi_valid,
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output [31:0] pcpi_insn,
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output [31:0] pcpi_insn,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs2,
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output [31:0] pcpi_rs2,
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input pcpi_wr,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_wait,
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input pcpi_ready,
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input pcpi_ready,
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// IRQ interface
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// IRQ interface
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input [31:0] irq,
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input [31:0] irq,
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output [31:0] eoi,
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output [31:0] eoi,
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// Trace Interface
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// Trace Interface
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output trace_valid,
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output trace_valid,
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output [35:0] trace_data,
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output [35:0] trace_data,
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output mem_instr
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output mem_instr
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);
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);
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wire mem_valid;
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wire mem_valid;
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wire [31:0] mem_addr;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [31:0] mem_wdata;
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wire [ 3:0] mem_wstrb;
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wire [ 3:0] mem_wstrb;
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reg mem_ready;
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reg mem_ready;
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reg [31:0] mem_rdata;
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reg [31:0] mem_rdata;
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wire mem_la_read;
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wire mem_la_read;
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wire mem_la_write;
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wire mem_la_write;
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wire [31:0] mem_la_addr;
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wire [31:0] mem_la_addr;
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wire [31:0] mem_la_wdata;
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wire [31:0] mem_la_wdata;
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wire [3:0] mem_la_wstrb;
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wire [ 3:0] mem_la_wstrb;
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wire clk;
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wire clk;
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wire resetn;
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wire resetn;
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initial exit = 0;
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initial exit = 0;
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assign clk = wb_clk_i;
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assign clk = wb_clk_i;
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assign resetn = ~wb_rst_i;
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assign resetn = ~wb_rst_i;
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picorv32 #(
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picorv32 #(
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.ENABLE_COUNTERS(1),
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.ENABLE_COUNTERS(1),
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.ENABLE_COUNTERS64(1),
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.ENABLE_COUNTERS64(1),
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.ENABLE_REGS_16_31(1),
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.ENABLE_REGS_16_31(1),
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.ENABLE_REGS_DUALPORT(1),
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.ENABLE_REGS_DUALPORT(1),
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.TWO_STAGE_SHIFT(1),
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.TWO_STAGE_SHIFT(1),
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.BARREL_SHIFTER(0),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(1),
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.COMPRESSED_ISA(1),
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.CATCH_MISALIGN(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(1),
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.CATCH_ILLINSN(1),
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.ENABLE_PCPI(0),
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.ENABLE_PCPI(0),
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.ENABLE_MUL(1),
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.ENABLE_MUL(1),
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.ENABLE_FAST_MUL(0),
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.ENABLE_FAST_MUL(0),
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.ENABLE_DIV(1),
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.ENABLE_DIV(1),
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.ENABLE_IRQ(1),
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.ENABLE_IRQ(1),
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.ENABLE_IRQ_QREGS(1),
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.ENABLE_IRQ_QREGS(1),
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.ENABLE_IRQ_TIMER(1),
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.ENABLE_IRQ_TIMER(1),
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.ENABLE_TRACE(1),
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.ENABLE_TRACE(1),
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.REGS_INIT_ZERO(0),
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.REGS_INIT_ZERO(0),
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.MASKED_IRQ(32'h 0000_0000),
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.MASKED_IRQ(32'h0000_0000),
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.LATCHED_IRQ(32'h ffff_ffff),
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.LATCHED_IRQ(32'hffff_ffff),
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.PROGADDR_RESET(32'h 0000_0000),
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.PROGADDR_RESET(32'h0000_0000),
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.PROGADDR_IRQ(32'h 0000_0010),
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.PROGADDR_IRQ(32'h0000_0010),
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.STACKADDR(32'h ffff_ffff)
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.STACKADDR(32'hffff_ffff)
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) picorv32_core (
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) picorv32_core (
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.clk (clk ),
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.clk (clk),
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.resetn (resetn),
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.resetn(resetn),
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.trap (trap ),
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.trap (trap),
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.mem_valid (mem_valid ),
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.mem_valid (mem_valid),
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.mem_instr (mem_instr ),
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.mem_instr (mem_instr),
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.mem_ready (mem_ready ),
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.mem_ready (mem_ready),
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.mem_addr (mem_addr ),
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.mem_addr (mem_addr),
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.mem_wdata (mem_wdata ),
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.mem_wdata (mem_wdata),
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.mem_wstrb (mem_wstrb ),
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.mem_wstrb (mem_wstrb),
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.mem_rdata (mem_rdata ),
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.mem_rdata (mem_rdata),
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.mem_la_read (mem_la_read ),
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.mem_la_read (mem_la_read),
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.mem_la_write(mem_la_write),
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr ),
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.mem_la_addr (mem_la_addr),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_wstrb(mem_la_wstrb),
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.mem_la_wstrb(mem_la_wstrb),
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.irq(irq),
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.irq (irq),
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.eoi(eoi),
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.eoi (eoi),
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.trace_valid(trace_valid),
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.trace_valid(trace_valid),
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.trace_data (trace_data)
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.trace_data (trace_data)
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);
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);
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reg [7:0] memory [0:256*1024-1];
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reg [7:0] memory[0:256*1024-1];
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assign mem_ready = 1;
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assign mem_ready = 1;
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always @(posedge clk) begin
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always @(posedge clk) begin
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mem_rdata[ 7: 0] <= mem_la_read ? memory[mem_la_addr + 0] : 'bx;
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mem_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
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mem_rdata[15: 8] <= mem_la_read ? memory[mem_la_addr + 1] : 'bx;
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mem_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
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mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr + 2] : 'bx;
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mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
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mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr + 3] : 'bx;
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mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
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if (mem_la_write) begin
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if (mem_la_write) begin
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case (mem_la_addr)
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case (mem_la_addr)
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32'h1000_0000: begin
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32'h1000_0000: begin
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`ifndef TIMING
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`ifndef TIMING
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$write("%c", mem_la_wdata);
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$write("%c", mem_la_wdata);
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$fflush();
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$fflush();
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`endif
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`endif
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end
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end
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32'h2000_0000: begin
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32'h2000_0000: begin
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if (mem_la_wdata[31:0] == 123456789)
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if (mem_la_wdata[31:0] == 123456789) exit = 1;
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exit = 1;
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end
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end
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default: begin
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default: begin
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if (mem_la_wstrb[0]) memory[mem_la_addr+0] <= mem_la_wdata[7:0];
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if (mem_la_wstrb[0]) memory[mem_la_addr + 0] <= mem_la_wdata[ 7: 0];
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if (mem_la_wstrb[1]) memory[mem_la_addr+1] <= mem_la_wdata[15:8];
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if (mem_la_wstrb[1]) memory[mem_la_addr + 1] <= mem_la_wdata[15: 8];
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if (mem_la_wstrb[2]) memory[mem_la_addr+2] <= mem_la_wdata[23:16];
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if (mem_la_wstrb[2]) memory[mem_la_addr + 2] <= mem_la_wdata[23:16];
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if (mem_la_wstrb[3]) memory[mem_la_addr+3] <= mem_la_wdata[31:24];
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if (mem_la_wstrb[3]) memory[mem_la_addr + 3] <= mem_la_wdata[31:24];
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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Reference in New Issue