Merge branch 'master' into compressed
Conflicts: picorv32.v
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Clifford Wolf
commit
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24
README.md
24
README.md
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@ -27,14 +27,14 @@ PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wi
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Features and Typical Applications
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---------------------------------
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- Small (~1000 LUTs in a 7-Series Xilinx FPGA)
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- High fMAX (~250 MHz on 7-Series Xilinx FPGAs)
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- Small (750-1700 LUTs in 7-Series Xilinx Architecture)
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- High f<sub>max</sub> (250-450 MHz on 7-Series Xilinx FPGAs)
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- Selectable native memory interface or AXI4-Lite master
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- Optional IRQ support (using a simple custom ISA)
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- Optional Co-Processor Interface
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This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due
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to its high fMAX it can be integrated in most existing designs without crossing
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to its high f<sub>max</sub> it can be integrated in most existing designs without crossing
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clock domains. When operated on a lower frequency, it will have a lot of timing
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slack and thus can be added to a design without compromising timing closure.
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@ -251,16 +251,16 @@ The start address of the interrupt handler.
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Cycles per Instruction Performance
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----------------------------------
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*A short reminder: This core is optimized for size, not performance.*
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*A short reminder: This core is optimized for size and f<sub>max</sub>, not performance.*
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Unless stated otherwise, the following numbers apply to a PicoRV32 with
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ENABLE_REGS_DUALPORT active and connected to a memory that can accommodate
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requests within one clock cycle.
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The average Cycles per Instruction (CPI) is 4 to 5, depending on the mix of
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instructions in the code. The CPI numbers for the individual instructions
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can be found in the table below. The column "CPI (SP)" contains the
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CPI numbers for a core built without ENABLE_REGS_DUALPORT.
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The average Cycles per Instruction (CPI) is approximately 4, depending on the mix of
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instructions in the code. The CPI numbers for the individual instructions can
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be found in the table below. The column "CPI (SP)" contains the CPI numbers for
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a core built without ENABLE_REGS_DUALPORT.
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| Instruction | CPI | CPI (SP) |
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| ---------------------| ----:| --------:|
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@ -277,9 +277,9 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT.
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When `ENABLE_MUL` is activated, then a `MUL` instruction will execute
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in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles.
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Dhrystone benchmark results: 0.311 DMIPS/MHz (547 Dhrystones/Second/MHz)
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Dhrystone benchmark results: 0.327 DMIPS/MHz (575 Dhrystones/Second/MHz)
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For the Dhrystone benchmark the average CPI is 4.144.
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For the Dhrystone benchmark the average CPI is 3.945.
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PicoRV32 Native Memory Interface
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@ -531,7 +531,7 @@ pure RV32I target, and install it in `/opt/riscv32i`:
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git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
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cd riscv-gnu-toolchain-rv32i
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git checkout 4bcd4f5
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git checkout 06c957a
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mkdir build; cd build
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../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i
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@ -541,7 +541,7 @@ The commands will all be named using the prefix `riscv32-unknown-elf-`, which
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makes it easy to install them side-by-side with the regular riscv-tools, which
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are using the name prefix `riscv64-unknown-elf-` by default.
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*Note: This instructions are for git rev 4bcd4f5 (2015-12-14) of riscv-gnu-toolchain.*
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*Note: This instructions are for git rev 06c957a (2016-01-20) of riscv-gnu-toolchain.*
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Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
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@ -15,6 +15,11 @@
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# undef ENABLE_RVTST
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#endif
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// Only save registers in IRQ wrapper that are to be saved by the caller in
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// the RISC-V ABI, with the excpetion of the stack pointer. The IRQ handler
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// will save the rest if necessary. I.e. skip x3, x4, x8, x9, and x18-x27.
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#undef ENABLE_FASTIRQ
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#include "custom_ops.S"
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.section .text
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@ -58,6 +63,23 @@ irq_vec:
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getq x2, q3
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sw x2, 2*4(x1)
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#ifdef ENABLE_FASTIRQ
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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#else
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sw x3, 3*4(x1)
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sw x4, 4*4(x1)
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sw x5, 5*4(x1)
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@ -87,9 +109,30 @@ irq_vec:
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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#endif
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#else // ENABLE_QREGS
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#ifdef ENABLE_FASTIRQ
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sw gp, 0*4+0x200(zero)
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sw x1, 1*4+0x200(zero)
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sw x2, 2*4+0x200(zero)
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sw x5, 5*4+0x200(zero)
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sw x6, 6*4+0x200(zero)
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sw x7, 7*4+0x200(zero)
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sw x10, 10*4+0x200(zero)
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sw x11, 11*4+0x200(zero)
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sw x12, 12*4+0x200(zero)
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sw x13, 13*4+0x200(zero)
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sw x14, 14*4+0x200(zero)
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sw x15, 15*4+0x200(zero)
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sw x16, 16*4+0x200(zero)
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sw x17, 17*4+0x200(zero)
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sw x28, 28*4+0x200(zero)
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sw x29, 29*4+0x200(zero)
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sw x30, 30*4+0x200(zero)
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sw x31, 31*4+0x200(zero)
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#else
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sw gp, 0*4+0x200(zero)
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sw x1, 1*4+0x200(zero)
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sw x2, 2*4+0x200(zero)
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@ -122,6 +165,7 @@ irq_vec:
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sw x29, 29*4+0x200(zero)
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sw x30, 30*4+0x200(zero)
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sw x31, 31*4+0x200(zero)
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#endif
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#endif // ENABLE_QREGS
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@ -160,6 +204,23 @@ irq_vec:
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lw x2, 2*4(x1)
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setq q2, x2
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#ifdef ENABLE_FASTIRQ
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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#else
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lw x3, 3*4(x1)
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lw x4, 4*4(x1)
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lw x5, 5*4(x1)
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@ -189,6 +250,7 @@ irq_vec:
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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#endif
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getq x1, q1
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getq x2, q2
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@ -201,6 +263,26 @@ irq_vec:
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sbreak
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1:
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#ifdef ENABLE_FASTIRQ
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lw gp, 0*4+0x200(zero)
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lw x1, 1*4+0x200(zero)
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lw x2, 2*4+0x200(zero)
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lw x5, 5*4+0x200(zero)
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lw x6, 6*4+0x200(zero)
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lw x7, 7*4+0x200(zero)
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lw x10, 10*4+0x200(zero)
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lw x11, 11*4+0x200(zero)
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lw x12, 12*4+0x200(zero)
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lw x13, 13*4+0x200(zero)
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lw x14, 14*4+0x200(zero)
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lw x15, 15*4+0x200(zero)
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lw x16, 16*4+0x200(zero)
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lw x17, 17*4+0x200(zero)
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lw x28, 28*4+0x200(zero)
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lw x29, 29*4+0x200(zero)
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lw x30, 30*4+0x200(zero)
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lw x31, 31*4+0x200(zero)
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#else
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lw gp, 0*4+0x200(zero)
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lw x1, 1*4+0x200(zero)
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lw x2, 2*4+0x200(zero)
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@ -233,6 +315,7 @@ irq_vec:
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lw x29, 29*4+0x200(zero)
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lw x30, 30*4+0x200(zero)
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lw x31, 31*4+0x200(zero)
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#endif
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#endif // ENABLE_QREGS
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@ -353,7 +353,7 @@ module picorv32 #(
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0: begin
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mem_addr <= mem_la_addr;
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mem_wdata <= mem_la_wdata;
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mem_wstrb <= mem_la_wstrb;
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mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
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if (mem_do_prefetch || mem_do_rinst) begin
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current_insn_addr <= next_pc;
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end
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@ -945,6 +945,7 @@ module picorv32 #(
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latched_is_lh <= 0;
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latched_is_lb <= 0;
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pcpi_valid <= 0;
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pcpi_timeout <= 0;
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irq_active <= 0;
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irq_mask <= ~0;
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next_irq_pending = 0;
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