Towards compressed ISA support
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Clifford Wolf
parent
c59b0043c4
commit
db26b51afe
93
picorv32.v
93
picorv32.v
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@ -45,6 +45,7 @@ module picorv32 #(
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
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parameter [ 0:0] TWO_CYCLE_ALU = 0,
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parameter [ 0:0] COMPRESSED_ISA = 0,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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@ -184,7 +185,7 @@ module picorv32 #(
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assign mem_la_write = resetn && !mem_state && mem_do_wdata;
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assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);
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assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? next_pc : {reg_op1[31:2], 2'b00};
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assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2], 2'b00} : {reg_op1[31:2], 2'b00};
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wire [31:0] mem_rdata_latched;
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assign mem_rdata_latched = ((mem_valid && mem_ready) || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
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@ -219,8 +220,33 @@ module picorv32 #(
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end
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always @(posedge clk) begin
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if (mem_valid && mem_ready)
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if (mem_valid && mem_ready) begin
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mem_rdata_q <= mem_rdata_latched;
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if (COMPRESSED_ISA && mem_do_rinst) begin
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case (mem_rdata_latched[1:0] == 1)
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2'b00: begin // Quadrant 0
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end
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2'b01: begin // Quadrant 1
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case (mem_rdata_latched[15:13])
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3'b 000: begin // C.ADDI
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mem_rdata_q[14:12] <= 3'b000;
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mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
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end
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3'b 011: begin
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if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
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mem_rdata_q[14:12] <= 3'b000;
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mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
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mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
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end
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end
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endcase
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end
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2'b10: begin // Quadrant 2
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end
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endcase
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end
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end
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end
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always @(posedge clk) begin
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@ -281,6 +307,7 @@ module picorv32 #(
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reg decoder_trigger;
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reg decoder_trigger_q;
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reg decoder_pseudo_trigger;
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reg compressed_instr;
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reg is_lui_auipc_jal;
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reg is_lb_lh_lw_lbu_lhu;
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@ -404,6 +431,47 @@ module picorv32 #(
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if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
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decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
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compressed_instr <= 0;
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if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
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compressed_instr <= 1;
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decoded_rd <= 0;
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{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
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decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
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case (mem_rdata_latched[1:0])
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2'b00: begin // Quadrant 0
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decoded_rs1 <= 8 + mem_rdata_latched[9:7];
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decoded_rd <= 8 + mem_rdata_latched[4:2];
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end
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2'b01: begin // Quadrant 1
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case (mem_rdata_latched[15:13])
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3'b000: begin // C.NOP / C.ADDI
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is_alu_reg_imm <= 1;
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decoded_rd <= mem_rdata_latched[11:7];
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decoded_rs1 <= mem_rdata_latched[11:7];
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end
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3'b001: begin // C.JAL
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instr_jal <= 1;
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decoded_rd <= 1;
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end
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3'b 011: begin
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if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
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is_alu_reg_imm <= 1;
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decoded_rd <= mem_rdata_latched[11:7];
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decoded_rs1 <= mem_rdata_latched[11:7];
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end
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end
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3'b101: begin // C.J
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instr_jal <= 1;
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end
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endcase
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end
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2'b10: begin // Quadrant 2
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end
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endcase
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end
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end
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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@ -535,6 +603,7 @@ module picorv32 #(
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reg latched_store;
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reg latched_stalu;
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reg latched_branch;
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reg latched_compr;
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reg latched_is_lu;
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reg latched_is_lh;
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reg latched_is_lb;
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@ -685,8 +754,8 @@ module picorv32 #(
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case (1'b1)
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latched_branch: begin
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current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) : reg_next_pc;
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
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cpuregs[latched_rd] <= reg_pc + 4;
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
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cpuregs[latched_rd] <= reg_pc + (latched_compr ? 2 : 4);
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end
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latched_store && !latched_branch: begin
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`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
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@ -715,6 +784,7 @@ module picorv32 #(
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latched_is_lh <= 0;
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latched_is_lb <= 0;
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latched_rd <= decoded_rd;
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latched_compr <= compressed_instr;
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if (ENABLE_IRQ && ((decoder_trigger && !irq_active && |(irq_pending & ~irq_mask)) || irq_state)) begin
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irq_state <=
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@ -729,14 +799,14 @@ module picorv32 #(
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if (irq_pending) begin
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latched_store <= 1;
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reg_out <= irq_pending;
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reg_next_pc <= current_pc + 4;
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reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
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mem_do_rinst <= 1;
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end else
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do_waitirq <= 1;
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end else
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if (decoder_trigger) begin
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`debug($display("-- %-0t", $time);)
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reg_next_pc <= current_pc + 4;
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reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
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if (ENABLE_COUNTERS)
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count_instr <= count_instr + 1;
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if (instr_jal) begin
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@ -1067,7 +1137,7 @@ module picorv32 #(
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cpu_state <= cpu_state_trap;
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end
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end
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if (CATCH_MISALIGN && resetn && mem_do_rinst && reg_pc[1:0] != 0) begin
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if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
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`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
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next_irq_pending[irq_buserror] = 1;
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@ -1091,8 +1161,13 @@ module picorv32 #(
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irq_pending <= next_irq_pending & ~MASKED_IRQ;
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reg_pc[1:0] <= 0;
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reg_next_pc[1:0] <= 0;
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if (COMPRESSED_ISA) begin
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reg_pc[0] <= 0;
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reg_next_pc[0] <= 0;
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end else begin
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reg_pc[1:0] <= 0;
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reg_next_pc[1:0] <= 0;
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end
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current_pc = 'bx;
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end
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