colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Delete trace code in picorv.

This commit is contained in:
colin.liang 2023-01-17 13:00:31 +08:00
parent ef6fb8848f
commit dcab0c3178
3 changed files with 0 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
picorv32.v
View File

@ -40,7 +40,6 @@
***************************************************************/
module picorv32 #(
parameter [0:0] ENABLE_TRACE = 0,
parameter [31:0] PROGADDR_RESET = 32'h0000_0000,
parameter [31:0] STACKADDR = 32'hffff_ffff
) (
@ -74,10 +73,6 @@ module picorv32 #(
input pcpi_wait,
input pcpi_ready,
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data,
// IF DEBUG
output reg fetch_next,
output reg [31:0] dbg_insn_opcode,
@ -87,8 +82,6 @@ module picorv32 #(
localparam integer regfile_size = 32;
localparam integer regindex_bits = 5;
localparam [35:0] TRACE_BRANCH = {4'b0001, 32'b0};
localparam [35:0] TRACE_ADDR = {4'b0010, 32'b0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
@ -699,7 +692,6 @@ module picorv32 #(
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
@ -832,10 +824,6 @@ module picorv32 #(
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
trace_valid <= 0;
if (!ENABLE_TRACE) trace_data <= 'bx;
if (!resetn) begin
reg_pc <= PROGADDR_RESET;
reg_next_pc <= PROGADDR_RESET;
@ -843,7 +831,6 @@ module picorv32 #(
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
@ -880,13 +867,6 @@ module picorv32 #(
end
endcase
if (ENABLE_TRACE && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch) trace_data <= TRACE_BRANCH | (current_pc & 32'hfffffffe);
else trace_data <= latched_stalu ? alu_out_q : reg_out;
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
@ -901,7 +881,6 @@ module picorv32 #(
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
reg_next_pc <= current_pc + 4;
if (ENABLE_TRACE) latched_trace <= 1;
count_instr <= count_instr + 1;
if (instr_jal) begin
mem_do_rinst <= 1;
@ -1095,7 +1074,6 @@ module picorv32 #(
end
cpu_state_stmem: begin
if (ENABLE_TRACE) reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
@ -1104,10 +1082,6 @@ module picorv32 #(
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
@ -1132,10 +1106,6 @@ module picorv32 #(
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end

2
testbench.cc
View File

@ -49,8 +49,6 @@ int main(int argc, char** argv, char** env) {
top->wb_clk = !top->wb_clk;
top->eval();
if (tfp) tfp->dump(t);
if (trace_fd && top->wb_clk && top->trace_valid)
fprintf(trace_fd, "%9.9lx\n", top->trace_data);
t += 5;
}
if (tfp) tfp->close();

12
testbench_wb.v
View File

@ -6,8 +6,6 @@ module picorv32_wrapper #(
input wb_clk,
input wb_rst,
output trap,
output trace_valid,
output [35:0] trace_data,
input [1024:0] hex_file
);
wire exit;
@ -36,8 +34,6 @@ module picorv32_wrapper #(
.trap(trap),
.exit(exit),
.irq(irq),
.trace_valid(trace_valid),
.trace_data(trace_data),
.mem_instr(mem_instr),
.wb_clk_i(wb_clk),
@ -79,10 +75,6 @@ module picorv32_wb #(
input [31:0] irq,
output [31:0] eoi,
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
@ -112,7 +104,6 @@ module picorv32_wb #(
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_TRACE(1),
.PROGADDR_RESET(32'h0001_0000),
.STACKADDR(32'h0001_0000)
) picorv32_core (
@ -133,9 +124,6 @@ module picorv32_wb #(
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb),
.trace_valid(trace_valid),
.trace_data (trace_data),
.fetch_next(fetch_next),
.dbg_insn_opcode(dbg_insn_opcode),
.dbg_insn_addr(dbg_insn_addr),