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Added documentation for COMPRESSED_ISA parameter

This commit is contained in:
Clifford Wolf 2016-04-09 14:35:17 +02:00
parent aa17d58784
commit df7f5915d7
2 changed files with 6 additions and 1 deletions
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2
Makefile
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@ -9,7 +9,7 @@ FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve.
GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf- TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
# COMPRESSED_ISA = C COMPRESSED_ISA = C
test: testbench.exe firmware/firmware.hex test: testbench.exe firmware/firmware.hex
vvp -N testbench.exe vvp -N testbench.exe

5
README.md
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@ -185,6 +185,11 @@ the ALU.
*Note: Enabling this parameter will be most effective when retiming (aka *Note: Enabling this parameter will be most effective when retiming (aka
"register balancing") is enabled in the synthesis flow.* "register balancing") is enabled in the synthesis flow.*
#### COMPRESSED_ISA (default = 0)
This enables support for the RISC-V Compressed Instruction Set. Currently
this implements the draft version 1.9 of the compressed ISA specification.
#### CATCH_MISALIGN (default = 1) #### CATCH_MISALIGN (default = 1)
Set this to 0 to disable the circuitry for catching misaligned memory Set this to 0 to disable the circuitry for catching misaligned memory