colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Cleanups in dhrystone/testbench_slow_mem.v, added results to README

This commit is contained in:
Clifford Wolf 2016-09-04 12:25:23 +02:00
parent 990f876a5b
commit e403c950b0
2 changed files with 6 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
README.md
View File

@ -351,6 +351,9 @@ Dhrystone benchmark results: 0.521 DMIPS/MHz (916 Dhrystones/Second/MHz)
For the Dhrystone benchmark the average CPI is 4.081. For the Dhrystone benchmark the average CPI is 4.081.
Without using the look-ahead memory interface (usually required for max
clock speed), this results drop to 0.305 DMIPS/MHz and 5.232 CPI.
PicoRV32 Native Memory Interface PicoRV32 Native Memory Interface
-------------------------------- --------------------------------

27
dhrystone/testbench_slow_mem.v
View File

@ -13,7 +13,6 @@ module testbench;
end end
wire mem_valid; wire mem_valid;
reg mem_valid_q;
wire mem_instr; wire mem_instr;
reg mem_ready; reg mem_ready;
wire [31:0] mem_addr; wire [31:0] mem_addr;
@ -37,12 +36,7 @@ module testbench;
.mem_addr (mem_addr ), .mem_addr (mem_addr ),
.mem_wdata (mem_wdata ), .mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ), .mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ), .mem_rdata (mem_rdata )
.mem_la_read (),
.mem_la_write(),
.mem_la_addr (),
.mem_la_wdata(),
.mem_la_wstrb()
); );
reg [7:0] memory [0:256*1024-1]; reg [7:0] memory [0:256*1024-1];
@ -56,16 +50,14 @@ module testbench;
mem_rdata[23:16] <= 'bx; mem_rdata[23:16] <= 'bx;
mem_rdata[31:24] <= 'bx; mem_rdata[31:24] <= 'bx;
if (mem_valid & !mem_valid_q) begin if (mem_valid & !mem_ready) begin
if (|mem_wstrb) begin if (|mem_wstrb) begin
mem_ready <= 1'b1; mem_ready <= 1'b1;
case (mem_addr) case (mem_addr)
32'h1000_0000: begin 32'h1000_0000: begin
`ifndef TIMING
$write("%c", mem_wdata); $write("%c", mem_wdata);
$fflush(); $fflush();
`endif
end end
default: begin default: begin
if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0]; if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
@ -84,12 +76,10 @@ module testbench;
mem_rdata[31:24] <= memory[mem_addr + 3]; mem_rdata[31:24] <= memory[mem_addr + 3];
end end
end end
mem_valid_q <= mem_valid;
end end
initial begin initial begin
$dumpfile("testbench.vcd"); $dumpfile("testbench_slow_mem.vcd");
$dumpvars(0, testbench); $dumpvars(0, testbench);
end end
@ -100,15 +90,4 @@ module testbench;
$finish; $finish;
end end
end end
`ifdef TIMING
initial begin
repeat (100000) @(posedge clk);
$finish;
end
always @(posedge clk) begin
if (uut.dbg_next)
$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "pcpi", uut.count_cycle);
end
`endif
endmodule endmodule