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Refine testbench.v.

This commit is contained in:
colin.liang 2023-01-13 14:57:13 +08:00
parent e44af58d63
commit eab4b918b9
1 changed files with 1 additions and 86 deletions
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87
testbench_wb.v
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@ -1,59 +1,5 @@
`timescale 1 ns / 1 ps `timescale 1 ns / 1 ps
`ifndef VERILATOR
module testbench #(
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 1;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 0;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.VERBOSE(VERBOSE)
) top (
.wb_clk(clk),
.wb_rst(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule
`endif
module picorv32_wrapper #( module picorv32_wrapper #(
parameter VERBOSE = 0 parameter VERBOSE = 0
) ( ) (
@ -95,7 +41,7 @@ module picorv32_wrapper #(
.mem_instr(mem_instr), .mem_instr(mem_instr),
.wb_clk_i(wb_clk), .wb_clk_i(wb_clk),
.wb_rst_i(wb_rst), .wb_rst_i(wb_rst)
); );
initial begin initial begin
@ -107,9 +53,6 @@ module picorv32_wrapper #(
always @(posedge wb_clk) begin always @(posedge wb_clk) begin
cycle_counter <= !wb_rst ? cycle_counter + 1 : 0; cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
if (!wb_rst && trap) begin if (!wb_rst && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge wb_clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter); $display("TRAP after %1d clock cycles", cycle_counter);
if (exit) begin if (exit) begin
$display("ALL TESTS PASSED."); $display("ALL TESTS PASSED.");
@ -123,12 +66,6 @@ module picorv32_wrapper #(
end end
endmodule endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #( module picorv32_wb #(
) ( ) (
output trap, output trap,
@ -138,25 +75,6 @@ module picorv32_wb #(
input wb_rst_i, input wb_rst_i,
input wb_clk_i, input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface // IRQ interface
input [31:0] irq, input [31:0] irq,
output [31:0] eoi, output [31:0] eoi,
@ -200,7 +118,6 @@ module picorv32_wb #(
.resetn(resetn), .resetn(resetn),
.trap (trap), .trap (trap),
.mem_valid (mem_valid), .mem_valid (mem_valid),
.mem_instr (mem_instr), .mem_instr (mem_instr),
.mem_ready (mem_ready), .mem_ready (mem_ready),
@ -233,10 +150,8 @@ module picorv32_wb #(
if (mem_la_write) begin if (mem_la_write) begin
case (mem_la_addr) case (mem_la_addr)
32'h1000_0000: begin 32'h1000_0000: begin
`ifndef TIMING
$write("%c", mem_la_wdata); $write("%c", mem_la_wdata);
$fflush(); $fflush();
`endif
end end
32'h2000_0000: begin 32'h2000_0000: begin
if (mem_la_wdata[31:0] == 123456789) exit = 1; if (mem_la_wdata[31:0] == 123456789) exit = 1;