commit
f00a88c36e
2
Makefile
2
Makefile
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@ -93,7 +93,7 @@ check-%: check.smt2
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check.smt2: picorv32.v
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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-p 'prep -top picorv32 -nordff' \
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-p 'prep -top picorv32 -nordff' \
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-p 'assertpmux -noinit; opt -fast' \
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-p 'assertpmux -noinit; opt -fast; dffunmap' \
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-p 'write_smt2 -wires check.smt2'
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-p 'write_smt2 -wires check.smt2'
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synth.v: picorv32.v scripts/yosys/synth_sim.ys
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synth.v: picorv32.v scripts/yosys/synth_sim.ys
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@ -1,6 +1,6 @@
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USE_MYSTDLIB = 0
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USE_MYSTDLIB = 0
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OBJS = dhry_1.o dhry_2.o stdlib.o
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OBJS = dhry_1.o dhry_2.o stdlib.o
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CFLAGS = -MD -O3 -march=rv32im -DTIME -DRISCV
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CFLAGS = -MD -O3 -mabi=ilp32 -march=rv32im -DTIME -DRISCV
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TOOLCHAIN_PREFIX = /opt/riscv32im/bin/riscv32-unknown-elf-
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TOOLCHAIN_PREFIX = /opt/riscv32im/bin/riscv32-unknown-elf-
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ifeq ($(USE_MYSTDLIB),1)
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ifeq ($(USE_MYSTDLIB),1)
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@ -383,8 +383,13 @@
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/* General definitions: */
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/* General definitions: */
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#ifdef USE_MYSTDLIB
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extern char *strcpy(char *dest, const char *src);
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extern int strcmp(const char *s1, const char *s2);
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#else
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#include <stdio.h>
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#include <stdio.h>
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/* for strcpy, strcmp */
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/* for strcpy, strcmp */
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#endif
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#define Null 0
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#define Null 0
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/* Value of a Null pointer */
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/* Value of a Null pointer */
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@ -2,7 +2,7 @@
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/spiflash_tb.vvp
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/spiflash_tb.vvp
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/hx8kdemo.asc
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/hx8kdemo.asc
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/hx8kdemo.bin
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/hx8kdemo.bin
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/hx8kdemo.blif
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/hx8kdemo.json
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/hx8kdemo.log
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/hx8kdemo.log
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/hx8kdemo.rpt
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/hx8kdemo.rpt
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/hx8kdemo_syn.v
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/hx8kdemo_syn.v
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@ -14,13 +14,13 @@ hx8kdemo.json: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
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yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^
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yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^
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hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
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hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
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hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v
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hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
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hx8kdemo_syn.v: hx8kdemo.blif
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hx8kdemo_syn.v: hx8kdemo.json
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yosys -p 'read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v'
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yosys -p 'read_json hx8kdemo.json; write_verilog hx8kdemo_syn.v'
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hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json
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hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json
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nextpnr-ice40 --hx8k --package ct256 --asc hx8kdemo.asc --json hx8kdemo.json --pcf hx8kdemo.pcf
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nextpnr-ice40 --hx8k --package ct256 --asc hx8kdemo.asc --json hx8kdemo.json --pcf hx8kdemo.pcf
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@ -60,10 +60,10 @@ icebreaker.json: icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.
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yosys -ql icebreaker.log -p 'synth_ice40 -dsp -top icebreaker -json icebreaker.json' $^
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yosys -ql icebreaker.log -p 'synth_ice40 -dsp -top icebreaker -json icebreaker.json' $^
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icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
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icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
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icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v
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icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
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icebreaker_syn.v: icebreaker.json
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icebreaker_syn.v: icebreaker.json
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yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v'
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yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v'
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@ -96,8 +96,8 @@ icebreaker_fw.bin: icebreaker_fw.elf
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# ---- Testbench for SPI Flash Model ----
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# ---- Testbench for SPI Flash Model ----
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spiflash_tb: spiflash_tb.vvp firmware.hex
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spiflash_tb: spiflash_tb.vvp icebreaker_fw.hex
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vvp -N $<
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vvp -N $< +firmware=icebreaker_fw.hex
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spiflash_tb.vvp: spiflash.v spiflash_tb.v
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spiflash_tb.vvp: spiflash.v spiflash_tb.v
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iverilog -s testbench -o $@ $^
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iverilog -s testbench -o $@ $^
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