From f02c0b23c49f803b95d244a832da9b78c04fb581 Mon Sep 17 00:00:00 2001 From: "colin.liang" Date: Mon, 9 Jan 2023 15:33:37 +0800 Subject: [PATCH] Delete axi ez sp. --- Makefile | 44 +----- picorv32.v | 253 ------------------------------ testbench.cc | 10 +- testbench.v | 410 ------------------------------------------------- testbench_ez.v | 86 ----------- 5 files changed, 9 insertions(+), 794 deletions(-) delete mode 100644 testbench.v delete mode 100644 testbench_ez.v diff --git a/Makefile b/Makefile index f9d7594..2a1f281 100644 --- a/Makefile +++ b/Makefile @@ -21,58 +21,21 @@ COMPRESSED_ISA = C # Add things like "export http_proxy=... https_proxy=..." here GIT_ENV = true -test: testbench.vvp firmware/firmware.hex - $(VVP) -N $< - -test_vcd: testbench.vvp firmware/firmware.hex - $(VVP) -N $< +vcd +trace +noerror - test_wb: testbench_wb.vvp firmware/firmware.hex $(VVP) -N $< test_wb_vcd: testbench_wb.vvp firmware/firmware.hex $(VVP) -N $< +vcd +trace +noerror -test_ez: testbench_ez.vvp - $(VVP) -N $< - -test_ez_vcd: testbench_ez.vvp - $(VVP) -N $< +vcd - -test_sp: testbench_sp.vvp firmware/firmware.hex - $(VVP) -N $< - -test_axi: testbench.vvp firmware/firmware.hex - $(VVP) -N $< +axi_test - -test_synth: testbench_synth.vvp firmware/firmware.hex - $(VVP) -N $< - test_verilator: testbench_verilator firmware/firmware.hex ./testbench_verilator -testbench.vvp: testbench.v picorv32.v - $(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^ - chmod -x $@ - testbench_wb.vvp: testbench_wb.v picorv32.v $(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^ chmod -x $@ -testbench_ez.vvp: testbench_ez.v picorv32.v - $(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^ - chmod -x $@ - -testbench_sp.vvp: testbench.v picorv32.v - $(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^ - chmod -x $@ - -testbench_synth.vvp: testbench.v synth.v - $(IVERILOG) -o $@ -DSYNTH_TEST $^ - chmod -x $@ - -testbench_verilator: testbench.v picorv32.v testbench.cc - $(VERILATOR) --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench.v picorv32.v testbench.cc \ +testbench_verilator: testbench_wb.v picorv32.v testbench.cc + $(VERILATOR) --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench_wb.v picorv32.v testbench.cc \ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) --Mdir testbench_verilator_dir $(MAKE) -C testbench_verilator_dir -f Vpicorv32_wrapper.mk cp testbench_verilator_dir/Vpicorv32_wrapper testbench_verilator @@ -170,8 +133,7 @@ clean: riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \ firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \ - testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \ testbench_wb.vvp testbench.vcd testbench.trace \ testbench_verilator testbench_verilator_dir -.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean +.PHONY: test_wb test_wb_vcd download-tools build-tools toc clean diff --git a/picorv32.v b/picorv32.v index 90640ac..57ea7db 100644 --- a/picorv32.v +++ b/picorv32.v @@ -2236,259 +2236,6 @@ module picorv32_pcpi_div ( endmodule -/*************************************************************** - * picorv32_axi - ***************************************************************/ - -module picorv32_axi #( - parameter [ 0:0] ENABLE_COUNTERS = 1, - parameter [ 0:0] ENABLE_COUNTERS64 = 1, - parameter [ 0:0] ENABLE_REGS_16_31 = 1, - parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, - parameter [ 0:0] TWO_STAGE_SHIFT = 1, - parameter [ 0:0] BARREL_SHIFTER = 0, - parameter [ 0:0] TWO_CYCLE_COMPARE = 0, - parameter [ 0:0] TWO_CYCLE_ALU = 0, - parameter [ 0:0] COMPRESSED_ISA = 0, - parameter [ 0:0] CATCH_MISALIGN = 1, - parameter [ 0:0] CATCH_ILLINSN = 1, - parameter [ 0:0] ENABLE_PCPI = 0, - parameter [ 0:0] ENABLE_MUL = 0, - parameter [ 0:0] ENABLE_FAST_MUL = 0, - parameter [ 0:0] ENABLE_DIV = 0, - parameter [ 0:0] ENABLE_IRQ = 0, - parameter [ 0:0] ENABLE_IRQ_QREGS = 1, - parameter [ 0:0] ENABLE_IRQ_TIMER = 1, - parameter [ 0:0] ENABLE_TRACE = 0, - parameter [ 0:0] REGS_INIT_ZERO = 0, - parameter [31:0] MASKED_IRQ = 32'h 0000_0000, - parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, - parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, - parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, - parameter [31:0] STACKADDR = 32'h ffff_ffff -) ( - input clk, resetn, - output trap, - - // AXI4-lite master memory interface - - output mem_axi_awvalid, - input mem_axi_awready, - output [31:0] mem_axi_awaddr, - output [ 2:0] mem_axi_awprot, - - output mem_axi_wvalid, - input mem_axi_wready, - output [31:0] mem_axi_wdata, - output [ 3:0] mem_axi_wstrb, - - input mem_axi_bvalid, - output mem_axi_bready, - - output mem_axi_arvalid, - input mem_axi_arready, - output [31:0] mem_axi_araddr, - output [ 2:0] mem_axi_arprot, - - input mem_axi_rvalid, - output mem_axi_rready, - input [31:0] mem_axi_rdata, - - // Pico Co-Processor Interface (PCPI) - output pcpi_valid, - output [31:0] pcpi_insn, - output [31:0] pcpi_rs1, - output [31:0] pcpi_rs2, - input pcpi_wr, - input [31:0] pcpi_rd, - input pcpi_wait, - input pcpi_ready, - - // IRQ interface - input [31:0] irq, - output [31:0] eoi, - - // Trace Interface - output trace_valid, - output [35:0] trace_data -); - wire mem_valid; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [ 3:0] mem_wstrb; - wire mem_instr; - wire mem_ready; - wire [31:0] mem_rdata; - - picorv32_axi_adapter axi_adapter ( - .clk (clk ), - .resetn (resetn ), - .mem_axi_awvalid(mem_axi_awvalid), - .mem_axi_awready(mem_axi_awready), - .mem_axi_awaddr (mem_axi_awaddr ), - .mem_axi_awprot (mem_axi_awprot ), - .mem_axi_wvalid (mem_axi_wvalid ), - .mem_axi_wready (mem_axi_wready ), - .mem_axi_wdata (mem_axi_wdata ), - .mem_axi_wstrb (mem_axi_wstrb ), - .mem_axi_bvalid (mem_axi_bvalid ), - .mem_axi_bready (mem_axi_bready ), - .mem_axi_arvalid(mem_axi_arvalid), - .mem_axi_arready(mem_axi_arready), - .mem_axi_araddr (mem_axi_araddr ), - .mem_axi_arprot (mem_axi_arprot ), - .mem_axi_rvalid (mem_axi_rvalid ), - .mem_axi_rready (mem_axi_rready ), - .mem_axi_rdata (mem_axi_rdata ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ) - ); - - picorv32 #( - .ENABLE_COUNTERS (ENABLE_COUNTERS ), - .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), - .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), - .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), - .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), - .BARREL_SHIFTER (BARREL_SHIFTER ), - .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), - .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), - .COMPRESSED_ISA (COMPRESSED_ISA ), - .CATCH_MISALIGN (CATCH_MISALIGN ), - .CATCH_ILLINSN (CATCH_ILLINSN ), - .ENABLE_PCPI (ENABLE_PCPI ), - .ENABLE_MUL (ENABLE_MUL ), - .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), - .ENABLE_DIV (ENABLE_DIV ), - .ENABLE_IRQ (ENABLE_IRQ ), - .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), - .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), - .ENABLE_TRACE (ENABLE_TRACE ), - .REGS_INIT_ZERO (REGS_INIT_ZERO ), - .MASKED_IRQ (MASKED_IRQ ), - .LATCHED_IRQ (LATCHED_IRQ ), - .PROGADDR_RESET (PROGADDR_RESET ), - .PROGADDR_IRQ (PROGADDR_IRQ ), - .STACKADDR (STACKADDR ) - ) picorv32_core ( - .clk (clk ), - .resetn (resetn), - .trap (trap ), - - .mem_valid(mem_valid), - .mem_addr (mem_addr ), - .mem_wdata(mem_wdata), - .mem_wstrb(mem_wstrb), - .mem_instr(mem_instr), - .mem_ready(mem_ready), - .mem_rdata(mem_rdata), - - .pcpi_valid(pcpi_valid), - .pcpi_insn (pcpi_insn ), - .pcpi_rs1 (pcpi_rs1 ), - .pcpi_rs2 (pcpi_rs2 ), - .pcpi_wr (pcpi_wr ), - .pcpi_rd (pcpi_rd ), - .pcpi_wait (pcpi_wait ), - .pcpi_ready(pcpi_ready), - - .irq(irq), - .eoi(eoi), - .trace_valid(trace_valid), - .trace_data (trace_data) - ); -endmodule - - -/*************************************************************** - * picorv32_axi_adapter - ***************************************************************/ - -module picorv32_axi_adapter ( - input clk, resetn, - - // AXI4-lite master memory interface - - output mem_axi_awvalid, - input mem_axi_awready, - output [31:0] mem_axi_awaddr, - output [ 2:0] mem_axi_awprot, - - output mem_axi_wvalid, - input mem_axi_wready, - output [31:0] mem_axi_wdata, - output [ 3:0] mem_axi_wstrb, - - input mem_axi_bvalid, - output mem_axi_bready, - - output mem_axi_arvalid, - input mem_axi_arready, - output [31:0] mem_axi_araddr, - output [ 2:0] mem_axi_arprot, - - input mem_axi_rvalid, - output mem_axi_rready, - input [31:0] mem_axi_rdata, - - // Native PicoRV32 memory interface - - input mem_valid, - input mem_instr, - output mem_ready, - input [31:0] mem_addr, - input [31:0] mem_wdata, - input [ 3:0] mem_wstrb, - output [31:0] mem_rdata -); - reg ack_awvalid; - reg ack_arvalid; - reg ack_wvalid; - reg xfer_done; - - assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid; - assign mem_axi_awaddr = mem_addr; - assign mem_axi_awprot = 0; - - assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid; - assign mem_axi_araddr = mem_addr; - assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000; - - assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid; - assign mem_axi_wdata = mem_wdata; - assign mem_axi_wstrb = mem_wstrb; - - assign mem_ready = mem_axi_bvalid || mem_axi_rvalid; - assign mem_axi_bready = mem_valid && |mem_wstrb; - assign mem_axi_rready = mem_valid && !mem_wstrb; - assign mem_rdata = mem_axi_rdata; - - always @(posedge clk) begin - if (!resetn) begin - ack_awvalid <= 0; - end else begin - xfer_done <= mem_valid && mem_ready; - if (mem_axi_awready && mem_axi_awvalid) - ack_awvalid <= 1; - if (mem_axi_arready && mem_axi_arvalid) - ack_arvalid <= 1; - if (mem_axi_wready && mem_axi_wvalid) - ack_wvalid <= 1; - if (xfer_done || !mem_valid) begin - ack_awvalid <= 0; - ack_arvalid <= 0; - ack_wvalid <= 0; - end - end - end -endmodule - - /*************************************************************** * picorv32_wb ***************************************************************/ diff --git a/testbench.cc b/testbench.cc index 61c4366..2d37492 100644 --- a/testbench.cc +++ b/testbench.cc @@ -26,15 +26,17 @@ int main(int argc, char **argv, char **env) trace_fd = fopen("testbench.trace", "w"); } - top->clk = 0; + top->wb_clk = 0; + top->wb_rst = 1; + int t = 0; while (!Verilated::gotFinish()) { if (t > 200) - top->resetn = 1; - top->clk = !top->clk; + top->wb_rst = 0; + top->wb_clk = !top->wb_clk; top->eval(); if (tfp) tfp->dump (t); - if (trace_fd && top->clk && top->trace_valid) fprintf(trace_fd, "%9.9lx\n", top->trace_data); + if (trace_fd && top->wb_clk && top->trace_valid) fprintf(trace_fd, "%9.9lx\n", top->trace_data); t += 5; } if (tfp) tfp->close(); diff --git a/testbench.v b/testbench.v deleted file mode 100644 index 04c1946..0000000 --- a/testbench.v +++ /dev/null @@ -1,410 +0,0 @@ -// This is free and unencumbered software released into the public domain. -// -// Anyone is free to copy, modify, publish, use, compile, sell, or -// distribute this software, either in source code form or as a compiled -// binary, for any purpose, commercial or non-commercial, and by any -// means. - -`timescale 1 ns / 1 ps - -`ifndef VERILATOR -module testbench #( - parameter AXI_TEST = 0, - parameter VERBOSE = 0 -); - reg clk = 1; - reg resetn = 0; - wire trap; - - always #5 clk = ~clk; - - initial begin - repeat (100) @(posedge clk); - resetn <= 1; - end - - initial begin - if ($test$plusargs("vcd")) begin - $dumpfile("testbench.vcd"); - $dumpvars(0, testbench); - end - repeat (1000000) @(posedge clk); - $display("TIMEOUT"); - $finish; - end - - wire trace_valid; - wire [35:0] trace_data; - integer trace_file; - - initial begin - if ($test$plusargs("trace")) begin - trace_file = $fopen("testbench.trace", "w"); - repeat (10) @(posedge clk); - while (!trap) begin - @(posedge clk); - if (trace_valid) - $fwrite(trace_file, "%x\n", trace_data); - end - $fclose(trace_file); - $display("Finished writing testbench.trace."); - end - end - - picorv32_wrapper #( - .AXI_TEST (AXI_TEST), - .VERBOSE (VERBOSE) - ) top ( - .clk(clk), - .resetn(resetn), - .trap(trap), - .trace_valid(trace_valid), - .trace_data(trace_data) - ); -endmodule -`endif - -module picorv32_wrapper #( - parameter AXI_TEST = 0, - parameter VERBOSE = 0 -) ( - input clk, - input resetn, - output trap, - output trace_valid, - output [35:0] trace_data -); - wire tests_passed; - reg [31:0] irq = 0; - - reg [15:0] count_cycle = 0; - always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0; - - always @* begin - irq = 0; - irq[4] = &count_cycle[12:0]; - irq[5] = &count_cycle[15:0]; - end - - wire mem_axi_awvalid; - wire mem_axi_awready; - wire [31:0] mem_axi_awaddr; - wire [ 2:0] mem_axi_awprot; - - wire mem_axi_wvalid; - wire mem_axi_wready; - wire [31:0] mem_axi_wdata; - wire [ 3:0] mem_axi_wstrb; - - wire mem_axi_bvalid; - wire mem_axi_bready; - - wire mem_axi_arvalid; - wire mem_axi_arready; - wire [31:0] mem_axi_araddr; - wire [ 2:0] mem_axi_arprot; - - wire mem_axi_rvalid; - wire mem_axi_rready; - wire [31:0] mem_axi_rdata; - - axi4_memory #( - .AXI_TEST (AXI_TEST), - .VERBOSE (VERBOSE) - ) mem ( - .clk (clk ), - .mem_axi_awvalid (mem_axi_awvalid ), - .mem_axi_awready (mem_axi_awready ), - .mem_axi_awaddr (mem_axi_awaddr ), - .mem_axi_awprot (mem_axi_awprot ), - - .mem_axi_wvalid (mem_axi_wvalid ), - .mem_axi_wready (mem_axi_wready ), - .mem_axi_wdata (mem_axi_wdata ), - .mem_axi_wstrb (mem_axi_wstrb ), - - .mem_axi_bvalid (mem_axi_bvalid ), - .mem_axi_bready (mem_axi_bready ), - - .mem_axi_arvalid (mem_axi_arvalid ), - .mem_axi_arready (mem_axi_arready ), - .mem_axi_araddr (mem_axi_araddr ), - .mem_axi_arprot (mem_axi_arprot ), - - .mem_axi_rvalid (mem_axi_rvalid ), - .mem_axi_rready (mem_axi_rready ), - .mem_axi_rdata (mem_axi_rdata ), - - .tests_passed (tests_passed ) - ); - - picorv32_axi #( -`ifndef SYNTH_TEST -`ifdef SP_TEST - .ENABLE_REGS_DUALPORT(0), -`endif -`ifdef COMPRESSED_ISA - .COMPRESSED_ISA(1), -`endif - .ENABLE_MUL(1), - .ENABLE_DIV(1), - .ENABLE_IRQ(1), - .ENABLE_TRACE(1) -`endif - ) uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_axi_awvalid(mem_axi_awvalid), - .mem_axi_awready(mem_axi_awready), - .mem_axi_awaddr (mem_axi_awaddr ), - .mem_axi_awprot (mem_axi_awprot ), - .mem_axi_wvalid (mem_axi_wvalid ), - .mem_axi_wready (mem_axi_wready ), - .mem_axi_wdata (mem_axi_wdata ), - .mem_axi_wstrb (mem_axi_wstrb ), - .mem_axi_bvalid (mem_axi_bvalid ), - .mem_axi_bready (mem_axi_bready ), - .mem_axi_arvalid(mem_axi_arvalid), - .mem_axi_arready(mem_axi_arready), - .mem_axi_araddr (mem_axi_araddr ), - .mem_axi_arprot (mem_axi_arprot ), - .mem_axi_rvalid (mem_axi_rvalid ), - .mem_axi_rready (mem_axi_rready ), - .mem_axi_rdata (mem_axi_rdata ), - .irq (irq ), - .trace_valid (trace_valid ), - .trace_data (trace_data ) - ); - - reg [1023:0] firmware_file; - initial begin - if (!$value$plusargs("firmware=%s", firmware_file)) - firmware_file = "firmware/firmware.hex"; - $readmemh(firmware_file, mem.memory); - end - - integer cycle_counter; - always @(posedge clk) begin - cycle_counter <= resetn ? cycle_counter + 1 : 0; - if (resetn && trap) begin -`ifndef VERILATOR - repeat (10) @(posedge clk); -`endif - $display("TRAP after %1d clock cycles", cycle_counter); - if (tests_passed) begin - $display("ALL TESTS PASSED."); - $finish; - end else begin - $display("ERROR!"); - if ($test$plusargs("noerror")) - $finish; - $stop; - end - end - end -endmodule - -module axi4_memory #( - parameter AXI_TEST = 0, - parameter VERBOSE = 0 -) ( - /* verilator lint_off MULTIDRIVEN */ - - input clk, - input mem_axi_awvalid, - output reg mem_axi_awready, - input [31:0] mem_axi_awaddr, - input [ 2:0] mem_axi_awprot, - - input mem_axi_wvalid, - output reg mem_axi_wready, - input [31:0] mem_axi_wdata, - input [ 3:0] mem_axi_wstrb, - - output reg mem_axi_bvalid, - input mem_axi_bready, - - input mem_axi_arvalid, - output reg mem_axi_arready, - input [31:0] mem_axi_araddr, - input [ 2:0] mem_axi_arprot, - - output reg mem_axi_rvalid, - input mem_axi_rready, - output reg [31:0] mem_axi_rdata, - - output reg tests_passed -); - reg [31:0] memory [0:128*1024/4-1] /* verilator public */; - reg verbose; - initial verbose = $test$plusargs("verbose") || VERBOSE; - - reg axi_test; - initial axi_test = $test$plusargs("axi_test") || AXI_TEST; - - initial begin - mem_axi_awready = 0; - mem_axi_wready = 0; - mem_axi_bvalid = 0; - mem_axi_arready = 0; - mem_axi_rvalid = 0; - tests_passed = 0; - end - - reg [63:0] xorshift64_state = 64'd88172645463325252; - - task xorshift64_next; - begin - // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14). - xorshift64_state = xorshift64_state ^ (xorshift64_state << 13); - xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7); - xorshift64_state = xorshift64_state ^ (xorshift64_state << 17); - end - endtask - - reg [2:0] fast_axi_transaction = ~0; - reg [4:0] async_axi_transaction = ~0; - reg [4:0] delay_axi_transaction = 0; - - always @(posedge clk) begin - if (axi_test) begin - xorshift64_next; - {fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state; - end - end - - reg latched_raddr_en = 0; - reg latched_waddr_en = 0; - reg latched_wdata_en = 0; - - reg fast_raddr = 0; - reg fast_waddr = 0; - reg fast_wdata = 0; - - reg [31:0] latched_raddr; - reg [31:0] latched_waddr; - reg [31:0] latched_wdata; - reg [ 3:0] latched_wstrb; - reg latched_rinsn; - - task handle_axi_arvalid; begin - mem_axi_arready <= 1; - latched_raddr = mem_axi_araddr; - latched_rinsn = mem_axi_arprot[2]; - latched_raddr_en = 1; - fast_raddr <= 1; - end endtask - - task handle_axi_awvalid; begin - mem_axi_awready <= 1; - latched_waddr = mem_axi_awaddr; - latched_waddr_en = 1; - fast_waddr <= 1; - end endtask - - task handle_axi_wvalid; begin - mem_axi_wready <= 1; - latched_wdata = mem_axi_wdata; - latched_wstrb = mem_axi_wstrb; - latched_wdata_en = 1; - fast_wdata <= 1; - end endtask - - task handle_axi_rvalid; begin - if (verbose) - $display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : ""); - if (latched_raddr < 128*1024) begin - mem_axi_rdata <= memory[latched_raddr >> 2]; - mem_axi_rvalid <= 1; - latched_raddr_en = 0; - end else begin - $display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr); - $finish; - end - end endtask - - task handle_axi_bvalid; begin - if (verbose) - $display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb); - if (latched_waddr < 128*1024) begin - if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0]; - if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8]; - if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16]; - if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24]; - end else - if (latched_waddr == 32'h1000_0000) begin - if (verbose) begin - if (32 <= latched_wdata && latched_wdata < 128) - $display("OUT: '%c'", latched_wdata[7:0]); - else - $display("OUT: %3d", latched_wdata); - end else begin - $write("%c", latched_wdata[7:0]); -`ifndef VERILATOR - $fflush(); -`endif - end - end else - if (latched_waddr == 32'h2000_0000) begin - if (latched_wdata == 123456789) - tests_passed = 1; - end else begin - $display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr); - $finish; - end - mem_axi_bvalid <= 1; - latched_waddr_en = 0; - latched_wdata_en = 0; - end endtask - - always @(negedge clk) begin - if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid; - if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid; - if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid; - if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid; - if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid; - end - - always @(posedge clk) begin - mem_axi_arready <= 0; - mem_axi_awready <= 0; - mem_axi_wready <= 0; - - fast_raddr <= 0; - fast_waddr <= 0; - fast_wdata <= 0; - - if (mem_axi_rvalid && mem_axi_rready) begin - mem_axi_rvalid <= 0; - end - - if (mem_axi_bvalid && mem_axi_bready) begin - mem_axi_bvalid <= 0; - end - - if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin - latched_raddr = mem_axi_araddr; - latched_rinsn = mem_axi_arprot[2]; - latched_raddr_en = 1; - end - - if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin - latched_waddr = mem_axi_awaddr; - latched_waddr_en = 1; - end - - if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin - latched_wdata = mem_axi_wdata; - latched_wstrb = mem_axi_wstrb; - latched_wdata_en = 1; - end - - if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid; - if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid; - if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid; - - if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid; - if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid; - end -endmodule diff --git a/testbench_ez.v b/testbench_ez.v deleted file mode 100644 index 55c9c69..0000000 --- a/testbench_ez.v +++ /dev/null @@ -1,86 +0,0 @@ -// This is free and unencumbered software released into the public domain. -// -// Anyone is free to copy, modify, publish, use, compile, sell, or -// distribute this software, either in source code form or as a compiled -// binary, for any purpose, commercial or non-commercial, and by any -// means. - -`timescale 1 ns / 1 ps - -module testbench; - reg clk = 1; - reg resetn = 0; - wire trap; - - always #5 clk = ~clk; - - initial begin - if ($test$plusargs("vcd")) begin - $dumpfile("testbench.vcd"); - $dumpvars(0, testbench); - end - repeat (100) @(posedge clk); - resetn <= 1; - repeat (1000) @(posedge clk); - $finish; - end - - wire mem_valid; - wire mem_instr; - reg mem_ready; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [3:0] mem_wstrb; - reg [31:0] mem_rdata; - - always @(posedge clk) begin - if (mem_valid && mem_ready) begin - if (mem_instr) - $display("ifetch 0x%08x: 0x%08x", mem_addr, mem_rdata); - else if (mem_wstrb) - $display("write 0x%08x: 0x%08x (wstrb=%b)", mem_addr, mem_wdata, mem_wstrb); - else - $display("read 0x%08x: 0x%08x", mem_addr, mem_rdata); - end - end - - picorv32 #( - ) uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ) - ); - - reg [31:0] memory [0:255]; - - initial begin - memory[0] = 32'h 3fc00093; // li x1,1020 - memory[1] = 32'h 0000a023; // sw x0,0(x1) - memory[2] = 32'h 0000a103; // loop: lw x2,0(x1) - memory[3] = 32'h 00110113; // addi x2,x2,1 - memory[4] = 32'h 0020a023; // sw x2,0(x1) - memory[5] = 32'h ff5ff06f; // j - end - - always @(posedge clk) begin - mem_ready <= 0; - if (mem_valid && !mem_ready) begin - if (mem_addr < 1024) begin - mem_ready <= 1; - mem_rdata <= memory[mem_addr >> 2]; - if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; - if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; - if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; - if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; - end - /* add memory-mapped IO here */ - end - end -endmodule