assembler support for custom0 is deprecated, using cpp macros now
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@ -5,32 +5,96 @@
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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#define q0 0
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#define q1 1
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#define q2 2
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#define q3 3
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#define regnum_q0 0
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#define regnum_q1 1
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#define regnum_q2 2
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#define regnum_q3 3
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.macro getq rd qs
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custom0 \rd,\qs,0,0
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.endm
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#define regnum_x0 0
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#define regnum_x1 1
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#define regnum_x2 2
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#define regnum_x3 3
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#define regnum_x4 4
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#define regnum_x5 5
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#define regnum_x6 6
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#define regnum_x7 7
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#define regnum_x8 8
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#define regnum_x9 9
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#define regnum_x10 10
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#define regnum_x11 11
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#define regnum_x12 12
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#define regnum_x13 13
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#define regnum_x14 14
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#define regnum_x15 15
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#define regnum_x16 16
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#define regnum_x17 17
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#define regnum_x18 18
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#define regnum_x19 19
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#define regnum_x20 20
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#define regnum_x21 21
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#define regnum_x22 22
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#define regnum_x23 23
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#define regnum_x24 24
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#define regnum_x25 25
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#define regnum_x26 26
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#define regnum_x27 27
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#define regnum_x28 28
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#define regnum_x29 29
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#define regnum_x30 30
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#define regnum_x31 31
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.macro setq qd rs
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custom0 \qd,\rs,0,1
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.endm
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#define regnum_zero 0
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#define regnum_ra 1
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#define regnum_sp 2
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#define regnum_gp 3
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#define regnum_tp 4
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#define regnum_t0 5
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#define regnum_t1 6
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#define regnum_t2 7
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#define regnum_fp 8 // x8 is s0 and also fp
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#define regnum_s0 8
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#define regnum_s1 9
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#define regnum_a0 10
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#define regnum_a1 11
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#define regnum_a2 12
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#define regnum_a3 13
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#define regnum_a4 14
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#define regnum_a5 15
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#define regnum_a6 16
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#define regnum_a7 17
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#define regnum_s2 18
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#define regnum_s3 19
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#define regnum_s4 20
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#define regnum_s5 21
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#define regnum_s6 22
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#define regnum_s7 23
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#define regnum_s8 24
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#define regnum_s9 25
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#define regnum_s10 26
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#define regnum_s11 27
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#define regnum_t3 28
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#define regnum_t4 29
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#define regnum_t5 30
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#define regnum_t6 31
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.macro retirq
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custom0 0,0,0,2
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.endm
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#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
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.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
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.macro maskirq rd rs
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custom0 \rd,\rs,0,3
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.endm
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#define picorv32_getq_insn(_rd, _qs) \
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r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
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.macro waitirq rd
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custom0 \rd,0,0,4
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.endm
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#define picorv32_setq_insn(_qd, _rs) \
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r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
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.macro timer rd rs
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custom0 \rd,\rs,0,5
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.endm
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#define picorv32_retirq_insn() \
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r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
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#define picorv32_maskirq_insn(_rd, _rs) \
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r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
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#define picorv32_waitirq_insn(_rd) \
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r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
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#define picorv32_timer_insn(_rd, _rs) \
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r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
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@ -34,8 +34,8 @@
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reset_vec:
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// no more than 16 bytes here !
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waitirq zero
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maskirq zero, zero
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picorv32_waitirq_insn(zero)
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picorv32_maskirq_insn(zero, zero)
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j start
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@ -48,19 +48,19 @@ irq_vec:
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#ifdef ENABLE_QREGS
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setq q2, x1
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setq q3, x2
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picorv32_setq_insn(q2, x1)
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picorv32_setq_insn(q3, x2)
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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getq x2, q0
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picorv32_getq_insn(x2, q0)
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sw x2, 0*4(x1)
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getq x2, q2
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picorv32_getq_insn(x2, q2)
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sw x2, 1*4(x1)
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getq x2, q3
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picorv32_getq_insn(x2, q3)
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sw x2, 2*4(x1)
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#ifdef ENABLE_FASTIRQ
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@ -180,7 +180,7 @@ irq_vec:
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// arg1 = interrupt type
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#ifdef ENABLE_QREGS
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getq a1, q1
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picorv32_getq_insn(a1, q1)
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#else
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addi a1, tp, 0
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#endif
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@ -196,13 +196,13 @@ irq_vec:
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addi x1, a0, 0
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lw x2, 0*4(x1)
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setq q0, x2
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picorv32_setq_insn(q0, x2)
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lw x2, 1*4(x1)
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setq q1, x2
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picorv32_setq_insn(q1, x2)
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lw x2, 2*4(x1)
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setq q2, x2
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picorv32_setq_insn(q2, x2)
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#ifdef ENABLE_FASTIRQ
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lw x5, 5*4(x1)
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lw x31, 31*4(x1)
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#endif
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getq x1, q1
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getq x2, q2
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picorv32_getq_insn(x1, q1)
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picorv32_getq_insn(x2, q2)
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#else // ENABLE_QREGS
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@ -319,7 +319,7 @@ irq_vec:
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#endif // ENABLE_QREGS
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retirq
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picorv32_retirq_insn()
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#ifndef ENABLE_QREGS
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.balign 0x200
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@ -378,7 +378,7 @@ start:
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# define TEST(n) \
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.global n; \
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addi x1, zero, 1000; \
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timer zero, x1; \
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picorv32_timer_insn(zero, x1); \
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jal zero,n; \
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.global n ## _ret; \
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n ## _ret:
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