Refine memory interface. Change start addr from 10000 to 0.
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parent
780c18e008
commit
f6b14b047b
1
Makefile
1
Makefile
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@ -85,6 +85,7 @@ build/dhry.hex: build/dhry.elf
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build/dhry.elf: $(DHRY_OBJS)
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$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) -Wl,-Bstatic,-T,firmware/riscv.ld,-Map,build/dhry.map,--strip-debug -o $@ $(DHRY_OBJS) -lgcc -lc
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$(TOOLCHAIN_PREFIX)objdump -S $@ > build/dhry.dis
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chmod -x $@
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build/dhry_1.o: dhrystone/dhry_1.c
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@ -10,7 +10,7 @@ OUTPUT_ARCH(riscv)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00010000;
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. = 0x00000000;
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.text :
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{
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*(.text)
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@ -15,7 +15,7 @@ MEMORY {
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SECTIONS {
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.memory : {
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. = 0x10000;
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. = 0x00000;
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start*(.text);
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*(.text);
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*(*);
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75
picorv32.v
75
picorv32.v
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@ -39,13 +39,7 @@ module picorv32 #(
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input resetn,
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output reg trap,
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output reg mem_valid,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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input [31:0] mem_la_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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@ -87,11 +81,11 @@ module picorv32 #(
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assign mem_la_addr = (mem_do_prefetch || mem_do_r_inst) ? {next_pc[31:2], 2'b00} : {reg_op1[31:2], 2'b00};
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wire [31:0] mem_rdata_latched;
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assign mem_rdata_latched = mem_xfer ? mem_rdata : mem_rdata_q;
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assign mem_rdata_latched = mem_xfer ? mem_la_rdata : mem_rdata_q;
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always @(posedge clk) begin
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if (mem_xfer) begin
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mem_rdata_q <= mem_rdata;
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mem_rdata_q <= mem_la_rdata;
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end
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end
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@ -101,24 +95,24 @@ module picorv32 #(
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0: begin
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mem_la_wdata = reg_op2;
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mem_la_wstrb = 4'b1111;
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mem_rdata_word = mem_rdata;
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mem_rdata_word = mem_la_rdata;
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end
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1: begin
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mem_la_wdata = {2{reg_op2[15:0]}};
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mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
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case (reg_op1[1])
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1'b0: mem_rdata_word = {16'b0, mem_rdata[15:0]};
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1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
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1'b0: mem_rdata_word = {16'b0, mem_la_rdata[15:0]};
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1'b1: mem_rdata_word = {16'b0, mem_la_rdata[31:16]};
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endcase
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end
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2: begin
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mem_la_wdata = {4{reg_op2[7:0]}};
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mem_la_wstrb = 4'b0001 << reg_op1[1:0];
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case (reg_op1[1:0])
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2'b00: mem_rdata_word = {24'b0, mem_rdata[7:0]};
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2'b01: mem_rdata_word = {24'b0, mem_rdata[15:8]};
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2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
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2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
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2'b00: mem_rdata_word = {24'b0, mem_la_rdata[7:0]};
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2'b01: mem_rdata_word = {24'b0, mem_la_rdata[15:8]};
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2'b10: mem_rdata_word = {24'b0, mem_la_rdata[23:16]};
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2'b11: mem_rdata_word = {24'b0, mem_la_rdata[31:24]};
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endcase
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end
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endcase
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@ -135,14 +129,9 @@ module picorv32 #(
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.resetn(resetn),
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.trap(trap),
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.mem_valid(mem_valid),
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.mem_ready(mem_ready),
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.mem_xfer(mem_xfer),
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.mem_addr (mem_addr),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata),
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.mem_la_rdata(mem_la_rdata),
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.mem_la_read (mem_la_read),
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.mem_la_write(mem_la_write),
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@ -1077,23 +1066,16 @@ module picorv32_memory (
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input resetn,
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input trap,
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output reg mem_valid,
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input mem_ready,
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output reg mem_xfer,
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output reg [31:0] mem_addr,
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output reg [31:0] mem_wdata,
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output reg [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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output mem_la_write,
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input [31:0] mem_la_addr,
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input [31:0] mem_la_wdata,
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input [31:0] mem_la_rdata,
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input [ 3:0] mem_la_wstrb,
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input mem_do_prefetch,
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input mem_do_r_inst,
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input mem_do_rdata,
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@ -1110,15 +1092,9 @@ module picorv32_memory (
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reg [1:0] mem_state;
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reg last_mem_valid;
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reg [15:0] mem_16bit_buffer;
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reg mem_instr;
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assign mem_xfer = mem_valid && mem_ready;
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wire mem_busy = |{mem_do_prefetch, mem_do_r_inst, mem_do_rdata, mem_do_wdata};
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assign mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_r_inst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_r_inst));
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assign mem_la_write = resetn && !mem_state && mem_do_wdata;
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assign mem_la_read = resetn && ((!mem_state && (mem_do_r_inst || mem_do_prefetch || mem_do_rdata)));
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@ -1126,7 +1102,7 @@ module picorv32_memory (
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if (!resetn) begin
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last_mem_valid <= 0;
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end else begin
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if (!last_mem_valid) last_mem_valid <= mem_valid && !mem_ready;
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if (!last_mem_valid) last_mem_valid <= 0;
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end
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end
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@ -1145,56 +1121,45 @@ module picorv32_memory (
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`assert(!(mem_do_prefetch || mem_do_r_inst || mem_do_rdata));
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if (mem_state == 2 || mem_state == 3)
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`assert(mem_valid || mem_do_prefetch);
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`assert(mem_xfer || mem_do_prefetch);
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end
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end
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always @(posedge clk) begin
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if (!resetn || trap) begin
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if (!resetn) mem_state <= 0;
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if (!resetn || mem_ready) mem_valid <= 0;
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mem_xfer <= 0;
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end else begin
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if (mem_la_read || mem_la_write) begin
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mem_addr <= mem_la_addr;
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mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
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end
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if (mem_la_write) begin
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mem_wdata <= mem_la_wdata;
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end
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case (mem_state)
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0: begin
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if (mem_do_prefetch || mem_do_r_inst || mem_do_rdata) begin
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mem_valid <= 1;
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mem_xfer <= 1;
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mem_instr <= mem_do_prefetch || mem_do_r_inst;
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mem_wstrb <= 0;
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mem_state <= 1;
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end
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if (mem_do_wdata) begin
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mem_valid <= 1;
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mem_xfer <= 1;
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mem_instr <= 0;
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mem_state <= 2;
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end
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end
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1: begin
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`assert(mem_wstrb == 0);
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`assert(mem_do_prefetch || mem_do_r_inst || mem_do_rdata);
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`assert(mem_valid == 1);
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`assert(mem_xfer == 1);
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`assert(mem_instr == (mem_do_prefetch || mem_do_r_inst));
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if (mem_xfer) begin
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mem_valid <= 0;
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mem_xfer <= 0;
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mem_state <= mem_do_r_inst || mem_do_rdata ? 0 : 3;
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end
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end
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2: begin
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`assert(mem_wstrb != 0);
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`assert(mem_do_wdata);
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if (mem_xfer) begin
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mem_valid <= 0;
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mem_xfer <= 0;
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mem_state <= 0;
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end
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end
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3: begin
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`assert(mem_wstrb == 0);
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`assert(mem_do_prefetch);
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if (mem_do_r_inst) begin
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mem_state <= 0;
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@ -60,17 +60,13 @@ module picorv32_wb #(
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input rst,
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input clk
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);
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wire mem_valid;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [ 3:0] mem_wstrb;
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reg mem_ready;
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reg [31:0] mem_rdata;
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wire mem_la_read;
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wire mem_la_write;
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wire [31:0] mem_la_addr;
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wire [31:0] mem_la_wdata;
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reg [31:0] mem_la_rdata;
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wire [ 3:0] mem_la_wstrb;
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wire resetn;
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@ -79,32 +75,24 @@ module picorv32_wb #(
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assign resetn = ~rst;
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picorv32 #(
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.PROGADDR_RESET(32'h0001_0000),
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.STACKADDR(32'h0001_0000)
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.PROGADDR_RESET(32'h0000_0000),
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.STACKADDR(32'h0004_0000)
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) picorv32_core (
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.clk (clk),
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.resetn(resetn),
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.trap (trap),
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.mem_valid (mem_valid),
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.mem_ready (mem_ready),
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.mem_addr (mem_addr),
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.mem_wdata (mem_wdata),
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.mem_wstrb (mem_wstrb),
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.mem_rdata (mem_rdata),
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.mem_la_read (mem_la_read),
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_rdata(mem_la_rdata),
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.mem_la_wstrb(mem_la_wstrb)
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);
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reg [7:0] memory[0:256*1024-1];
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assign mem_ready = 1;
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integer fconsole, fif;
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initial begin
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fconsole = $fopen("console.log", "w");
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@ -112,10 +100,10 @@ module picorv32_wb #(
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end
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always @(posedge clk) begin
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mem_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
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mem_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
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mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
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mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
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mem_la_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
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mem_la_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
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mem_la_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
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mem_la_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
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if (mem_la_write) begin
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case (mem_la_addr)
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32'h1000_0000: begin
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