Improvements in scripts/torture/

This commit is contained in:
Clifford Wolf 2016-04-09 14:09:22 +02:00
parent 649faca27e
commit f7435eca96
3 changed files with 23 additions and 1 deletions

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@ -18,7 +18,9 @@ riscv-fesvr/build.ok:
riscv-isa-sim/build.ok: riscv-fesvr/build.ok riscv-isa-sim/build.ok: riscv-fesvr/build.ok
rm -rf riscv-isa-sim rm -rf riscv-isa-sim
git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim
cd riscv-isa-sim && git checkout 10ae74e && patch -p1 < ../riscv-isa-sim-sbreak.diff cd riscv-isa-sim && git checkout 10ae74e
cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-sbreak.diff
cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-notrap.diff
cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok +cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok

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@ -0,0 +1,16 @@
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 3b834c5..e112029 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -201,9 +201,10 @@ void processor_t::set_privilege(reg_t prv)
void processor_t::take_trap(trap_t& t, reg_t epc)
{
- if (debug)
+ // if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
+ exit(1);
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();

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@ -48,6 +48,10 @@ module testbench (
repeat (10) @(posedge clk); repeat (10) @(posedge clk);
resetn <= 1; resetn <= 1;
repeat (100000) @(posedge clk);
$display("FAILED: Timeout!");
$finish;
end end
always @(posedge clk) begin always @(posedge clk) begin