From f79c8344fe4d28bc9dce3952fffb7867ff242904 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 23 Oct 2016 14:32:26 +0200 Subject: [PATCH] Added scripts/tomthumbtestgen --- scripts/tomthumbtestgen/.gitignore | 4 ++ scripts/tomthumbtestgen/README | 7 +++ scripts/tomthumbtestgen/run.sh | 29 ++++++++++ scripts/tomthumbtestgen/sections.lds | 7 +++ scripts/tomthumbtestgen/start.S | 57 ++++++++++++++++++++ scripts/tomthumbtestgen/testbench.v | 79 ++++++++++++++++++++++++++++ 6 files changed, 183 insertions(+) create mode 100644 scripts/tomthumbtestgen/.gitignore create mode 100644 scripts/tomthumbtestgen/README create mode 100644 scripts/tomthumbtestgen/run.sh create mode 100644 scripts/tomthumbtestgen/sections.lds create mode 100644 scripts/tomthumbtestgen/start.S create mode 100644 scripts/tomthumbtestgen/testbench.v diff --git a/scripts/tomthumbtestgen/.gitignore b/scripts/tomthumbtestgen/.gitignore new file mode 100644 index 0000000..0f06936 --- /dev/null +++ b/scripts/tomthumbtestgen/.gitignore @@ -0,0 +1,4 @@ +testbench +testgen.tgz +testgen +tests diff --git a/scripts/tomthumbtestgen/README b/scripts/tomthumbtestgen/README new file mode 100644 index 0000000..4e12ba8 --- /dev/null +++ b/scripts/tomthumbtestgen/README @@ -0,0 +1,7 @@ + +Testing PicoRV32 using the test case generator from +the Tom Thumb RISC-V CPU project: + +https://github.com/maikmerten/riscv-tomthumb +https://github.com/maikmerten/riscv-tomthumb-testgen + diff --git a/scripts/tomthumbtestgen/run.sh b/scripts/tomthumbtestgen/run.sh new file mode 100644 index 0000000..e9c1fe5 --- /dev/null +++ b/scripts/tomthumbtestgen/run.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +set -ex + +if [ ! -f testgen.tgz ]; then + rm -f testgen.tgz.part + wget -O testgen.tgz.part http://maikmerten.de/testgen.tgz + mv testgen.tgz.part testgen.tgz +fi + +rm -rf tests testgen/ +tar xvzf testgen.tgz + +iverilog -o testbench -s testbench testbench.v ../../picorv32.v + +mkdir -p tests +for i in {0..999}; do + fn="tests/test_`printf '%03d' $i`" + + { + cat start.S + java -jar testgen/tomthumb-testgen-1.0-SNAPSHOT.jar + } > $fn.s + + riscv32-unknown-elf-gcc -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o $fn.elf $fn.s + riscv32-unknown-elf-objcopy -O binary $fn.elf $fn.bin + python3 ../../firmware/makehex.py $fn.bin 16384 > $fn.hex + vvp -N ./testbench +hex=tests/test_000.hex +done diff --git a/scripts/tomthumbtestgen/sections.lds b/scripts/tomthumbtestgen/sections.lds new file mode 100644 index 0000000..8962f5c --- /dev/null +++ b/scripts/tomthumbtestgen/sections.lds @@ -0,0 +1,7 @@ +SECTIONS { + .memory : { + . = 0; + *(.text); + *(*); + } +} diff --git a/scripts/tomthumbtestgen/start.S b/scripts/tomthumbtestgen/start.S new file mode 100644 index 0000000..541c8a4 --- /dev/null +++ b/scripts/tomthumbtestgen/start.S @@ -0,0 +1,57 @@ +.section .text.start +.global testcollection + +/* zero-initialize all registers */ +addi x1, zero, 0 +addi x2, zero, 0 +addi x3, zero, 0 +addi x4, zero, 0 +addi x5, zero, 0 +addi x6, zero, 0 +addi x7, zero, 0 +addi x8, zero, 0 +addi x9, zero, 0 +addi x10, zero, 0 +addi x11, zero, 0 +addi x12, zero, 0 +addi x13, zero, 0 +addi x14, zero, 0 +addi x15, zero, 0 +addi x16, zero, 0 +addi x17, zero, 0 +addi x18, zero, 0 +addi x19, zero, 0 +addi x20, zero, 0 +addi x21, zero, 0 +addi x22, zero, 0 +addi x23, zero, 0 +addi x24, zero, 0 +addi x25, zero, 0 +addi x26, zero, 0 +addi x27, zero, 0 +addi x28, zero, 0 +addi x29, zero, 0 +addi x30, zero, 0 +addi x31, zero, 0 + +/* set stack pointer */ +lui sp, %hi(64*1024) +addi sp, sp, %lo(64*1024) + +/* push zeros on the stack for argc and argv */ +/* (stack is aligned to 16 bytes in riscv calling convention) */ +addi sp,sp,-16 +sw zero,0(sp) +sw zero,4(sp) +sw zero,8(sp) +sw zero,12(sp) + +/* call test */ +call testcollection + +/* write test results */ +lui x1, %hi(0x10000000) +addi x1, x1, %lo(0x10000000) +sw x5, 0(x1) + +ebreak diff --git a/scripts/tomthumbtestgen/testbench.v b/scripts/tomthumbtestgen/testbench.v new file mode 100644 index 0000000..169700e --- /dev/null +++ b/scripts/tomthumbtestgen/testbench.v @@ -0,0 +1,79 @@ +`timescale 1 ns / 1 ps + +module testbench; + reg clk = 1; + reg resetn = 0; + wire trap; + + always #5 clk = ~clk; + + initial begin + repeat (100) @(posedge clk); + resetn <= 1; + end + + wire mem_valid; + wire mem_instr; + reg mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + reg [31:0] mem_rdata; + + picorv32 #( + ) uut ( + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + reg [31:0] memory [0:16*1024-1]; + reg [1023:0] hex_filename; + + initial begin + if ($value$plusargs("hex=%s", hex_filename)) + $readmemh(hex_filename, memory); + end + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + end + + always @(posedge clk) begin + if (resetn && trap) begin + repeat (10) @(posedge clk); + $display("TRAP"); + $stop; + end + end + + always @(posedge clk) begin + mem_ready <= 0; + if (mem_valid && !mem_ready) begin + mem_ready <= 1; + if (mem_addr == 32'h 1000_0000) begin + if (mem_wdata != -32'd1) begin + $display("Failed test case: %d", mem_wdata); + $stop; + end else begin + $display("OK."); + $finish; + end + end else begin + mem_rdata <= memory[mem_addr >> 2]; + if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; + if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; + if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; + if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; + end + end + end +endmodule