Minor fixes in scripts/icestorm/
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288a043aca
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@ -18,11 +18,11 @@ firmware.hex: firmware.bin
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synth.blif: example.v ../../picorv32.v firmware.hex
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synth.blif: example.v ../../picorv32.v firmware.hex
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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example.txt: synth.blif
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example.asc: synth.blif
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arachne-pnr -d 8k -o example.txt -p example.pcf synth.blif
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arachne-pnr -d 8k -o example.asc -p example.pcf synth.blif
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example.bin: example.txt
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example.bin: example.asc
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icepack example.txt example.bin
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icepack example.asc example.bin
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example_tb.vvp: example_tb.v example.v firmware.hex
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example_tb.vvp: example_tb.v example.v firmware.hex
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iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
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iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
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@ -44,8 +44,8 @@ synth_sim: synth_tb.vvp
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synth_sim_vcd: synth_tb.vvp
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synth_sim_vcd: synth_tb.vvp
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vvp -N synth_tb.vvp +vcd
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vvp -N synth_tb.vvp +vcd
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route.v: example.txt
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route.v: example.asc
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icebox_vlog -L -n top -sp example.pcf example.txt > route.v
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icebox_vlog -L -n top -sp example.pcf example.asc > route.v
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route_tb.vvp: example_tb.v route.v
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route_tb.vvp: example_tb.v route.v
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iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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@ -65,7 +65,7 @@ view:
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clean:
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clean:
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f synth.log synth.v synth.blif route.v example.txt example.bin
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rm -f synth.log synth.v synth.blif route.v example.asc example.bin
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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.PHONY: all prog_sram view clean
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.PHONY: all prog_sram view clean
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@ -1,12 +1,12 @@
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`timescale 1 ns / 1 ps
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`timescale 1 ns / 1 ps
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module testbench;
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module testbench;
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reg clk_pin = 1;
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reg clk = 1;
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always #5 clk_pin = ~clk_pin;
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always #5 clk = ~clk;
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wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;
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wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;
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top uut (
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top uut (
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.clk_pin(clk_pin),
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.clk(clk),
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.LED0(LED0),
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.LED0(LED0),
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.LED1(LED1),
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.LED1(LED1),
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.LED2(LED2),
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.LED2(LED2),
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@ -24,7 +24,7 @@ module testbench;
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end
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end
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$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
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$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
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repeat (10000) @(posedge clk_pin);
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repeat (10000) @(posedge clk);
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$finish;
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$finish;
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end
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end
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endmodule
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endmodule
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