`timescale 1 ns / 1 ps

module picorv32_wrapper #(
    parameter VERBOSE = 0
) (
    input clk,
    input rst,
    output trap,
    input [1024:0] hex_file
);
  wire exit;

  reg [15:0] count_cycle = 0;
  always @(posedge clk) count_cycle <= !rst ? count_cycle + 1 : 0;

  wire [31:0] wb_m2s_adr;
  wire [31:0] wb_m2s_dat;
  wire [3:0] wb_m2s_sel;
  wire wb_m2s_we;
  wire wb_m2s_cyc;
  wire wb_m2s_stb;
  wire [31:0] wb_s2m_dat;
  wire wb_s2m_ack;

  picorv32_wb #() uut (
      .trap(trap),
      .exit(exit),

      .clk(clk),
      .rst(rst)
  );

  initial begin
    $readmemh(hex_file, uut.memory);
    $display("HEX File : %s", hex_file);
  end

  integer cycle_counter;
  always @(posedge clk) begin
    cycle_counter <= !rst ? cycle_counter + 1 : 0;
    if (!rst && trap) begin
      $display("TRAP after %1d clock cycles", cycle_counter);
      if (exit) begin
        $display("ALL TESTS PASSED.");
        $finish;
      end else begin
        $display("ERROR!");
        if ($test$plusargs("noerror")) $finish;
        $stop;
      end
    end
  end
endmodule

module picorv32_wb #(
) (
    output trap,
    output reg exit,

    input rst,
    input clk
);
  wire        mem_valid;
  wire [31:0] mem_addr;
  wire [31:0] mem_wdata;
  wire [ 3:0] mem_wstrb;
  reg         mem_ready;
  reg  [31:0] mem_rdata;

  wire        mem_la_read;
  wire        mem_la_write;
  wire [31:0] mem_la_addr;
  wire [31:0] mem_la_wdata;
  wire [ 3:0] mem_la_wstrb;

  wire        resetn;
  initial exit = 0;

  assign resetn = ~rst;

  picorv32 #(
      .PROGADDR_RESET(32'h0001_0000),
      .STACKADDR(32'h0001_0000)
  ) picorv32_core (
      .clk   (clk),
      .resetn(resetn),
      .trap  (trap),

      .mem_valid   (mem_valid),
      .mem_ready   (mem_ready),
      .mem_addr    (mem_addr),
      .mem_wdata   (mem_wdata),
      .mem_wstrb   (mem_wstrb),
      .mem_rdata   (mem_rdata),
      .mem_la_read (mem_la_read),
      .mem_la_write(mem_la_write),
      .mem_la_addr (mem_la_addr),
      .mem_la_wdata(mem_la_wdata),
      .mem_la_wstrb(mem_la_wstrb)

  );


  reg [7:0] memory[0:256*1024-1];

  assign mem_ready = 1;

  integer fconsole, fif;
  initial begin
    fconsole = $fopen("console.log", "w");
    fif = $fopen("if.log", "w");
  end

  always @(posedge clk) begin
    mem_rdata[7:0]   <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
    mem_rdata[15:8]  <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
    mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
    mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
    if (mem_la_write) begin
      case (mem_la_addr)
        32'h1000_0000: begin
          $fwrite(fconsole, "%c", mem_la_wdata);
        end
        32'h2000_0000: begin
          if (mem_la_wdata[31:0] == 123456789) exit = 1;
        end
        default: begin
          if (mem_la_wstrb[0]) memory[mem_la_addr+0] <= mem_la_wdata[7:0];
          if (mem_la_wstrb[1]) memory[mem_la_addr+1] <= mem_la_wdata[15:8];
          if (mem_la_wstrb[2]) memory[mem_la_addr+2] <= mem_la_wdata[23:16];
          if (mem_la_wstrb[3]) memory[mem_la_addr+3] <= mem_la_wdata[31:24];
        end
      endcase
    end
  end

  // always @(posedge clk) begin
  //   if (fetch_next) begin
  //     if (&dbg_insn_opcode[1:0])
  //       $fwrite(
  //           fif,
  //           "DECODE: 0x%08x 0x%08x %-0s\n",
  //           dbg_insn_addr,
  //           dbg_insn_opcode,
  //           dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
  //       );
  //     else
  //       $fwrite(
  //           fif,
  //           "DECODE: 0x%08x     0x%04x %-0s\n",
  //           dbg_insn_addr,
  //           dbg_insn_opcode[15:0],
  //           dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
  //       );
  //   end
  // end

endmodule