`timescale 1 ns / 1 ps

module picorv32_wrapper #(
    parameter VERBOSE = 0
) (
    input wb_clk,
    input wb_rst,
    output trap,
    output trace_valid,
    output [35:0] trace_data,
    input [1024:0] hex_file
);
  wire exit;
  reg [31:0] irq = 0;
  wire mem_instr;

  reg [15:0] count_cycle = 0;
  always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;

  always @* begin
    irq = 0;
    irq[4] = &count_cycle[12:0];
    irq[5] = &count_cycle[15:0];
  end

  wire [31:0] wb_m2s_adr;
  wire [31:0] wb_m2s_dat;
  wire [3:0] wb_m2s_sel;
  wire wb_m2s_we;
  wire wb_m2s_cyc;
  wire wb_m2s_stb;
  wire [31:0] wb_s2m_dat;
  wire wb_s2m_ack;

  picorv32_wb #() uut (
      .trap(trap),
      .exit(exit),
      .irq(irq),
      .trace_valid(trace_valid),
      .trace_data(trace_data),
      .mem_instr(mem_instr),

      .wb_clk_i(wb_clk),
      .wb_rst_i(wb_rst)
  );

  initial begin
    $readmemh(hex_file, uut.memory);
    $display("HEX File : %s", hex_file);
  end

  integer cycle_counter;
  always @(posedge wb_clk) begin
    cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
    if (!wb_rst && trap) begin
      $display("TRAP after %1d clock cycles", cycle_counter);
      if (exit) begin
        $display("ALL TESTS PASSED.");
        $finish;
      end else begin
        $display("ERROR!");
        if ($test$plusargs("noerror")) $finish;
        $stop;
      end
    end
  end
endmodule

module picorv32_wb #(
) (
    output trap,
    output reg exit,

    // Wishbone interfaces
    input wb_rst_i,
    input wb_clk_i,

    // IRQ interface
    input  [31:0] irq,
    output [31:0] eoi,

    // Trace Interface
    output        trace_valid,
    output [35:0] trace_data,

    output mem_instr
);
  wire        mem_valid;
  wire [31:0] mem_addr;
  wire [31:0] mem_wdata;
  wire [ 3:0] mem_wstrb;
  reg         mem_ready;
  reg  [31:0] mem_rdata;

  wire        mem_la_read;
  wire        mem_la_write;
  wire [31:0] mem_la_addr;
  wire [31:0] mem_la_wdata;
  wire [ 3:0] mem_la_wstrb;


  wire        clk;
  wire        resetn;
  initial exit = 0;

  assign clk = wb_clk_i;
  assign resetn = ~wb_rst_i;

  picorv32 #(
      .ENABLE_TRACE(1),
      .MASKED_IRQ(32'h0000_0000),
      .LATCHED_IRQ(32'hffff_ffff),
      .PROGADDR_RESET(32'h0001_0000),
      .PROGADDR_IRQ(32'h0001_0010),
      .STACKADDR(32'h0001_0000)
  ) picorv32_core (
      .clk   (clk),
      .resetn(resetn),
      .trap  (trap),

      .mem_valid   (mem_valid),
      .mem_instr   (mem_instr),
      .mem_ready   (mem_ready),
      .mem_addr    (mem_addr),
      .mem_wdata   (mem_wdata),
      .mem_wstrb   (mem_wstrb),
      .mem_rdata   (mem_rdata),
      .mem_la_read (mem_la_read),
      .mem_la_write(mem_la_write),
      .mem_la_addr (mem_la_addr),
      .mem_la_wdata(mem_la_wdata),
      .mem_la_wstrb(mem_la_wstrb),
      .irq         (irq),
      .eoi         (eoi),

      .trace_valid(trace_valid),
      .trace_data (trace_data)
  );


  reg [7:0] memory[0:256*1024-1];

  assign mem_ready = 1;

  always @(posedge clk) begin
    mem_rdata[7:0]   <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
    mem_rdata[15:8]  <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
    mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
    mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
    if (mem_la_write) begin
      case (mem_la_addr)
        32'h1000_0000: begin
          $write("%c", mem_la_wdata);
          $fflush();
        end
        32'h2000_0000: begin
          if (mem_la_wdata[31:0] == 123456789) exit = 1;
        end
        default: begin
          if (mem_la_wstrb[0]) memory[mem_la_addr+0] <= mem_la_wdata[7:0];
          if (mem_la_wstrb[1]) memory[mem_la_addr+1] <= mem_la_wdata[15:8];
          if (mem_la_wstrb[2]) memory[mem_la_addr+2] <= mem_la_wdata[23:16];
          if (mem_la_wstrb[3]) memory[mem_la_addr+3] <= mem_la_wdata[31:24];
        end
      endcase
    end
  end
endmodule