read_verilog main.v
read_verilog ../../picorv32.v
rename main main_a
hierarchy -top main_a
proc
opt
memory -nordff -nomap
flatten
opt
write_smt2 -bv -mem -regs sync_a.smt2
design -reset

read_verilog main.v
read_verilog ../../picorv32.v
rename main main_b
chparam -set ENABLE_COUNTERS 1 \
        -set CATCH_MISALIGN  0 \
	-set CATCH_ILLINSN   0 \
	-set ENABLE_MUL      1 \
	-set ENABLE_IRQ      0 main_b
hierarchy -top main_b
proc
opt
memory -nordff -nomap
flatten
opt
write_smt2 -bv -mem -regs sync_b.smt2
design -reset