147 lines
3.4 KiB
Verilog
147 lines
3.4 KiB
Verilog
`timescale 1 ns / 1 ps
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module picorv32_wrapper #(
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parameter VERBOSE = 0
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) (
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input clk,
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input rst,
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output trap,
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input [1024:0] hex_file
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);
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wire exit;
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reg [15:0] count_cycle = 0;
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always @(posedge clk) count_cycle <= !rst ? count_cycle + 1 : 0;
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wire [31:0] wb_m2s_adr;
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wire [31:0] wb_m2s_dat;
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wire [3:0] wb_m2s_sel;
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wire wb_m2s_we;
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wire wb_m2s_cyc;
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wire wb_m2s_stb;
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wire [31:0] wb_s2m_dat;
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wire wb_s2m_ack;
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picorv32_wb #() uut (
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.trap(trap),
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.exit(exit),
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.clk(clk),
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.rst(rst)
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);
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initial begin
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$readmemh(hex_file, uut.memory);
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$display("HEX File : %s", hex_file);
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end
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integer cycle_counter;
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always @(posedge clk) begin
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cycle_counter <= !rst ? cycle_counter + 1 : 0;
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if (!rst && trap) begin
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$display("TRAP after %1d clock cycles", cycle_counter);
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if (exit) begin
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$display("ALL TESTS PASSED.");
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$finish;
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end else begin
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$display("ERROR!");
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if ($test$plusargs("noerror")) $finish;
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$stop;
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end
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end
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end
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endmodule
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module picorv32_wb #(
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) (
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output trap,
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output reg exit,
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input rst,
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input clk
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);
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wire mem_la_read;
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wire mem_la_write;
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wire [31:0] mem_la_addr;
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wire [31:0] mem_la_wdata;
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reg [31:0] mem_la_rdata;
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wire [ 3:0] mem_la_wstrb;
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wire resetn;
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initial exit = 0;
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assign resetn = ~rst;
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picorv32 #(
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.PROGADDR_RESET(32'h0000_0000),
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.STACKADDR(32'h0004_0000)
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) picorv32_core (
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.clk (clk),
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.resetn(resetn),
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.trap (trap),
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.mem_la_read (mem_la_read),
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_rdata(mem_la_rdata),
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.mem_la_wstrb(mem_la_wstrb)
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);
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reg [7:0] memory[0:256*1024-1];
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integer fconsole, fif;
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initial begin
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fconsole = $fopen("console.log", "w");
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fif = $fopen("if.log", "w");
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end
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always @(posedge clk) begin
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mem_la_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
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mem_la_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
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mem_la_rdata[23:16] <= mem_la_read ? memory[mem_la_addr+2] : 'bx;
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mem_la_rdata[31:24] <= mem_la_read ? memory[mem_la_addr+3] : 'bx;
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if (mem_la_write) begin
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case (mem_la_addr)
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32'h1000_0000: begin
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$fwrite(fconsole, "%c", mem_la_wdata);
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end
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32'h2000_0000: begin
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if (mem_la_wdata[31:0] == 123456789) exit = 1;
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end
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default: begin
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if (mem_la_wstrb[0]) memory[mem_la_addr+0] <= mem_la_wdata[7:0];
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if (mem_la_wstrb[1]) memory[mem_la_addr+1] <= mem_la_wdata[15:8];
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if (mem_la_wstrb[2]) memory[mem_la_addr+2] <= mem_la_wdata[23:16];
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if (mem_la_wstrb[3]) memory[mem_la_addr+3] <= mem_la_wdata[31:24];
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end
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endcase
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end
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end
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// always @(posedge clk) begin
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// if (fetch_next) begin
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// if (&dbg_insn_opcode[1:0])
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// $fwrite(
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// fif,
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// "DECODE: 0x%08x 0x%08x %-0s\n",
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// dbg_insn_addr,
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// dbg_insn_opcode,
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// dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
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// );
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// else
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// $fwrite(
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// fif,
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// "DECODE: 0x%08x 0x%04x %-0s\n",
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// dbg_insn_addr,
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// dbg_insn_opcode[15:0],
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// dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
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// );
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// end
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// end
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endmodule
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