101 lines
2.1 KiB
Verilog
101 lines
2.1 KiB
Verilog
`timescale 1 ns / 1 ps
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module testbench (
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`ifdef VERILATOR
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input clk
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`endif
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);
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`ifndef VERILATOR
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reg clk = 1;
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always #5 clk = ~clk;
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`endif
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reg resetn = 0;
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integer resetn_cnt = 0;
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wire trap;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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end
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always @(posedge clk) begin
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if (resetn_cnt < 100)
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resetn_cnt <= resetn_cnt + 1;
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else
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resetn <= 1;
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end
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wire mem_valid;
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wire mem_instr;
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wire mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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wire [31:0] mem_rdata;
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reg [31:0] x32 = 314159265;
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reg [31:0] next_x32;
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always @(posedge clk) begin
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if (resetn) begin
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next_x32 = x32;
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next_x32 = next_x32 ^ (next_x32 << 13);
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next_x32 = next_x32 ^ (next_x32 >> 17);
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next_x32 = next_x32 ^ (next_x32 << 5);
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x32 <= next_x32;
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end
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end
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picorv32 #(
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.COMPRESSED_ISA(1),
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.ENABLE_MUL(1),
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.ENABLE_DIV(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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reg [7:0] memory [0:4*1024*1024-1];
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initial $readmemh("test.hex", memory);
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assign mem_ready = x32[0] && mem_valid;
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assign mem_rdata[ 7: 0] = memory[mem_addr + 0];
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assign mem_rdata[15: 8] = memory[mem_addr + 1];
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assign mem_rdata[23:16] = memory[mem_addr + 2];
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assign mem_rdata[31:24] = memory[mem_addr + 3];
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always @(posedge clk) begin
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if (mem_valid && mem_ready) begin
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if (mem_wstrb && mem_addr == 'h10000000) begin
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$write("%c", mem_wdata[ 7: 0]);
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`ifndef VERILATOR
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$fflush;
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`endif
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end else begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end
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end
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end
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always @(posedge clk) begin
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if (resetn && trap) begin
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// repeat (10) @(posedge clk);
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// $display("TRAP");
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$finish;
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end
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end
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endmodule
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