102 lines
2.8 KiB
Verilog
102 lines
2.8 KiB
Verilog
`timescale 1 ns / 1 ps
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module system (
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input clk,
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input resetn,
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output trap,
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output reg [7:0] out_byte,
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output reg out_byte_en
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);
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// set this to 0 for better timing but less performance/MHz
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parameter FAST_MEMORY = 0;
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// 4096 32bit words = 16kB memory
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parameter MEM_SIZE = 4096;
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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wire mem_la_read;
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wire mem_la_write;
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wire [31:0] mem_la_addr;
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wire [31:0] mem_la_wdata;
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wire [3:0] mem_la_wstrb;
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picorv32 picorv32_core (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read (mem_la_read ),
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr ),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_wstrb(mem_la_wstrb)
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);
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reg [31:0] memory [0:MEM_SIZE-1];
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initial $readmemh("firmware.hex", memory);
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reg [31:0] m_read_data;
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reg m_read_en;
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generate if (FAST_MEMORY) begin
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always @(posedge clk) begin
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mem_ready <= 1;
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out_byte_en <= 0;
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mem_rdata <= memory[mem_la_addr >> 2];
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if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
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if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
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if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
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if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
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if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
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end
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else
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if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
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out_byte_en <= 1;
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out_byte <= mem_la_wdata;
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end
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end
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end else begin
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always @(posedge clk) begin
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m_read_en <= 0;
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mem_ready <= mem_valid && !mem_ready && m_read_en;
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m_read_data <= memory[mem_addr >> 2];
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mem_rdata <= m_read_data;
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out_byte_en <= 0;
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(* parallel_case *)
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case (1)
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mem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
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m_read_en <= 1;
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end
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mem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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mem_ready <= 1;
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end
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mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32'h1000_0000: begin
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out_byte_en <= 1;
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out_byte <= mem_wdata;
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mem_ready <= 1;
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end
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endcase
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end
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end endgenerate
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endmodule
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