39 lines
648 B
Verilog
39 lines
648 B
Verilog
`timescale 1 ns / 1 ps
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module system_tb;
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reg clk = 1;
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always #5 clk = ~clk;
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reg resetn = 0;
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("system.vcd");
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$dumpvars(0, system_tb);
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end
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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wire trap;
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wire [7:0] out_byte;
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wire out_byte_en;
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system uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.out_byte (out_byte ),
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.out_byte_en(out_byte_en)
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);
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always @(posedge clk) begin
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if (resetn && out_byte_en) begin
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$write("%c", out_byte);
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$fflush;
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end
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if (resetn && trap) begin
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$finish;
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end
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end
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endmodule
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