119 lines
3.9 KiB
Verilog
119 lines
3.9 KiB
Verilog
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module top (
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input clk, io_resetn,
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output io_trap,
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output io_mem_axi_awvalid,
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input io_mem_axi_awready,
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output [31:0] io_mem_axi_awaddr,
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output [ 2:0] io_mem_axi_awprot,
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output io_mem_axi_wvalid,
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input io_mem_axi_wready,
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output [31:0] io_mem_axi_wdata,
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output [ 3:0] io_mem_axi_wstrb,
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input io_mem_axi_bvalid,
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output io_mem_axi_bready,
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output io_mem_axi_arvalid,
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input io_mem_axi_arready,
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output [31:0] io_mem_axi_araddr,
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output [ 2:0] io_mem_axi_arprot,
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input io_mem_axi_rvalid,
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output io_mem_axi_rready,
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input [31:0] io_mem_axi_rdata,
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input [31:0] io_irq,
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output [31:0] io_eoi
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);
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wire resetn;
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wire trap;
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wire mem_axi_awvalid;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [3:0] mem_axi_wstrb;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [2:0] mem_axi_arprot;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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wire [31:0] mem_axi_rdata;
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wire [31:0] irq;
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wire [31:0] eoi;
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delay4 #( 1) delay_resetn (clk, io_resetn , resetn );
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delay4 #( 1) delay_trap (clk, trap , io_trap );
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delay4 #( 1) delay_mem_axi_awvalid (clk, mem_axi_awvalid, io_mem_axi_awvalid);
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delay4 #( 1) delay_mem_axi_awready (clk, io_mem_axi_awready, mem_axi_awready);
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delay4 #(32) delay_mem_axi_awaddr (clk, mem_axi_awaddr , io_mem_axi_awaddr );
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delay4 #( 3) delay_mem_axi_awprot (clk, mem_axi_awprot , io_mem_axi_awprot );
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delay4 #( 1) delay_mem_axi_wvalid (clk, mem_axi_wvalid , io_mem_axi_wvalid );
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delay4 #( 1) delay_mem_axi_wready (clk, io_mem_axi_wready , mem_axi_wready );
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delay4 #(32) delay_mem_axi_wdata (clk, mem_axi_wdata , io_mem_axi_wdata );
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delay4 #( 4) delay_mem_axi_wstrb (clk, mem_axi_wstrb , io_mem_axi_wstrb );
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delay4 #( 1) delay_mem_axi_bvalid (clk, io_mem_axi_bvalid , mem_axi_bvalid );
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delay4 #( 1) delay_mem_axi_bready (clk, mem_axi_bready , io_mem_axi_bready );
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delay4 #( 1) delay_mem_axi_arvalid (clk, mem_axi_arvalid, io_mem_axi_arvalid);
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delay4 #( 1) delay_mem_axi_arready (clk, io_mem_axi_arready, mem_axi_arready);
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delay4 #(32) delay_mem_axi_araddr (clk, mem_axi_araddr , io_mem_axi_araddr );
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delay4 #( 3) delay_mem_axi_arprot (clk, mem_axi_arprot , io_mem_axi_arprot );
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delay4 #( 1) delay_mem_axi_rvalid (clk, io_mem_axi_rvalid , mem_axi_rvalid );
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delay4 #( 1) delay_mem_axi_rready (clk, mem_axi_rready , io_mem_axi_rready );
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delay4 #(32) delay_mem_axi_rdata (clk, io_mem_axi_rdata , mem_axi_rdata );
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delay4 #(32) delay_irq (clk, io_irq , irq );
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delay4 #(32) delay_eoi (clk, eoi , io_eoi );
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picorv32_axi #(
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.TWO_CYCLE_ALU(1)
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_axi_awvalid(mem_axi_awvalid),
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.mem_axi_awready(mem_axi_awready),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid(mem_axi_arvalid),
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.mem_axi_arready(mem_axi_arready),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.irq (irq ),
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.eoi (eoi )
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);
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endmodule
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module delay4 #(
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parameter WIDTH = 1
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) (
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input clk,
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input [WIDTH-1:0] in,
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output reg [WIDTH-1:0] out
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);
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reg [WIDTH-1:0] q1, q2, q3;
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always @(posedge clk) begin
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q1 <= in;
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q2 <= q1;
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q3 <= q2;
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out <= q3;
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end
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endmodule
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