75 lines
2.1 KiB
Makefile
75 lines
2.1 KiB
Makefile
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TOOLCHAIN_PREFIX = riscv32-unknown-elf-
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all: example.bin
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firmware.elf: firmware.S firmware.c firmware.lds
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$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o firmware.elf firmware.S firmware.c \
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--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug -lgcc
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chmod -x firmware.elf
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firmware.bin: firmware.elf
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$(TOOLCHAIN_PREFIX)objcopy -O binary firmware.elf firmware.bin
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chmod -x firmware.bin
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firmware.hex: firmware.bin
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python3 ../../firmware/makehex.py firmware.bin 128 > firmware.hex
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synth.blif: example.v ../../picorv32.v firmware.hex
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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example.asc: synth.blif
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arachne-pnr -d 8k -o example.asc -p example.pcf synth.blif
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example.bin: example.asc
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icepack example.asc example.bin
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example_tb.vvp: example_tb.v example.v firmware.hex
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iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
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chmod -x example_tb.vvp
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example_sim: example_tb.vvp
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vvp -N example_tb.vvp
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example_sim_vcd: example_tb.vvp
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vvp -N example_tb.vvp +vcd
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synth_tb.vvp: example_tb.v synth.blif
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iverilog -o synth_tb.vvp -s testbench synth.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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chmod -x synth_tb.vvp
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synth_sim: synth_tb.vvp
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vvp -N synth_tb.vvp
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synth_sim_vcd: synth_tb.vvp
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vvp -N synth_tb.vvp +vcd
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route.v: example.asc
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icebox_vlog -L -n top -sp example.pcf example.asc > route.v
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route_tb.vvp: example_tb.v route.v
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iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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chmod -x route_tb.vvp
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route_sim: route_tb.vvp
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vvp -N route_tb.vvp
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route_sim_vcd: route_tb.vvp
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vvp -N route_tb.vvp +vcd
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prog_sram:
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iceprog -S example.bin
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view:
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gtkwave example.vcd example.gtkw
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clean:
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f synth.log synth.v synth.blif route.v example.asc example.bin
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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.PHONY: all prog_sram view clean
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.PHONY: example_sim synth_sim route_sim
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.PHONY: example_sim_vcd synth_sim_vcd route_sim_vcd
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