349 lines
7.2 KiB
Verilog
349 lines
7.2 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module spimemio (
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input clk, resetn,
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input valid,
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output ready,
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input [23:0] addr,
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output reg [31:0] rdata,
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output flash_csb,
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output flash_clk,
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output flash_io0_oe,
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output flash_io1_oe,
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output flash_io2_oe,
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output flash_io3_oe,
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output flash_io0_do,
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output flash_io1_do,
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output flash_io2_do,
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output flash_io3_do,
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input flash_io0_di,
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input flash_io1_di,
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input flash_io2_di,
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input flash_io3_di
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);
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reg xfer_resetn;
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reg din_valid;
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wire din_ready;
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reg [7:0] din_data;
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reg din_cont;
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reg din_qspi;
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reg din_ddr;
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reg din_rd;
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wire dout_valid;
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wire [7:0] dout_data;
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reg [23:0] buffer;
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reg [3:0] buffer_wen;
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reg [23:0] rd_addr;
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reg rd_valid;
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reg rd_wait;
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reg rd_inc;
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assign ready = valid && (addr == rd_addr) && rd_valid;
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wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;
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spimemio_xfer xfer (
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.clk (clk ),
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.resetn (xfer_resetn ),
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.din_valid (din_valid ),
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.din_ready (din_ready ),
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.din_data (din_data ),
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.din_cont (din_cont ),
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.din_qspi (din_qspi ),
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.din_ddr (din_ddr ),
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.din_rd (din_rd ),
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.dout_valid (dout_valid ),
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.dout_data (dout_data ),
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.flash_csb (flash_csb ),
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.flash_clk (flash_clk ),
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.flash_io0_oe (flash_io0_oe),
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.flash_io1_oe (flash_io1_oe),
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.flash_io2_oe (flash_io2_oe),
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.flash_io3_oe (flash_io3_oe),
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.flash_io0_do (flash_io0_do),
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.flash_io1_do (flash_io1_do),
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.flash_io2_do (flash_io2_do),
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.flash_io3_do (flash_io3_do),
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.flash_io0_di (flash_io0_di),
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.flash_io1_di (flash_io1_di),
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.flash_io2_di (flash_io2_di),
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.flash_io3_di (flash_io3_di)
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);
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reg [3:0] state;
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always @(posedge clk) begin
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xfer_resetn <= 1;
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din_valid <= 0;
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din_data <= 8'h 00;
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if (!resetn) begin
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state <= 0;
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xfer_resetn <= 0;
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rd_valid <= 0;
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din_cont <= 0;
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din_qspi <= 0;
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din_ddr <= 0;
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din_rd <= 0;
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end else begin
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if (dout_valid && buffer_wen[0]) buffer[ 7: 0] <= dout_data;
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if (dout_valid && buffer_wen[1]) buffer[15: 8] <= dout_data;
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if (dout_valid && buffer_wen[2]) buffer[23:16] <= dout_data;
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if (dout_valid && buffer_wen[3]) begin
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rdata <= {dout_data, buffer};
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rd_addr <= rd_inc ? rd_addr + 4 : addr;
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rd_valid <= 1;
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rd_wait <= rd_inc;
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rd_inc <= 1;
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end
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if (dout_valid && buffer_wen) begin
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buffer_wen <= 0;
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end
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if (valid)
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rd_wait <= 0;
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case (state)
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0: begin
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din_valid <= 1;
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din_data <= 8'h ff;
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if (din_ready)
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state <= 1;
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end
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1: begin
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if (dout_valid) begin
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xfer_resetn <= 0;
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state <= 2;
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end
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end
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2: begin
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din_valid <= 1;
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din_data <= 8'h ab;
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if (din_ready)
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state <= 3;
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end
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3: begin
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if (dout_valid) begin
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xfer_resetn <= 0;
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state <= 4;
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end
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end
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4: begin
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rd_inc <= 0;
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din_valid <= 1;
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din_data <= 8'h 03;
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if (din_ready)
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state <= 5;
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end
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5: begin
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if (valid && !ready) begin
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din_valid <= 1;
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din_data <= addr[23:16];
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if (din_ready)
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state <= 6;
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end
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end
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6: begin
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din_valid <= 1;
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din_data <= addr[15:8];
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if (din_ready)
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state <= 7;
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end
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7: begin
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din_valid <= 1;
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din_data <= addr[7:0];
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if (din_ready)
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state <= 8;
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end
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8: begin
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din_valid <= 1;
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din_data <= 8'h 00;
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if (din_ready) begin
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buffer_wen <= 4'b 0001;
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state <= 9;
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end
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end
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9: begin
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din_valid <= 1;
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din_data <= 8'h 00;
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if (din_ready) begin
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buffer_wen <= 4'b 0010;
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state <= 10;
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end
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end
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10: begin
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din_valid <= 1;
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din_data <= 8'h 00;
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if (din_ready) begin
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buffer_wen <= 4'b 0100;
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state <= 11;
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end
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end
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11: begin
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if (!rd_wait || valid) begin
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din_valid <= 1;
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din_data <= 8'h 00;
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if (din_ready) begin
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buffer_wen <= 4'b 1000;
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state <= 8;
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end
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end
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end
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endcase
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if (jump) begin
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rd_inc <= 0;
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rd_valid <= 0;
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xfer_resetn <= 0;
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state <= 4;
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end
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end
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end
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endmodule
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module spimemio_xfer (
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input clk, resetn,
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input din_valid,
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output din_ready,
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input [7:0] din_data,
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input din_cont,
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input din_qspi,
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input din_ddr,
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input din_rd,
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output dout_valid,
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output [7:0] dout_data,
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output reg flash_csb,
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output reg flash_clk,
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output reg flash_io0_oe,
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output reg flash_io1_oe,
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output reg flash_io2_oe,
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output reg flash_io3_oe,
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output reg flash_io0_do,
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output reg flash_io1_do,
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output reg flash_io2_do,
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output reg flash_io3_do,
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input flash_io0_di,
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input flash_io1_di,
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input flash_io2_di,
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input flash_io3_di
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);
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localparam [3:0] mode_spi = 0;
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reg [3:0] mode;
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reg [7:0] obuffer;
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reg [7:0] ibuffer;
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reg [3:0] count;
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reg xfer_cont;
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reg xfer_qspi;
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reg xfer_ddr;
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reg xfer_rd;
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reg [7:0] next_obuffer;
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reg [7:0] next_ibuffer;
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reg [3:0] next_count;
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reg fetch_next;
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reg last_fetch_next;
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assign din_ready = din_valid && resetn && fetch_next;
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assign dout_valid = fetch_next && !last_fetch_next;
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assign dout_data = ibuffer;
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always @* begin
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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flash_io0_do = 0;
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flash_io1_do = 0;
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flash_io2_do = 0;
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flash_io3_do = 0;
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next_obuffer = obuffer;
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next_ibuffer = ibuffer;
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next_count = count;
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fetch_next = 0;
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case (mode)
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mode_spi: begin
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flash_io0_oe = 1;
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flash_io0_do = obuffer[7];
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if (flash_clk) begin
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next_obuffer = {obuffer[6:0], 1'b 0};
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next_count = count - |count;
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end else begin
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next_ibuffer = {ibuffer[6:0], flash_io1_di};
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end
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fetch_next = (next_count == 0);
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end
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endcase
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end
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always @(posedge clk) begin
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if (!resetn) begin
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mode <= mode_spi;
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last_fetch_next <= 1;
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flash_csb <= 1;
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flash_clk <= 0;
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count <= 0;
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end else begin
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last_fetch_next <= fetch_next;
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if (count) begin
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flash_clk <= !flash_clk && !flash_csb;
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obuffer <= next_obuffer;
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ibuffer <= next_ibuffer;
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count <= next_count;
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end
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if (din_valid && din_ready) begin
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flash_csb <= 0;
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flash_clk <= 0;
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obuffer <= din_data;
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ibuffer <= 8'h 00;
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count <= 8;
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xfer_cont <= din_cont;
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xfer_qspi <= din_qspi;
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xfer_ddr <= din_ddr;
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xfer_rd <= din_rd;
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end
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end
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end
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endmodule
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