353 lines
7.0 KiB
Verilog
353 lines
7.0 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`timescale 1 ns / 1 ps
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//
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// Simple SPI flash simulation model
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//
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// This model samples io input signals 1ns before the SPI clock edge and
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// updates output signals 1ns after the SPI clock edge.
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//
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// Supported commands:
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// AB, B9, FF, 03, EB, ED
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//
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// Well written SPI flash data sheets:
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// Cypress S25FL064L http://www.cypress.com/file/316661/download
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// Cypress S25FL128L http://www.cypress.com/file/316171/download
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//
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module spiflash (
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input csb,
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input clk,
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inout io0, // MOSI
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inout io1, // MISO
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inout io2,
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inout io3
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);
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localparam verbose = 0;
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reg [7:0] buffer;
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integer bitcount = 0;
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integer bytecount = 0;
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integer dummycount = 0;
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reg [7:0] spi_cmd;
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reg [7:0] xip_cmd = 0;
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reg [23:0] spi_addr;
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reg [7:0] spi_in;
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reg [7:0] spi_out;
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reg spi_io_vld;
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reg powered_up = 0;
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localparam [3:0] mode_spi = 1;
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localparam [3:0] mode_qspi_rd = 2;
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localparam [3:0] mode_qspi_wr = 3;
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localparam [3:0] mode_qspi_ddr_rd = 4;
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localparam [3:0] mode_qspi_ddr_wr = 5;
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reg [3:0] mode = 0;
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reg [3:0] next_mode = 0;
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reg io0_oe = 0;
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reg io1_oe = 0;
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reg io2_oe = 0;
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reg io3_oe = 0;
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reg io0_dout = 0;
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reg io1_dout = 0;
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reg io2_dout = 0;
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reg io3_dout = 0;
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assign #1 io0 = io0_oe ? io0_dout : 1'bz;
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assign #1 io1 = io1_oe ? io1_dout : 1'bz;
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assign #1 io2 = io2_oe ? io2_dout : 1'bz;
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assign #1 io3 = io3_oe ? io3_dout : 1'bz;
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wire io0_delayed;
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wire io1_delayed;
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wire io2_delayed;
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wire io3_delayed;
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assign #1 io0_delayed = io0;
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assign #1 io1_delayed = io1;
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assign #1 io2_delayed = io2;
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assign #1 io3_delayed = io3;
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// 16 MB (128Mb) Flash
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reg [7:0] memory [0:16*1024*1024-1];
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initial begin
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$readmemh("firmware.hex", memory);
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end
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task spi_action;
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begin
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spi_in = buffer;
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if (bytecount == 1) begin
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spi_cmd = buffer;
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if (spi_cmd == 8'h ab)
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powered_up = 1;
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if (spi_cmd == 8'h b9)
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powered_up = 0;
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if (spi_cmd == 8'h ff)
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xip_cmd = 0;
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end
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if (powered_up && spi_cmd == 'h 03) begin
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount >= 4) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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if (powered_up && spi_cmd == 'h eb) begin
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if (bytecount == 1)
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mode = mode_qspi_rd;
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount == 5) begin
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xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
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mode = mode_qspi_wr;
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dummycount = 1;
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end
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if (bytecount >= 5) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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if (powered_up && spi_cmd == 'h ed) begin
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if (bytecount == 1)
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next_mode = mode_qspi_ddr_rd;
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount == 5) begin
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xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
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mode = mode_qspi_ddr_wr;
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dummycount = 1;
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end
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if (bytecount >= 5) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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spi_out = buffer;
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spi_io_vld = 1;
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if (verbose) begin
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if (bytecount == 1)
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$write("<SPI-START>");
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$write("<SPI:%02x:%02x>", spi_in, spi_out);
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end
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end
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endtask
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task ddr_rd_edge;
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begin
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buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
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bitcount = bitcount + 4;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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endtask
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task ddr_wr_edge;
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begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 1;
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io3_oe = 1;
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io0_dout = buffer[4];
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io1_dout = buffer[5];
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io2_dout = buffer[6];
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io3_dout = buffer[7];
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buffer = {buffer, 4'h 0};
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bitcount = bitcount + 4;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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endtask
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always @(csb) begin
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if (csb) begin
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if (verbose) begin
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$display("");
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$fflush;
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end
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buffer = 0;
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bitcount = 0;
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bytecount = 0;
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mode = mode_spi;
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end else
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if (xip_cmd) begin
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buffer = xip_cmd;
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bitcount = 0;
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bytecount = 1;
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spi_action;
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end
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end
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always @(csb, clk) begin
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spi_io_vld = 0;
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if (!csb && !clk) begin
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if (dummycount > 0) begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end else
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case (mode)
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mode_spi: begin
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io0_oe = 0;
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io1_oe = 1;
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io2_oe = 0;
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io3_oe = 0;
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io1_dout = buffer[7];
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end
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mode_qspi_rd: begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end
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mode_qspi_wr: begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 1;
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io3_oe = 1;
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io0_dout = buffer[4];
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io1_dout = buffer[5];
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io2_dout = buffer[6];
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io3_dout = buffer[7];
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end
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mode_qspi_ddr_rd: begin
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ddr_rd_edge;
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end
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mode_qspi_ddr_wr: begin
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ddr_wr_edge;
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end
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endcase
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if (next_mode) begin
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case (next_mode)
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mode_qspi_ddr_rd: begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end
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mode_qspi_ddr_wr: begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 1;
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io3_oe = 1;
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io0_dout = buffer[4];
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io1_dout = buffer[5];
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io2_dout = buffer[6];
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io3_dout = buffer[7];
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end
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endcase
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mode = next_mode;
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next_mode = 0;
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end
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end
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end
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always @(posedge clk) begin
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if (!csb) begin
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if (dummycount > 0) begin
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dummycount = dummycount - 1;
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end else
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case (mode)
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mode_spi: begin
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buffer = {buffer, io0};
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bitcount = bitcount + 1;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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mode_qspi_rd, mode_qspi_wr: begin
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buffer = {buffer, io3, io2, io1, io0};
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bitcount = bitcount + 4;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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mode_qspi_ddr_rd: begin
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ddr_rd_edge;
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end
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mode_qspi_ddr_wr: begin
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ddr_wr_edge;
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end
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endcase
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end
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end
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endmodule
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