89 lines
1.8 KiB
Verilog
89 lines
1.8 KiB
Verilog
`timescale 1 ns / 1 ps
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module testbench;
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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wire mem_valid;
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wire mem_instr;
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wire mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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wire mem_la_read;
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wire [31:0] mem_la_addr;
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picorv32 uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read(mem_la_read),
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.mem_la_addr(mem_la_addr)
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);
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reg [31:0] memory [0:64*1024/4-1];
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initial $readmemh("dhry.hex", memory);
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assign mem_ready = 1;
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always @(posedge clk) begin
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if (mem_la_read)
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mem_rdata <= memory[mem_la_addr >> 2];
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if (mem_valid) begin
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case (mem_addr)
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32'h1000_0000: begin
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`ifndef TIMING
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$write("%c", mem_wdata);
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$fflush();
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`endif
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end
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default: begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end
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endcase
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end
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end
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP");
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$finish;
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end
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end
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`ifdef TIMING
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initial begin
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repeat (100000) @(posedge clk);
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$finish;
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end
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always @(uut.count_instr[0]) begin
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$display("## %-s %d", uut.instruction, uut.count_cycle);
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end
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`endif
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endmodule
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