picorv32/picosoc
Clifford Wolf ff7855900d Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
..
.gitignore Refactor picosoc code 2017-08-07 15:13:27 +02:00
Makefile Refactor picosoc code 2017-08-07 15:13:27 +02:00
README.md Refactor picosoc code 2017-08-07 15:13:27 +02:00
firmware.s Refactor picosoc code 2017-08-07 15:13:27 +02:00
hx8kdemo.pcf Refactor picosoc code 2017-08-07 15:13:27 +02:00
hx8kdemo.v Refactor picosoc code 2017-08-07 15:13:27 +02:00
picosoc.v Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
spiflash.v Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
spiflash_tb.v Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
spimemio.v Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
testbench.v Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00

README.md

PicoSoC - A simple example SoC using PicoRV32

This is a simple PicoRV32 example design that can run code directly from an SPI flash chip. This example design uses the Lattice iCE40-HX8K Breakout Board.

The flash is mapped to the memory region starting at 0x01000000. The reset vector is set to 0x01100000, i.e. at the 1MB offset inside the flash memory.

A small scratchpad memory (default 256 words, i.e. 1 kB) is mapped to address 0x00000000.

Run make test to run the test bench (and create testbench.vcd).

Run make prog to build the configuration bit-stream and firmware images and upload them to a connected iCE40-HX8K Breakout Board.

File Description
picosoc.v Top-level PicoSoC Verilog module
picosoc.v Top-level PicoSoC Verilog module
spimemio.v Memory controller that interfaces to external SPI flash
spiflash.v Simulation model of an SPI flash (used by testbench.v)
testbench.v Simple test bench for the design (requires firmware.hex).
firmware.s Assembler source for firmware.hex/firmware.bin.
hx8kdemo.v FPGA-based example implementation on iCE40-HX8K Breakout Board
hx8kdemo.pcf Pin constraints for implementation on iCE40-HX8K Breakout Board