;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_addrcheck : 
  module el2_lsu_addrcheck : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
    
    node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 253:27]
    node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 253:49]
    wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
    node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 258:24]
    node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
    start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 258:16]
    node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 253:27]
    node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 253:49]
    wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
    node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 258:24]
    node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
    end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 258:16]
    wire addr_in_iccm : UInt<1>
    addr_in_iccm <= UInt<1>("h00")
    node _T_6 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 42:37]
    node _T_7 = eq(_T_6, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 42:45]
    addr_in_iccm <= _T_7 @[el2_lsu_addrcheck.scala 42:18]
    node _T_8 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 50:89]
    node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 253:27]
    node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 253:49]
    wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
    node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 258:24]
    node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
    start_addr_in_pic_d <= _T_11 @[el2_lib.scala 258:16]
    node _T_12 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 52:83]
    node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 253:27]
    node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 253:49]
    wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
    node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 258:24]
    node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
    end_addr_in_pic_d <= _T_15 @[el2_lib.scala 258:16]
    node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 54:60]
    node _T_16 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:48]
    node _T_17 = eq(_T_16, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:54]
    node _T_18 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:91]
    node _T_19 = eq(_T_18, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:97]
    node base_reg_dccm_or_pic = or(_T_17, _T_19) @[el2_lsu_addrcheck.scala 55:73]
    node _T_20 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 56:57]
    io.addr_in_dccm_d <= _T_20 @[el2_lsu_addrcheck.scala 56:32]
    node _T_21 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 57:56]
    io.addr_in_pic_d <= _T_21 @[el2_lsu_addrcheck.scala 57:32]
    node _T_22 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 59:63]
    node _T_23 = not(_T_22) @[el2_lsu_addrcheck.scala 59:33]
    io.addr_external_d <= _T_23 @[el2_lsu_addrcheck.scala 59:30]
    node _T_24 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 60:51]
    node csr_idx = cat(_T_24, UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_25 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 61:50]
    node _T_26 = bits(_T_25, 0, 0) @[el2_lsu_addrcheck.scala 61:50]
    node _T_27 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 61:92]
    node _T_28 = or(_T_27, addr_in_iccm) @[el2_lsu_addrcheck.scala 61:121]
    node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62]
    node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60]
    node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137]
    node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180]
    node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158]
    node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69]
    node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75]
    node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51]
    node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124]
    node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128]
    node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106]
    node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85]
    node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138]
    node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
    node _T_43 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58]
    node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58]
    node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:87]
    node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 65:33]
    node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:47]
    node _T_50 = or(_T_49, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:54]
    node _T_51 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:99]
    node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:76]
    node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:28]
    node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:47]
    node _T_55 = or(_T_54, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:54]
    node _T_56 = or(UInt<32>("h00"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:99]
    node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:76]
    node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:28]
    node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:121]
    node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:47]
    node _T_61 = or(_T_60, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:54]
    node _T_62 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:99]
    node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:76]
    node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:28]
    node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:121]
    node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:47]
    node _T_67 = or(_T_66, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:54]
    node _T_68 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:99]
    node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:76]
    node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:28]
    node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:121]
    node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:47]
    node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:54]
    node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:99]
    node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:76]
    node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:28]
    node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:121]
    node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:47]
    node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:54]
    node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:99]
    node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:76]
    node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:28]
    node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:121]
    node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:47]
    node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:54]
    node _T_86 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:99]
    node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:76]
    node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:28]
    node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:121]
    node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:47]
    node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:54]
    node _T_92 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:99]
    node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:76]
    node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:28]
    node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:121]
    node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:46]
    node _T_97 = or(_T_96, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:55]
    node _T_98 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:100]
    node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:77]
    node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:29]
    node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:47]
    node _T_102 = or(_T_101, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:56]
    node _T_103 = or(UInt<32>("h00"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:101]
    node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:78]
    node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:30]
    node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:122]
    node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:47]
    node _T_108 = or(_T_107, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:56]
    node _T_109 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:101]
    node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:78]
    node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:30]
    node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:123]
    node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:47]
    node _T_114 = or(_T_113, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:56]
    node _T_115 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:101]
    node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:78]
    node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:30]
    node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:123]
    node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:47]
    node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:56]
    node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:101]
    node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:78]
    node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:30]
    node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:123]
    node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:47]
    node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:56]
    node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:101]
    node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:78]
    node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:30]
    node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:123]
    node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:47]
    node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:56]
    node _T_133 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:101]
    node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:78]
    node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:30]
    node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:123]
    node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:47]
    node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:56]
    node _T_139 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:101]
    node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:78]
    node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:30]
    node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:123]
    node _T_143 = and(_T_95, _T_142) @[el2_lsu_addrcheck.scala 75:7]
    node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:92]
    node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57]
    node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70]
    node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76]
    node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92]
    node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90]
    node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51]
    wire unmapped_access_fault_d : UInt<1>
    unmapped_access_fault_d <= UInt<1>("h01")
    wire mpu_access_fault_d : UInt<1>
    mpu_access_fault_d <= UInt<1>("h01")
    node _T_148 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[el2_lsu_addrcheck.scala 91:87]
    node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 91:64]
    node _T_150 = and(start_addr_in_dccm_region_d, _T_149) @[el2_lsu_addrcheck.scala 91:62]
    node _T_151 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 93:57]
    node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:36]
    node _T_153 = and(end_addr_in_dccm_region_d, _T_152) @[el2_lsu_addrcheck.scala 93:34]
    node _T_154 = or(_T_150, _T_153) @[el2_lsu_addrcheck.scala 91:112]
    node _T_155 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 95:29]
    node _T_156 = or(_T_154, _T_155) @[el2_lsu_addrcheck.scala 93:85]
    node _T_157 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 97:29]
    node _T_158 = or(_T_156, _T_157) @[el2_lsu_addrcheck.scala 95:85]
    unmapped_access_fault_d <= _T_158 @[el2_lsu_addrcheck.scala 91:29]
    node _T_159 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:33]
    node _T_160 = eq(non_dccm_access_ok, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:64]
    node _T_161 = and(_T_159, _T_160) @[el2_lsu_addrcheck.scala 99:62]
    mpu_access_fault_d <= _T_161 @[el2_lsu_addrcheck.scala 99:29]
    node _T_162 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 111:49]
    node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70]
    node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92]
    node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118]
    node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141]
    node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139]
    io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21]
    node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60]
    node _T_169 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:100]
    node _T_170 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:144]
    node _T_171 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:185]
    node _T_172 = mux(_T_171, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 112:164]
    node _T_173 = mux(_T_170, UInt<4>("h05"), _T_172) @[el2_lsu_addrcheck.scala 112:120]
    node _T_174 = mux(_T_169, UInt<4>("h03"), _T_173) @[el2_lsu_addrcheck.scala 112:80]
    node access_fault_mscause_d = mux(_T_168, UInt<4>("h02"), _T_174) @[el2_lsu_addrcheck.scala 112:35]
    node _T_175 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:53]
    node _T_176 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:78]
    node regcross_misaligned_fault_d = neq(_T_175, _T_176) @[el2_lsu_addrcheck.scala 113:61]
    node _T_177 = eq(is_aligned_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 114:59]
    node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_177) @[el2_lsu_addrcheck.scala 114:57]
    node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90]
    node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57]
    node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113]
    node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136]
    node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134]
    io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25]
    node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111]
    node _T_184 = mux(_T_183, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 116:80]
    node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_184) @[el2_lsu_addrcheck.scala 116:39]
    node _T_185 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 117:50]
    node _T_186 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:84]
    node _T_187 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:113]
    node _T_188 = mux(_T_185, _T_186, _T_187) @[el2_lsu_addrcheck.scala 117:27]
    io.exc_mscause_d <= _T_188 @[el2_lsu_addrcheck.scala 117:21]
    node _T_189 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:66]
    node _T_190 = and(start_addr_in_dccm_region_d, _T_189) @[el2_lsu_addrcheck.scala 118:64]
    node _T_191 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:120]
    node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118]
    node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88]
    node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142]
    node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163]
    io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31]
    node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66]
    node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36]
    node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95]
    node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116]
    io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33]
    reg _T_200 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
    _T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60]
    io.is_sideeffects_m <= _T_200 @[el2_lsu_addrcheck.scala 121:50]
    
