[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
      "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
      "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
    "sources":[
      "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
    ]
  },
  {
    "class":"logger.LogLevelAnnotation",
    "globalLogLevel":{
      
    }
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"el2_dma_ctrl.gated_latch",
    "resourceId":"/vsrc/gated_latch.v"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"el2_dma_ctrl"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]