;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_dec_tlu_ctl : 
  extmodule gated_latch : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_1 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_1 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_2 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_2 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_3 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_3 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module el2_dec_timer_ctl : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>}
    
    wire mitctl1 : UInt<4>
    mitctl1 <= UInt<1>("h00")
    wire mitctl0 : UInt<3>
    mitctl0 <= UInt<1>("h00")
    wire mitb1 : UInt<32>
    mitb1 <= UInt<1>("h00")
    wire mitb0 : UInt<32>
    mitb0 <= UInt<1>("h00")
    wire mitcnt1 : UInt<32>
    mitcnt1 <= UInt<1>("h00")
    wire mitcnt0 : UInt<32>
    mitcnt0 <= UInt<1>("h00")
    node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30]
    node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30]
    io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25]
    io.dec_timer_t1_pulse <= mit1_match_ns @[el2_dec_tlu_ctl.scala 2756:25]
    node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[el2_dec_tlu_ctl.scala 2763:66]
    node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[el2_dec_tlu_ctl.scala 2763:43]
    node _T_1 = bits(mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2765:31]
    node _T_2 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2765:50]
    node _T_3 = bits(mitctl0, 2, 2) @[el2_dec_tlu_ctl.scala 2765:79]
    node _T_4 = or(_T_2, _T_3) @[el2_dec_tlu_ctl.scala 2765:70]
    node _T_5 = and(_T_1, _T_4) @[el2_dec_tlu_ctl.scala 2765:47]
    node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2765:106]
    node _T_7 = bits(mitctl0, 1, 1) @[el2_dec_tlu_ctl.scala 2765:141]
    node _T_8 = or(_T_6, _T_7) @[el2_dec_tlu_ctl.scala 2765:132]
    node _T_9 = and(_T_5, _T_8) @[el2_dec_tlu_ctl.scala 2765:103]
    node _T_10 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2765:167]
    node mitcnt0_inc_ok = and(_T_9, _T_10) @[el2_dec_tlu_ctl.scala 2765:165]
    node _T_11 = add(mitcnt0, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2766:29]
    node mitcnt0_inc = tail(_T_11, 1) @[el2_dec_tlu_ctl.scala 2766:29]
    node _T_12 = bits(mit0_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2767:38]
    node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68]
    node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54]
    node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23]
    node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:59]
    node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:76]
    node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:93]
    inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr.io.en <= _T_17 @[el2_lib.scala 511:17]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_18 <= mitcnt0_ns @[el2_lib.scala 514:16]
    mitcnt0 <= _T_18 @[el2_dec_tlu_ctl.scala 2768:25]
    node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[el2_dec_tlu_ctl.scala 2775:66]
    node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[el2_dec_tlu_ctl.scala 2775:43]
    node _T_20 = bits(mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2777:31]
    node _T_21 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2777:50]
    node _T_22 = bits(mitctl1, 2, 2) @[el2_dec_tlu_ctl.scala 2777:79]
    node _T_23 = or(_T_21, _T_22) @[el2_dec_tlu_ctl.scala 2777:70]
    node _T_24 = and(_T_20, _T_23) @[el2_dec_tlu_ctl.scala 2777:47]
    node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2777:106]
    node _T_26 = bits(mitctl1, 1, 1) @[el2_dec_tlu_ctl.scala 2777:141]
    node _T_27 = or(_T_25, _T_26) @[el2_dec_tlu_ctl.scala 2777:132]
    node _T_28 = and(_T_24, _T_27) @[el2_dec_tlu_ctl.scala 2777:103]
    node _T_29 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2777:167]
    node mitcnt1_inc_ok = and(_T_28, _T_29) @[el2_dec_tlu_ctl.scala 2777:165]
    node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
    node _T_31 = bits(mitctl1, 3, 3) @[el2_dec_tlu_ctl.scala 2780:62]
    node _T_32 = not(_T_31) @[el2_dec_tlu_ctl.scala 2780:54]
    node _T_33 = or(_T_32, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2780:66]
    node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58]
    node _T_35 = add(mitcnt1, _T_34) @[el2_dec_tlu_ctl.scala 2780:29]
    node mitcnt1_inc = tail(_T_35, 1) @[el2_dec_tlu_ctl.scala 2780:29]
    node _T_36 = bits(mit1_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2781:39]
    node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2781:69]
    node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[el2_dec_tlu_ctl.scala 2781:55]
    node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[el2_dec_tlu_ctl.scala 2781:24]
    node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[el2_dec_tlu_ctl.scala 2782:52]
    node _T_40 = or(_T_39, mit1_match_ns) @[el2_dec_tlu_ctl.scala 2782:69]
    node _T_41 = bits(_T_40, 0, 0) @[el2_dec_tlu_ctl.scala 2782:86]
    inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 511:17]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_42 <= mitcnt1_ns @[el2_lib.scala 514:16]
    mitcnt1 <= _T_42 @[el2_dec_tlu_ctl.scala 2782:17]
    node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[el2_dec_tlu_ctl.scala 2789:64]
    node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[el2_dec_tlu_ctl.scala 2789:41]
    node _T_44 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2790:30]
    node _T_45 = bits(wr_mitb0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2790:63]
    inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_2.io.en <= _T_45 @[el2_lib.scala 511:17]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    mitb0_b <= _T_44 @[el2_lib.scala 514:16]
    node _T_46 = not(mitb0_b) @[el2_dec_tlu_ctl.scala 2791:14]
    mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11]
    node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63]
    node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41]
    node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:23]
    node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56]
    inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
    rvclkhdr_3.clock <= clock
    rvclkhdr_3.reset <= reset
    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_3.io.en <= _T_49 @[el2_lib.scala 511:17]
    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    mitb1_b <= _T_48 @[el2_lib.scala 514:16]
    node _T_50 = not(mitb1_b) @[el2_dec_tlu_ctl.scala 2800:12]
    mitb1 <= _T_50 @[el2_dec_tlu_ctl.scala 2800:9]
    node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[el2_dec_tlu_ctl.scala 2811:66]
    node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[el2_dec_tlu_ctl.scala 2811:43]
    node _T_52 = bits(wr_mitctl0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2812:45]
    node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[el2_dec_tlu_ctl.scala 2812:72]
    node _T_54 = bits(mitctl0, 2, 0) @[el2_dec_tlu_ctl.scala 2812:86]
    node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[el2_dec_tlu_ctl.scala 2812:31]
    node _T_55 = bits(mitctl0_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2814:35]
    node mitctl0_0_b_ns = not(_T_55) @[el2_dec_tlu_ctl.scala 2814:24]
    reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2815:54]
    mitctl0_0_b <= mitctl0_0_b_ns @[el2_dec_tlu_ctl.scala 2815:54]
    node _T_56 = bits(mitctl0_ns, 2, 1) @[el2_dec_tlu_ctl.scala 2816:78]
    reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2816:67]
    _T_57 <= _T_56 @[el2_dec_tlu_ctl.scala 2816:67]
    node _T_58 = not(mitctl0_0_b) @[el2_dec_tlu_ctl.scala 2816:90]
    node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58]
    mitctl0 <= _T_59 @[el2_dec_tlu_ctl.scala 2816:31]
    node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[el2_dec_tlu_ctl.scala 2826:65]
    node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[el2_dec_tlu_ctl.scala 2826:43]
    node _T_61 = bits(wr_mitctl1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2827:45]
    node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2827:71]
    node _T_63 = bits(mitctl1, 3, 0) @[el2_dec_tlu_ctl.scala 2827:85]
    node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[el2_dec_tlu_ctl.scala 2827:31]
    node _T_64 = bits(mitctl1_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2828:34]
    node mitctl1_0_b_ns = not(_T_64) @[el2_dec_tlu_ctl.scala 2828:23]
    reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2829:49]
    mitctl1_0_b <= mitctl1_0_b_ns @[el2_dec_tlu_ctl.scala 2829:49]
    node _T_65 = bits(mitctl1_ns, 3, 1) @[el2_dec_tlu_ctl.scala 2830:57]
    reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2830:46]
    _T_66 <= _T_65 @[el2_dec_tlu_ctl.scala 2830:46]
    node _T_67 = not(mitctl1_0_b) @[el2_dec_tlu_ctl.scala 2830:69]
    node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58]
    mitctl1 <= _T_68 @[el2_dec_tlu_ctl.scala 2830:10]
    node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[el2_dec_tlu_ctl.scala 2832:43]
    node _T_70 = or(_T_69, io.csr_mitb1) @[el2_dec_tlu_ctl.scala 2832:60]
    node _T_71 = or(_T_70, io.csr_mitb0) @[el2_dec_tlu_ctl.scala 2832:75]
    node _T_72 = or(_T_71, io.csr_mitctl0) @[el2_dec_tlu_ctl.scala 2832:90]
    node _T_73 = or(_T_72, io.csr_mitctl1) @[el2_dec_tlu_ctl.scala 2832:107]
    io.dec_timer_read_d <= _T_73 @[el2_dec_tlu_ctl.scala 2832:25]
    node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[el2_dec_tlu_ctl.scala 2834:20]
    node _T_75 = bits(mitcnt0, 31, 0) @[el2_dec_tlu_ctl.scala 2834:39]
    node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[el2_dec_tlu_ctl.scala 2835:20]
    node _T_77 = bits(io.csr_mitb0, 0, 0) @[el2_dec_tlu_ctl.scala 2836:18]
    node _T_78 = bits(io.csr_mitb1, 0, 0) @[el2_dec_tlu_ctl.scala 2837:18]
    node _T_79 = bits(io.csr_mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2838:20]
    node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
    node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58]
    node _T_82 = bits(io.csr_mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2839:20]
    node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
    node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58]
    node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_86 = mux(_T_76, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_87 = mux(_T_77, mitb0, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_88 = mux(_T_78, mitb1, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_89 = mux(_T_79, _T_81, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_90 = mux(_T_82, _T_84, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_91 = or(_T_85, _T_86) @[Mux.scala 27:72]
    node _T_92 = or(_T_91, _T_87) @[Mux.scala 27:72]
    node _T_93 = or(_T_92, _T_88) @[Mux.scala 27:72]
    node _T_94 = or(_T_93, _T_89) @[Mux.scala 27:72]
    node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72]
    wire _T_96 : UInt<32> @[Mux.scala 27:72]
    _T_96 <= _T_95 @[Mux.scala 27:72]
    io.dec_timer_rddata_d <= _T_96 @[el2_dec_tlu_ctl.scala 2833:33]
    
  extmodule gated_latch_4 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_4 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_5 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_5 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_6 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_6 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_7 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_7 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_8 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_8 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_9 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_9 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_10 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_10 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_11 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_11 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_12 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_12 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_13 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_13 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_14 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_14 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_15 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_15 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_16 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_16 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_17 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_17 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_18 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_18 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_19 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_19 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_20 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_20 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_21 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_21 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_22 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_22 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_23 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_23 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_24 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_24 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_25 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_25 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_26 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_26 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_27 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_27 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_28 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_28 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_29 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_29 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_30 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_30 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_31 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_31 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_31 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_32 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_32 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_32 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_33 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_33 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_33 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_34 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_34 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_34 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_35 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_35 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_35 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_36 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_36 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_36 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_37 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_37 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_37 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_38 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_38 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_38 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_39 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_39 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_39 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_40 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_40 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_40 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_41 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_41 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_41 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_42 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_42 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_42 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module csr_tlu : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]}
    
    wire miccme_ce_req : UInt<1>
    miccme_ce_req <= UInt<1>("h00")
    wire mice_ce_req : UInt<1>
    mice_ce_req <= UInt<1>("h00")
    wire mdccme_ce_req : UInt<1>
    mdccme_ce_req <= UInt<1>("h00")
    wire pc_r_d1 : UInt<31>
    pc_r_d1 <= UInt<1>("h00")
    wire mpmc_b_ns : UInt<1>
    mpmc_b_ns <= UInt<1>("h00")
    wire mpmc_b : UInt<1>
    mpmc_b <= UInt<1>("h00")
    wire wr_mcycleh_r : UInt<1>
    wr_mcycleh_r <= UInt<1>("h00")
    wire mcycleh : UInt<32>
    mcycleh <= UInt<1>("h00")
    wire minstretl_inc : UInt<33>
    minstretl_inc <= UInt<1>("h00")
    wire wr_minstreth_r : UInt<1>
    wr_minstreth_r <= UInt<1>("h00")
    wire minstretl : UInt<32>
    minstretl <= UInt<1>("h00")
    wire minstreth_inc : UInt<32>
    minstreth_inc <= UInt<1>("h00")
    wire minstreth : UInt<32>
    minstreth <= UInt<1>("h00")
    wire mfdc_ns : UInt<15>
    mfdc_ns <= UInt<1>("h00")
    wire mfdc_int : UInt<15>
    mfdc_int <= UInt<1>("h00")
    wire mhpmc6_incr : UInt<64>
    mhpmc6_incr <= UInt<1>("h00")
    wire mhpmc5_incr : UInt<64>
    mhpmc5_incr <= UInt<1>("h00")
    wire mhpmc4_incr : UInt<64>
    mhpmc4_incr <= UInt<1>("h00")
    wire perfcnt_halted : UInt<1>
    perfcnt_halted <= UInt<1>("h00")
    wire mhpmc3_incr : UInt<64>
    mhpmc3_incr <= UInt<1>("h00")
    wire mhpme_vec : UInt<10>[4] @[el2_dec_tlu_ctl.scala 1474:41]
    wire mtdata2_t : UInt<32>[4] @[el2_dec_tlu_ctl.scala 1475:65]
    wire wr_meicpct_r : UInt<1>
    wr_meicpct_r <= UInt<1>("h00")
    wire force_halt_ctr_f : UInt<32>
    force_halt_ctr_f <= UInt<1>("h00")
    wire mdccmect_inc : UInt<27>
    mdccmect_inc <= UInt<1>("h00")
    wire miccmect_inc : UInt<27>
    miccmect_inc <= UInt<1>("h00")
    wire fw_halted : UInt<1>
    fw_halted <= UInt<1>("h00")
    wire micect_inc : UInt<27>
    micect_inc <= UInt<1>("h00")
    wire mdseac_en : UInt<1>
    mdseac_en <= UInt<1>("h00")
    wire mie : UInt<6>
    mie <= UInt<1>("h00")
    wire mcyclel : UInt<32>
    mcyclel <= UInt<1>("h00")
    wire mscratch : UInt<32>
    mscratch <= UInt<1>("h00")
    wire mcause : UInt<32>
    mcause <= UInt<1>("h00")
    wire mscause : UInt<4>
    mscause <= UInt<1>("h00")
    wire mtval : UInt<32>
    mtval <= UInt<1>("h00")
    wire meicurpl : UInt<4>
    meicurpl <= UInt<1>("h00")
    wire meicidpl : UInt<4>
    meicidpl <= UInt<1>("h00")
    wire meipt : UInt<4>
    meipt <= UInt<1>("h00")
    wire mfdc : UInt<19>
    mfdc <= UInt<1>("h00")
    wire mtsel : UInt<2>
    mtsel <= UInt<1>("h00")
    wire micect : UInt<32>
    micect <= UInt<1>("h00")
    wire miccmect : UInt<32>
    miccmect <= UInt<1>("h00")
    wire mdccmect : UInt<32>
    mdccmect <= UInt<1>("h00")
    wire mhpmc3h : UInt<32>
    mhpmc3h <= UInt<1>("h00")
    wire mhpmc3 : UInt<32>
    mhpmc3 <= UInt<1>("h00")
    wire mhpmc4h : UInt<32>
    mhpmc4h <= UInt<1>("h00")
    wire mhpmc4 : UInt<32>
    mhpmc4 <= UInt<1>("h00")
    wire mhpmc5h : UInt<32>
    mhpmc5h <= UInt<1>("h00")
    wire mhpmc5 : UInt<32>
    mhpmc5 <= UInt<1>("h00")
    wire mhpmc6h : UInt<32>
    mhpmc6h <= UInt<1>("h00")
    wire mhpmc6 : UInt<32>
    mhpmc6 <= UInt<1>("h00")
    wire mhpme3 : UInt<10>
    mhpme3 <= UInt<1>("h00")
    wire mhpme4 : UInt<10>
    mhpme4 <= UInt<1>("h00")
    wire mhpme5 : UInt<10>
    mhpme5 <= UInt<1>("h00")
    wire mhpme6 : UInt<10>
    mhpme6 <= UInt<1>("h00")
    wire mfdht : UInt<6>
    mfdht <= UInt<1>("h00")
    wire mfdhs : UInt<2>
    mfdhs <= UInt<1>("h00")
    wire mcountinhibit : UInt<7>
    mcountinhibit <= UInt<1>("h00")
    wire mpmc : UInt<1>
    mpmc <= UInt<1>("h00")
    wire dicad1 : UInt<32>
    dicad1 <= UInt<1>("h00")
    node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:46]
    node _T_1 = and(io.dec_csr_wen_r, _T) @[el2_dec_tlu_ctl.scala 1530:44]
    node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:69]
    node _T_3 = and(_T_1, _T_2) @[el2_dec_tlu_ctl.scala 1530:67]
    io.dec_csr_wen_r_mod <= _T_3 @[el2_dec_tlu_ctl.scala 1530:24]
    node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1531:65]
    node _T_5 = eq(_T_4, UInt<12>("h0300")) @[el2_dec_tlu_ctl.scala 1531:72]
    node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[el2_dec_tlu_ctl.scala 1531:43]
    node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1534:29]
    node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[el2_dec_tlu_ctl.scala 1534:40]
    node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:6]
    node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1537:20]
    node _T_9 = bits(_T_8, 0, 0) @[el2_dec_tlu_ctl.scala 1537:45]
    node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:69]
    node _T_11 = bits(_T_10, 0, 0) @[el2_dec_tlu_ctl.scala 1537:69]
    node _T_12 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1538:19]
    node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 1538:44]
    node _T_14 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1538:77]
    node _T_15 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1539:18]
    node _T_16 = and(io.mret_r, _T_15) @[el2_dec_tlu_ctl.scala 1539:16]
    node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 1539:42]
    node _T_18 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1539:71]
    node _T_19 = cat(UInt<1>("h01"), _T_18) @[Cat.scala 29:58]
    node _T_20 = bits(set_mie_pmu_fw_halt, 0, 0) @[el2_dec_tlu_ctl.scala 1540:27]
    node _T_21 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1540:51]
    node _T_22 = cat(_T_21, UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_23 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1541:21]
    node _T_24 = and(wr_mstatus_r, _T_23) @[el2_dec_tlu_ctl.scala 1541:19]
    node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 1541:45]
    node _T_26 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1541:78]
    node _T_27 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1541:102]
    node _T_28 = cat(_T_26, _T_27) @[Cat.scala 29:58]
    node _T_29 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:6]
    node _T_30 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:22]
    node _T_31 = and(_T_29, _T_30) @[el2_dec_tlu_ctl.scala 1542:20]
    node _T_32 = eq(io.mret_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:47]
    node _T_33 = and(_T_31, _T_32) @[el2_dec_tlu_ctl.scala 1542:45]
    node _T_34 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:60]
    node _T_35 = and(_T_33, _T_34) @[el2_dec_tlu_ctl.scala 1542:58]
    node _T_36 = bits(_T_35, 0, 0) @[el2_dec_tlu_ctl.scala 1542:82]
    node _T_37 = mux(_T_9, _T_11, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_38 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_39 = mux(_T_17, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_40 = mux(_T_20, _T_22, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_41 = mux(_T_25, _T_28, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_42 = mux(_T_36, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_43 = or(_T_37, _T_38) @[Mux.scala 27:72]
    node _T_44 = or(_T_43, _T_39) @[Mux.scala 27:72]
    node _T_45 = or(_T_44, _T_40) @[Mux.scala 27:72]
    node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72]
    node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72]
    wire mstatus_ns : UInt<2> @[Mux.scala 27:72]
    mstatus_ns <= _T_47 @[Mux.scala 27:72]
    node _T_48 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1545:34]
    node _T_49 = bits(_T_48, 0, 0) @[el2_dec_tlu_ctl.scala 1545:34]
    node _T_50 = not(io.dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 1545:51]
    node _T_51 = bits(io.dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 1545:91]
    node _T_52 = or(_T_50, _T_51) @[el2_dec_tlu_ctl.scala 1545:82]
    node _T_53 = and(_T_49, _T_52) @[el2_dec_tlu_ctl.scala 1545:48]
    io.mstatus_mie_ns <= _T_53 @[el2_dec_tlu_ctl.scala 1545:21]
    reg _T_54 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1547:12]
    _T_54 <= mstatus_ns @[el2_dec_tlu_ctl.scala 1547:12]
    io.mstatus <= _T_54 @[el2_dec_tlu_ctl.scala 1546:14]
    node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1556:63]
    node _T_56 = eq(_T_55, UInt<12>("h0305")) @[el2_dec_tlu_ctl.scala 1556:70]
    node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_56) @[el2_dec_tlu_ctl.scala 1556:41]
    node _T_57 = bits(io.dec_csr_wrdata_r, 31, 2) @[el2_dec_tlu_ctl.scala 1557:41]
    node _T_58 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1557:69]
    node mtvec_ns = cat(_T_57, _T_58) @[Cat.scala 29:58]
    node _T_59 = bits(wr_mtvec_r, 0, 0) @[el2_dec_tlu_ctl.scala 1558:43]
    inst rvclkhdr of rvclkhdr_8 @[el2_lib.scala 508:23]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr.io.en <= _T_59 @[el2_lib.scala 511:17]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_60 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_60 <= mtvec_ns @[el2_lib.scala 514:16]
    io.mtvec <= _T_60 @[el2_dec_tlu_ctl.scala 1558:12]
    node _T_61 = or(mdccme_ce_req, miccme_ce_req) @[el2_dec_tlu_ctl.scala 1570:31]
    node ce_int = or(_T_61, mice_ce_req) @[el2_dec_tlu_ctl.scala 1570:47]
    node _T_62 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58]
    node _T_63 = cat(_T_62, io.soft_int_sync) @[Cat.scala 29:58]
    node _T_64 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58]
    node _T_65 = cat(_T_64, io.dec_timer_t1_pulse) @[Cat.scala 29:58]
    node mip_ns = cat(_T_65, _T_63) @[Cat.scala 29:58]
    reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1574:12]
    _T_66 <= mip_ns @[el2_dec_tlu_ctl.scala 1574:12]
    io.mip <= _T_66 @[el2_dec_tlu_ctl.scala 1573:10]
    node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1586:61]
    node _T_68 = eq(_T_67, UInt<12>("h0304")) @[el2_dec_tlu_ctl.scala 1586:68]
    node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[el2_dec_tlu_ctl.scala 1586:39]
    node _T_69 = bits(wr_mie_r, 0, 0) @[el2_dec_tlu_ctl.scala 1587:29]
    node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[el2_dec_tlu_ctl.scala 1587:60]
    node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1587:89]
    node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1587:114]
    node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1587:138]
    node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58]
    node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58]
    node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58]
    node _T_77 = mux(_T_69, _T_76, mie) @[el2_dec_tlu_ctl.scala 1587:19]
    io.mie_ns <= _T_77 @[el2_dec_tlu_ctl.scala 1587:13]
    reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1589:12]
    _T_78 <= io.mie_ns @[el2_dec_tlu_ctl.scala 1589:12]
    mie <= _T_78 @[el2_dec_tlu_ctl.scala 1588:7]
    node _T_79 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1596:64]
    node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[el2_dec_tlu_ctl.scala 1596:55]
    node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1598:65]
    node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[el2_dec_tlu_ctl.scala 1598:72]
    node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[el2_dec_tlu_ctl.scala 1598:43]
    node _T_82 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1600:81]
    node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[el2_dec_tlu_ctl.scala 1600:72]
    node _T_84 = or(kill_ebreak_count_r, _T_83) @[el2_dec_tlu_ctl.scala 1600:47]
    node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 1600:95]
    node _T_86 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 1600:137]
    node _T_87 = or(_T_85, _T_86) @[el2_dec_tlu_ctl.scala 1600:122]
    node mcyclel_cout_in = not(_T_87) @[el2_dec_tlu_ctl.scala 1600:25]
    wire mcyclel_inc : UInt<33>
    mcyclel_inc <= UInt<1>("h00")
    node _T_88 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58]
    node _T_89 = add(mcyclel, _T_88) @[el2_dec_tlu_ctl.scala 1604:26]
    node _T_90 = tail(_T_89, 1) @[el2_dec_tlu_ctl.scala 1604:26]
    mcyclel_inc <= _T_90 @[el2_dec_tlu_ctl.scala 1604:15]
    node _T_91 = bits(wr_mcyclel_r, 0, 0) @[el2_dec_tlu_ctl.scala 1605:37]
    node mcyclel_ns = mux(_T_91, io.dec_csr_wrdata_r, mcyclel_inc) @[el2_dec_tlu_ctl.scala 1605:23]
    node _T_92 = bits(mcyclel_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1606:33]
    node mcyclel_cout = bits(_T_92, 0, 0) @[el2_dec_tlu_ctl.scala 1606:38]
    node _T_93 = or(wr_mcyclel_r, mcyclel_cout_in) @[el2_dec_tlu_ctl.scala 1607:47]
    node _T_94 = bits(_T_93, 0, 0) @[el2_dec_tlu_ctl.scala 1607:73]
    inst rvclkhdr_1 of rvclkhdr_9 @[el2_lib.scala 508:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_1.io.en <= _T_94 @[el2_lib.scala 511:17]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_95 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_95 <= mcyclel_ns @[el2_lib.scala 514:16]
    mcyclel <= _T_95 @[el2_dec_tlu_ctl.scala 1607:11]
    node _T_96 = eq(wr_mcycleh_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1608:72]
    node _T_97 = and(mcyclel_cout, _T_96) @[el2_dec_tlu_ctl.scala 1608:70]
    reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1608:55]
    mcyclel_cout_f <= _T_97 @[el2_dec_tlu_ctl.scala 1608:55]
    node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1614:62]
    node _T_99 = eq(_T_98, UInt<12>("h0b80")) @[el2_dec_tlu_ctl.scala 1614:69]
    node _T_100 = and(io.dec_csr_wen_r_mod, _T_99) @[el2_dec_tlu_ctl.scala 1614:40]
    wr_mcycleh_r <= _T_100 @[el2_dec_tlu_ctl.scala 1614:16]
    node _T_101 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58]
    node _T_102 = add(mcycleh, _T_101) @[el2_dec_tlu_ctl.scala 1616:29]
    node mcycleh_inc = tail(_T_102, 1) @[el2_dec_tlu_ctl.scala 1616:29]
    node _T_103 = bits(wr_mcycleh_r, 0, 0) @[el2_dec_tlu_ctl.scala 1617:37]
    node mcycleh_ns = mux(_T_103, io.dec_csr_wrdata_r, mcycleh_inc) @[el2_dec_tlu_ctl.scala 1617:23]
    node _T_104 = or(wr_mcycleh_r, mcyclel_cout_f) @[el2_dec_tlu_ctl.scala 1619:47]
    node _T_105 = bits(_T_104, 0, 0) @[el2_dec_tlu_ctl.scala 1619:65]
    inst rvclkhdr_2 of rvclkhdr_10 @[el2_lib.scala 508:23]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_2.io.en <= _T_105 @[el2_lib.scala 511:17]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_106 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_106 <= mcycleh_ns @[el2_lib.scala 514:16]
    mcycleh <= _T_106 @[el2_dec_tlu_ctl.scala 1619:11]
    node _T_107 = or(io.ebreak_r, io.ecall_r) @[el2_dec_tlu_ctl.scala 1633:73]
    node _T_108 = or(_T_107, io.ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 1633:86]
    node _T_109 = or(_T_108, io.illegal_r) @[el2_dec_tlu_ctl.scala 1633:114]
    node _T_110 = bits(mcountinhibit, 2, 2) @[el2_dec_tlu_ctl.scala 1633:144]
    node _T_111 = or(_T_109, _T_110) @[el2_dec_tlu_ctl.scala 1633:129]
    node _T_112 = bits(_T_111, 0, 0) @[el2_dec_tlu_ctl.scala 1633:149]
    node _T_113 = not(_T_112) @[el2_dec_tlu_ctl.scala 1633:59]
    node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_113) @[el2_dec_tlu_ctl.scala 1633:57]
    node _T_114 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1635:67]
    node _T_115 = eq(_T_114, UInt<12>("h0b02")) @[el2_dec_tlu_ctl.scala 1635:74]
    node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_115) @[el2_dec_tlu_ctl.scala 1635:45]
    node _T_116 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58]
    node _T_117 = add(minstretl, _T_116) @[el2_dec_tlu_ctl.scala 1637:30]
    node _T_118 = tail(_T_117, 1) @[el2_dec_tlu_ctl.scala 1637:30]
    minstretl_inc <= _T_118 @[el2_dec_tlu_ctl.scala 1637:17]
    node minstretl_cout = bits(minstretl_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1638:37]
    node _T_119 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[el2_dec_tlu_ctl.scala 1639:53]
    node minstret_enable = bits(_T_119, 0, 0) @[el2_dec_tlu_ctl.scala 1639:71]
    node _T_120 = bits(wr_minstretl_r, 0, 0) @[el2_dec_tlu_ctl.scala 1641:41]
    node minstretl_ns = mux(_T_120, io.dec_csr_wrdata_r, minstretl_inc) @[el2_dec_tlu_ctl.scala 1641:25]
    node _T_121 = bits(minstret_enable, 0, 0) @[el2_dec_tlu_ctl.scala 1642:52]
    inst rvclkhdr_3 of rvclkhdr_11 @[el2_lib.scala 508:23]
    rvclkhdr_3.clock <= clock
    rvclkhdr_3.reset <= reset
    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_3.io.en <= _T_121 @[el2_lib.scala 511:17]
    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_122 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_122 <= minstretl_ns @[el2_lib.scala 514:16]
    minstretl <= _T_122 @[el2_dec_tlu_ctl.scala 1642:13]
    reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1643:57]
    minstret_enable_f <= minstret_enable @[el2_dec_tlu_ctl.scala 1643:57]
    node _T_123 = not(wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1644:76]
    node _T_124 = and(minstretl_cout, _T_123) @[el2_dec_tlu_ctl.scala 1644:74]
    reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1644:57]
    minstretl_cout_f <= _T_124 @[el2_dec_tlu_ctl.scala 1644:57]
    node _T_125 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1652:65]
    node _T_126 = eq(_T_125, UInt<12>("h0b82")) @[el2_dec_tlu_ctl.scala 1652:72]
    node _T_127 = and(io.dec_csr_wen_r_mod, _T_126) @[el2_dec_tlu_ctl.scala 1652:43]
    node _T_128 = bits(_T_127, 0, 0) @[el2_dec_tlu_ctl.scala 1652:88]
    wr_minstreth_r <= _T_128 @[el2_dec_tlu_ctl.scala 1652:18]
    node _T_129 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58]
    node _T_130 = add(minstreth, _T_129) @[el2_dec_tlu_ctl.scala 1655:30]
    node _T_131 = tail(_T_130, 1) @[el2_dec_tlu_ctl.scala 1655:30]
    minstreth_inc <= _T_131 @[el2_dec_tlu_ctl.scala 1655:17]
    node _T_132 = bits(wr_minstreth_r, 0, 0) @[el2_dec_tlu_ctl.scala 1656:42]
    node minstreth_ns = mux(_T_132, io.dec_csr_wrdata_r, minstreth_inc) @[el2_dec_tlu_ctl.scala 1656:26]
    node _T_133 = or(minstret_enable_f, wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1658:56]
    node _T_134 = bits(_T_133, 0, 0) @[el2_dec_tlu_ctl.scala 1658:74]
    inst rvclkhdr_4 of rvclkhdr_12 @[el2_lib.scala 508:23]
    rvclkhdr_4.clock <= clock
    rvclkhdr_4.reset <= reset
    rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_4.io.en <= _T_134 @[el2_lib.scala 511:17]
    rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_135 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_135 <= minstreth_ns @[el2_lib.scala 514:16]
    minstreth <= _T_135 @[el2_dec_tlu_ctl.scala 1658:13]
    node _T_136 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1666:66]
    node _T_137 = eq(_T_136, UInt<12>("h0340")) @[el2_dec_tlu_ctl.scala 1666:73]
    node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_137) @[el2_dec_tlu_ctl.scala 1666:44]
    node _T_138 = bits(wr_mscratch_r, 0, 0) @[el2_dec_tlu_ctl.scala 1668:56]
    inst rvclkhdr_5 of rvclkhdr_13 @[el2_lib.scala 508:23]
    rvclkhdr_5.clock <= clock
    rvclkhdr_5.reset <= reset
    rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_5.io.en <= _T_138 @[el2_lib.scala 511:17]
    rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_139 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_139 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
    mscratch <= _T_139 @[el2_dec_tlu_ctl.scala 1668:12]
    node _T_140 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:23]
    node _T_141 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:48]
    node _T_142 = and(_T_140, _T_141) @[el2_dec_tlu_ctl.scala 1677:46]
    node sel_exu_npc_r = and(_T_142, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1677:73]
    node _T_143 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:25]
    node _T_144 = and(_T_143, io.tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 1678:48]
    node _T_145 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:76]
    node sel_flush_npc_r = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 1678:74]
    node _T_146 = eq(sel_exu_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:24]
    node _T_147 = eq(sel_flush_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:41]
    node sel_hold_npc_r = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 1679:39]
    node _T_148 = bits(sel_exu_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1682:19]
    node _T_149 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1683:6]
    node _T_150 = and(_T_149, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1683:28]
    node _T_151 = bits(_T_150, 0, 0) @[el2_dec_tlu_ctl.scala 1683:48]
    node _T_152 = bits(sel_flush_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1684:21]
    node _T_153 = bits(sel_hold_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1685:20]
    node _T_154 = mux(_T_148, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_155 = mux(_T_151, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_156 = mux(_T_152, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_157 = mux(_T_153, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_158 = or(_T_154, _T_155) @[Mux.scala 27:72]
    node _T_159 = or(_T_158, _T_156) @[Mux.scala 27:72]
    node _T_160 = or(_T_159, _T_157) @[Mux.scala 27:72]
    wire _T_161 : UInt<31> @[Mux.scala 27:72]
    _T_161 <= _T_160 @[Mux.scala 27:72]
    io.npc_r <= _T_161 @[el2_dec_tlu_ctl.scala 1681:12]
    node _T_162 = or(sel_exu_npc_r, sel_flush_npc_r) @[el2_dec_tlu_ctl.scala 1687:49]
    node _T_163 = or(_T_162, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1687:67]
    node _T_164 = bits(_T_163, 0, 0) @[el2_dec_tlu_ctl.scala 1687:87]
    inst rvclkhdr_6 of rvclkhdr_14 @[el2_lib.scala 508:23]
    rvclkhdr_6.clock <= clock
    rvclkhdr_6.reset <= reset
    rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_6.io.en <= _T_164 @[el2_lib.scala 511:17]
    rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_165 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_165 <= io.npc_r @[el2_lib.scala 514:16]
    io.npc_r_d1 <= _T_165 @[el2_dec_tlu_ctl.scala 1687:15]
    node _T_166 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1690:22]
    node _T_167 = and(_T_166, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1690:45]
    node pc0_valid_r = bits(_T_167, 0, 0) @[el2_dec_tlu_ctl.scala 1690:70]
    node _T_168 = not(pc0_valid_r) @[el2_dec_tlu_ctl.scala 1694:5]
    node _T_169 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_170 = mux(_T_168, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_171 = or(_T_169, _T_170) @[Mux.scala 27:72]
    wire pc_r : UInt<31> @[Mux.scala 27:72]
    pc_r <= _T_171 @[Mux.scala 27:72]
    inst rvclkhdr_7 of rvclkhdr_15 @[el2_lib.scala 508:23]
    rvclkhdr_7.clock <= clock
    rvclkhdr_7.reset <= reset
    rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_7.io.en <= pc0_valid_r @[el2_lib.scala 511:17]
    rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_172 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_172 <= pc_r @[el2_lib.scala 514:16]
    pc_r_d1 <= _T_172 @[el2_dec_tlu_ctl.scala 1696:11]
    node _T_173 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1698:62]
    node _T_174 = eq(_T_173, UInt<12>("h0341")) @[el2_dec_tlu_ctl.scala 1698:69]
    node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_174) @[el2_dec_tlu_ctl.scala 1698:40]
    node _T_175 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1701:30]
    node _T_176 = or(_T_175, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1701:51]
    node _T_177 = bits(_T_176, 0, 0) @[el2_dec_tlu_ctl.scala 1701:83]
    node _T_178 = bits(io.interrupt_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1702:28]
    node _T_179 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1703:18]
    node _T_180 = and(wr_mepc_r, _T_179) @[el2_dec_tlu_ctl.scala 1703:16]
    node _T_181 = bits(_T_180, 0, 0) @[el2_dec_tlu_ctl.scala 1703:42]
    node _T_182 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 1703:107]
    node _T_183 = eq(wr_mepc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:6]
    node _T_184 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:19]
    node _T_185 = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 1704:17]
    node _T_186 = bits(_T_185, 0, 0) @[el2_dec_tlu_ctl.scala 1704:43]
    node _T_187 = mux(_T_177, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_188 = mux(_T_178, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_189 = mux(_T_181, _T_182, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_190 = mux(_T_186, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_191 = or(_T_187, _T_188) @[Mux.scala 27:72]
    node _T_192 = or(_T_191, _T_189) @[Mux.scala 27:72]
    node _T_193 = or(_T_192, _T_190) @[Mux.scala 27:72]
    wire mepc_ns : UInt<31> @[Mux.scala 27:72]
    mepc_ns <= _T_193 @[Mux.scala 27:72]
    reg _T_194 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1706:48]
    _T_194 <= mepc_ns @[el2_dec_tlu_ctl.scala 1706:48]
    io.mepc <= _T_194 @[el2_dec_tlu_ctl.scala 1706:11]
    node _T_195 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1713:64]
    node _T_196 = eq(_T_195, UInt<12>("h0342")) @[el2_dec_tlu_ctl.scala 1713:71]
    node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_196) @[el2_dec_tlu_ctl.scala 1713:42]
    node _T_197 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1714:52]
    node mcause_sel_nmi_store = and(_T_197, io.nmi_lsu_store_type) @[el2_dec_tlu_ctl.scala 1714:66]
    node _T_198 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1715:51]
    node mcause_sel_nmi_load = and(_T_198, io.nmi_lsu_load_type) @[el2_dec_tlu_ctl.scala 1715:65]
    node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1716:50]
    node _T_200 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1716:83]
    node mcause_sel_nmi_ext = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 1716:64]
    node _T_201 = andr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1722:52]
    node _T_202 = bits(io.lsu_fir_error, 1, 1) @[el2_dec_tlu_ctl.scala 1722:75]
    node _T_203 = bits(io.lsu_fir_error, 0, 0) @[el2_dec_tlu_ctl.scala 1722:98]
    node _T_204 = not(_T_203) @[el2_dec_tlu_ctl.scala 1722:81]
    node _T_205 = and(_T_202, _T_204) @[el2_dec_tlu_ctl.scala 1722:79]
    node mcause_fir_error_type = cat(_T_201, _T_205) @[Cat.scala 29:58]
    node _T_206 = bits(mcause_sel_nmi_store, 0, 0) @[el2_dec_tlu_ctl.scala 1725:26]
    node _T_207 = bits(mcause_sel_nmi_load, 0, 0) @[el2_dec_tlu_ctl.scala 1726:25]
    node _T_208 = bits(mcause_sel_nmi_ext, 0, 0) @[el2_dec_tlu_ctl.scala 1727:24]
    node _T_209 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58]
    node _T_210 = cat(_T_209, mcause_fir_error_type) @[Cat.scala 29:58]
    node _T_211 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1728:30]
    node _T_212 = and(io.exc_or_int_valid_r, _T_211) @[el2_dec_tlu_ctl.scala 1728:28]
    node _T_213 = bits(_T_212, 0, 0) @[el2_dec_tlu_ctl.scala 1728:44]
    node _T_214 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58]
    node _T_215 = cat(_T_214, io.exc_cause_r) @[Cat.scala 29:58]
    node _T_216 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1729:20]
    node _T_217 = and(wr_mcause_r, _T_216) @[el2_dec_tlu_ctl.scala 1729:18]
    node _T_218 = bits(_T_217, 0, 0) @[el2_dec_tlu_ctl.scala 1729:44]
    node _T_219 = not(wr_mcause_r) @[el2_dec_tlu_ctl.scala 1730:6]
    node _T_220 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1730:21]
    node _T_221 = and(_T_219, _T_220) @[el2_dec_tlu_ctl.scala 1730:19]
    node _T_222 = bits(_T_221, 0, 0) @[el2_dec_tlu_ctl.scala 1730:45]
    node _T_223 = mux(_T_206, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_224 = mux(_T_207, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_225 = mux(_T_208, _T_210, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_226 = mux(_T_213, _T_215, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_227 = mux(_T_218, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_228 = mux(_T_222, mcause, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_229 = or(_T_223, _T_224) @[Mux.scala 27:72]
    node _T_230 = or(_T_229, _T_225) @[Mux.scala 27:72]
    node _T_231 = or(_T_230, _T_226) @[Mux.scala 27:72]
    node _T_232 = or(_T_231, _T_227) @[Mux.scala 27:72]
    node _T_233 = or(_T_232, _T_228) @[Mux.scala 27:72]
    wire mcause_ns : UInt<32> @[Mux.scala 27:72]
    mcause_ns <= _T_233 @[Mux.scala 27:72]
    reg _T_234 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1732:47]
    _T_234 <= mcause_ns @[el2_dec_tlu_ctl.scala 1732:47]
    mcause <= _T_234 @[el2_dec_tlu_ctl.scala 1732:10]
    node _T_235 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1739:65]
    node _T_236 = eq(_T_235, UInt<12>("h07ff")) @[el2_dec_tlu_ctl.scala 1739:72]
    node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_236) @[el2_dec_tlu_ctl.scala 1739:43]
    node _T_237 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 1741:57]
    node _T_238 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58]
    node ifu_mscause = mux(_T_237, UInt<4>("h09"), _T_238) @[el2_dec_tlu_ctl.scala 1741:25]
    node _T_239 = bits(io.lsu_i0_exc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1744:21]
    node _T_240 = bits(io.i0_trigger_hit_r, 0, 0) @[el2_dec_tlu_ctl.scala 1745:25]
    node _T_241 = bits(io.ebreak_r, 0, 0) @[el2_dec_tlu_ctl.scala 1746:17]
    node _T_242 = bits(io.inst_acc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1747:19]
    node _T_243 = mux(_T_239, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_244 = mux(_T_240, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_245 = mux(_T_241, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_246 = mux(_T_242, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_247 = or(_T_243, _T_244) @[Mux.scala 27:72]
    node _T_248 = or(_T_247, _T_245) @[Mux.scala 27:72]
    node _T_249 = or(_T_248, _T_246) @[Mux.scala 27:72]
    wire mscause_type : UInt<4> @[Mux.scala 27:72]
    mscause_type <= _T_249 @[Mux.scala 27:72]
    node _T_250 = bits(io.exc_or_int_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1751:29]
    node _T_251 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1752:21]
    node _T_252 = and(wr_mscause_r, _T_251) @[el2_dec_tlu_ctl.scala 1752:19]
    node _T_253 = bits(_T_252, 0, 0) @[el2_dec_tlu_ctl.scala 1752:45]
    node _T_254 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 1752:84]
    node _T_255 = eq(wr_mscause_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:6]
    node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:22]
    node _T_257 = and(_T_255, _T_256) @[el2_dec_tlu_ctl.scala 1753:20]
    node _T_258 = bits(_T_257, 0, 0) @[el2_dec_tlu_ctl.scala 1753:46]
    node _T_259 = mux(_T_250, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_261 = mux(_T_258, mscause, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72]
    node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72]
    wire mscause_ns : UInt<4> @[Mux.scala 27:72]
    mscause_ns <= _T_263 @[Mux.scala 27:72]
    reg _T_264 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1755:48]
    _T_264 <= mscause_ns @[el2_dec_tlu_ctl.scala 1755:48]
    mscause <= _T_264 @[el2_dec_tlu_ctl.scala 1755:11]
    node _T_265 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1762:63]
    node _T_266 = eq(_T_265, UInt<12>("h0343")) @[el2_dec_tlu_ctl.scala 1762:70]
    node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_266) @[el2_dec_tlu_ctl.scala 1762:41]
    node _T_267 = not(io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1763:84]
    node _T_268 = and(io.inst_acc_r, _T_267) @[el2_dec_tlu_ctl.scala 1763:82]
    node _T_269 = or(io.ebreak_r, _T_268) @[el2_dec_tlu_ctl.scala 1763:65]
    node _T_270 = or(_T_269, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1763:107]
    node _T_271 = and(io.exc_or_int_valid_r, _T_270) @[el2_dec_tlu_ctl.scala 1763:50]
    node _T_272 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1763:141]
    node mtval_capture_pc_r = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 1763:139]
    node _T_273 = and(io.inst_acc_r, io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1764:73]
    node _T_274 = and(io.exc_or_int_valid_r, _T_273) @[el2_dec_tlu_ctl.scala 1764:56]
    node _T_275 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1764:99]
    node mtval_capture_pc_plus2_r = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 1764:97]
    node _T_276 = and(io.exc_or_int_valid_r, io.illegal_r) @[el2_dec_tlu_ctl.scala 1765:52]
    node _T_277 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1765:69]
    node mtval_capture_inst_r = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 1765:67]
    node _T_278 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1766:51]
    node _T_279 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1766:74]
    node mtval_capture_lsu_r = and(_T_278, _T_279) @[el2_dec_tlu_ctl.scala 1766:72]
    node _T_280 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1767:47]
    node _T_281 = and(io.exc_or_int_valid_r, _T_280) @[el2_dec_tlu_ctl.scala 1767:45]
    node _T_282 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1767:69]
    node _T_283 = and(_T_281, _T_282) @[el2_dec_tlu_ctl.scala 1767:67]
    node _T_284 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1767:93]
    node _T_285 = and(_T_283, _T_284) @[el2_dec_tlu_ctl.scala 1767:91]
    node _T_286 = not(io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1767:116]
    node mtval_clear_r = and(_T_285, _T_286) @[el2_dec_tlu_ctl.scala 1767:114]
    node _T_287 = bits(mtval_capture_pc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1771:26]
    node _T_288 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_289 = bits(mtval_capture_pc_plus2_r, 0, 0) @[el2_dec_tlu_ctl.scala 1772:32]
    node _T_290 = add(pc_r, UInt<31>("h01")) @[el2_dec_tlu_ctl.scala 1772:84]
    node _T_291 = tail(_T_290, 1) @[el2_dec_tlu_ctl.scala 1772:84]
    node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_293 = bits(mtval_capture_inst_r, 0, 0) @[el2_dec_tlu_ctl.scala 1773:28]
    node _T_294 = bits(mtval_capture_lsu_r, 0, 0) @[el2_dec_tlu_ctl.scala 1774:27]
    node _T_295 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1775:19]
    node _T_296 = and(wr_mtval_r, _T_295) @[el2_dec_tlu_ctl.scala 1775:17]
    node _T_297 = bits(_T_296, 0, 0) @[el2_dec_tlu_ctl.scala 1775:49]
    node _T_298 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1776:6]
    node _T_299 = not(wr_mtval_r) @[el2_dec_tlu_ctl.scala 1776:21]
    node _T_300 = and(_T_298, _T_299) @[el2_dec_tlu_ctl.scala 1776:19]
    node _T_301 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1776:35]
    node _T_302 = and(_T_300, _T_301) @[el2_dec_tlu_ctl.scala 1776:33]
    node _T_303 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1776:57]
    node _T_304 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 1776:55]
    node _T_305 = not(mtval_clear_r) @[el2_dec_tlu_ctl.scala 1776:81]
    node _T_306 = and(_T_304, _T_305) @[el2_dec_tlu_ctl.scala 1776:79]
    node _T_307 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1776:98]
    node _T_308 = and(_T_306, _T_307) @[el2_dec_tlu_ctl.scala 1776:96]
    node _T_309 = bits(_T_308, 0, 0) @[el2_dec_tlu_ctl.scala 1776:120]
    node _T_310 = mux(_T_287, _T_288, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_311 = mux(_T_289, _T_292, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_312 = mux(_T_293, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_313 = mux(_T_294, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_314 = mux(_T_297, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_315 = mux(_T_309, mtval, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_316 = or(_T_310, _T_311) @[Mux.scala 27:72]
    node _T_317 = or(_T_316, _T_312) @[Mux.scala 27:72]
    node _T_318 = or(_T_317, _T_313) @[Mux.scala 27:72]
    node _T_319 = or(_T_318, _T_314) @[Mux.scala 27:72]
    node _T_320 = or(_T_319, _T_315) @[Mux.scala 27:72]
    wire mtval_ns : UInt<32> @[Mux.scala 27:72]
    mtval_ns <= _T_320 @[Mux.scala 27:72]
    reg _T_321 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1778:47]
    _T_321 <= mtval_ns @[el2_dec_tlu_ctl.scala 1778:47]
    mtval <= _T_321 @[el2_dec_tlu_ctl.scala 1778:9]
    node _T_322 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1793:62]
    node _T_323 = eq(_T_322, UInt<12>("h07f8")) @[el2_dec_tlu_ctl.scala 1793:69]
    node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_323) @[el2_dec_tlu_ctl.scala 1793:40]
    node _T_324 = bits(io.dec_csr_wrdata_r, 8, 0) @[el2_dec_tlu_ctl.scala 1795:40]
    node _T_325 = bits(wr_mcgc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1795:56]
    inst rvclkhdr_8 of rvclkhdr_16 @[el2_lib.scala 508:23]
    rvclkhdr_8.clock <= clock
    rvclkhdr_8.reset <= reset
    rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_8.io.en <= _T_325 @[el2_lib.scala 511:17]
    rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    mcgc <= _T_324 @[el2_lib.scala 514:16]
    node _T_326 = bits(mcgc, 8, 8) @[el2_dec_tlu_ctl.scala 1797:39]
    io.dec_tlu_misc_clk_override <= _T_326 @[el2_dec_tlu_ctl.scala 1797:32]
    node _T_327 = bits(mcgc, 7, 7) @[el2_dec_tlu_ctl.scala 1798:39]
    io.dec_tlu_dec_clk_override <= _T_327 @[el2_dec_tlu_ctl.scala 1798:32]
    node _T_328 = bits(mcgc, 5, 5) @[el2_dec_tlu_ctl.scala 1799:39]
    io.dec_tlu_ifu_clk_override <= _T_328 @[el2_dec_tlu_ctl.scala 1799:32]
    node _T_329 = bits(mcgc, 4, 4) @[el2_dec_tlu_ctl.scala 1800:39]
    io.dec_tlu_lsu_clk_override <= _T_329 @[el2_dec_tlu_ctl.scala 1800:32]
    node _T_330 = bits(mcgc, 3, 3) @[el2_dec_tlu_ctl.scala 1801:39]
    io.dec_tlu_bus_clk_override <= _T_330 @[el2_dec_tlu_ctl.scala 1801:32]
    node _T_331 = bits(mcgc, 2, 2) @[el2_dec_tlu_ctl.scala 1802:39]
    io.dec_tlu_pic_clk_override <= _T_331 @[el2_dec_tlu_ctl.scala 1802:32]
    node _T_332 = bits(mcgc, 1, 1) @[el2_dec_tlu_ctl.scala 1803:39]
    io.dec_tlu_dccm_clk_override <= _T_332 @[el2_dec_tlu_ctl.scala 1803:32]
    node _T_333 = bits(mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 1804:39]
    io.dec_tlu_icm_clk_override <= _T_333 @[el2_dec_tlu_ctl.scala 1804:32]
    node _T_334 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1823:62]
    node _T_335 = eq(_T_334, UInt<12>("h07f9")) @[el2_dec_tlu_ctl.scala 1823:69]
    node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_335) @[el2_dec_tlu_ctl.scala 1823:40]
    node _T_336 = bits(wr_mfdc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1827:40]
    inst rvclkhdr_9 of rvclkhdr_17 @[el2_lib.scala 508:23]
    rvclkhdr_9.clock <= clock
    rvclkhdr_9.reset <= reset
    rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_9.io.en <= _T_336 @[el2_lib.scala 511:17]
    rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_337 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_337 <= mfdc_ns @[el2_lib.scala 514:16]
    mfdc_int <= _T_337 @[el2_dec_tlu_ctl.scala 1827:12]
    node _T_338 = bits(io.dec_csr_wrdata_r, 18, 16) @[el2_dec_tlu_ctl.scala 1832:40]
    node _T_339 = not(_T_338) @[el2_dec_tlu_ctl.scala 1832:20]
    node _T_340 = bits(io.dec_csr_wrdata_r, 11, 7) @[el2_dec_tlu_ctl.scala 1832:67]
    node _T_341 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1832:95]
    node _T_342 = not(_T_341) @[el2_dec_tlu_ctl.scala 1832:75]
    node _T_343 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1832:119]
    node _T_344 = cat(_T_342, _T_343) @[Cat.scala 29:58]
    node _T_345 = cat(_T_339, _T_340) @[Cat.scala 29:58]
    node _T_346 = cat(_T_345, _T_344) @[Cat.scala 29:58]
    mfdc_ns <= _T_346 @[el2_dec_tlu_ctl.scala 1832:13]
    node _T_347 = bits(mfdc_int, 14, 12) @[el2_dec_tlu_ctl.scala 1833:29]
    node _T_348 = not(_T_347) @[el2_dec_tlu_ctl.scala 1833:20]
    node _T_349 = bits(mfdc_int, 11, 7) @[el2_dec_tlu_ctl.scala 1833:55]
    node _T_350 = bits(mfdc_int, 6, 6) @[el2_dec_tlu_ctl.scala 1833:72]
    node _T_351 = not(_T_350) @[el2_dec_tlu_ctl.scala 1833:63]
    node _T_352 = bits(mfdc_int, 5, 0) @[el2_dec_tlu_ctl.scala 1833:85]
    node _T_353 = cat(_T_351, _T_352) @[Cat.scala 29:58]
    node _T_354 = cat(_T_348, UInt<4>("h00")) @[Cat.scala 29:58]
    node _T_355 = cat(_T_354, _T_349) @[Cat.scala 29:58]
    node _T_356 = cat(_T_355, _T_353) @[Cat.scala 29:58]
    mfdc <= _T_356 @[el2_dec_tlu_ctl.scala 1833:13]
    node _T_357 = bits(mfdc, 18, 16) @[el2_dec_tlu_ctl.scala 1841:47]
    io.dec_tlu_dma_qos_prty <= _T_357 @[el2_dec_tlu_ctl.scala 1841:40]
    node _T_358 = bits(mfdc, 11, 11) @[el2_dec_tlu_ctl.scala 1842:47]
    io.dec_tlu_external_ldfwd_disable <= _T_358 @[el2_dec_tlu_ctl.scala 1842:40]
    node _T_359 = bits(mfdc, 8, 8) @[el2_dec_tlu_ctl.scala 1843:47]
    io.dec_tlu_core_ecc_disable <= _T_359 @[el2_dec_tlu_ctl.scala 1843:40]
    node _T_360 = bits(mfdc, 6, 6) @[el2_dec_tlu_ctl.scala 1844:47]
    io.dec_tlu_sideeffect_posted_disable <= _T_360 @[el2_dec_tlu_ctl.scala 1844:40]
    node _T_361 = bits(mfdc, 3, 3) @[el2_dec_tlu_ctl.scala 1845:47]
    io.dec_tlu_bpred_disable <= _T_361 @[el2_dec_tlu_ctl.scala 1845:40]
    node _T_362 = bits(mfdc, 2, 2) @[el2_dec_tlu_ctl.scala 1846:47]
    io.dec_tlu_wb_coalescing_disable <= _T_362 @[el2_dec_tlu_ctl.scala 1846:40]
    node _T_363 = bits(mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 1847:47]
    io.dec_tlu_pipelining_disable <= _T_363 @[el2_dec_tlu_ctl.scala 1847:40]
    node _T_364 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1856:71]
    node _T_365 = eq(_T_364, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 1856:78]
    node _T_366 = and(io.dec_csr_wen_r_mod, _T_365) @[el2_dec_tlu_ctl.scala 1856:49]
    node _T_367 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1856:90]
    node _T_368 = and(_T_366, _T_367) @[el2_dec_tlu_ctl.scala 1856:88]
    node _T_369 = not(io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 1856:114]
    node _T_370 = and(_T_368, _T_369) @[el2_dec_tlu_ctl.scala 1856:112]
    io.dec_tlu_wr_pause_r <= _T_370 @[el2_dec_tlu_ctl.scala 1856:25]
    node _T_371 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1863:62]
    node _T_372 = eq(_T_371, UInt<12>("h07c0")) @[el2_dec_tlu_ctl.scala 1863:69]
    node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_372) @[el2_dec_tlu_ctl.scala 1863:40]
    node _T_373 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:40]
    node _T_374 = bits(io.dec_csr_wrdata_r, 30, 30) @[el2_dec_tlu_ctl.scala 1866:65]
    node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:92]
    node _T_376 = not(_T_375) @[el2_dec_tlu_ctl.scala 1866:72]
    node _T_377 = and(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 1866:70]
    node _T_378 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:24]
    node _T_379 = bits(io.dec_csr_wrdata_r, 28, 28) @[el2_dec_tlu_ctl.scala 1867:49]
    node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:76]
    node _T_381 = not(_T_380) @[el2_dec_tlu_ctl.scala 1867:56]
    node _T_382 = and(_T_379, _T_381) @[el2_dec_tlu_ctl.scala 1867:54]
    node _T_383 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:24]
    node _T_384 = bits(io.dec_csr_wrdata_r, 26, 26) @[el2_dec_tlu_ctl.scala 1868:49]
    node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:76]
    node _T_386 = not(_T_385) @[el2_dec_tlu_ctl.scala 1868:56]
    node _T_387 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 1868:54]
    node _T_388 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:24]
    node _T_389 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 1869:49]
    node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:76]
    node _T_391 = not(_T_390) @[el2_dec_tlu_ctl.scala 1869:56]
    node _T_392 = and(_T_389, _T_391) @[el2_dec_tlu_ctl.scala 1869:54]
    node _T_393 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:24]
    node _T_394 = bits(io.dec_csr_wrdata_r, 22, 22) @[el2_dec_tlu_ctl.scala 1870:49]
    node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:76]
    node _T_396 = not(_T_395) @[el2_dec_tlu_ctl.scala 1870:56]
    node _T_397 = and(_T_394, _T_396) @[el2_dec_tlu_ctl.scala 1870:54]
    node _T_398 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:24]
    node _T_399 = bits(io.dec_csr_wrdata_r, 20, 20) @[el2_dec_tlu_ctl.scala 1871:49]
    node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:76]
    node _T_401 = not(_T_400) @[el2_dec_tlu_ctl.scala 1871:56]
    node _T_402 = and(_T_399, _T_401) @[el2_dec_tlu_ctl.scala 1871:54]
    node _T_403 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:24]
    node _T_404 = bits(io.dec_csr_wrdata_r, 18, 18) @[el2_dec_tlu_ctl.scala 1872:49]
    node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:76]
    node _T_406 = not(_T_405) @[el2_dec_tlu_ctl.scala 1872:56]
    node _T_407 = and(_T_404, _T_406) @[el2_dec_tlu_ctl.scala 1872:54]
    node _T_408 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:24]
    node _T_409 = bits(io.dec_csr_wrdata_r, 16, 16) @[el2_dec_tlu_ctl.scala 1873:49]
    node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:76]
    node _T_411 = not(_T_410) @[el2_dec_tlu_ctl.scala 1873:56]
    node _T_412 = and(_T_409, _T_411) @[el2_dec_tlu_ctl.scala 1873:54]
    node _T_413 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:24]
    node _T_414 = bits(io.dec_csr_wrdata_r, 14, 14) @[el2_dec_tlu_ctl.scala 1874:49]
    node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:76]
    node _T_416 = not(_T_415) @[el2_dec_tlu_ctl.scala 1874:56]
    node _T_417 = and(_T_414, _T_416) @[el2_dec_tlu_ctl.scala 1874:54]
    node _T_418 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:24]
    node _T_419 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 1875:49]
    node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:76]
    node _T_421 = not(_T_420) @[el2_dec_tlu_ctl.scala 1875:56]
    node _T_422 = and(_T_419, _T_421) @[el2_dec_tlu_ctl.scala 1875:54]
    node _T_423 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:24]
    node _T_424 = bits(io.dec_csr_wrdata_r, 10, 10) @[el2_dec_tlu_ctl.scala 1876:49]
    node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:76]
    node _T_426 = not(_T_425) @[el2_dec_tlu_ctl.scala 1876:56]
    node _T_427 = and(_T_424, _T_426) @[el2_dec_tlu_ctl.scala 1876:54]
    node _T_428 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:24]
    node _T_429 = bits(io.dec_csr_wrdata_r, 8, 8) @[el2_dec_tlu_ctl.scala 1877:49]
    node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:76]
    node _T_431 = not(_T_430) @[el2_dec_tlu_ctl.scala 1877:56]
    node _T_432 = and(_T_429, _T_431) @[el2_dec_tlu_ctl.scala 1877:53]
    node _T_433 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:24]
    node _T_434 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1878:49]
    node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:76]
    node _T_436 = not(_T_435) @[el2_dec_tlu_ctl.scala 1878:56]
    node _T_437 = and(_T_434, _T_436) @[el2_dec_tlu_ctl.scala 1878:53]
    node _T_438 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:24]
    node _T_439 = bits(io.dec_csr_wrdata_r, 4, 4) @[el2_dec_tlu_ctl.scala 1879:49]
    node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:76]
    node _T_441 = not(_T_440) @[el2_dec_tlu_ctl.scala 1879:56]
    node _T_442 = and(_T_439, _T_441) @[el2_dec_tlu_ctl.scala 1879:53]
    node _T_443 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:24]
    node _T_444 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 1880:49]
    node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:76]
    node _T_446 = not(_T_445) @[el2_dec_tlu_ctl.scala 1880:56]
    node _T_447 = and(_T_444, _T_446) @[el2_dec_tlu_ctl.scala 1880:53]
    node _T_448 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:24]
    node _T_449 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1881:49]
    node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:76]
    node _T_451 = not(_T_450) @[el2_dec_tlu_ctl.scala 1881:56]
    node _T_452 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 1881:53]
    node _T_453 = cat(_T_448, _T_452) @[Cat.scala 29:58]
    node _T_454 = cat(_T_443, _T_447) @[Cat.scala 29:58]
    node _T_455 = cat(_T_454, _T_453) @[Cat.scala 29:58]
    node _T_456 = cat(_T_438, _T_442) @[Cat.scala 29:58]
    node _T_457 = cat(_T_433, _T_437) @[Cat.scala 29:58]
    node _T_458 = cat(_T_457, _T_456) @[Cat.scala 29:58]
    node _T_459 = cat(_T_458, _T_455) @[Cat.scala 29:58]
    node _T_460 = cat(_T_428, _T_432) @[Cat.scala 29:58]
    node _T_461 = cat(_T_423, _T_427) @[Cat.scala 29:58]
    node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58]
    node _T_463 = cat(_T_418, _T_422) @[Cat.scala 29:58]
    node _T_464 = cat(_T_413, _T_417) @[Cat.scala 29:58]
    node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58]
    node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58]
    node _T_467 = cat(_T_466, _T_459) @[Cat.scala 29:58]
    node _T_468 = cat(_T_408, _T_412) @[Cat.scala 29:58]
    node _T_469 = cat(_T_403, _T_407) @[Cat.scala 29:58]
    node _T_470 = cat(_T_469, _T_468) @[Cat.scala 29:58]
    node _T_471 = cat(_T_398, _T_402) @[Cat.scala 29:58]
    node _T_472 = cat(_T_393, _T_397) @[Cat.scala 29:58]
    node _T_473 = cat(_T_472, _T_471) @[Cat.scala 29:58]
    node _T_474 = cat(_T_473, _T_470) @[Cat.scala 29:58]
    node _T_475 = cat(_T_388, _T_392) @[Cat.scala 29:58]
    node _T_476 = cat(_T_383, _T_387) @[Cat.scala 29:58]
    node _T_477 = cat(_T_476, _T_475) @[Cat.scala 29:58]
    node _T_478 = cat(_T_378, _T_382) @[Cat.scala 29:58]
    node _T_479 = cat(_T_373, _T_377) @[Cat.scala 29:58]
    node _T_480 = cat(_T_479, _T_478) @[Cat.scala 29:58]
    node _T_481 = cat(_T_480, _T_477) @[Cat.scala 29:58]
    node _T_482 = cat(_T_481, _T_474) @[Cat.scala 29:58]
    node mrac_in = cat(_T_482, _T_467) @[Cat.scala 29:58]
    node _T_483 = bits(wr_mrac_r, 0, 0) @[el2_dec_tlu_ctl.scala 1884:39]
    inst rvclkhdr_10 of rvclkhdr_18 @[el2_lib.scala 508:23]
    rvclkhdr_10.clock <= clock
    rvclkhdr_10.reset <= reset
    rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_10.io.en <= _T_483 @[el2_lib.scala 511:17]
    rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    mrac <= mrac_in @[el2_lib.scala 514:16]
    io.dec_tlu_mrac_ff <= mrac @[el2_dec_tlu_ctl.scala 1886:22]
    node _T_484 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1894:63]
    node _T_485 = eq(_T_484, UInt<12>("h0bc0")) @[el2_dec_tlu_ctl.scala 1894:70]
    node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_485) @[el2_dec_tlu_ctl.scala 1894:41]
    node _T_486 = not(wr_mdeau_r) @[el2_dec_tlu_ctl.scala 1904:60]
    node _T_487 = and(io.mdseac_locked_f, _T_486) @[el2_dec_tlu_ctl.scala 1904:58]
    node _T_488 = or(mdseac_en, _T_487) @[el2_dec_tlu_ctl.scala 1904:36]
    io.mdseac_locked_ns <= _T_488 @[el2_dec_tlu_ctl.scala 1904:23]
    node _T_489 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 1906:50]
    node _T_490 = not(io.nmi_int_detected_f) @[el2_dec_tlu_ctl.scala 1906:87]
    node _T_491 = and(_T_489, _T_490) @[el2_dec_tlu_ctl.scala 1906:85]
    node _T_492 = not(io.mdseac_locked_f) @[el2_dec_tlu_ctl.scala 1906:112]
    node _T_493 = and(_T_491, _T_492) @[el2_dec_tlu_ctl.scala 1906:110]
    mdseac_en <= _T_493 @[el2_dec_tlu_ctl.scala 1906:13]
    node _T_494 = bits(mdseac_en, 0, 0) @[el2_dec_tlu_ctl.scala 1908:65]
    inst rvclkhdr_11 of rvclkhdr_19 @[el2_lib.scala 508:23]
    rvclkhdr_11.clock <= clock
    rvclkhdr_11.reset <= reset
    rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_11.io.en <= _T_494 @[el2_lib.scala 511:17]
    rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    mdseac <= io.lsu_imprecise_error_addr_any @[el2_lib.scala 514:16]
    node _T_495 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1917:62]
    node _T_496 = eq(_T_495, UInt<12>("h07c6")) @[el2_dec_tlu_ctl.scala 1917:69]
    node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_496) @[el2_dec_tlu_ctl.scala 1917:40]
    node _T_497 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1921:52]
    node _T_498 = and(wr_mpmc_r, _T_497) @[el2_dec_tlu_ctl.scala 1921:31]
    node _T_499 = not(io.internal_dbg_halt_mode_f2) @[el2_dec_tlu_ctl.scala 1921:58]
    node _T_500 = and(_T_498, _T_499) @[el2_dec_tlu_ctl.scala 1921:56]
    node _T_501 = not(io.ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 1921:90]
    node _T_502 = and(_T_500, _T_501) @[el2_dec_tlu_ctl.scala 1921:88]
    io.fw_halt_req <= _T_502 @[el2_dec_tlu_ctl.scala 1921:18]
    node _T_503 = or(io.fw_halt_req, fw_halted) @[el2_dec_tlu_ctl.scala 1923:38]
    node _T_504 = not(set_mie_pmu_fw_halt) @[el2_dec_tlu_ctl.scala 1923:53]
    node fw_halted_ns = and(_T_503, _T_504) @[el2_dec_tlu_ctl.scala 1923:51]
    node _T_505 = bits(wr_mpmc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1924:30]
    node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1924:58]
    node _T_507 = not(_T_506) @[el2_dec_tlu_ctl.scala 1924:38]
    node _T_508 = not(mpmc) @[el2_dec_tlu_ctl.scala 1924:63]
    node _T_509 = mux(_T_505, _T_507, _T_508) @[el2_dec_tlu_ctl.scala 1924:19]
    mpmc_b_ns <= _T_509 @[el2_dec_tlu_ctl.scala 1924:13]
    reg _T_510 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1926:45]
    _T_510 <= mpmc_b_ns @[el2_dec_tlu_ctl.scala 1926:45]
    mpmc_b <= _T_510 @[el2_dec_tlu_ctl.scala 1926:10]
    reg _T_511 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1927:46]
    _T_511 <= fw_halted_ns @[el2_dec_tlu_ctl.scala 1927:46]
    fw_halted <= _T_511 @[el2_dec_tlu_ctl.scala 1927:13]
    node _T_512 = not(mpmc_b) @[el2_dec_tlu_ctl.scala 1929:11]
    mpmc <= _T_512 @[el2_dec_tlu_ctl.scala 1929:8]
    node _T_513 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:41]
    node _T_514 = gt(_T_513, UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 1938:49]
    node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:93]
    node csr_sat = mux(_T_514, UInt<5>("h01a"), _T_515) @[el2_dec_tlu_ctl.scala 1938:20]
    node _T_516 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1940:64]
    node _T_517 = eq(_T_516, UInt<12>("h07f0")) @[el2_dec_tlu_ctl.scala 1940:71]
    node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_517) @[el2_dec_tlu_ctl.scala 1940:42]
    node _T_518 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58]
    node _T_519 = add(micect, _T_518) @[el2_dec_tlu_ctl.scala 1941:24]
    node _T_520 = tail(_T_519, 1) @[el2_dec_tlu_ctl.scala 1941:24]
    micect_inc <= _T_520 @[el2_dec_tlu_ctl.scala 1941:14]
    node _T_521 = bits(wr_micect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1942:36]
    node _T_522 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1942:76]
    node _T_523 = cat(csr_sat, _T_522) @[Cat.scala 29:58]
    node _T_524 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1942:96]
    node _T_525 = cat(_T_524, micect_inc) @[Cat.scala 29:58]
    node micect_ns = mux(_T_521, _T_523, _T_525) @[el2_dec_tlu_ctl.scala 1942:23]
    node _T_526 = or(wr_micect_r, io.ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 1944:43]
    node _T_527 = bits(_T_526, 0, 0) @[el2_dec_tlu_ctl.scala 1944:62]
    inst rvclkhdr_12 of rvclkhdr_20 @[el2_lib.scala 508:23]
    rvclkhdr_12.clock <= clock
    rvclkhdr_12.reset <= reset
    rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_12.io.en <= _T_527 @[el2_lib.scala 511:17]
    rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_528 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_528 <= micect_ns @[el2_lib.scala 514:16]
    micect <= _T_528 @[el2_dec_tlu_ctl.scala 1944:10]
    node _T_529 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1946:48]
    node _T_530 = dshl(UInt<32>("h0ffffffff"), _T_529) @[el2_dec_tlu_ctl.scala 1946:39]
    node _T_531 = orr(_T_530) @[el2_dec_tlu_ctl.scala 1946:57]
    node _T_532 = bits(micect, 26, 0) @[el2_dec_tlu_ctl.scala 1946:83]
    node _T_533 = cat(UInt<5>("h00"), _T_532) @[Cat.scala 29:58]
    node _T_534 = and(_T_531, _T_533) @[el2_dec_tlu_ctl.scala 1946:61]
    mice_ce_req <= _T_534 @[el2_dec_tlu_ctl.scala 1946:15]
    node _T_535 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1955:70]
    node _T_536 = eq(_T_535, UInt<12>("h07f1")) @[el2_dec_tlu_ctl.scala 1955:77]
    node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_536) @[el2_dec_tlu_ctl.scala 1955:48]
    node _T_537 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1956:27]
    node _T_538 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1956:71]
    node _T_539 = cat(UInt<26>("h00"), _T_538) @[Cat.scala 29:58]
    node _T_540 = add(_T_537, _T_539) @[el2_dec_tlu_ctl.scala 1956:34]
    node _T_541 = tail(_T_540, 1) @[el2_dec_tlu_ctl.scala 1956:34]
    miccmect_inc <= _T_541 @[el2_dec_tlu_ctl.scala 1956:16]
    node _T_542 = bits(wr_miccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1957:46]
    node _T_543 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1957:86]
    node _T_544 = cat(csr_sat, _T_543) @[Cat.scala 29:58]
    node _T_545 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1957:108]
    node _T_546 = cat(_T_545, miccmect_inc) @[Cat.scala 29:58]
    node miccmect_ns = mux(_T_542, _T_544, _T_546) @[el2_dec_tlu_ctl.scala 1957:31]
    node _T_547 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 1959:49]
    node _T_548 = or(_T_547, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1959:70]
    node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 1959:94]
    inst rvclkhdr_13 of rvclkhdr_21 @[el2_lib.scala 508:23]
    rvclkhdr_13.clock <= clock
    rvclkhdr_13.reset <= reset
    rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_13.io.en <= _T_549 @[el2_lib.scala 511:17]
    rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_550 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_550 <= miccmect_ns @[el2_lib.scala 514:16]
    miccmect <= _T_550 @[el2_dec_tlu_ctl.scala 1959:12]
    node _T_551 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1960:53]
    node _T_552 = dshl(UInt<32>("h0ffffffff"), _T_551) @[el2_dec_tlu_ctl.scala 1960:42]
    node _T_553 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1960:86]
    node _T_554 = cat(UInt<5>("h00"), _T_553) @[Cat.scala 29:58]
    node _T_555 = and(_T_552, _T_554) @[el2_dec_tlu_ctl.scala 1960:62]
    node _T_556 = orr(_T_555) @[el2_dec_tlu_ctl.scala 1960:95]
    miccme_ce_req <= _T_556 @[el2_dec_tlu_ctl.scala 1960:17]
    node _T_557 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1969:70]
    node _T_558 = eq(_T_557, UInt<12>("h07f2")) @[el2_dec_tlu_ctl.scala 1969:77]
    node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_558) @[el2_dec_tlu_ctl.scala 1969:48]
    node _T_559 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1970:27]
    node _T_560 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58]
    node _T_561 = add(_T_559, _T_560) @[el2_dec_tlu_ctl.scala 1970:34]
    node _T_562 = tail(_T_561, 1) @[el2_dec_tlu_ctl.scala 1970:34]
    mdccmect_inc <= _T_562 @[el2_dec_tlu_ctl.scala 1970:16]
    node _T_563 = bits(wr_mdccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1971:46]
    node _T_564 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1971:86]
    node _T_565 = cat(csr_sat, _T_564) @[Cat.scala 29:58]
    node _T_566 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1971:108]
    node _T_567 = cat(_T_566, mdccmect_inc) @[Cat.scala 29:58]
    node mdccmect_ns = mux(_T_563, _T_565, _T_567) @[el2_dec_tlu_ctl.scala 1971:31]
    node _T_568 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[el2_dec_tlu_ctl.scala 1973:50]
    node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 1973:82]
    inst rvclkhdr_14 of rvclkhdr_22 @[el2_lib.scala 508:23]
    rvclkhdr_14.clock <= clock
    rvclkhdr_14.reset <= reset
    rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_14.io.en <= _T_569 @[el2_lib.scala 511:17]
    rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_570 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_570 <= mdccmect_ns @[el2_lib.scala 514:16]
    mdccmect <= _T_570 @[el2_dec_tlu_ctl.scala 1973:12]
    node _T_571 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1975:53]
    node _T_572 = dshl(UInt<32>("h0ffffffff"), _T_571) @[el2_dec_tlu_ctl.scala 1975:42]
    node _T_573 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1975:86]
    node _T_574 = cat(UInt<5>("h00"), _T_573) @[Cat.scala 29:58]
    node _T_575 = and(_T_572, _T_574) @[el2_dec_tlu_ctl.scala 1975:62]
    node _T_576 = orr(_T_575) @[el2_dec_tlu_ctl.scala 1975:95]
    mdccme_ce_req <= _T_576 @[el2_dec_tlu_ctl.scala 1975:17]
    node _T_577 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1985:63]
    node _T_578 = eq(_T_577, UInt<12>("h07ce")) @[el2_dec_tlu_ctl.scala 1985:70]
    node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_578) @[el2_dec_tlu_ctl.scala 1985:41]
    node _T_579 = bits(wr_mfdht_r, 0, 0) @[el2_dec_tlu_ctl.scala 1987:33]
    node _T_580 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1987:60]
    node mfdht_ns = mux(_T_579, _T_580, mfdht) @[el2_dec_tlu_ctl.scala 1987:21]
    reg _T_581 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1989:44]
    _T_581 <= mfdht_ns @[el2_dec_tlu_ctl.scala 1989:44]
    mfdht <= _T_581 @[el2_dec_tlu_ctl.scala 1989:9]
    node _T_582 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1998:63]
    node _T_583 = eq(_T_582, UInt<12>("h07cf")) @[el2_dec_tlu_ctl.scala 1998:70]
    node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_583) @[el2_dec_tlu_ctl.scala 1998:41]
    node _T_584 = bits(wr_mfdhs_r, 0, 0) @[el2_dec_tlu_ctl.scala 2000:33]
    node _T_585 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2000:61]
    node _T_586 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2001:30]
    node _T_587 = and(io.dbg_tlu_halted, _T_586) @[el2_dec_tlu_ctl.scala 2001:28]
    node _T_588 = bits(_T_587, 0, 0) @[el2_dec_tlu_ctl.scala 2001:52]
    node _T_589 = not(io.lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 2001:65]
    node _T_590 = not(io.ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 2001:85]
    node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58]
    node _T_592 = mux(_T_588, _T_591, mfdhs) @[el2_dec_tlu_ctl.scala 2001:8]
    node mfdhs_ns = mux(_T_584, _T_585, _T_592) @[el2_dec_tlu_ctl.scala 2000:21]
    node _T_593 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2003:72]
    node _T_594 = bits(_T_593, 0, 0) @[el2_dec_tlu_ctl.scala 2003:93]
    reg _T_595 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_594 : @[Reg.scala 28:19]
      _T_595 <= mfdhs_ns @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    mfdhs <= _T_595 @[el2_dec_tlu_ctl.scala 2003:9]
    node _T_596 = bits(io.debug_halt_req_f, 0, 0) @[el2_dec_tlu_ctl.scala 2005:48]
    node _T_597 = add(force_halt_ctr_f, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2005:75]
    node _T_598 = tail(_T_597, 1) @[el2_dec_tlu_ctl.scala 2005:75]
    node _T_599 = bits(io.dbg_tlu_halted_f, 0, 0) @[el2_dec_tlu_ctl.scala 2006:29]
    node _T_600 = mux(_T_599, UInt<32>("h00"), force_halt_ctr_f) @[el2_dec_tlu_ctl.scala 2006:8]
    node force_halt_ctr = mux(_T_596, _T_598, _T_600) @[el2_dec_tlu_ctl.scala 2005:27]
    node _T_601 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2008:82]
    reg _T_602 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_601 : @[Reg.scala 28:19]
      _T_602 <= force_halt_ctr @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    force_halt_ctr_f <= _T_602 @[el2_dec_tlu_ctl.scala 2008:20]
    node _T_603 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2010:25]
    node _T_604 = bits(mfdht, 5, 1) @[el2_dec_tlu_ctl.scala 2010:80]
    node _T_605 = dshl(UInt<32>("h0ffffffff"), _T_604) @[el2_dec_tlu_ctl.scala 2010:72]
    node _T_606 = and(force_halt_ctr_f, _T_605) @[el2_dec_tlu_ctl.scala 2010:49]
    node _T_607 = orr(_T_606) @[el2_dec_tlu_ctl.scala 2010:88]
    node _T_608 = and(_T_603, _T_607) @[el2_dec_tlu_ctl.scala 2010:29]
    io.force_halt <= _T_608 @[el2_dec_tlu_ctl.scala 2010:17]
    node _T_609 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2018:63]
    node _T_610 = eq(_T_609, UInt<12>("h0bc8")) @[el2_dec_tlu_ctl.scala 2018:70]
    node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_610) @[el2_dec_tlu_ctl.scala 2018:41]
    node _T_611 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2020:41]
    node _T_612 = bits(wr_meivt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2020:60]
    inst rvclkhdr_15 of rvclkhdr_23 @[el2_lib.scala 508:23]
    rvclkhdr_15.clock <= clock
    rvclkhdr_15.reset <= reset
    rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_15.io.en <= _T_612 @[el2_lib.scala 511:17]
    rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    meivt <= _T_611 @[el2_lib.scala 514:16]
    node _T_613 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2032:50]
    inst rvclkhdr_16 of rvclkhdr_24 @[el2_lib.scala 508:23]
    rvclkhdr_16.clock <= clock
    rvclkhdr_16.reset <= reset
    rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_16.io.en <= _T_613 @[el2_lib.scala 511:17]
    rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    meihap <= io.pic_claimid @[el2_lib.scala 514:16]
    node _T_614 = cat(meivt, meihap) @[Cat.scala 29:58]
    node _T_615 = cat(_T_614, UInt<2>("h00")) @[Cat.scala 29:58]
    io.dec_tlu_meihap <= _T_615 @[el2_dec_tlu_ctl.scala 2033:21]
    node _T_616 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2042:66]
    node _T_617 = eq(_T_616, UInt<12>("h0bcc")) @[el2_dec_tlu_ctl.scala 2042:73]
    node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_617) @[el2_dec_tlu_ctl.scala 2042:44]
    node _T_618 = bits(wr_meicurpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2043:39]
    node _T_619 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2043:66]
    node meicurpl_ns = mux(_T_618, _T_619, meicurpl) @[el2_dec_tlu_ctl.scala 2043:24]
    reg _T_620 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2045:47]
    _T_620 <= meicurpl_ns @[el2_dec_tlu_ctl.scala 2045:47]
    meicurpl <= _T_620 @[el2_dec_tlu_ctl.scala 2045:12]
    io.dec_tlu_meicurpl <= meicurpl @[el2_dec_tlu_ctl.scala 2047:23]
    node _T_621 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2057:67]
    node _T_622 = eq(_T_621, UInt<12>("h0bcb")) @[el2_dec_tlu_ctl.scala 2057:74]
    node _T_623 = and(io.dec_csr_wen_r_mod, _T_622) @[el2_dec_tlu_ctl.scala 2057:45]
    node wr_meicidpl_r = or(_T_623, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2057:89]
    node _T_624 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2059:38]
    node _T_625 = bits(wr_meicidpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2060:23]
    node _T_626 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2060:50]
    node _T_627 = mux(_T_625, _T_626, meicidpl) @[el2_dec_tlu_ctl.scala 2060:8]
    node meicidpl_ns = mux(_T_624, io.pic_pl, _T_627) @[el2_dec_tlu_ctl.scala 2059:24]
    reg _T_628 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2062:45]
    _T_628 <= meicidpl_ns @[el2_dec_tlu_ctl.scala 2062:45]
    meicidpl <= _T_628 @[el2_dec_tlu_ctl.scala 2062:12]
    node _T_629 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2069:63]
    node _T_630 = eq(_T_629, UInt<12>("h0bca")) @[el2_dec_tlu_ctl.scala 2069:70]
    node _T_631 = and(io.dec_csr_wen_r_mod, _T_630) @[el2_dec_tlu_ctl.scala 2069:41]
    node _T_632 = or(_T_631, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2069:84]
    wr_meicpct_r <= _T_632 @[el2_dec_tlu_ctl.scala 2069:16]
    node _T_633 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2078:63]
    node _T_634 = eq(_T_633, UInt<12>("h0bc9")) @[el2_dec_tlu_ctl.scala 2078:70]
    node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_634) @[el2_dec_tlu_ctl.scala 2078:41]
    node _T_635 = bits(wr_meipt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2079:33]
    node _T_636 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2079:60]
    node meipt_ns = mux(_T_635, _T_636, meipt) @[el2_dec_tlu_ctl.scala 2079:21]
    reg _T_637 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2081:44]
    _T_637 <= meipt_ns @[el2_dec_tlu_ctl.scala 2081:44]
    meipt <= _T_637 @[el2_dec_tlu_ctl.scala 2081:9]
    io.dec_tlu_meipt <= meipt @[el2_dec_tlu_ctl.scala 2083:20]
    node _T_638 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 2109:90]
    node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_638) @[el2_dec_tlu_ctl.scala 2109:67]
    node _T_639 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2112:35]
    node _T_640 = and(io.dcsr_single_step_done_f, _T_639) @[el2_dec_tlu_ctl.scala 2112:33]
    node _T_641 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2112:67]
    node _T_642 = and(_T_640, _T_641) @[el2_dec_tlu_ctl.scala 2112:65]
    node _T_643 = not(io.debug_halt_req) @[el2_dec_tlu_ctl.scala 2112:102]
    node _T_644 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2112:100]
    node _T_645 = bits(_T_644, 0, 0) @[el2_dec_tlu_ctl.scala 2112:122]
    node _T_646 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2113:26]
    node _T_647 = and(io.debug_halt_req, _T_646) @[el2_dec_tlu_ctl.scala 2113:24]
    node _T_648 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2113:58]
    node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 2113:56]
    node _T_650 = bits(_T_649, 0, 0) @[el2_dec_tlu_ctl.scala 2113:92]
    node _T_651 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2114:37]
    node _T_652 = and(io.ebreak_to_debug_mode_r_d1, _T_651) @[el2_dec_tlu_ctl.scala 2114:35]
    node _T_653 = bits(_T_652, 0, 0) @[el2_dec_tlu_ctl.scala 2114:71]
    node _T_654 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[el2_dec_tlu_ctl.scala 2115:39]
    node _T_655 = mux(_T_645, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_656 = mux(_T_650, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_657 = mux(_T_653, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_658 = mux(_T_654, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_659 = or(_T_655, _T_656) @[Mux.scala 27:72]
    node _T_660 = or(_T_659, _T_657) @[Mux.scala 27:72]
    node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72]
    wire dcsr_cause : UInt<3> @[Mux.scala 27:72]
    dcsr_cause <= _T_661 @[Mux.scala 27:72]
    node _T_662 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2117:47]
    node _T_663 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2117:92]
    node _T_664 = eq(_T_663, UInt<12>("h07b0")) @[el2_dec_tlu_ctl.scala 2117:99]
    node wr_dcsr_r = and(_T_662, _T_664) @[el2_dec_tlu_ctl.scala 2117:70]
    node _T_665 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2123:70]
    node _T_666 = eq(_T_665, UInt<3>("h03")) @[el2_dec_tlu_ctl.scala 2123:76]
    node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_666) @[el2_dec_tlu_ctl.scala 2123:60]
    node _T_667 = not(io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2124:60]
    node _T_668 = or(_T_667, dcsr_cause_upgradeable) @[el2_dec_tlu_ctl.scala 2124:79]
    node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_668) @[el2_dec_tlu_ctl.scala 2124:57]
    node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[el2_dec_tlu_ctl.scala 2126:49]
    node _T_669 = bits(enter_debug_halt_req_le, 0, 0) @[el2_dec_tlu_ctl.scala 2127:45]
    node _T_670 = bits(io.dcsr, 15, 9) @[el2_dec_tlu_ctl.scala 2127:65]
    node _T_671 = bits(io.dcsr, 5, 2) @[el2_dec_tlu_ctl.scala 2127:92]
    node _T_672 = cat(_T_671, UInt<2>("h03")) @[Cat.scala 29:58]
    node _T_673 = cat(_T_670, dcsr_cause) @[Cat.scala 29:58]
    node _T_674 = cat(_T_673, _T_672) @[Cat.scala 29:58]
    node _T_675 = bits(wr_dcsr_r, 0, 0) @[el2_dec_tlu_ctl.scala 2128:19]
    node _T_676 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 2128:50]
    node _T_677 = bits(io.dec_csr_wrdata_r, 11, 10) @[el2_dec_tlu_ctl.scala 2128:85]
    node _T_678 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2128:111]
    node _T_679 = bits(io.dcsr, 3, 3) @[el2_dec_tlu_ctl.scala 2128:155]
    node _T_680 = or(nmi_in_debug_mode, _T_679) @[el2_dec_tlu_ctl.scala 2128:146]
    node _T_681 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2128:179]
    node _T_682 = cat(_T_681, UInt<2>("h03")) @[Cat.scala 29:58]
    node _T_683 = cat(UInt<2>("h00"), _T_680) @[Cat.scala 29:58]
    node _T_684 = cat(_T_683, _T_682) @[Cat.scala 29:58]
    node _T_685 = cat(UInt<1>("h00"), _T_678) @[Cat.scala 29:58]
    node _T_686 = cat(_T_676, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_687 = cat(_T_686, _T_677) @[Cat.scala 29:58]
    node _T_688 = cat(_T_687, _T_685) @[Cat.scala 29:58]
    node _T_689 = cat(_T_688, _T_684) @[Cat.scala 29:58]
    node _T_690 = bits(io.dcsr, 15, 4) @[el2_dec_tlu_ctl.scala 2128:212]
    node _T_691 = bits(io.dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 2128:246]
    node _T_692 = cat(_T_691, UInt<2>("h03")) @[Cat.scala 29:58]
    node _T_693 = cat(_T_690, nmi_in_debug_mode) @[Cat.scala 29:58]
    node _T_694 = cat(_T_693, _T_692) @[Cat.scala 29:58]
    node _T_695 = mux(_T_675, _T_689, _T_694) @[el2_dec_tlu_ctl.scala 2128:8]
    node dcsr_ns = mux(_T_669, _T_674, _T_695) @[el2_dec_tlu_ctl.scala 2127:20]
    node _T_696 = or(enter_debug_halt_req_le, wr_dcsr_r) @[el2_dec_tlu_ctl.scala 2130:55]
    node _T_697 = or(_T_696, io.internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 2130:67]
    node _T_698 = or(_T_697, io.take_nmi) @[el2_dec_tlu_ctl.scala 2130:95]
    node _T_699 = bits(_T_698, 0, 0) @[el2_dec_tlu_ctl.scala 2130:110]
    inst rvclkhdr_17 of rvclkhdr_25 @[el2_lib.scala 508:23]
    rvclkhdr_17.clock <= clock
    rvclkhdr_17.reset <= reset
    rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_17.io.en <= _T_699 @[el2_lib.scala 511:17]
    rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_700 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_700 <= dcsr_ns @[el2_lib.scala 514:16]
    io.dcsr <= _T_700 @[el2_dec_tlu_ctl.scala 2130:11]
    node _T_701 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2138:46]
    node _T_702 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2138:91]
    node _T_703 = eq(_T_702, UInt<12>("h07b1")) @[el2_dec_tlu_ctl.scala 2138:98]
    node wr_dpc_r = and(_T_701, _T_703) @[el2_dec_tlu_ctl.scala 2138:69]
    node _T_704 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2139:45]
    node _T_705 = and(io.dbg_tlu_halted, _T_704) @[el2_dec_tlu_ctl.scala 2139:43]
    node _T_706 = not(io.request_debug_mode_done) @[el2_dec_tlu_ctl.scala 2139:68]
    node dpc_capture_npc = and(_T_705, _T_706) @[el2_dec_tlu_ctl.scala 2139:66]
    node _T_707 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2143:6]
    node _T_708 = not(dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2143:24]
    node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 2143:22]
    node _T_710 = and(_T_709, wr_dpc_r) @[el2_dec_tlu_ctl.scala 2143:41]
    node _T_711 = bits(_T_710, 0, 0) @[el2_dec_tlu_ctl.scala 2143:53]
    node _T_712 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 2143:82]
    node _T_713 = bits(io.request_debug_mode_r, 0, 0) @[el2_dec_tlu_ctl.scala 2144:22]
    node _T_714 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2145:6]
    node _T_715 = and(_T_714, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2145:22]
    node _T_716 = bits(_T_715, 0, 0) @[el2_dec_tlu_ctl.scala 2145:41]
    node _T_717 = mux(_T_711, _T_712, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_718 = mux(_T_713, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_719 = mux(_T_716, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_720 = or(_T_717, _T_718) @[Mux.scala 27:72]
    node _T_721 = or(_T_720, _T_719) @[Mux.scala 27:72]
    wire dpc_ns : UInt<31> @[Mux.scala 27:72]
    dpc_ns <= _T_721 @[Mux.scala 27:72]
    node _T_722 = or(wr_dpc_r, io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2147:37]
    node _T_723 = or(_T_722, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2147:54]
    node _T_724 = bits(_T_723, 0, 0) @[el2_dec_tlu_ctl.scala 2147:73]
    inst rvclkhdr_18 of rvclkhdr_26 @[el2_lib.scala 508:23]
    rvclkhdr_18.clock <= clock
    rvclkhdr_18.reset <= reset
    rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_18.io.en <= _T_724 @[el2_lib.scala 511:17]
    rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_725 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_725 <= dpc_ns @[el2_lib.scala 514:16]
    io.dpc <= _T_725 @[el2_dec_tlu_ctl.scala 2147:10]
    node _T_726 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 2161:44]
    node _T_727 = bits(io.dec_csr_wrdata_r, 21, 20) @[el2_dec_tlu_ctl.scala 2161:69]
    node _T_728 = bits(io.dec_csr_wrdata_r, 16, 3) @[el2_dec_tlu_ctl.scala 2161:97]
    node _T_729 = cat(_T_726, _T_727) @[Cat.scala 29:58]
    node dicawics_ns = cat(_T_729, _T_728) @[Cat.scala 29:58]
    node _T_730 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2162:51]
    node _T_731 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2162:96]
    node _T_732 = eq(_T_731, UInt<12>("h07c8")) @[el2_dec_tlu_ctl.scala 2162:103]
    node wr_dicawics_r = and(_T_730, _T_732) @[el2_dec_tlu_ctl.scala 2162:74]
    node _T_733 = bits(wr_dicawics_r, 0, 0) @[el2_dec_tlu_ctl.scala 2164:51]
    inst rvclkhdr_19 of rvclkhdr_27 @[el2_lib.scala 508:23]
    rvclkhdr_19.clock <= clock
    rvclkhdr_19.reset <= reset
    rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_19.io.en <= _T_733 @[el2_lib.scala 511:17]
    rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    dicawics <= dicawics_ns @[el2_lib.scala 514:16]
    node _T_734 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2180:49]
    node _T_735 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2180:94]
    node _T_736 = eq(_T_735, UInt<12>("h07c9")) @[el2_dec_tlu_ctl.scala 2180:101]
    node wr_dicad0_r = and(_T_734, _T_736) @[el2_dec_tlu_ctl.scala 2180:72]
    node _T_737 = bits(wr_dicad0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2181:35]
    node dicad0_ns = mux(_T_737, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[el2_dec_tlu_ctl.scala 2181:22]
    node _T_738 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2183:47]
    node _T_739 = bits(_T_738, 0, 0) @[el2_dec_tlu_ctl.scala 2183:80]
    inst rvclkhdr_20 of rvclkhdr_28 @[el2_lib.scala 508:23]
    rvclkhdr_20.clock <= clock
    rvclkhdr_20.reset <= reset
    rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_20.io.en <= _T_739 @[el2_lib.scala 511:17]
    rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    dicad0 <= dicad0_ns @[el2_lib.scala 514:16]
    node _T_740 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2193:50]
    node _T_741 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2193:95]
    node _T_742 = eq(_T_741, UInt<12>("h07cc")) @[el2_dec_tlu_ctl.scala 2193:102]
    node wr_dicad0h_r = and(_T_740, _T_742) @[el2_dec_tlu_ctl.scala 2193:73]
    node _T_743 = bits(wr_dicad0h_r, 0, 0) @[el2_dec_tlu_ctl.scala 2195:37]
    node _T_744 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[el2_dec_tlu_ctl.scala 2195:89]
    node dicad0h_ns = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[el2_dec_tlu_ctl.scala 2195:23]
    node _T_745 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2197:49]
    node _T_746 = bits(_T_745, 0, 0) @[el2_dec_tlu_ctl.scala 2197:82]
    inst rvclkhdr_21 of rvclkhdr_29 @[el2_lib.scala 508:23]
    rvclkhdr_21.clock <= clock
    rvclkhdr_21.reset <= reset
    rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_21.io.en <= _T_746 @[el2_lib.scala 511:17]
    rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    dicad0h <= dicad0h_ns @[el2_lib.scala 514:16]
    wire _T_747 : UInt<7>
    _T_747 <= UInt<1>("h00")
    node _T_748 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2205:51]
    node _T_749 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2205:96]
    node _T_750 = eq(_T_749, UInt<12>("h07ca")) @[el2_dec_tlu_ctl.scala 2205:103]
    node _T_751 = and(_T_748, _T_750) @[el2_dec_tlu_ctl.scala 2205:74]
    node _T_752 = bits(_T_751, 0, 0) @[el2_dec_tlu_ctl.scala 2207:37]
    node _T_753 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[el2_dec_tlu_ctl.scala 2207:89]
    node _T_754 = mux(_T_752, io.dec_csr_wrdata_r, _T_753) @[el2_dec_tlu_ctl.scala 2207:24]
    node _T_755 = or(_T_751, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2209:81]
    node _T_756 = bits(_T_755, 0, 0) @[el2_dec_tlu_ctl.scala 2209:114]
    reg _T_757 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_756 : @[Reg.scala 28:19]
      _T_757 <= _T_754 @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    _T_747 <= _T_757 @[el2_dec_tlu_ctl.scala 2209:16]
    node _T_758 = cat(UInt<25>("h00"), _T_747) @[Cat.scala 29:58]
    dicad1 <= _T_758 @[el2_dec_tlu_ctl.scala 2210:12]
    node _T_759 = bits(dicad1, 6, 0) @[el2_dec_tlu_ctl.scala 2232:78]
    node _T_760 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2232:92]
    node _T_761 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2232:106]
    node _T_762 = cat(_T_759, _T_760) @[Cat.scala 29:58]
    node _T_763 = cat(_T_762, _T_761) @[Cat.scala 29:58]
    io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_763 @[el2_dec_tlu_ctl.scala 2232:65]
    io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[el2_dec_tlu_ctl.scala 2235:42]
    node _T_764 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 2237:53]
    node _T_765 = and(_T_764, io.dec_i0_decode_d) @[el2_dec_tlu_ctl.scala 2237:76]
    node _T_766 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 2237:99]
    node _T_767 = and(_T_765, _T_766) @[el2_dec_tlu_ctl.scala 2237:97]
    node _T_768 = bits(io.dec_csr_rdaddr_d, 11, 0) @[el2_dec_tlu_ctl.scala 2237:143]
    node _T_769 = eq(_T_768, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2237:150]
    node icache_rd_valid = and(_T_767, _T_769) @[el2_dec_tlu_ctl.scala 2237:121]
    node _T_770 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2238:53]
    node _T_771 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2238:98]
    node _T_772 = eq(_T_771, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2238:105]
    node icache_wr_valid = and(_T_770, _T_772) @[el2_dec_tlu_ctl.scala 2238:76]
    reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2240:59]
    icache_rd_valid_f <= icache_rd_valid @[el2_dec_tlu_ctl.scala 2240:59]
    reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2241:59]
    icache_wr_valid_f <= icache_wr_valid @[el2_dec_tlu_ctl.scala 2241:59]
    io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[el2_dec_tlu_ctl.scala 2243:42]
    io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[el2_dec_tlu_ctl.scala 2244:42]
    node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2252:63]
    node _T_774 = eq(_T_773, UInt<12>("h07a0")) @[el2_dec_tlu_ctl.scala 2252:70]
    node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_774) @[el2_dec_tlu_ctl.scala 2252:41]
    node _T_775 = bits(wr_mtsel_r, 0, 0) @[el2_dec_tlu_ctl.scala 2253:33]
    node _T_776 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2253:60]
    node mtsel_ns = mux(_T_775, _T_776, mtsel) @[el2_dec_tlu_ctl.scala 2253:21]
    reg _T_777 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2255:44]
    _T_777 <= mtsel_ns @[el2_dec_tlu_ctl.scala 2255:44]
    mtsel <= _T_777 @[el2_dec_tlu_ctl.scala 2255:9]
    node _T_778 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2290:39]
    node _T_779 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2290:65]
    node _T_780 = not(_T_779) @[el2_dec_tlu_ctl.scala 2290:45]
    node tdata_load = and(_T_778, _T_780) @[el2_dec_tlu_ctl.scala 2290:43]
    node _T_781 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2292:41]
    node _T_782 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2292:67]
    node _T_783 = not(_T_782) @[el2_dec_tlu_ctl.scala 2292:47]
    node tdata_opcode = and(_T_781, _T_783) @[el2_dec_tlu_ctl.scala 2292:45]
    node _T_784 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2294:42]
    node _T_785 = and(_T_784, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2294:47]
    node _T_786 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 2294:91]
    node tdata_action = and(_T_785, _T_786) @[el2_dec_tlu_ctl.scala 2294:70]
    node _T_787 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2296:48]
    node _T_788 = and(_T_787, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2296:53]
    node _T_789 = bits(io.dec_csr_wrdata_r, 20, 19) @[el2_dec_tlu_ctl.scala 2296:95]
    node _T_790 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 2296:137]
    node _T_791 = bits(io.dec_csr_wrdata_r, 7, 6) @[el2_dec_tlu_ctl.scala 2297:24]
    node _T_792 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 2297:64]
    node _T_793 = cat(_T_792, tdata_load) @[Cat.scala 29:58]
    node _T_794 = cat(_T_791, tdata_opcode) @[Cat.scala 29:58]
    node _T_795 = cat(_T_794, _T_793) @[Cat.scala 29:58]
    node _T_796 = cat(tdata_action, _T_790) @[Cat.scala 29:58]
    node _T_797 = cat(_T_788, _T_789) @[Cat.scala 29:58]
    node _T_798 = cat(_T_797, _T_796) @[Cat.scala 29:58]
    node tdata_wrdata_r = cat(_T_798, _T_795) @[Cat.scala 29:58]
    node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93]
    node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100]
    node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[el2_dec_tlu_ctl.scala 2300:71]
    node _T_802 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122]
    node _T_803 = and(_T_801, _T_802) @[el2_dec_tlu_ctl.scala 2300:113]
    node _T_804 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155]
    node _T_805 = not(_T_804) @[el2_dec_tlu_ctl.scala 2300:139]
    node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171]
    node _T_807 = and(_T_803, _T_806) @[el2_dec_tlu_ctl.scala 2300:136]
    node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93]
    node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100]
    node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[el2_dec_tlu_ctl.scala 2300:71]
    node _T_811 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122]
    node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 2300:113]
    node _T_813 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155]
    node _T_814 = not(_T_813) @[el2_dec_tlu_ctl.scala 2300:139]
    node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171]
    node _T_816 = and(_T_812, _T_815) @[el2_dec_tlu_ctl.scala 2300:136]
    node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93]
    node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100]
    node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[el2_dec_tlu_ctl.scala 2300:71]
    node _T_820 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122]
    node _T_821 = and(_T_819, _T_820) @[el2_dec_tlu_ctl.scala 2300:113]
    node _T_822 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155]
    node _T_823 = not(_T_822) @[el2_dec_tlu_ctl.scala 2300:139]
    node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171]
    node _T_825 = and(_T_821, _T_824) @[el2_dec_tlu_ctl.scala 2300:136]
    node _T_826 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93]
    node _T_827 = eq(_T_826, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100]
    node _T_828 = and(io.dec_csr_wen_r_mod, _T_827) @[el2_dec_tlu_ctl.scala 2300:71]
    node _T_829 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122]
    node _T_830 = and(_T_828, _T_829) @[el2_dec_tlu_ctl.scala 2300:113]
    node _T_831 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155]
    node _T_832 = not(_T_831) @[el2_dec_tlu_ctl.scala 2300:139]
    node _T_833 = or(_T_832, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171]
    node _T_834 = and(_T_830, _T_833) @[el2_dec_tlu_ctl.scala 2300:136]
    wire wr_mtdata1_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2300:43]
    wr_mtdata1_t_r[0] <= _T_807 @[el2_dec_tlu_ctl.scala 2300:43]
    wr_mtdata1_t_r[1] <= _T_816 @[el2_dec_tlu_ctl.scala 2300:43]
    wr_mtdata1_t_r[2] <= _T_825 @[el2_dec_tlu_ctl.scala 2300:43]
    wr_mtdata1_t_r[3] <= _T_834 @[el2_dec_tlu_ctl.scala 2300:43]
    node _T_835 = bits(wr_mtdata1_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69]
    node _T_836 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112]
    node _T_837 = bits(io.update_hit_bit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2301:136]
    node _T_838 = bits(io.mtdata1_t[0], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157]
    node _T_839 = or(_T_837, _T_838) @[el2_dec_tlu_ctl.scala 2301:140]
    node _T_840 = bits(io.mtdata1_t[0], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177]
    node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58]
    node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58]
    node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[el2_dec_tlu_ctl.scala 2301:50]
    node _T_844 = bits(wr_mtdata1_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69]
    node _T_845 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112]
    node _T_846 = bits(io.update_hit_bit_r, 1, 1) @[el2_dec_tlu_ctl.scala 2301:136]
    node _T_847 = bits(io.mtdata1_t[1], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157]
    node _T_848 = or(_T_846, _T_847) @[el2_dec_tlu_ctl.scala 2301:140]
    node _T_849 = bits(io.mtdata1_t[1], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177]
    node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58]
    node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58]
    node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[el2_dec_tlu_ctl.scala 2301:50]
    node _T_853 = bits(wr_mtdata1_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69]
    node _T_854 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112]
    node _T_855 = bits(io.update_hit_bit_r, 2, 2) @[el2_dec_tlu_ctl.scala 2301:136]
    node _T_856 = bits(io.mtdata1_t[2], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157]
    node _T_857 = or(_T_855, _T_856) @[el2_dec_tlu_ctl.scala 2301:140]
    node _T_858 = bits(io.mtdata1_t[2], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177]
    node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58]
    node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58]
    node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[el2_dec_tlu_ctl.scala 2301:50]
    node _T_862 = bits(wr_mtdata1_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69]
    node _T_863 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112]
    node _T_864 = bits(io.update_hit_bit_r, 3, 3) @[el2_dec_tlu_ctl.scala 2301:136]
    node _T_865 = bits(io.mtdata1_t[3], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157]
    node _T_866 = or(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 2301:140]
    node _T_867 = bits(io.mtdata1_t[3], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177]
    node _T_868 = cat(_T_863, _T_866) @[Cat.scala 29:58]
    node _T_869 = cat(_T_868, _T_867) @[Cat.scala 29:58]
    node _T_870 = mux(_T_862, tdata_wrdata_r, _T_869) @[el2_dec_tlu_ctl.scala 2301:50]
    wire mtdata1_t_ns : UInt<10>[4] @[el2_dec_tlu_ctl.scala 2301:41]
    mtdata1_t_ns[0] <= _T_843 @[el2_dec_tlu_ctl.scala 2301:41]
    mtdata1_t_ns[1] <= _T_852 @[el2_dec_tlu_ctl.scala 2301:41]
    mtdata1_t_ns[2] <= _T_861 @[el2_dec_tlu_ctl.scala 2301:41]
    mtdata1_t_ns[3] <= _T_870 @[el2_dec_tlu_ctl.scala 2301:41]
    reg _T_871 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76]
    _T_871 <= mtdata1_t_ns[0] @[el2_dec_tlu_ctl.scala 2303:76]
    io.mtdata1_t[0] <= _T_871 @[el2_dec_tlu_ctl.scala 2303:41]
    reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76]
    _T_872 <= mtdata1_t_ns[1] @[el2_dec_tlu_ctl.scala 2303:76]
    io.mtdata1_t[1] <= _T_872 @[el2_dec_tlu_ctl.scala 2303:41]
    reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76]
    _T_873 <= mtdata1_t_ns[2] @[el2_dec_tlu_ctl.scala 2303:76]
    io.mtdata1_t[2] <= _T_873 @[el2_dec_tlu_ctl.scala 2303:41]
    reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76]
    _T_874 <= mtdata1_t_ns[3] @[el2_dec_tlu_ctl.scala 2303:76]
    io.mtdata1_t[3] <= _T_874 @[el2_dec_tlu_ctl.scala 2303:41]
    node _T_875 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2306:60]
    node _T_876 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106]
    node _T_877 = bits(io.mtdata1_t[0], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144]
    node _T_878 = bits(io.mtdata1_t[0], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176]
    node _T_879 = bits(io.mtdata1_t[0], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208]
    node _T_880 = bits(io.mtdata1_t[0], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240]
    node _T_881 = cat(UInt<3>("h00"), _T_880) @[Cat.scala 29:58]
    node _T_882 = cat(_T_878, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_883 = cat(_T_882, _T_879) @[Cat.scala 29:58]
    node _T_884 = cat(_T_883, _T_881) @[Cat.scala 29:58]
    node _T_885 = cat(_T_877, UInt<6>("h00")) @[Cat.scala 29:58]
    node _T_886 = cat(UInt<4>("h02"), _T_876) @[Cat.scala 29:58]
    node _T_887 = cat(_T_886, UInt<6>("h01f")) @[Cat.scala 29:58]
    node _T_888 = cat(_T_887, _T_885) @[Cat.scala 29:58]
    node _T_889 = cat(_T_888, _T_884) @[Cat.scala 29:58]
    node _T_890 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2306:60]
    node _T_891 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106]
    node _T_892 = bits(io.mtdata1_t[1], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144]
    node _T_893 = bits(io.mtdata1_t[1], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176]
    node _T_894 = bits(io.mtdata1_t[1], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208]
    node _T_895 = bits(io.mtdata1_t[1], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240]
    node _T_896 = cat(UInt<3>("h00"), _T_895) @[Cat.scala 29:58]
    node _T_897 = cat(_T_893, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_898 = cat(_T_897, _T_894) @[Cat.scala 29:58]
    node _T_899 = cat(_T_898, _T_896) @[Cat.scala 29:58]
    node _T_900 = cat(_T_892, UInt<6>("h00")) @[Cat.scala 29:58]
    node _T_901 = cat(UInt<4>("h02"), _T_891) @[Cat.scala 29:58]
    node _T_902 = cat(_T_901, UInt<6>("h01f")) @[Cat.scala 29:58]
    node _T_903 = cat(_T_902, _T_900) @[Cat.scala 29:58]
    node _T_904 = cat(_T_903, _T_899) @[Cat.scala 29:58]
    node _T_905 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2306:60]
    node _T_906 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106]
    node _T_907 = bits(io.mtdata1_t[2], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144]
    node _T_908 = bits(io.mtdata1_t[2], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176]
    node _T_909 = bits(io.mtdata1_t[2], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208]
    node _T_910 = bits(io.mtdata1_t[2], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240]
    node _T_911 = cat(UInt<3>("h00"), _T_910) @[Cat.scala 29:58]
    node _T_912 = cat(_T_908, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_913 = cat(_T_912, _T_909) @[Cat.scala 29:58]
    node _T_914 = cat(_T_913, _T_911) @[Cat.scala 29:58]
    node _T_915 = cat(_T_907, UInt<6>("h00")) @[Cat.scala 29:58]
    node _T_916 = cat(UInt<4>("h02"), _T_906) @[Cat.scala 29:58]
    node _T_917 = cat(_T_916, UInt<6>("h01f")) @[Cat.scala 29:58]
    node _T_918 = cat(_T_917, _T_915) @[Cat.scala 29:58]
    node _T_919 = cat(_T_918, _T_914) @[Cat.scala 29:58]
    node _T_920 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2306:60]
    node _T_921 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106]
    node _T_922 = bits(io.mtdata1_t[3], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144]
    node _T_923 = bits(io.mtdata1_t[3], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176]
    node _T_924 = bits(io.mtdata1_t[3], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208]
    node _T_925 = bits(io.mtdata1_t[3], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240]
    node _T_926 = cat(UInt<3>("h00"), _T_925) @[Cat.scala 29:58]
    node _T_927 = cat(_T_923, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_928 = cat(_T_927, _T_924) @[Cat.scala 29:58]
    node _T_929 = cat(_T_928, _T_926) @[Cat.scala 29:58]
    node _T_930 = cat(_T_922, UInt<6>("h00")) @[Cat.scala 29:58]
    node _T_931 = cat(UInt<4>("h02"), _T_921) @[Cat.scala 29:58]
    node _T_932 = cat(_T_931, UInt<6>("h01f")) @[Cat.scala 29:58]
    node _T_933 = cat(_T_932, _T_930) @[Cat.scala 29:58]
    node _T_934 = cat(_T_933, _T_929) @[Cat.scala 29:58]
    node _T_935 = mux(_T_875, _T_889, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_936 = mux(_T_890, _T_904, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_937 = mux(_T_905, _T_919, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_938 = mux(_T_920, _T_934, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_939 = or(_T_935, _T_936) @[Mux.scala 27:72]
    node _T_940 = or(_T_939, _T_937) @[Mux.scala 27:72]
    node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72]
    wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72]
    mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72]
    node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54]
    io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36]
    node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57]
    io.trigger_pkt_any[0].match_pkt <= _T_943 @[el2_dec_tlu_ctl.scala 2309:39]
    node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54]
    io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36]
    node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54]
    io.trigger_pkt_any[0].load <= _T_945 @[el2_dec_tlu_ctl.scala 2311:36]
    node _T_946 = bits(io.mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54]
    io.trigger_pkt_any[0].execute <= _T_946 @[el2_dec_tlu_ctl.scala 2312:36]
    node _T_947 = bits(io.mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54]
    io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36]
    node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54]
    io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36]
    node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57]
    io.trigger_pkt_any[1].match_pkt <= _T_949 @[el2_dec_tlu_ctl.scala 2309:39]
    node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54]
    io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36]
    node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54]
    io.trigger_pkt_any[1].load <= _T_951 @[el2_dec_tlu_ctl.scala 2311:36]
    node _T_952 = bits(io.mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54]
    io.trigger_pkt_any[1].execute <= _T_952 @[el2_dec_tlu_ctl.scala 2312:36]
    node _T_953 = bits(io.mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54]
    io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36]
    node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54]
    io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36]
    node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57]
    io.trigger_pkt_any[2].match_pkt <= _T_955 @[el2_dec_tlu_ctl.scala 2309:39]
    node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54]
    io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36]
    node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54]
    io.trigger_pkt_any[2].load <= _T_957 @[el2_dec_tlu_ctl.scala 2311:36]
    node _T_958 = bits(io.mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54]
    io.trigger_pkt_any[2].execute <= _T_958 @[el2_dec_tlu_ctl.scala 2312:36]
    node _T_959 = bits(io.mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54]
    io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36]
    node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54]
    io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36]
    node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57]
    io.trigger_pkt_any[3].match_pkt <= _T_961 @[el2_dec_tlu_ctl.scala 2309:39]
    node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54]
    io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36]
    node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54]
    io.trigger_pkt_any[3].load <= _T_963 @[el2_dec_tlu_ctl.scala 2311:36]
    node _T_964 = bits(io.mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54]
    io.trigger_pkt_any[3].execute <= _T_964 @[el2_dec_tlu_ctl.scala 2312:36]
    node _T_965 = bits(io.mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54]
    io.trigger_pkt_any[3].m <= _T_965 @[el2_dec_tlu_ctl.scala 2313:36]
    node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92]
    node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99]
    node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[el2_dec_tlu_ctl.scala 2320:70]
    node _T_969 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2320:121]
    node _T_970 = and(_T_968, _T_969) @[el2_dec_tlu_ctl.scala 2320:112]
    node _T_971 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154]
    node _T_972 = not(_T_971) @[el2_dec_tlu_ctl.scala 2320:138]
    node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170]
    node _T_974 = and(_T_970, _T_973) @[el2_dec_tlu_ctl.scala 2320:135]
    node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92]
    node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99]
    node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[el2_dec_tlu_ctl.scala 2320:70]
    node _T_978 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2320:121]
    node _T_979 = and(_T_977, _T_978) @[el2_dec_tlu_ctl.scala 2320:112]
    node _T_980 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154]
    node _T_981 = not(_T_980) @[el2_dec_tlu_ctl.scala 2320:138]
    node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170]
    node _T_983 = and(_T_979, _T_982) @[el2_dec_tlu_ctl.scala 2320:135]
    node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92]
    node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99]
    node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[el2_dec_tlu_ctl.scala 2320:70]
    node _T_987 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2320:121]
    node _T_988 = and(_T_986, _T_987) @[el2_dec_tlu_ctl.scala 2320:112]
    node _T_989 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154]
    node _T_990 = not(_T_989) @[el2_dec_tlu_ctl.scala 2320:138]
    node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170]
    node _T_992 = and(_T_988, _T_991) @[el2_dec_tlu_ctl.scala 2320:135]
    node _T_993 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92]
    node _T_994 = eq(_T_993, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99]
    node _T_995 = and(io.dec_csr_wen_r_mod, _T_994) @[el2_dec_tlu_ctl.scala 2320:70]
    node _T_996 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2320:121]
    node _T_997 = and(_T_995, _T_996) @[el2_dec_tlu_ctl.scala 2320:112]
    node _T_998 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154]
    node _T_999 = not(_T_998) @[el2_dec_tlu_ctl.scala 2320:138]
    node _T_1000 = or(_T_999, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170]
    node _T_1001 = and(_T_997, _T_1000) @[el2_dec_tlu_ctl.scala 2320:135]
    wire wr_mtdata2_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2320:43]
    wr_mtdata2_t_r[0] <= _T_974 @[el2_dec_tlu_ctl.scala 2320:43]
    wr_mtdata2_t_r[1] <= _T_983 @[el2_dec_tlu_ctl.scala 2320:43]
    wr_mtdata2_t_r[2] <= _T_992 @[el2_dec_tlu_ctl.scala 2320:43]
    wr_mtdata2_t_r[3] <= _T_1001 @[el2_dec_tlu_ctl.scala 2320:43]
    node _T_1002 = bits(wr_mtdata2_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86]
    inst rvclkhdr_22 of rvclkhdr_30 @[el2_lib.scala 508:23]
    rvclkhdr_22.clock <= clock
    rvclkhdr_22.reset <= reset
    rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_22.io.en <= _T_1002 @[el2_lib.scala 511:17]
    rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1003 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1003 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
    mtdata2_t[0] <= _T_1003 @[el2_dec_tlu_ctl.scala 2321:38]
    node _T_1004 = bits(wr_mtdata2_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86]
    inst rvclkhdr_23 of rvclkhdr_31 @[el2_lib.scala 508:23]
    rvclkhdr_23.clock <= clock
    rvclkhdr_23.reset <= reset
    rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_23.io.en <= _T_1004 @[el2_lib.scala 511:17]
    rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1005 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1005 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
    mtdata2_t[1] <= _T_1005 @[el2_dec_tlu_ctl.scala 2321:38]
    node _T_1006 = bits(wr_mtdata2_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86]
    inst rvclkhdr_24 of rvclkhdr_32 @[el2_lib.scala 508:23]
    rvclkhdr_24.clock <= clock
    rvclkhdr_24.reset <= reset
    rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_24.io.en <= _T_1006 @[el2_lib.scala 511:17]
    rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1007 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1007 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
    mtdata2_t[2] <= _T_1007 @[el2_dec_tlu_ctl.scala 2321:38]
    node _T_1008 = bits(wr_mtdata2_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86]
    inst rvclkhdr_25 of rvclkhdr_33 @[el2_lib.scala 508:23]
    rvclkhdr_25.clock <= clock
    rvclkhdr_25.reset <= reset
    rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_25.io.en <= _T_1008 @[el2_lib.scala 511:17]
    rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1009 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1009 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
    mtdata2_t[3] <= _T_1009 @[el2_dec_tlu_ctl.scala 2321:38]
    node _T_1010 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2325:59]
    node _T_1011 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2325:59]
    node _T_1012 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2325:59]
    node _T_1013 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2325:59]
    node _T_1014 = mux(_T_1010, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1015 = mux(_T_1011, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1016 = mux(_T_1012, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1017 = mux(_T_1013, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1018 = or(_T_1014, _T_1015) @[Mux.scala 27:72]
    node _T_1019 = or(_T_1018, _T_1016) @[Mux.scala 27:72]
    node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72]
    wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72]
    mtdata2_tsel_out <= _T_1020 @[Mux.scala 27:72]
    io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[el2_dec_tlu_ctl.scala 2326:53]
    io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[el2_dec_tlu_ctl.scala 2326:53]
    io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[el2_dec_tlu_ctl.scala 2326:53]
    io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[el2_dec_tlu_ctl.scala 2326:53]
    mhpme_vec[0] <= mhpme3 @[el2_dec_tlu_ctl.scala 2336:16]
    mhpme_vec[1] <= mhpme4 @[el2_dec_tlu_ctl.scala 2337:16]
    mhpme_vec[2] <= mhpme5 @[el2_dec_tlu_ctl.scala 2338:16]
    mhpme_vec[3] <= mhpme6 @[el2_dec_tlu_ctl.scala 2339:16]
    node _T_1021 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15]
    node _T_1022 = mux(_T_1021, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1022) @[el2_dec_tlu_ctl.scala 2345:60]
    wire mhpmc_inc_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2346:25]
    wire mhpmc_inc_r_d1 : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2347:28]
    node _T_1023 = bits(mcountinhibit, 3, 3) @[el2_dec_tlu_ctl.scala 2351:39]
    node _T_1024 = not(_T_1023) @[el2_dec_tlu_ctl.scala 2351:25]
    node _T_1025 = eq(mhpme_vec[0], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21]
    node _T_1026 = bits(_T_1025, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49]
    node _T_1027 = eq(mhpme_vec[0], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21]
    node _T_1028 = bits(_T_1027, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49]
    node _T_1029 = eq(mhpme_vec[0], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21]
    node _T_1030 = bits(_T_1029, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49]
    node _T_1031 = eq(mhpme_vec[0], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21]
    node _T_1032 = bits(_T_1031, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49]
    node _T_1033 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83]
    node _T_1034 = and(io.tlu_i0_commit_cmt, _T_1033) @[el2_dec_tlu_ctl.scala 2355:81]
    node _T_1035 = eq(mhpme_vec[0], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21]
    node _T_1036 = bits(_T_1035, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49]
    node _T_1037 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83]
    node _T_1038 = and(io.tlu_i0_commit_cmt, _T_1037) @[el2_dec_tlu_ctl.scala 2356:81]
    node _T_1039 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104]
    node _T_1040 = and(_T_1038, _T_1039) @[el2_dec_tlu_ctl.scala 2356:102]
    node _T_1041 = eq(mhpme_vec[0], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21]
    node _T_1042 = bits(_T_1041, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49]
    node _T_1043 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81]
    node _T_1044 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104]
    node _T_1045 = and(_T_1043, _T_1044) @[el2_dec_tlu_ctl.scala 2357:102]
    node _T_1046 = eq(mhpme_vec[0], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21]
    node _T_1047 = bits(_T_1046, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49]
    node _T_1048 = eq(mhpme_vec[0], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21]
    node _T_1049 = bits(_T_1048, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49]
    node _T_1050 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21]
    node _T_1051 = bits(_T_1050, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49]
    node _T_1052 = eq(mhpme_vec[0], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21]
    node _T_1053 = bits(_T_1052, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49]
    node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78]
    node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21]
    node _T_1056 = bits(_T_1055, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49]
    node _T_1057 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92]
    node _T_1058 = eq(mhpme_vec[0], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21]
    node _T_1059 = bits(_T_1058, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49]
    node _T_1060 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78]
    node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21]
    node _T_1062 = bits(_T_1061, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49]
    node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78]
    node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21]
    node _T_1065 = bits(_T_1064, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49]
    node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79]
    node _T_1067 = eq(mhpme_vec[0], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21]
    node _T_1068 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1067) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1069 = bits(_T_1068, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1070 = and(_T_1066, _T_1069) @[el2_dec_tlu_ctl.scala 2365:89]
    node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66]
    node _T_1072 = and(_T_1070, _T_1071) @[el2_dec_tlu_ctl.scala 2366:45]
    node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48]
    node _T_1074 = and(_T_1072, _T_1073) @[el2_dec_tlu_ctl.scala 2366:77]
    node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21]
    node _T_1076 = bits(_T_1075, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41]
    node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76]
    node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21]
    node _T_1079 = bits(_T_1078, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46]
    node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76]
    node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21]
    node _T_1082 = bits(_T_1081, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46]
    node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76]
    node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21]
    node _T_1085 = bits(_T_1084, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46]
    node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76]
    node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21]
    node _T_1088 = bits(_T_1087, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46]
    node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76]
    node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21]
    node _T_1091 = bits(_T_1090, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46]
    node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76]
    node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21]
    node _T_1094 = bits(_T_1093, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46]
    node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76]
    node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21]
    node _T_1097 = bits(_T_1096, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46]
    node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76]
    node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21]
    node _T_1100 = bits(_T_1099, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46]
    node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76]
    node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21]
    node _T_1103 = bits(_T_1102, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46]
    node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76]
    node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109]
    node _T_1106 = or(_T_1104, _T_1105) @[el2_dec_tlu_ctl.scala 2377:88]
    node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21]
    node _T_1108 = bits(_T_1107, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49]
    node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82]
    node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21]
    node _T_1111 = bits(_T_1110, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49]
    node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84]
    node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21]
    node _T_1114 = bits(_T_1113, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49]
    node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97]
    node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21]
    node _T_1117 = bits(_T_1116, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49]
    node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21]
    node _T_1119 = bits(_T_1118, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49]
    node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21]
    node _T_1121 = bits(_T_1120, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49]
    node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21]
    node _T_1123 = bits(_T_1122, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49]
    node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21]
    node _T_1125 = bits(_T_1124, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49]
    node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21]
    node _T_1127 = bits(_T_1126, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49]
    node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21]
    node _T_1129 = bits(_T_1128, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49]
    node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21]
    node _T_1131 = bits(_T_1130, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49]
    node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85]
    node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107]
    node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21]
    node _T_1135 = bits(_T_1134, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49]
    node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79]
    node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104]
    node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21]
    node _T_1139 = bits(_T_1138, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49]
    node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21]
    node _T_1141 = bits(_T_1140, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49]
    node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21]
    node _T_1143 = bits(_T_1142, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49]
    node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84]
    node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116]
    node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21]
    node _T_1147 = bits(_T_1146, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49]
    node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21]
    node _T_1149 = bits(_T_1148, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49]
    node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21]
    node _T_1151 = bits(_T_1150, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49]
    node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21]
    node _T_1153 = bits(_T_1152, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49]
    node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21]
    node _T_1155 = bits(_T_1154, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49]
    node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21]
    node _T_1157 = bits(_T_1156, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49]
    node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21]
    node _T_1159 = bits(_T_1158, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49]
    node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21]
    node _T_1161 = bits(_T_1160, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49]
    node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_1163 = bits(_T_1162, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_1164 = not(_T_1163) @[el2_dec_tlu_ctl.scala 2400:60]
    node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21]
    node _T_1166 = bits(_T_1165, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49]
    node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_1168 = bits(_T_1167, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_1169 = not(_T_1168) @[el2_dec_tlu_ctl.scala 2401:60]
    node _T_1170 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94]
    node _T_1171 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105]
    node _T_1172 = and(_T_1170, _T_1171) @[el2_dec_tlu_ctl.scala 2401:100]
    node _T_1173 = and(_T_1169, _T_1172) @[el2_dec_tlu_ctl.scala 2401:85]
    node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21]
    node _T_1175 = bits(_T_1174, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49]
    node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78]
    node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21]
    node _T_1178 = bits(_T_1177, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49]
    node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81]
    node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21]
    node _T_1181 = bits(_T_1180, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49]
    node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81]
    node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21]
    node _T_1184 = bits(_T_1183, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49]
    node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21]
    node _T_1186 = bits(_T_1185, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49]
    node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21]
    node _T_1188 = bits(_T_1187, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49]
    node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21]
    node _T_1190 = bits(_T_1189, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49]
    node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21]
    node _T_1192 = bits(_T_1191, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49]
    node _T_1193 = mux(_T_1026, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1194 = mux(_T_1028, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1196 = mux(_T_1032, _T_1034, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1197 = mux(_T_1036, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1198 = mux(_T_1042, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1199 = mux(_T_1047, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1200 = mux(_T_1049, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1201 = mux(_T_1051, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1202 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1203 = mux(_T_1056, _T_1057, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1204 = mux(_T_1059, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1205 = mux(_T_1062, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1206 = mux(_T_1065, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1207 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1208 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1209 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1210 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1211 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1212 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1213 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1214 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1215 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1216 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1217 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1218 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1219 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1220 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1221 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1222 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1223 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1224 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1225 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1226 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1227 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1228 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1229 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1230 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1231 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1232 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1233 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1234 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1235 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1236 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1237 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1238 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1239 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1240 = mux(_T_1166, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1241 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1242 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1243 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1244 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1245 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1246 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1247 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1248 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1249 = or(_T_1193, _T_1194) @[Mux.scala 27:72]
    node _T_1250 = or(_T_1249, _T_1195) @[Mux.scala 27:72]
    node _T_1251 = or(_T_1250, _T_1196) @[Mux.scala 27:72]
    node _T_1252 = or(_T_1251, _T_1197) @[Mux.scala 27:72]
    node _T_1253 = or(_T_1252, _T_1198) @[Mux.scala 27:72]
    node _T_1254 = or(_T_1253, _T_1199) @[Mux.scala 27:72]
    node _T_1255 = or(_T_1254, _T_1200) @[Mux.scala 27:72]
    node _T_1256 = or(_T_1255, _T_1201) @[Mux.scala 27:72]
    node _T_1257 = or(_T_1256, _T_1202) @[Mux.scala 27:72]
    node _T_1258 = or(_T_1257, _T_1203) @[Mux.scala 27:72]
    node _T_1259 = or(_T_1258, _T_1204) @[Mux.scala 27:72]
    node _T_1260 = or(_T_1259, _T_1205) @[Mux.scala 27:72]
    node _T_1261 = or(_T_1260, _T_1206) @[Mux.scala 27:72]
    node _T_1262 = or(_T_1261, _T_1207) @[Mux.scala 27:72]
    node _T_1263 = or(_T_1262, _T_1208) @[Mux.scala 27:72]
    node _T_1264 = or(_T_1263, _T_1209) @[Mux.scala 27:72]
    node _T_1265 = or(_T_1264, _T_1210) @[Mux.scala 27:72]
    node _T_1266 = or(_T_1265, _T_1211) @[Mux.scala 27:72]
    node _T_1267 = or(_T_1266, _T_1212) @[Mux.scala 27:72]
    node _T_1268 = or(_T_1267, _T_1213) @[Mux.scala 27:72]
    node _T_1269 = or(_T_1268, _T_1214) @[Mux.scala 27:72]
    node _T_1270 = or(_T_1269, _T_1215) @[Mux.scala 27:72]
    node _T_1271 = or(_T_1270, _T_1216) @[Mux.scala 27:72]
    node _T_1272 = or(_T_1271, _T_1217) @[Mux.scala 27:72]
    node _T_1273 = or(_T_1272, _T_1218) @[Mux.scala 27:72]
    node _T_1274 = or(_T_1273, _T_1219) @[Mux.scala 27:72]
    node _T_1275 = or(_T_1274, _T_1220) @[Mux.scala 27:72]
    node _T_1276 = or(_T_1275, _T_1221) @[Mux.scala 27:72]
    node _T_1277 = or(_T_1276, _T_1222) @[Mux.scala 27:72]
    node _T_1278 = or(_T_1277, _T_1223) @[Mux.scala 27:72]
    node _T_1279 = or(_T_1278, _T_1224) @[Mux.scala 27:72]
    node _T_1280 = or(_T_1279, _T_1225) @[Mux.scala 27:72]
    node _T_1281 = or(_T_1280, _T_1226) @[Mux.scala 27:72]
    node _T_1282 = or(_T_1281, _T_1227) @[Mux.scala 27:72]
    node _T_1283 = or(_T_1282, _T_1228) @[Mux.scala 27:72]
    node _T_1284 = or(_T_1283, _T_1229) @[Mux.scala 27:72]
    node _T_1285 = or(_T_1284, _T_1230) @[Mux.scala 27:72]
    node _T_1286 = or(_T_1285, _T_1231) @[Mux.scala 27:72]
    node _T_1287 = or(_T_1286, _T_1232) @[Mux.scala 27:72]
    node _T_1288 = or(_T_1287, _T_1233) @[Mux.scala 27:72]
    node _T_1289 = or(_T_1288, _T_1234) @[Mux.scala 27:72]
    node _T_1290 = or(_T_1289, _T_1235) @[Mux.scala 27:72]
    node _T_1291 = or(_T_1290, _T_1236) @[Mux.scala 27:72]
    node _T_1292 = or(_T_1291, _T_1237) @[Mux.scala 27:72]
    node _T_1293 = or(_T_1292, _T_1238) @[Mux.scala 27:72]
    node _T_1294 = or(_T_1293, _T_1239) @[Mux.scala 27:72]
    node _T_1295 = or(_T_1294, _T_1240) @[Mux.scala 27:72]
    node _T_1296 = or(_T_1295, _T_1241) @[Mux.scala 27:72]
    node _T_1297 = or(_T_1296, _T_1242) @[Mux.scala 27:72]
    node _T_1298 = or(_T_1297, _T_1243) @[Mux.scala 27:72]
    node _T_1299 = or(_T_1298, _T_1244) @[Mux.scala 27:72]
    node _T_1300 = or(_T_1299, _T_1245) @[Mux.scala 27:72]
    node _T_1301 = or(_T_1300, _T_1246) @[Mux.scala 27:72]
    node _T_1302 = or(_T_1301, _T_1247) @[Mux.scala 27:72]
    node _T_1303 = or(_T_1302, _T_1248) @[Mux.scala 27:72]
    wire _T_1304 : UInt<6> @[Mux.scala 27:72]
    _T_1304 <= _T_1303 @[Mux.scala 27:72]
    node _T_1305 = and(_T_1024, _T_1304) @[el2_dec_tlu_ctl.scala 2351:45]
    mhpmc_inc_r[0] <= _T_1305 @[el2_dec_tlu_ctl.scala 2351:20]
    node _T_1306 = bits(mcountinhibit, 4, 4) @[el2_dec_tlu_ctl.scala 2351:39]
    node _T_1307 = not(_T_1306) @[el2_dec_tlu_ctl.scala 2351:25]
    node _T_1308 = eq(mhpme_vec[1], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21]
    node _T_1309 = bits(_T_1308, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49]
    node _T_1310 = eq(mhpme_vec[1], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21]
    node _T_1311 = bits(_T_1310, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49]
    node _T_1312 = eq(mhpme_vec[1], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21]
    node _T_1313 = bits(_T_1312, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49]
    node _T_1314 = eq(mhpme_vec[1], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21]
    node _T_1315 = bits(_T_1314, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49]
    node _T_1316 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83]
    node _T_1317 = and(io.tlu_i0_commit_cmt, _T_1316) @[el2_dec_tlu_ctl.scala 2355:81]
    node _T_1318 = eq(mhpme_vec[1], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21]
    node _T_1319 = bits(_T_1318, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49]
    node _T_1320 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83]
    node _T_1321 = and(io.tlu_i0_commit_cmt, _T_1320) @[el2_dec_tlu_ctl.scala 2356:81]
    node _T_1322 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104]
    node _T_1323 = and(_T_1321, _T_1322) @[el2_dec_tlu_ctl.scala 2356:102]
    node _T_1324 = eq(mhpme_vec[1], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21]
    node _T_1325 = bits(_T_1324, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49]
    node _T_1326 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81]
    node _T_1327 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104]
    node _T_1328 = and(_T_1326, _T_1327) @[el2_dec_tlu_ctl.scala 2357:102]
    node _T_1329 = eq(mhpme_vec[1], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21]
    node _T_1330 = bits(_T_1329, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49]
    node _T_1331 = eq(mhpme_vec[1], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21]
    node _T_1332 = bits(_T_1331, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49]
    node _T_1333 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21]
    node _T_1334 = bits(_T_1333, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49]
    node _T_1335 = eq(mhpme_vec[1], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21]
    node _T_1336 = bits(_T_1335, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49]
    node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78]
    node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21]
    node _T_1339 = bits(_T_1338, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49]
    node _T_1340 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92]
    node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21]
    node _T_1342 = bits(_T_1341, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49]
    node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78]
    node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21]
    node _T_1345 = bits(_T_1344, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49]
    node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78]
    node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21]
    node _T_1348 = bits(_T_1347, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49]
    node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79]
    node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21]
    node _T_1351 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1350) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1352 = bits(_T_1351, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1353 = and(_T_1349, _T_1352) @[el2_dec_tlu_ctl.scala 2365:89]
    node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66]
    node _T_1355 = and(_T_1353, _T_1354) @[el2_dec_tlu_ctl.scala 2366:45]
    node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48]
    node _T_1357 = and(_T_1355, _T_1356) @[el2_dec_tlu_ctl.scala 2366:77]
    node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21]
    node _T_1359 = bits(_T_1358, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41]
    node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76]
    node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21]
    node _T_1362 = bits(_T_1361, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46]
    node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76]
    node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21]
    node _T_1365 = bits(_T_1364, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46]
    node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76]
    node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21]
    node _T_1368 = bits(_T_1367, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46]
    node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76]
    node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21]
    node _T_1371 = bits(_T_1370, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46]
    node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76]
    node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21]
    node _T_1374 = bits(_T_1373, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46]
    node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76]
    node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21]
    node _T_1377 = bits(_T_1376, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46]
    node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76]
    node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21]
    node _T_1380 = bits(_T_1379, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46]
    node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76]
    node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21]
    node _T_1383 = bits(_T_1382, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46]
    node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76]
    node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21]
    node _T_1386 = bits(_T_1385, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46]
    node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76]
    node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109]
    node _T_1389 = or(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2377:88]
    node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21]
    node _T_1391 = bits(_T_1390, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49]
    node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82]
    node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21]
    node _T_1394 = bits(_T_1393, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49]
    node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84]
    node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21]
    node _T_1397 = bits(_T_1396, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49]
    node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97]
    node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21]
    node _T_1400 = bits(_T_1399, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49]
    node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21]
    node _T_1402 = bits(_T_1401, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49]
    node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21]
    node _T_1404 = bits(_T_1403, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49]
    node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21]
    node _T_1406 = bits(_T_1405, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49]
    node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21]
    node _T_1408 = bits(_T_1407, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49]
    node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21]
    node _T_1410 = bits(_T_1409, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49]
    node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21]
    node _T_1412 = bits(_T_1411, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49]
    node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21]
    node _T_1414 = bits(_T_1413, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49]
    node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85]
    node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107]
    node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21]
    node _T_1418 = bits(_T_1417, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49]
    node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79]
    node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104]
    node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21]
    node _T_1422 = bits(_T_1421, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49]
    node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21]
    node _T_1424 = bits(_T_1423, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49]
    node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21]
    node _T_1426 = bits(_T_1425, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49]
    node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84]
    node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116]
    node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21]
    node _T_1430 = bits(_T_1429, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49]
    node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21]
    node _T_1432 = bits(_T_1431, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49]
    node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21]
    node _T_1434 = bits(_T_1433, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49]
    node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21]
    node _T_1436 = bits(_T_1435, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49]
    node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21]
    node _T_1438 = bits(_T_1437, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49]
    node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21]
    node _T_1440 = bits(_T_1439, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49]
    node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21]
    node _T_1442 = bits(_T_1441, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49]
    node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21]
    node _T_1444 = bits(_T_1443, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49]
    node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_1446 = bits(_T_1445, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_1447 = not(_T_1446) @[el2_dec_tlu_ctl.scala 2400:60]
    node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21]
    node _T_1449 = bits(_T_1448, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49]
    node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_1451 = bits(_T_1450, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_1452 = not(_T_1451) @[el2_dec_tlu_ctl.scala 2401:60]
    node _T_1453 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94]
    node _T_1454 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105]
    node _T_1455 = and(_T_1453, _T_1454) @[el2_dec_tlu_ctl.scala 2401:100]
    node _T_1456 = and(_T_1452, _T_1455) @[el2_dec_tlu_ctl.scala 2401:85]
    node _T_1457 = eq(mhpme_vec[1], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21]
    node _T_1458 = bits(_T_1457, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49]
    node _T_1459 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78]
    node _T_1460 = eq(mhpme_vec[1], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21]
    node _T_1461 = bits(_T_1460, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49]
    node _T_1462 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81]
    node _T_1463 = eq(mhpme_vec[1], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21]
    node _T_1464 = bits(_T_1463, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49]
    node _T_1465 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81]
    node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21]
    node _T_1467 = bits(_T_1466, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49]
    node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21]
    node _T_1469 = bits(_T_1468, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49]
    node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21]
    node _T_1471 = bits(_T_1470, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49]
    node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21]
    node _T_1473 = bits(_T_1472, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49]
    node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21]
    node _T_1475 = bits(_T_1474, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49]
    node _T_1476 = mux(_T_1309, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1477 = mux(_T_1311, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1479 = mux(_T_1315, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1480 = mux(_T_1319, _T_1323, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1481 = mux(_T_1325, _T_1328, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1482 = mux(_T_1330, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1483 = mux(_T_1332, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1484 = mux(_T_1334, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1485 = mux(_T_1336, _T_1337, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1486 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1487 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1488 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1489 = mux(_T_1348, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1490 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1491 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1492 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1493 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1494 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1495 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1496 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1497 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1498 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1499 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1500 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1501 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1502 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1503 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1504 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1505 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1506 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1507 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1508 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1509 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1510 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1511 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1512 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1513 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1514 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1515 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1516 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1517 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1518 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1519 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1520 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1521 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1522 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1523 = mux(_T_1449, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1524 = mux(_T_1458, _T_1459, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1525 = mux(_T_1461, _T_1462, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1526 = mux(_T_1464, _T_1465, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1527 = mux(_T_1467, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1528 = mux(_T_1469, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1529 = mux(_T_1471, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1530 = mux(_T_1473, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1531 = mux(_T_1475, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1532 = or(_T_1476, _T_1477) @[Mux.scala 27:72]
    node _T_1533 = or(_T_1532, _T_1478) @[Mux.scala 27:72]
    node _T_1534 = or(_T_1533, _T_1479) @[Mux.scala 27:72]
    node _T_1535 = or(_T_1534, _T_1480) @[Mux.scala 27:72]
    node _T_1536 = or(_T_1535, _T_1481) @[Mux.scala 27:72]
    node _T_1537 = or(_T_1536, _T_1482) @[Mux.scala 27:72]
    node _T_1538 = or(_T_1537, _T_1483) @[Mux.scala 27:72]
    node _T_1539 = or(_T_1538, _T_1484) @[Mux.scala 27:72]
    node _T_1540 = or(_T_1539, _T_1485) @[Mux.scala 27:72]
    node _T_1541 = or(_T_1540, _T_1486) @[Mux.scala 27:72]
    node _T_1542 = or(_T_1541, _T_1487) @[Mux.scala 27:72]
    node _T_1543 = or(_T_1542, _T_1488) @[Mux.scala 27:72]
    node _T_1544 = or(_T_1543, _T_1489) @[Mux.scala 27:72]
    node _T_1545 = or(_T_1544, _T_1490) @[Mux.scala 27:72]
    node _T_1546 = or(_T_1545, _T_1491) @[Mux.scala 27:72]
    node _T_1547 = or(_T_1546, _T_1492) @[Mux.scala 27:72]
    node _T_1548 = or(_T_1547, _T_1493) @[Mux.scala 27:72]
    node _T_1549 = or(_T_1548, _T_1494) @[Mux.scala 27:72]
    node _T_1550 = or(_T_1549, _T_1495) @[Mux.scala 27:72]
    node _T_1551 = or(_T_1550, _T_1496) @[Mux.scala 27:72]
    node _T_1552 = or(_T_1551, _T_1497) @[Mux.scala 27:72]
    node _T_1553 = or(_T_1552, _T_1498) @[Mux.scala 27:72]
    node _T_1554 = or(_T_1553, _T_1499) @[Mux.scala 27:72]
    node _T_1555 = or(_T_1554, _T_1500) @[Mux.scala 27:72]
    node _T_1556 = or(_T_1555, _T_1501) @[Mux.scala 27:72]
    node _T_1557 = or(_T_1556, _T_1502) @[Mux.scala 27:72]
    node _T_1558 = or(_T_1557, _T_1503) @[Mux.scala 27:72]
    node _T_1559 = or(_T_1558, _T_1504) @[Mux.scala 27:72]
    node _T_1560 = or(_T_1559, _T_1505) @[Mux.scala 27:72]
    node _T_1561 = or(_T_1560, _T_1506) @[Mux.scala 27:72]
    node _T_1562 = or(_T_1561, _T_1507) @[Mux.scala 27:72]
    node _T_1563 = or(_T_1562, _T_1508) @[Mux.scala 27:72]
    node _T_1564 = or(_T_1563, _T_1509) @[Mux.scala 27:72]
    node _T_1565 = or(_T_1564, _T_1510) @[Mux.scala 27:72]
    node _T_1566 = or(_T_1565, _T_1511) @[Mux.scala 27:72]
    node _T_1567 = or(_T_1566, _T_1512) @[Mux.scala 27:72]
    node _T_1568 = or(_T_1567, _T_1513) @[Mux.scala 27:72]
    node _T_1569 = or(_T_1568, _T_1514) @[Mux.scala 27:72]
    node _T_1570 = or(_T_1569, _T_1515) @[Mux.scala 27:72]
    node _T_1571 = or(_T_1570, _T_1516) @[Mux.scala 27:72]
    node _T_1572 = or(_T_1571, _T_1517) @[Mux.scala 27:72]
    node _T_1573 = or(_T_1572, _T_1518) @[Mux.scala 27:72]
    node _T_1574 = or(_T_1573, _T_1519) @[Mux.scala 27:72]
    node _T_1575 = or(_T_1574, _T_1520) @[Mux.scala 27:72]
    node _T_1576 = or(_T_1575, _T_1521) @[Mux.scala 27:72]
    node _T_1577 = or(_T_1576, _T_1522) @[Mux.scala 27:72]
    node _T_1578 = or(_T_1577, _T_1523) @[Mux.scala 27:72]
    node _T_1579 = or(_T_1578, _T_1524) @[Mux.scala 27:72]
    node _T_1580 = or(_T_1579, _T_1525) @[Mux.scala 27:72]
    node _T_1581 = or(_T_1580, _T_1526) @[Mux.scala 27:72]
    node _T_1582 = or(_T_1581, _T_1527) @[Mux.scala 27:72]
    node _T_1583 = or(_T_1582, _T_1528) @[Mux.scala 27:72]
    node _T_1584 = or(_T_1583, _T_1529) @[Mux.scala 27:72]
    node _T_1585 = or(_T_1584, _T_1530) @[Mux.scala 27:72]
    node _T_1586 = or(_T_1585, _T_1531) @[Mux.scala 27:72]
    wire _T_1587 : UInt<6> @[Mux.scala 27:72]
    _T_1587 <= _T_1586 @[Mux.scala 27:72]
    node _T_1588 = and(_T_1307, _T_1587) @[el2_dec_tlu_ctl.scala 2351:45]
    mhpmc_inc_r[1] <= _T_1588 @[el2_dec_tlu_ctl.scala 2351:20]
    node _T_1589 = bits(mcountinhibit, 5, 5) @[el2_dec_tlu_ctl.scala 2351:39]
    node _T_1590 = not(_T_1589) @[el2_dec_tlu_ctl.scala 2351:25]
    node _T_1591 = eq(mhpme_vec[2], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21]
    node _T_1592 = bits(_T_1591, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49]
    node _T_1593 = eq(mhpme_vec[2], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21]
    node _T_1594 = bits(_T_1593, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49]
    node _T_1595 = eq(mhpme_vec[2], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21]
    node _T_1596 = bits(_T_1595, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49]
    node _T_1597 = eq(mhpme_vec[2], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21]
    node _T_1598 = bits(_T_1597, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49]
    node _T_1599 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83]
    node _T_1600 = and(io.tlu_i0_commit_cmt, _T_1599) @[el2_dec_tlu_ctl.scala 2355:81]
    node _T_1601 = eq(mhpme_vec[2], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21]
    node _T_1602 = bits(_T_1601, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49]
    node _T_1603 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83]
    node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[el2_dec_tlu_ctl.scala 2356:81]
    node _T_1605 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104]
    node _T_1606 = and(_T_1604, _T_1605) @[el2_dec_tlu_ctl.scala 2356:102]
    node _T_1607 = eq(mhpme_vec[2], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21]
    node _T_1608 = bits(_T_1607, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49]
    node _T_1609 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81]
    node _T_1610 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104]
    node _T_1611 = and(_T_1609, _T_1610) @[el2_dec_tlu_ctl.scala 2357:102]
    node _T_1612 = eq(mhpme_vec[2], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21]
    node _T_1613 = bits(_T_1612, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49]
    node _T_1614 = eq(mhpme_vec[2], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21]
    node _T_1615 = bits(_T_1614, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49]
    node _T_1616 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21]
    node _T_1617 = bits(_T_1616, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49]
    node _T_1618 = eq(mhpme_vec[2], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21]
    node _T_1619 = bits(_T_1618, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49]
    node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78]
    node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21]
    node _T_1622 = bits(_T_1621, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49]
    node _T_1623 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92]
    node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21]
    node _T_1625 = bits(_T_1624, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49]
    node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78]
    node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21]
    node _T_1628 = bits(_T_1627, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49]
    node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78]
    node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21]
    node _T_1631 = bits(_T_1630, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49]
    node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79]
    node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21]
    node _T_1634 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1633) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1635 = bits(_T_1634, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1636 = and(_T_1632, _T_1635) @[el2_dec_tlu_ctl.scala 2365:89]
    node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66]
    node _T_1638 = and(_T_1636, _T_1637) @[el2_dec_tlu_ctl.scala 2366:45]
    node _T_1639 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48]
    node _T_1640 = and(_T_1638, _T_1639) @[el2_dec_tlu_ctl.scala 2366:77]
    node _T_1641 = eq(mhpme_vec[2], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21]
    node _T_1642 = bits(_T_1641, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41]
    node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76]
    node _T_1644 = eq(mhpme_vec[2], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21]
    node _T_1645 = bits(_T_1644, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46]
    node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76]
    node _T_1647 = eq(mhpme_vec[2], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21]
    node _T_1648 = bits(_T_1647, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46]
    node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76]
    node _T_1650 = eq(mhpme_vec[2], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21]
    node _T_1651 = bits(_T_1650, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46]
    node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76]
    node _T_1653 = eq(mhpme_vec[2], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21]
    node _T_1654 = bits(_T_1653, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46]
    node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76]
    node _T_1656 = eq(mhpme_vec[2], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21]
    node _T_1657 = bits(_T_1656, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46]
    node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76]
    node _T_1659 = eq(mhpme_vec[2], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21]
    node _T_1660 = bits(_T_1659, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46]
    node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76]
    node _T_1662 = eq(mhpme_vec[2], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21]
    node _T_1663 = bits(_T_1662, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46]
    node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76]
    node _T_1665 = eq(mhpme_vec[2], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21]
    node _T_1666 = bits(_T_1665, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46]
    node _T_1667 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76]
    node _T_1668 = eq(mhpme_vec[2], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21]
    node _T_1669 = bits(_T_1668, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46]
    node _T_1670 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76]
    node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109]
    node _T_1672 = or(_T_1670, _T_1671) @[el2_dec_tlu_ctl.scala 2377:88]
    node _T_1673 = eq(mhpme_vec[2], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21]
    node _T_1674 = bits(_T_1673, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49]
    node _T_1675 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82]
    node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21]
    node _T_1677 = bits(_T_1676, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49]
    node _T_1678 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84]
    node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21]
    node _T_1680 = bits(_T_1679, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49]
    node _T_1681 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97]
    node _T_1682 = eq(mhpme_vec[2], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21]
    node _T_1683 = bits(_T_1682, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49]
    node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21]
    node _T_1685 = bits(_T_1684, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49]
    node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21]
    node _T_1687 = bits(_T_1686, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49]
    node _T_1688 = eq(mhpme_vec[2], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21]
    node _T_1689 = bits(_T_1688, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49]
    node _T_1690 = eq(mhpme_vec[2], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21]
    node _T_1691 = bits(_T_1690, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49]
    node _T_1692 = eq(mhpme_vec[2], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21]
    node _T_1693 = bits(_T_1692, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49]
    node _T_1694 = eq(mhpme_vec[2], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21]
    node _T_1695 = bits(_T_1694, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49]
    node _T_1696 = eq(mhpme_vec[2], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21]
    node _T_1697 = bits(_T_1696, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49]
    node _T_1698 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85]
    node _T_1699 = or(_T_1698, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107]
    node _T_1700 = eq(mhpme_vec[2], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21]
    node _T_1701 = bits(_T_1700, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49]
    node _T_1702 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79]
    node _T_1703 = or(_T_1702, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104]
    node _T_1704 = eq(mhpme_vec[2], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21]
    node _T_1705 = bits(_T_1704, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49]
    node _T_1706 = eq(mhpme_vec[2], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21]
    node _T_1707 = bits(_T_1706, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49]
    node _T_1708 = eq(mhpme_vec[2], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21]
    node _T_1709 = bits(_T_1708, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49]
    node _T_1710 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84]
    node _T_1711 = and(_T_1710, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116]
    node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21]
    node _T_1713 = bits(_T_1712, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49]
    node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21]
    node _T_1715 = bits(_T_1714, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49]
    node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21]
    node _T_1717 = bits(_T_1716, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49]
    node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21]
    node _T_1719 = bits(_T_1718, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49]
    node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21]
    node _T_1721 = bits(_T_1720, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49]
    node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21]
    node _T_1723 = bits(_T_1722, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49]
    node _T_1724 = eq(mhpme_vec[2], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21]
    node _T_1725 = bits(_T_1724, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49]
    node _T_1726 = eq(mhpme_vec[2], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21]
    node _T_1727 = bits(_T_1726, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49]
    node _T_1728 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_1729 = bits(_T_1728, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_1730 = not(_T_1729) @[el2_dec_tlu_ctl.scala 2400:60]
    node _T_1731 = eq(mhpme_vec[2], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21]
    node _T_1732 = bits(_T_1731, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49]
    node _T_1733 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_1734 = bits(_T_1733, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_1735 = not(_T_1734) @[el2_dec_tlu_ctl.scala 2401:60]
    node _T_1736 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94]
    node _T_1737 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105]
    node _T_1738 = and(_T_1736, _T_1737) @[el2_dec_tlu_ctl.scala 2401:100]
    node _T_1739 = and(_T_1735, _T_1738) @[el2_dec_tlu_ctl.scala 2401:85]
    node _T_1740 = eq(mhpme_vec[2], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21]
    node _T_1741 = bits(_T_1740, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49]
    node _T_1742 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78]
    node _T_1743 = eq(mhpme_vec[2], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21]
    node _T_1744 = bits(_T_1743, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49]
    node _T_1745 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81]
    node _T_1746 = eq(mhpme_vec[2], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21]
    node _T_1747 = bits(_T_1746, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49]
    node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81]
    node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21]
    node _T_1750 = bits(_T_1749, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49]
    node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21]
    node _T_1752 = bits(_T_1751, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49]
    node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21]
    node _T_1754 = bits(_T_1753, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49]
    node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21]
    node _T_1756 = bits(_T_1755, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49]
    node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21]
    node _T_1758 = bits(_T_1757, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49]
    node _T_1759 = mux(_T_1592, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1760 = mux(_T_1594, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1761 = mux(_T_1596, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1762 = mux(_T_1598, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1763 = mux(_T_1602, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1764 = mux(_T_1608, _T_1611, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1765 = mux(_T_1613, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1766 = mux(_T_1615, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1767 = mux(_T_1617, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1768 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1769 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1770 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1771 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1772 = mux(_T_1631, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1773 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1774 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1775 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1776 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1777 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1778 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1779 = mux(_T_1660, _T_1661, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1780 = mux(_T_1663, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1781 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1782 = mux(_T_1669, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1783 = mux(_T_1674, _T_1675, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1784 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1785 = mux(_T_1680, _T_1681, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1786 = mux(_T_1683, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1787 = mux(_T_1685, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1788 = mux(_T_1687, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1789 = mux(_T_1689, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1790 = mux(_T_1691, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1791 = mux(_T_1693, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1792 = mux(_T_1695, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1793 = mux(_T_1697, _T_1699, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1794 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1795 = mux(_T_1705, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1796 = mux(_T_1707, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1797 = mux(_T_1709, _T_1711, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1798 = mux(_T_1713, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1799 = mux(_T_1715, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1800 = mux(_T_1717, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1801 = mux(_T_1719, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1802 = mux(_T_1721, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1803 = mux(_T_1723, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1804 = mux(_T_1725, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1805 = mux(_T_1727, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1806 = mux(_T_1732, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1807 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1808 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1809 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1810 = mux(_T_1750, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1811 = mux(_T_1752, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1812 = mux(_T_1754, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1813 = mux(_T_1756, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1814 = mux(_T_1758, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1815 = or(_T_1759, _T_1760) @[Mux.scala 27:72]
    node _T_1816 = or(_T_1815, _T_1761) @[Mux.scala 27:72]
    node _T_1817 = or(_T_1816, _T_1762) @[Mux.scala 27:72]
    node _T_1818 = or(_T_1817, _T_1763) @[Mux.scala 27:72]
    node _T_1819 = or(_T_1818, _T_1764) @[Mux.scala 27:72]
    node _T_1820 = or(_T_1819, _T_1765) @[Mux.scala 27:72]
    node _T_1821 = or(_T_1820, _T_1766) @[Mux.scala 27:72]
    node _T_1822 = or(_T_1821, _T_1767) @[Mux.scala 27:72]
    node _T_1823 = or(_T_1822, _T_1768) @[Mux.scala 27:72]
    node _T_1824 = or(_T_1823, _T_1769) @[Mux.scala 27:72]
    node _T_1825 = or(_T_1824, _T_1770) @[Mux.scala 27:72]
    node _T_1826 = or(_T_1825, _T_1771) @[Mux.scala 27:72]
    node _T_1827 = or(_T_1826, _T_1772) @[Mux.scala 27:72]
    node _T_1828 = or(_T_1827, _T_1773) @[Mux.scala 27:72]
    node _T_1829 = or(_T_1828, _T_1774) @[Mux.scala 27:72]
    node _T_1830 = or(_T_1829, _T_1775) @[Mux.scala 27:72]
    node _T_1831 = or(_T_1830, _T_1776) @[Mux.scala 27:72]
    node _T_1832 = or(_T_1831, _T_1777) @[Mux.scala 27:72]
    node _T_1833 = or(_T_1832, _T_1778) @[Mux.scala 27:72]
    node _T_1834 = or(_T_1833, _T_1779) @[Mux.scala 27:72]
    node _T_1835 = or(_T_1834, _T_1780) @[Mux.scala 27:72]
    node _T_1836 = or(_T_1835, _T_1781) @[Mux.scala 27:72]
    node _T_1837 = or(_T_1836, _T_1782) @[Mux.scala 27:72]
    node _T_1838 = or(_T_1837, _T_1783) @[Mux.scala 27:72]
    node _T_1839 = or(_T_1838, _T_1784) @[Mux.scala 27:72]
    node _T_1840 = or(_T_1839, _T_1785) @[Mux.scala 27:72]
    node _T_1841 = or(_T_1840, _T_1786) @[Mux.scala 27:72]
    node _T_1842 = or(_T_1841, _T_1787) @[Mux.scala 27:72]
    node _T_1843 = or(_T_1842, _T_1788) @[Mux.scala 27:72]
    node _T_1844 = or(_T_1843, _T_1789) @[Mux.scala 27:72]
    node _T_1845 = or(_T_1844, _T_1790) @[Mux.scala 27:72]
    node _T_1846 = or(_T_1845, _T_1791) @[Mux.scala 27:72]
    node _T_1847 = or(_T_1846, _T_1792) @[Mux.scala 27:72]
    node _T_1848 = or(_T_1847, _T_1793) @[Mux.scala 27:72]
    node _T_1849 = or(_T_1848, _T_1794) @[Mux.scala 27:72]
    node _T_1850 = or(_T_1849, _T_1795) @[Mux.scala 27:72]
    node _T_1851 = or(_T_1850, _T_1796) @[Mux.scala 27:72]
    node _T_1852 = or(_T_1851, _T_1797) @[Mux.scala 27:72]
    node _T_1853 = or(_T_1852, _T_1798) @[Mux.scala 27:72]
    node _T_1854 = or(_T_1853, _T_1799) @[Mux.scala 27:72]
    node _T_1855 = or(_T_1854, _T_1800) @[Mux.scala 27:72]
    node _T_1856 = or(_T_1855, _T_1801) @[Mux.scala 27:72]
    node _T_1857 = or(_T_1856, _T_1802) @[Mux.scala 27:72]
    node _T_1858 = or(_T_1857, _T_1803) @[Mux.scala 27:72]
    node _T_1859 = or(_T_1858, _T_1804) @[Mux.scala 27:72]
    node _T_1860 = or(_T_1859, _T_1805) @[Mux.scala 27:72]
    node _T_1861 = or(_T_1860, _T_1806) @[Mux.scala 27:72]
    node _T_1862 = or(_T_1861, _T_1807) @[Mux.scala 27:72]
    node _T_1863 = or(_T_1862, _T_1808) @[Mux.scala 27:72]
    node _T_1864 = or(_T_1863, _T_1809) @[Mux.scala 27:72]
    node _T_1865 = or(_T_1864, _T_1810) @[Mux.scala 27:72]
    node _T_1866 = or(_T_1865, _T_1811) @[Mux.scala 27:72]
    node _T_1867 = or(_T_1866, _T_1812) @[Mux.scala 27:72]
    node _T_1868 = or(_T_1867, _T_1813) @[Mux.scala 27:72]
    node _T_1869 = or(_T_1868, _T_1814) @[Mux.scala 27:72]
    wire _T_1870 : UInt<6> @[Mux.scala 27:72]
    _T_1870 <= _T_1869 @[Mux.scala 27:72]
    node _T_1871 = and(_T_1590, _T_1870) @[el2_dec_tlu_ctl.scala 2351:45]
    mhpmc_inc_r[2] <= _T_1871 @[el2_dec_tlu_ctl.scala 2351:20]
    node _T_1872 = bits(mcountinhibit, 6, 6) @[el2_dec_tlu_ctl.scala 2351:39]
    node _T_1873 = not(_T_1872) @[el2_dec_tlu_ctl.scala 2351:25]
    node _T_1874 = eq(mhpme_vec[3], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21]
    node _T_1875 = bits(_T_1874, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49]
    node _T_1876 = eq(mhpme_vec[3], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21]
    node _T_1877 = bits(_T_1876, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49]
    node _T_1878 = eq(mhpme_vec[3], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21]
    node _T_1879 = bits(_T_1878, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49]
    node _T_1880 = eq(mhpme_vec[3], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21]
    node _T_1881 = bits(_T_1880, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49]
    node _T_1882 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83]
    node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[el2_dec_tlu_ctl.scala 2355:81]
    node _T_1884 = eq(mhpme_vec[3], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21]
    node _T_1885 = bits(_T_1884, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49]
    node _T_1886 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83]
    node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[el2_dec_tlu_ctl.scala 2356:81]
    node _T_1888 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104]
    node _T_1889 = and(_T_1887, _T_1888) @[el2_dec_tlu_ctl.scala 2356:102]
    node _T_1890 = eq(mhpme_vec[3], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21]
    node _T_1891 = bits(_T_1890, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49]
    node _T_1892 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81]
    node _T_1893 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104]
    node _T_1894 = and(_T_1892, _T_1893) @[el2_dec_tlu_ctl.scala 2357:102]
    node _T_1895 = eq(mhpme_vec[3], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21]
    node _T_1896 = bits(_T_1895, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49]
    node _T_1897 = eq(mhpme_vec[3], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21]
    node _T_1898 = bits(_T_1897, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49]
    node _T_1899 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21]
    node _T_1900 = bits(_T_1899, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49]
    node _T_1901 = eq(mhpme_vec[3], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21]
    node _T_1902 = bits(_T_1901, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49]
    node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78]
    node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21]
    node _T_1905 = bits(_T_1904, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49]
    node _T_1906 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92]
    node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21]
    node _T_1908 = bits(_T_1907, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49]
    node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78]
    node _T_1910 = eq(mhpme_vec[3], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21]
    node _T_1911 = bits(_T_1910, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49]
    node _T_1912 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78]
    node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21]
    node _T_1914 = bits(_T_1913, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49]
    node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79]
    node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21]
    node _T_1917 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1916) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1918 = bits(_T_1917, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7]
    node _T_1919 = and(_T_1915, _T_1918) @[el2_dec_tlu_ctl.scala 2365:89]
    node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66]
    node _T_1921 = and(_T_1919, _T_1920) @[el2_dec_tlu_ctl.scala 2366:45]
    node _T_1922 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48]
    node _T_1923 = and(_T_1921, _T_1922) @[el2_dec_tlu_ctl.scala 2366:77]
    node _T_1924 = eq(mhpme_vec[3], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21]
    node _T_1925 = bits(_T_1924, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41]
    node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76]
    node _T_1927 = eq(mhpme_vec[3], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21]
    node _T_1928 = bits(_T_1927, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46]
    node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76]
    node _T_1930 = eq(mhpme_vec[3], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21]
    node _T_1931 = bits(_T_1930, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46]
    node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76]
    node _T_1933 = eq(mhpme_vec[3], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21]
    node _T_1934 = bits(_T_1933, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46]
    node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76]
    node _T_1936 = eq(mhpme_vec[3], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21]
    node _T_1937 = bits(_T_1936, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46]
    node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76]
    node _T_1939 = eq(mhpme_vec[3], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21]
    node _T_1940 = bits(_T_1939, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46]
    node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76]
    node _T_1942 = eq(mhpme_vec[3], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21]
    node _T_1943 = bits(_T_1942, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46]
    node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76]
    node _T_1945 = eq(mhpme_vec[3], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21]
    node _T_1946 = bits(_T_1945, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46]
    node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76]
    node _T_1948 = eq(mhpme_vec[3], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21]
    node _T_1949 = bits(_T_1948, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46]
    node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76]
    node _T_1951 = eq(mhpme_vec[3], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21]
    node _T_1952 = bits(_T_1951, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46]
    node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76]
    node _T_1954 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109]
    node _T_1955 = or(_T_1953, _T_1954) @[el2_dec_tlu_ctl.scala 2377:88]
    node _T_1956 = eq(mhpme_vec[3], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21]
    node _T_1957 = bits(_T_1956, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49]
    node _T_1958 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82]
    node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21]
    node _T_1960 = bits(_T_1959, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49]
    node _T_1961 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84]
    node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21]
    node _T_1963 = bits(_T_1962, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49]
    node _T_1964 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97]
    node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21]
    node _T_1966 = bits(_T_1965, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49]
    node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21]
    node _T_1968 = bits(_T_1967, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49]
    node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21]
    node _T_1970 = bits(_T_1969, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49]
    node _T_1971 = eq(mhpme_vec[3], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21]
    node _T_1972 = bits(_T_1971, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49]
    node _T_1973 = eq(mhpme_vec[3], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21]
    node _T_1974 = bits(_T_1973, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49]
    node _T_1975 = eq(mhpme_vec[3], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21]
    node _T_1976 = bits(_T_1975, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49]
    node _T_1977 = eq(mhpme_vec[3], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21]
    node _T_1978 = bits(_T_1977, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49]
    node _T_1979 = eq(mhpme_vec[3], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21]
    node _T_1980 = bits(_T_1979, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49]
    node _T_1981 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85]
    node _T_1982 = or(_T_1981, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107]
    node _T_1983 = eq(mhpme_vec[3], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21]
    node _T_1984 = bits(_T_1983, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49]
    node _T_1985 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79]
    node _T_1986 = or(_T_1985, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104]
    node _T_1987 = eq(mhpme_vec[3], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21]
    node _T_1988 = bits(_T_1987, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49]
    node _T_1989 = eq(mhpme_vec[3], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21]
    node _T_1990 = bits(_T_1989, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49]
    node _T_1991 = eq(mhpme_vec[3], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21]
    node _T_1992 = bits(_T_1991, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49]
    node _T_1993 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84]
    node _T_1994 = and(_T_1993, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116]
    node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21]
    node _T_1996 = bits(_T_1995, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49]
    node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21]
    node _T_1998 = bits(_T_1997, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49]
    node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21]
    node _T_2000 = bits(_T_1999, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49]
    node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21]
    node _T_2002 = bits(_T_2001, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49]
    node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21]
    node _T_2004 = bits(_T_2003, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49]
    node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21]
    node _T_2006 = bits(_T_2005, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49]
    node _T_2007 = eq(mhpme_vec[3], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21]
    node _T_2008 = bits(_T_2007, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49]
    node _T_2009 = eq(mhpme_vec[3], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21]
    node _T_2010 = bits(_T_2009, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49]
    node _T_2011 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_2012 = bits(_T_2011, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71]
    node _T_2013 = not(_T_2012) @[el2_dec_tlu_ctl.scala 2400:60]
    node _T_2014 = eq(mhpme_vec[3], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21]
    node _T_2015 = bits(_T_2014, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49]
    node _T_2016 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_2017 = bits(_T_2016, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71]
    node _T_2018 = not(_T_2017) @[el2_dec_tlu_ctl.scala 2401:60]
    node _T_2019 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94]
    node _T_2020 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105]
    node _T_2021 = and(_T_2019, _T_2020) @[el2_dec_tlu_ctl.scala 2401:100]
    node _T_2022 = and(_T_2018, _T_2021) @[el2_dec_tlu_ctl.scala 2401:85]
    node _T_2023 = eq(mhpme_vec[3], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21]
    node _T_2024 = bits(_T_2023, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49]
    node _T_2025 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78]
    node _T_2026 = eq(mhpme_vec[3], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21]
    node _T_2027 = bits(_T_2026, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49]
    node _T_2028 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81]
    node _T_2029 = eq(mhpme_vec[3], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21]
    node _T_2030 = bits(_T_2029, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49]
    node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81]
    node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21]
    node _T_2033 = bits(_T_2032, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49]
    node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21]
    node _T_2035 = bits(_T_2034, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49]
    node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21]
    node _T_2037 = bits(_T_2036, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49]
    node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21]
    node _T_2039 = bits(_T_2038, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49]
    node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21]
    node _T_2041 = bits(_T_2040, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49]
    node _T_2042 = mux(_T_1875, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2043 = mux(_T_1877, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2044 = mux(_T_1879, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2045 = mux(_T_1881, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2046 = mux(_T_1885, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2047 = mux(_T_1891, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2048 = mux(_T_1896, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2049 = mux(_T_1898, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2050 = mux(_T_1900, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2051 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2052 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2053 = mux(_T_1908, _T_1909, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2054 = mux(_T_1911, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2055 = mux(_T_1914, _T_1923, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2056 = mux(_T_1925, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2057 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2058 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2059 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2060 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2061 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2062 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2063 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2064 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2065 = mux(_T_1952, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2066 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2067 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2068 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2069 = mux(_T_1966, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2070 = mux(_T_1968, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2071 = mux(_T_1970, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2072 = mux(_T_1972, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2073 = mux(_T_1974, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2074 = mux(_T_1976, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2075 = mux(_T_1978, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2076 = mux(_T_1980, _T_1982, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2077 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2078 = mux(_T_1988, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2079 = mux(_T_1990, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2080 = mux(_T_1992, _T_1994, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2081 = mux(_T_1996, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2082 = mux(_T_1998, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2083 = mux(_T_2000, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2084 = mux(_T_2002, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2085 = mux(_T_2004, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2086 = mux(_T_2006, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2087 = mux(_T_2008, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2088 = mux(_T_2010, _T_2013, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2089 = mux(_T_2015, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2090 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2091 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2092 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2093 = mux(_T_2033, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2094 = mux(_T_2035, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2095 = mux(_T_2037, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2096 = mux(_T_2039, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2097 = mux(_T_2041, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2098 = or(_T_2042, _T_2043) @[Mux.scala 27:72]
    node _T_2099 = or(_T_2098, _T_2044) @[Mux.scala 27:72]
    node _T_2100 = or(_T_2099, _T_2045) @[Mux.scala 27:72]
    node _T_2101 = or(_T_2100, _T_2046) @[Mux.scala 27:72]
    node _T_2102 = or(_T_2101, _T_2047) @[Mux.scala 27:72]
    node _T_2103 = or(_T_2102, _T_2048) @[Mux.scala 27:72]
    node _T_2104 = or(_T_2103, _T_2049) @[Mux.scala 27:72]
    node _T_2105 = or(_T_2104, _T_2050) @[Mux.scala 27:72]
    node _T_2106 = or(_T_2105, _T_2051) @[Mux.scala 27:72]
    node _T_2107 = or(_T_2106, _T_2052) @[Mux.scala 27:72]
    node _T_2108 = or(_T_2107, _T_2053) @[Mux.scala 27:72]
    node _T_2109 = or(_T_2108, _T_2054) @[Mux.scala 27:72]
    node _T_2110 = or(_T_2109, _T_2055) @[Mux.scala 27:72]
    node _T_2111 = or(_T_2110, _T_2056) @[Mux.scala 27:72]
    node _T_2112 = or(_T_2111, _T_2057) @[Mux.scala 27:72]
    node _T_2113 = or(_T_2112, _T_2058) @[Mux.scala 27:72]
    node _T_2114 = or(_T_2113, _T_2059) @[Mux.scala 27:72]
    node _T_2115 = or(_T_2114, _T_2060) @[Mux.scala 27:72]
    node _T_2116 = or(_T_2115, _T_2061) @[Mux.scala 27:72]
    node _T_2117 = or(_T_2116, _T_2062) @[Mux.scala 27:72]
    node _T_2118 = or(_T_2117, _T_2063) @[Mux.scala 27:72]
    node _T_2119 = or(_T_2118, _T_2064) @[Mux.scala 27:72]
    node _T_2120 = or(_T_2119, _T_2065) @[Mux.scala 27:72]
    node _T_2121 = or(_T_2120, _T_2066) @[Mux.scala 27:72]
    node _T_2122 = or(_T_2121, _T_2067) @[Mux.scala 27:72]
    node _T_2123 = or(_T_2122, _T_2068) @[Mux.scala 27:72]
    node _T_2124 = or(_T_2123, _T_2069) @[Mux.scala 27:72]
    node _T_2125 = or(_T_2124, _T_2070) @[Mux.scala 27:72]
    node _T_2126 = or(_T_2125, _T_2071) @[Mux.scala 27:72]
    node _T_2127 = or(_T_2126, _T_2072) @[Mux.scala 27:72]
    node _T_2128 = or(_T_2127, _T_2073) @[Mux.scala 27:72]
    node _T_2129 = or(_T_2128, _T_2074) @[Mux.scala 27:72]
    node _T_2130 = or(_T_2129, _T_2075) @[Mux.scala 27:72]
    node _T_2131 = or(_T_2130, _T_2076) @[Mux.scala 27:72]
    node _T_2132 = or(_T_2131, _T_2077) @[Mux.scala 27:72]
    node _T_2133 = or(_T_2132, _T_2078) @[Mux.scala 27:72]
    node _T_2134 = or(_T_2133, _T_2079) @[Mux.scala 27:72]
    node _T_2135 = or(_T_2134, _T_2080) @[Mux.scala 27:72]
    node _T_2136 = or(_T_2135, _T_2081) @[Mux.scala 27:72]
    node _T_2137 = or(_T_2136, _T_2082) @[Mux.scala 27:72]
    node _T_2138 = or(_T_2137, _T_2083) @[Mux.scala 27:72]
    node _T_2139 = or(_T_2138, _T_2084) @[Mux.scala 27:72]
    node _T_2140 = or(_T_2139, _T_2085) @[Mux.scala 27:72]
    node _T_2141 = or(_T_2140, _T_2086) @[Mux.scala 27:72]
    node _T_2142 = or(_T_2141, _T_2087) @[Mux.scala 27:72]
    node _T_2143 = or(_T_2142, _T_2088) @[Mux.scala 27:72]
    node _T_2144 = or(_T_2143, _T_2089) @[Mux.scala 27:72]
    node _T_2145 = or(_T_2144, _T_2090) @[Mux.scala 27:72]
    node _T_2146 = or(_T_2145, _T_2091) @[Mux.scala 27:72]
    node _T_2147 = or(_T_2146, _T_2092) @[Mux.scala 27:72]
    node _T_2148 = or(_T_2147, _T_2093) @[Mux.scala 27:72]
    node _T_2149 = or(_T_2148, _T_2094) @[Mux.scala 27:72]
    node _T_2150 = or(_T_2149, _T_2095) @[Mux.scala 27:72]
    node _T_2151 = or(_T_2150, _T_2096) @[Mux.scala 27:72]
    node _T_2152 = or(_T_2151, _T_2097) @[Mux.scala 27:72]
    wire _T_2153 : UInt<6> @[Mux.scala 27:72]
    _T_2153 <= _T_2152 @[Mux.scala 27:72]
    node _T_2154 = and(_T_1873, _T_2153) @[el2_dec_tlu_ctl.scala 2351:45]
    mhpmc_inc_r[3] <= _T_2154 @[el2_dec_tlu_ctl.scala 2351:20]
    reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2413:54]
    _T_2155 <= mhpmc_inc_r[0] @[el2_dec_tlu_ctl.scala 2413:54]
    mhpmc_inc_r_d1[0] <= _T_2155 @[el2_dec_tlu_ctl.scala 2413:21]
    reg _T_2156 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2414:54]
    _T_2156 <= mhpmc_inc_r[1] @[el2_dec_tlu_ctl.scala 2414:54]
    mhpmc_inc_r_d1[1] <= _T_2156 @[el2_dec_tlu_ctl.scala 2414:21]
    reg _T_2157 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2415:54]
    _T_2157 <= mhpmc_inc_r[2] @[el2_dec_tlu_ctl.scala 2415:54]
    mhpmc_inc_r_d1[2] <= _T_2157 @[el2_dec_tlu_ctl.scala 2415:21]
    reg _T_2158 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2416:54]
    _T_2158 <= mhpmc_inc_r[3] @[el2_dec_tlu_ctl.scala 2416:54]
    mhpmc_inc_r_d1[3] <= _T_2158 @[el2_dec_tlu_ctl.scala 2416:21]
    reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2417:57]
    perfcnt_halted_d1 <= perfcnt_halted @[el2_dec_tlu_ctl.scala 2417:57]
    node _T_2159 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2420:54]
    node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[el2_dec_tlu_ctl.scala 2420:45]
    node _T_2161 = or(_T_2160, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2420:68]
    perfcnt_halted <= _T_2161 @[el2_dec_tlu_ctl.scala 2420:18]
    node _T_2162 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2421:71]
    node _T_2163 = and(io.dec_tlu_dbg_halted, _T_2162) @[el2_dec_tlu_ctl.scala 2421:62]
    node _T_2164 = not(_T_2163) @[el2_dec_tlu_ctl.scala 2421:38]
    node _T_2165 = bits(_T_2164, 0, 0) @[Bitwise.scala 72:15]
    node _T_2166 = mux(_T_2165, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_2167 = bits(mhpme_vec[3], 9, 9) @[el2_dec_tlu_ctl.scala 2421:105]
    node _T_2168 = bits(mhpme_vec[2], 9, 9) @[el2_dec_tlu_ctl.scala 2421:121]
    node _T_2169 = bits(mhpme_vec[1], 9, 9) @[el2_dec_tlu_ctl.scala 2421:137]
    node _T_2170 = bits(mhpme_vec[0], 9, 9) @[el2_dec_tlu_ctl.scala 2421:153]
    node _T_2171 = cat(_T_2169, _T_2170) @[Cat.scala 29:58]
    node _T_2172 = cat(_T_2167, _T_2168) @[Cat.scala 29:58]
    node _T_2173 = cat(_T_2172, _T_2171) @[Cat.scala 29:58]
    node perfcnt_during_sleep = and(_T_2166, _T_2173) @[el2_dec_tlu_ctl.scala 2421:87]
    node _T_2174 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2423:89]
    node _T_2175 = not(_T_2174) @[el2_dec_tlu_ctl.scala 2423:68]
    node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[el2_dec_tlu_ctl.scala 2423:66]
    node _T_2177 = not(_T_2176) @[el2_dec_tlu_ctl.scala 2423:46]
    node _T_2178 = and(mhpmc_inc_r_d1[0], _T_2177) @[el2_dec_tlu_ctl.scala 2423:44]
    io.dec_tlu_perfcnt0 <= _T_2178 @[el2_dec_tlu_ctl.scala 2423:23]
    node _T_2179 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2424:89]
    node _T_2180 = not(_T_2179) @[el2_dec_tlu_ctl.scala 2424:68]
    node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[el2_dec_tlu_ctl.scala 2424:66]
    node _T_2182 = not(_T_2181) @[el2_dec_tlu_ctl.scala 2424:46]
    node _T_2183 = and(mhpmc_inc_r_d1[1], _T_2182) @[el2_dec_tlu_ctl.scala 2424:44]
    io.dec_tlu_perfcnt1 <= _T_2183 @[el2_dec_tlu_ctl.scala 2424:23]
    node _T_2184 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2425:89]
    node _T_2185 = not(_T_2184) @[el2_dec_tlu_ctl.scala 2425:68]
    node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[el2_dec_tlu_ctl.scala 2425:66]
    node _T_2187 = not(_T_2186) @[el2_dec_tlu_ctl.scala 2425:46]
    node _T_2188 = and(mhpmc_inc_r_d1[2], _T_2187) @[el2_dec_tlu_ctl.scala 2425:44]
    io.dec_tlu_perfcnt2 <= _T_2188 @[el2_dec_tlu_ctl.scala 2425:23]
    node _T_2189 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2426:89]
    node _T_2190 = not(_T_2189) @[el2_dec_tlu_ctl.scala 2426:68]
    node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[el2_dec_tlu_ctl.scala 2426:66]
    node _T_2192 = not(_T_2191) @[el2_dec_tlu_ctl.scala 2426:46]
    node _T_2193 = and(mhpmc_inc_r_d1[3], _T_2192) @[el2_dec_tlu_ctl.scala 2426:44]
    io.dec_tlu_perfcnt3 <= _T_2193 @[el2_dec_tlu_ctl.scala 2426:23]
    node _T_2194 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2432:66]
    node _T_2195 = eq(_T_2194, UInt<12>("h0b03")) @[el2_dec_tlu_ctl.scala 2432:73]
    node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2195) @[el2_dec_tlu_ctl.scala 2432:44]
    node _T_2196 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2433:24]
    node _T_2197 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2433:62]
    node _T_2198 = or(_T_2196, _T_2197) @[el2_dec_tlu_ctl.scala 2433:40]
    node _T_2199 = orr(mhpmc_inc_r[0]) @[el2_dec_tlu_ctl.scala 2433:87]
    node mhpmc3_wr_en1 = and(_T_2198, _T_2199) @[el2_dec_tlu_ctl.scala 2433:67]
    node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2434:37]
    node _T_2200 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2437:29]
    node _T_2201 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2437:42]
    node _T_2202 = cat(_T_2200, _T_2201) @[Cat.scala 29:58]
    node _T_2203 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58]
    node _T_2204 = add(_T_2202, _T_2203) @[el2_dec_tlu_ctl.scala 2437:50]
    node _T_2205 = tail(_T_2204, 1) @[el2_dec_tlu_ctl.scala 2437:50]
    mhpmc3_incr <= _T_2205 @[el2_dec_tlu_ctl.scala 2437:15]
    node _T_2206 = bits(mhpmc3_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2438:37]
    node _T_2207 = bits(mhpmc3_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2438:77]
    node mhpmc3_ns = mux(_T_2206, io.dec_csr_wrdata_r, _T_2207) @[el2_dec_tlu_ctl.scala 2438:22]
    node _T_2208 = bits(mhpmc3_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2440:43]
    inst rvclkhdr_26 of rvclkhdr_34 @[el2_lib.scala 508:23]
    rvclkhdr_26.clock <= clock
    rvclkhdr_26.reset <= reset
    rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_26.io.en <= _T_2208 @[el2_lib.scala 511:17]
    rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2209 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2209 <= mhpmc3_ns @[el2_lib.scala 514:16]
    mhpmc3 <= _T_2209 @[el2_dec_tlu_ctl.scala 2440:10]
    node _T_2210 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2442:67]
    node _T_2211 = eq(_T_2210, UInt<12>("h0b83")) @[el2_dec_tlu_ctl.scala 2442:74]
    node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2211) @[el2_dec_tlu_ctl.scala 2442:45]
    node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2443:39]
    node _T_2212 = bits(mhpmc3h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2444:39]
    node _T_2213 = bits(mhpmc3_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2444:79]
    node mhpmc3h_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[el2_dec_tlu_ctl.scala 2444:23]
    node _T_2214 = bits(mhpmc3h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2446:47]
    inst rvclkhdr_27 of rvclkhdr_35 @[el2_lib.scala 508:23]
    rvclkhdr_27.clock <= clock
    rvclkhdr_27.reset <= reset
    rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_27.io.en <= _T_2214 @[el2_lib.scala 511:17]
    rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2215 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2215 <= mhpmc3h_ns @[el2_lib.scala 514:16]
    mhpmc3h <= _T_2215 @[el2_dec_tlu_ctl.scala 2446:11]
    node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2451:66]
    node _T_2217 = eq(_T_2216, UInt<12>("h0b04")) @[el2_dec_tlu_ctl.scala 2451:73]
    node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[el2_dec_tlu_ctl.scala 2451:44]
    node _T_2218 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2452:24]
    node _T_2219 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2452:62]
    node _T_2220 = or(_T_2218, _T_2219) @[el2_dec_tlu_ctl.scala 2452:40]
    node _T_2221 = orr(mhpmc_inc_r[1]) @[el2_dec_tlu_ctl.scala 2452:87]
    node mhpmc4_wr_en1 = and(_T_2220, _T_2221) @[el2_dec_tlu_ctl.scala 2452:67]
    node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2453:37]
    node _T_2222 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2457:29]
    node _T_2223 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2457:42]
    node _T_2224 = cat(_T_2222, _T_2223) @[Cat.scala 29:58]
    node _T_2225 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58]
    node _T_2226 = add(_T_2224, _T_2225) @[el2_dec_tlu_ctl.scala 2457:50]
    node _T_2227 = tail(_T_2226, 1) @[el2_dec_tlu_ctl.scala 2457:50]
    mhpmc4_incr <= _T_2227 @[el2_dec_tlu_ctl.scala 2457:15]
    node _T_2228 = bits(mhpmc4_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2458:37]
    node _T_2229 = bits(io.dec_csr_wrdata_r, 31, 0) @[el2_dec_tlu_ctl.scala 2458:64]
    node _T_2230 = bits(mhpmc4_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2458:83]
    node mhpmc4_ns = mux(_T_2228, _T_2229, _T_2230) @[el2_dec_tlu_ctl.scala 2458:22]
    node _T_2231 = bits(mhpmc4_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2459:44]
    inst rvclkhdr_28 of rvclkhdr_36 @[el2_lib.scala 508:23]
    rvclkhdr_28.clock <= clock
    rvclkhdr_28.reset <= reset
    rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_28.io.en <= _T_2231 @[el2_lib.scala 511:17]
    rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2232 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2232 <= mhpmc4_ns @[el2_lib.scala 514:16]
    mhpmc4 <= _T_2232 @[el2_dec_tlu_ctl.scala 2459:10]
    node _T_2233 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2461:67]
    node _T_2234 = eq(_T_2233, UInt<12>("h0b84")) @[el2_dec_tlu_ctl.scala 2461:74]
    node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2234) @[el2_dec_tlu_ctl.scala 2461:45]
    node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2462:39]
    node _T_2235 = bits(mhpmc4h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2463:39]
    node _T_2236 = bits(mhpmc4_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2463:79]
    node mhpmc4h_ns = mux(_T_2235, io.dec_csr_wrdata_r, _T_2236) @[el2_dec_tlu_ctl.scala 2463:23]
    node _T_2237 = bits(mhpmc4h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2464:47]
    inst rvclkhdr_29 of rvclkhdr_37 @[el2_lib.scala 508:23]
    rvclkhdr_29.clock <= clock
    rvclkhdr_29.reset <= reset
    rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_29.io.en <= _T_2237 @[el2_lib.scala 511:17]
    rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2238 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2238 <= mhpmc4h_ns @[el2_lib.scala 514:16]
    mhpmc4h <= _T_2238 @[el2_dec_tlu_ctl.scala 2464:11]
    node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2470:66]
    node _T_2240 = eq(_T_2239, UInt<12>("h0b05")) @[el2_dec_tlu_ctl.scala 2470:73]
    node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[el2_dec_tlu_ctl.scala 2470:44]
    node _T_2241 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2471:24]
    node _T_2242 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2471:62]
    node _T_2243 = or(_T_2241, _T_2242) @[el2_dec_tlu_ctl.scala 2471:40]
    node _T_2244 = orr(mhpmc_inc_r[2]) @[el2_dec_tlu_ctl.scala 2471:87]
    node mhpmc5_wr_en1 = and(_T_2243, _T_2244) @[el2_dec_tlu_ctl.scala 2471:67]
    node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2472:37]
    node _T_2245 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2474:29]
    node _T_2246 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2474:42]
    node _T_2247 = cat(_T_2245, _T_2246) @[Cat.scala 29:58]
    node _T_2248 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58]
    node _T_2249 = add(_T_2247, _T_2248) @[el2_dec_tlu_ctl.scala 2474:50]
    node _T_2250 = tail(_T_2249, 1) @[el2_dec_tlu_ctl.scala 2474:50]
    mhpmc5_incr <= _T_2250 @[el2_dec_tlu_ctl.scala 2474:15]
    node _T_2251 = bits(mhpmc5_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2475:37]
    node _T_2252 = bits(mhpmc5_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2475:77]
    node mhpmc5_ns = mux(_T_2251, io.dec_csr_wrdata_r, _T_2252) @[el2_dec_tlu_ctl.scala 2475:22]
    node _T_2253 = bits(mhpmc5_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2477:44]
    inst rvclkhdr_30 of rvclkhdr_38 @[el2_lib.scala 508:23]
    rvclkhdr_30.clock <= clock
    rvclkhdr_30.reset <= reset
    rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_30.io.en <= _T_2253 @[el2_lib.scala 511:17]
    rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2254 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2254 <= mhpmc5_ns @[el2_lib.scala 514:16]
    mhpmc5 <= _T_2254 @[el2_dec_tlu_ctl.scala 2477:10]
    node _T_2255 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2479:67]
    node _T_2256 = eq(_T_2255, UInt<12>("h0b85")) @[el2_dec_tlu_ctl.scala 2479:74]
    node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2256) @[el2_dec_tlu_ctl.scala 2479:45]
    node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2480:39]
    node _T_2257 = bits(mhpmc5h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2481:39]
    node _T_2258 = bits(mhpmc5_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2481:79]
    node mhpmc5h_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[el2_dec_tlu_ctl.scala 2481:23]
    node _T_2259 = bits(mhpmc5h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2483:47]
    inst rvclkhdr_31 of rvclkhdr_39 @[el2_lib.scala 508:23]
    rvclkhdr_31.clock <= clock
    rvclkhdr_31.reset <= reset
    rvclkhdr_31.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_31.io.en <= _T_2259 @[el2_lib.scala 511:17]
    rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2260 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2260 <= mhpmc5h_ns @[el2_lib.scala 514:16]
    mhpmc5h <= _T_2260 @[el2_dec_tlu_ctl.scala 2483:11]
    node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2488:66]
    node _T_2262 = eq(_T_2261, UInt<12>("h0b06")) @[el2_dec_tlu_ctl.scala 2488:73]
    node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[el2_dec_tlu_ctl.scala 2488:44]
    node _T_2263 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2489:24]
    node _T_2264 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2489:62]
    node _T_2265 = or(_T_2263, _T_2264) @[el2_dec_tlu_ctl.scala 2489:40]
    node _T_2266 = orr(mhpmc_inc_r[3]) @[el2_dec_tlu_ctl.scala 2489:87]
    node mhpmc6_wr_en1 = and(_T_2265, _T_2266) @[el2_dec_tlu_ctl.scala 2489:67]
    node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2490:37]
    node _T_2267 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2492:29]
    node _T_2268 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2492:42]
    node _T_2269 = cat(_T_2267, _T_2268) @[Cat.scala 29:58]
    node _T_2270 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58]
    node _T_2271 = add(_T_2269, _T_2270) @[el2_dec_tlu_ctl.scala 2492:50]
    node _T_2272 = tail(_T_2271, 1) @[el2_dec_tlu_ctl.scala 2492:50]
    mhpmc6_incr <= _T_2272 @[el2_dec_tlu_ctl.scala 2492:15]
    node _T_2273 = bits(mhpmc6_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2493:37]
    node _T_2274 = bits(mhpmc6_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2493:77]
    node mhpmc6_ns = mux(_T_2273, io.dec_csr_wrdata_r, _T_2274) @[el2_dec_tlu_ctl.scala 2493:22]
    node _T_2275 = bits(mhpmc6_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2495:44]
    inst rvclkhdr_32 of rvclkhdr_40 @[el2_lib.scala 508:23]
    rvclkhdr_32.clock <= clock
    rvclkhdr_32.reset <= reset
    rvclkhdr_32.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_32.io.en <= _T_2275 @[el2_lib.scala 511:17]
    rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2276 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2276 <= mhpmc6_ns @[el2_lib.scala 514:16]
    mhpmc6 <= _T_2276 @[el2_dec_tlu_ctl.scala 2495:10]
    node _T_2277 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2497:67]
    node _T_2278 = eq(_T_2277, UInt<12>("h0b86")) @[el2_dec_tlu_ctl.scala 2497:74]
    node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2278) @[el2_dec_tlu_ctl.scala 2497:45]
    node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2498:39]
    node _T_2279 = bits(mhpmc6h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2499:39]
    node _T_2280 = bits(mhpmc6_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2499:79]
    node mhpmc6h_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[el2_dec_tlu_ctl.scala 2499:23]
    node _T_2281 = bits(mhpmc6h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2501:47]
    inst rvclkhdr_33 of rvclkhdr_41 @[el2_lib.scala 508:23]
    rvclkhdr_33.clock <= clock
    rvclkhdr_33.reset <= reset
    rvclkhdr_33.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_33.io.en <= _T_2281 @[el2_lib.scala 511:17]
    rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_2282 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_2282 <= mhpmc6h_ns @[el2_lib.scala 514:16]
    mhpmc6h <= _T_2282 @[el2_dec_tlu_ctl.scala 2501:11]
    node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:51]
    node _T_2284 = gt(_T_2283, UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2508:57]
    node _T_2285 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2508:94]
    node _T_2286 = orr(_T_2285) @[el2_dec_tlu_ctl.scala 2508:103]
    node _T_2287 = or(_T_2284, _T_2286) @[el2_dec_tlu_ctl.scala 2508:72]
    node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:142]
    node event_saturate_r = mux(_T_2287, UInt<10>("h0204"), _T_2288) @[el2_dec_tlu_ctl.scala 2508:29]
    node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2510:64]
    node _T_2290 = eq(_T_2289, UInt<12>("h0323")) @[el2_dec_tlu_ctl.scala 2510:71]
    node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2290) @[el2_dec_tlu_ctl.scala 2510:42]
    node _T_2291 = bits(wr_mhpme3_r, 0, 0) @[el2_dec_tlu_ctl.scala 2512:81]
    reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_2291 : @[Reg.scala 28:19]
      _T_2292 <= event_saturate_r @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    mhpme3 <= _T_2292 @[el2_dec_tlu_ctl.scala 2512:10]
    node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2517:64]
    node _T_2294 = eq(_T_2293, UInt<12>("h0324")) @[el2_dec_tlu_ctl.scala 2517:71]
    node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2294) @[el2_dec_tlu_ctl.scala 2517:42]
    node _T_2295 = bits(wr_mhpme4_r, 0, 0) @[el2_dec_tlu_ctl.scala 2518:81]
    reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_2295 : @[Reg.scala 28:19]
      _T_2296 <= event_saturate_r @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    mhpme4 <= _T_2296 @[el2_dec_tlu_ctl.scala 2518:10]
    node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2524:64]
    node _T_2298 = eq(_T_2297, UInt<12>("h0325")) @[el2_dec_tlu_ctl.scala 2524:71]
    node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2298) @[el2_dec_tlu_ctl.scala 2524:42]
    node _T_2299 = bits(wr_mhpme5_r, 0, 0) @[el2_dec_tlu_ctl.scala 2525:81]
    reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_2299 : @[Reg.scala 28:19]
      _T_2300 <= event_saturate_r @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    mhpme5 <= _T_2300 @[el2_dec_tlu_ctl.scala 2525:10]
    node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2531:64]
    node _T_2302 = eq(_T_2301, UInt<12>("h0326")) @[el2_dec_tlu_ctl.scala 2531:71]
    node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2302) @[el2_dec_tlu_ctl.scala 2531:42]
    node _T_2303 = bits(wr_mhpme6_r, 0, 0) @[el2_dec_tlu_ctl.scala 2532:81]
    reg _T_2304 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_2303 : @[Reg.scala 28:19]
      _T_2304 <= event_saturate_r @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    mhpme6 <= _T_2304 @[el2_dec_tlu_ctl.scala 2532:10]
    node _T_2305 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2548:71]
    node _T_2306 = eq(_T_2305, UInt<12>("h0320")) @[el2_dec_tlu_ctl.scala 2548:78]
    node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2306) @[el2_dec_tlu_ctl.scala 2548:49]
    node _T_2307 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2550:55]
    wire temp_ncount0 : UInt<1>
    temp_ncount0 <= _T_2307
    node _T_2308 = bits(mcountinhibit, 1, 1) @[el2_dec_tlu_ctl.scala 2551:55]
    wire temp_ncount1 : UInt<1>
    temp_ncount1 <= _T_2308
    node _T_2309 = bits(mcountinhibit, 6, 2) @[el2_dec_tlu_ctl.scala 2552:56]
    wire temp_ncount6_2 : UInt<5>
    temp_ncount6_2 <= _T_2309
    node _T_2310 = bits(io.dec_csr_wrdata_r, 6, 2) @[el2_dec_tlu_ctl.scala 2553:75]
    node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2553:104]
    reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_2311 : @[Reg.scala 28:19]
      _T_2312 <= _T_2310 @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    temp_ncount6_2 <= _T_2312 @[el2_dec_tlu_ctl.scala 2553:18]
    node _T_2313 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:73]
    node _T_2314 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:100]
    reg _T_2315 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_2314 : @[Reg.scala 28:19]
      _T_2315 <= _T_2313 @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    temp_ncount0 <= _T_2315 @[el2_dec_tlu_ctl.scala 2555:16]
    node _T_2316 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_2317 = cat(_T_2316, temp_ncount0) @[Cat.scala 29:58]
    mcountinhibit <= _T_2317 @[el2_dec_tlu_ctl.scala 2556:17]
    node _T_2318 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:52]
    node _T_2319 = or(_T_2318, io.interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:79]
    node _T_2320 = or(_T_2319, io.dec_tlu_i0_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:105]
    node _T_2321 = or(_T_2320, io.dec_tlu_i0_exc_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:131]
    node _T_2322 = or(_T_2321, io.dec_tlu_int_valid_wb1) @[el2_dec_tlu_ctl.scala 2564:33]
    node _T_2323 = or(_T_2322, io.clk_override) @[el2_dec_tlu_ctl.scala 2564:60]
    node _T_2324 = bits(_T_2323, 0, 0) @[el2_dec_tlu_ctl.scala 2564:79]
    inst rvclkhdr_34 of rvclkhdr_42 @[el2_lib.scala 483:22]
    rvclkhdr_34.clock <= clock
    rvclkhdr_34.reset <= reset
    rvclkhdr_34.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr_34.io.en <= _T_2324 @[el2_lib.scala 485:16]
    rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2566:63]
    _T_2325 <= io.i0_valid_wb @[el2_dec_tlu_ctl.scala 2566:63]
    io.dec_tlu_i0_valid_wb1 <= _T_2325 @[el2_dec_tlu_ctl.scala 2566:31]
    node _T_2326 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[el2_dec_tlu_ctl.scala 2567:92]
    node _T_2327 = not(io.trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 2567:138]
    node _T_2328 = and(io.trigger_hit_r_d1, _T_2327) @[el2_dec_tlu_ctl.scala 2567:136]
    node _T_2329 = or(_T_2326, _T_2328) @[el2_dec_tlu_ctl.scala 2567:113]
    reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2567:63]
    _T_2330 <= _T_2329 @[el2_dec_tlu_ctl.scala 2567:63]
    io.dec_tlu_i0_exc_valid_wb1 <= _T_2330 @[el2_dec_tlu_ctl.scala 2567:31]
    reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2568:63]
    _T_2331 <= io.exc_cause_wb @[el2_dec_tlu_ctl.scala 2568:63]
    io.dec_tlu_exc_cause_wb1 <= _T_2331 @[el2_dec_tlu_ctl.scala 2568:31]
    reg _T_2332 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2569:63]
    _T_2332 <= io.interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 2569:63]
    io.dec_tlu_int_valid_wb1 <= _T_2332 @[el2_dec_tlu_ctl.scala 2569:31]
    io.dec_tlu_mtval_wb1 <= mtval @[el2_dec_tlu_ctl.scala 2571:25]
    node _T_2333 = bits(io.csr_pkt.csr_misa, 0, 0) @[el2_dec_tlu_ctl.scala 2577:25]
    node _T_2334 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[el2_dec_tlu_ctl.scala 2578:30]
    node _T_2335 = bits(io.csr_pkt.csr_marchid, 0, 0) @[el2_dec_tlu_ctl.scala 2579:28]
    node _T_2336 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[el2_dec_tlu_ctl.scala 2580:27]
    node _T_2337 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[el2_dec_tlu_ctl.scala 2581:28]
    node _T_2338 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58]
    node _T_2339 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:28]
    node _T_2340 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 2582:91]
    node _T_2341 = bits(io.mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:116]
    node _T_2342 = cat(UInt<3>("h00"), _T_2341) @[Cat.scala 29:58]
    node _T_2343 = cat(_T_2342, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2344 = cat(UInt<3>("h00"), _T_2340) @[Cat.scala 29:58]
    node _T_2345 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
    node _T_2346 = cat(_T_2345, _T_2344) @[Cat.scala 29:58]
    node _T_2347 = cat(_T_2346, _T_2343) @[Cat.scala 29:58]
    node _T_2348 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:26]
    node _T_2349 = bits(io.mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 2583:58]
    node _T_2350 = bits(io.mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:84]
    node _T_2351 = cat(_T_2349, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58]
    node _T_2353 = bits(io.csr_pkt.csr_mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:24]
    node _T_2354 = bits(io.mip, 5, 3) @[el2_dec_tlu_ctl.scala 2584:66]
    node _T_2355 = bits(io.mip, 2, 2) @[el2_dec_tlu_ctl.scala 2584:90]
    node _T_2356 = bits(io.mip, 1, 1) @[el2_dec_tlu_ctl.scala 2584:111]
    node _T_2357 = bits(io.mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:132]
    node _T_2358 = cat(_T_2357, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2359 = cat(_T_2356, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2360 = cat(_T_2359, _T_2358) @[Cat.scala 29:58]
    node _T_2361 = cat(_T_2355, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2362 = cat(UInt<1>("h00"), _T_2354) @[Cat.scala 29:58]
    node _T_2363 = cat(_T_2362, UInt<16>("h00")) @[Cat.scala 29:58]
    node _T_2364 = cat(_T_2363, _T_2361) @[Cat.scala 29:58]
    node _T_2365 = cat(_T_2364, _T_2360) @[Cat.scala 29:58]
    node _T_2366 = bits(io.csr_pkt.csr_mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:24]
    node _T_2367 = bits(mie, 5, 3) @[el2_dec_tlu_ctl.scala 2585:63]
    node _T_2368 = bits(mie, 2, 2) @[el2_dec_tlu_ctl.scala 2585:84]
    node _T_2369 = bits(mie, 1, 1) @[el2_dec_tlu_ctl.scala 2585:102]
    node _T_2370 = bits(mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:120]
    node _T_2371 = cat(_T_2370, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2372 = cat(_T_2369, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2373 = cat(_T_2372, _T_2371) @[Cat.scala 29:58]
    node _T_2374 = cat(_T_2368, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2375 = cat(UInt<1>("h00"), _T_2367) @[Cat.scala 29:58]
    node _T_2376 = cat(_T_2375, UInt<16>("h00")) @[Cat.scala 29:58]
    node _T_2377 = cat(_T_2376, _T_2374) @[Cat.scala 29:58]
    node _T_2378 = cat(_T_2377, _T_2373) @[Cat.scala 29:58]
    node _T_2379 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[el2_dec_tlu_ctl.scala 2586:28]
    node _T_2380 = bits(mcyclel, 31, 0) @[el2_dec_tlu_ctl.scala 2586:53]
    node _T_2381 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[el2_dec_tlu_ctl.scala 2587:28]
    node _T_2382 = bits(mcycleh_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2587:57]
    node _T_2383 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[el2_dec_tlu_ctl.scala 2588:30]
    node _T_2384 = bits(minstretl, 31, 0) @[el2_dec_tlu_ctl.scala 2588:60]
    node _T_2385 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[el2_dec_tlu_ctl.scala 2589:30]
    node _T_2386 = bits(minstreth_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2589:60]
    node _T_2387 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[el2_dec_tlu_ctl.scala 2590:29]
    node _T_2388 = bits(mscratch, 31, 0) @[el2_dec_tlu_ctl.scala 2590:54]
    node _T_2389 = bits(io.csr_pkt.csr_mepc, 0, 0) @[el2_dec_tlu_ctl.scala 2591:25]
    node _T_2390 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_2391 = bits(io.csr_pkt.csr_mcause, 0, 0) @[el2_dec_tlu_ctl.scala 2592:27]
    node _T_2392 = bits(mcause, 31, 0) @[el2_dec_tlu_ctl.scala 2592:52]
    node _T_2393 = bits(io.csr_pkt.csr_mscause, 0, 0) @[el2_dec_tlu_ctl.scala 2593:28]
    node _T_2394 = bits(mscause, 3, 0) @[el2_dec_tlu_ctl.scala 2593:68]
    node _T_2395 = cat(UInt<28>("h00"), _T_2394) @[Cat.scala 29:58]
    node _T_2396 = bits(io.csr_pkt.csr_mtval, 0, 0) @[el2_dec_tlu_ctl.scala 2594:26]
    node _T_2397 = bits(mtval, 31, 0) @[el2_dec_tlu_ctl.scala 2594:51]
    node _T_2398 = bits(io.csr_pkt.csr_mrac, 0, 0) @[el2_dec_tlu_ctl.scala 2595:25]
    node _T_2399 = bits(mrac, 31, 0) @[el2_dec_tlu_ctl.scala 2595:50]
    node _T_2400 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[el2_dec_tlu_ctl.scala 2596:27]
    node _T_2401 = bits(mdseac, 31, 0) @[el2_dec_tlu_ctl.scala 2596:52]
    node _T_2402 = bits(io.csr_pkt.csr_meivt, 0, 0) @[el2_dec_tlu_ctl.scala 2597:26]
    node _T_2403 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58]
    node _T_2404 = bits(io.csr_pkt.csr_meihap, 0, 0) @[el2_dec_tlu_ctl.scala 2598:27]
    node _T_2405 = cat(meivt, meihap) @[Cat.scala 29:58]
    node _T_2406 = cat(_T_2405, UInt<2>("h00")) @[Cat.scala 29:58]
    node _T_2407 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[el2_dec_tlu_ctl.scala 2599:29]
    node _T_2408 = bits(meicurpl, 3, 0) @[el2_dec_tlu_ctl.scala 2599:69]
    node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58]
    node _T_2410 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[el2_dec_tlu_ctl.scala 2600:29]
    node _T_2411 = bits(meicidpl, 3, 0) @[el2_dec_tlu_ctl.scala 2600:69]
    node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58]
    node _T_2413 = bits(io.csr_pkt.csr_meipt, 0, 0) @[el2_dec_tlu_ctl.scala 2601:26]
    node _T_2414 = bits(meipt, 3, 0) @[el2_dec_tlu_ctl.scala 2601:66]
    node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58]
    node _T_2416 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 2602:25]
    node _T_2417 = bits(mcgc, 8, 0) @[el2_dec_tlu_ctl.scala 2602:65]
    node _T_2418 = cat(UInt<23>("h00"), _T_2417) @[Cat.scala 29:58]
    node _T_2419 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 2603:25]
    node _T_2420 = bits(mfdc, 18, 0) @[el2_dec_tlu_ctl.scala 2603:65]
    node _T_2421 = cat(UInt<13>("h00"), _T_2420) @[Cat.scala 29:58]
    node _T_2422 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[el2_dec_tlu_ctl.scala 2604:25]
    node _T_2423 = bits(io.dcsr, 15, 2) @[el2_dec_tlu_ctl.scala 2604:73]
    node _T_2424 = cat(UInt<16>("h04000"), _T_2423) @[Cat.scala 29:58]
    node _T_2425 = cat(_T_2424, UInt<2>("h03")) @[Cat.scala 29:58]
    node _T_2426 = bits(io.csr_pkt.csr_dpc, 0, 0) @[el2_dec_tlu_ctl.scala 2605:24]
    node _T_2427 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_2428 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[el2_dec_tlu_ctl.scala 2606:27]
    node _T_2429 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2606:52]
    node _T_2430 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[el2_dec_tlu_ctl.scala 2607:28]
    node _T_2431 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2607:53]
    node _T_2432 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[el2_dec_tlu_ctl.scala 2608:27]
    node _T_2433 = bits(dicad1, 31, 0) @[el2_dec_tlu_ctl.scala 2608:52]
    node _T_2434 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[el2_dec_tlu_ctl.scala 2609:29]
    node _T_2435 = bits(dicawics, 16, 16) @[el2_dec_tlu_ctl.scala 2609:68]
    node _T_2436 = bits(dicawics, 15, 14) @[el2_dec_tlu_ctl.scala 2609:92]
    node _T_2437 = bits(dicawics, 13, 0) @[el2_dec_tlu_ctl.scala 2609:119]
    node _T_2438 = cat(UInt<3>("h00"), _T_2437) @[Cat.scala 29:58]
    node _T_2439 = cat(_T_2438, UInt<3>("h00")) @[Cat.scala 29:58]
    node _T_2440 = cat(UInt<2>("h00"), _T_2436) @[Cat.scala 29:58]
    node _T_2441 = cat(UInt<7>("h00"), _T_2435) @[Cat.scala 29:58]
    node _T_2442 = cat(_T_2441, _T_2440) @[Cat.scala 29:58]
    node _T_2443 = cat(_T_2442, _T_2439) @[Cat.scala 29:58]
    node _T_2444 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[el2_dec_tlu_ctl.scala 2610:26]
    node _T_2445 = bits(mtsel, 1, 0) @[el2_dec_tlu_ctl.scala 2610:66]
    node _T_2446 = cat(UInt<30>("h00"), _T_2445) @[Cat.scala 29:58]
    node _T_2447 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[el2_dec_tlu_ctl.scala 2611:28]
    node _T_2448 = bits(mtdata1_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2611:62]
    node _T_2449 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[el2_dec_tlu_ctl.scala 2612:28]
    node _T_2450 = bits(mtdata2_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2612:62]
    node _T_2451 = bits(io.csr_pkt.csr_micect, 0, 0) @[el2_dec_tlu_ctl.scala 2613:27]
    node _T_2452 = bits(micect, 31, 0) @[el2_dec_tlu_ctl.scala 2613:52]
    node _T_2453 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2614:29]
    node _T_2454 = bits(miccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2614:54]
    node _T_2455 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2615:29]
    node _T_2456 = bits(mdccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2615:54]
    node _T_2457 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[el2_dec_tlu_ctl.scala 2616:27]
    node _T_2458 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2616:52]
    node _T_2459 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[el2_dec_tlu_ctl.scala 2617:27]
    node _T_2460 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2617:52]
    node _T_2461 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[el2_dec_tlu_ctl.scala 2618:27]
    node _T_2462 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2618:52]
    node _T_2463 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[el2_dec_tlu_ctl.scala 2619:27]
    node _T_2464 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2619:52]
    node _T_2465 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[el2_dec_tlu_ctl.scala 2620:28]
    node _T_2466 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2620:53]
    node _T_2467 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[el2_dec_tlu_ctl.scala 2621:28]
    node _T_2468 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2621:53]
    node _T_2469 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[el2_dec_tlu_ctl.scala 2622:28]
    node _T_2470 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2622:53]
    node _T_2471 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[el2_dec_tlu_ctl.scala 2623:28]
    node _T_2472 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2623:53]
    node _T_2473 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2624:26]
    node _T_2474 = bits(mfdht, 5, 0) @[el2_dec_tlu_ctl.scala 2624:66]
    node _T_2475 = cat(UInt<26>("h00"), _T_2474) @[Cat.scala 29:58]
    node _T_2476 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[el2_dec_tlu_ctl.scala 2625:26]
    node _T_2477 = bits(mfdhs, 1, 0) @[el2_dec_tlu_ctl.scala 2625:66]
    node _T_2478 = cat(UInt<30>("h00"), _T_2477) @[Cat.scala 29:58]
    node _T_2479 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[el2_dec_tlu_ctl.scala 2626:27]
    node _T_2480 = bits(mhpme3, 9, 0) @[el2_dec_tlu_ctl.scala 2626:67]
    node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58]
    node _T_2482 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[el2_dec_tlu_ctl.scala 2627:27]
    node _T_2483 = bits(mhpme4, 9, 0) @[el2_dec_tlu_ctl.scala 2627:67]
    node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58]
    node _T_2485 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[el2_dec_tlu_ctl.scala 2628:27]
    node _T_2486 = bits(mhpme5, 9, 0) @[el2_dec_tlu_ctl.scala 2628:66]
    node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58]
    node _T_2488 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[el2_dec_tlu_ctl.scala 2629:27]
    node _T_2489 = bits(mhpme6, 9, 0) @[el2_dec_tlu_ctl.scala 2629:66]
    node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58]
    node _T_2491 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2630:34]
    node _T_2492 = bits(mcountinhibit, 6, 0) @[el2_dec_tlu_ctl.scala 2630:74]
    node _T_2493 = cat(UInt<25>("h00"), _T_2492) @[Cat.scala 29:58]
    node _T_2494 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[el2_dec_tlu_ctl.scala 2631:25]
    node _T_2495 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58]
    node _T_2496 = cat(_T_2495, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_2497 = bits(io.dec_timer_read_d, 0, 0) @[el2_dec_tlu_ctl.scala 2632:25]
    node _T_2498 = bits(io.dec_timer_rddata_d, 31, 0) @[el2_dec_tlu_ctl.scala 2632:64]
    node _T_2499 = mux(_T_2333, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2500 = mux(_T_2334, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2501 = mux(_T_2335, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2502 = mux(_T_2336, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2503 = mux(_T_2337, _T_2338, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2504 = mux(_T_2339, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2505 = mux(_T_2348, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2506 = mux(_T_2353, _T_2365, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2507 = mux(_T_2366, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2508 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2509 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2510 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2511 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2512 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2513 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2514 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2515 = mux(_T_2393, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2516 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2517 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2518 = mux(_T_2400, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2519 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2520 = mux(_T_2404, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2521 = mux(_T_2407, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2522 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2523 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2524 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2525 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2526 = mux(_T_2422, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2527 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2528 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2529 = mux(_T_2430, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2530 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2531 = mux(_T_2434, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2532 = mux(_T_2444, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2533 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2534 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2535 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2536 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2537 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2538 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2539 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2540 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2541 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2542 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2543 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2544 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2545 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2546 = mux(_T_2473, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2547 = mux(_T_2476, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2548 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2549 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2550 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2551 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2552 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2553 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2554 = mux(_T_2497, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_2555 = or(_T_2499, _T_2500) @[Mux.scala 27:72]
    node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72]
    node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72]
    node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72]
    node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72]
    node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72]
    node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72]
    node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72]
    node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72]
    node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72]
    node _T_2565 = or(_T_2564, _T_2510) @[Mux.scala 27:72]
    node _T_2566 = or(_T_2565, _T_2511) @[Mux.scala 27:72]
    node _T_2567 = or(_T_2566, _T_2512) @[Mux.scala 27:72]
    node _T_2568 = or(_T_2567, _T_2513) @[Mux.scala 27:72]
    node _T_2569 = or(_T_2568, _T_2514) @[Mux.scala 27:72]
    node _T_2570 = or(_T_2569, _T_2515) @[Mux.scala 27:72]
    node _T_2571 = or(_T_2570, _T_2516) @[Mux.scala 27:72]
    node _T_2572 = or(_T_2571, _T_2517) @[Mux.scala 27:72]
    node _T_2573 = or(_T_2572, _T_2518) @[Mux.scala 27:72]
    node _T_2574 = or(_T_2573, _T_2519) @[Mux.scala 27:72]
    node _T_2575 = or(_T_2574, _T_2520) @[Mux.scala 27:72]
    node _T_2576 = or(_T_2575, _T_2521) @[Mux.scala 27:72]
    node _T_2577 = or(_T_2576, _T_2522) @[Mux.scala 27:72]
    node _T_2578 = or(_T_2577, _T_2523) @[Mux.scala 27:72]
    node _T_2579 = or(_T_2578, _T_2524) @[Mux.scala 27:72]
    node _T_2580 = or(_T_2579, _T_2525) @[Mux.scala 27:72]
    node _T_2581 = or(_T_2580, _T_2526) @[Mux.scala 27:72]
    node _T_2582 = or(_T_2581, _T_2527) @[Mux.scala 27:72]
    node _T_2583 = or(_T_2582, _T_2528) @[Mux.scala 27:72]
    node _T_2584 = or(_T_2583, _T_2529) @[Mux.scala 27:72]
    node _T_2585 = or(_T_2584, _T_2530) @[Mux.scala 27:72]
    node _T_2586 = or(_T_2585, _T_2531) @[Mux.scala 27:72]
    node _T_2587 = or(_T_2586, _T_2532) @[Mux.scala 27:72]
    node _T_2588 = or(_T_2587, _T_2533) @[Mux.scala 27:72]
    node _T_2589 = or(_T_2588, _T_2534) @[Mux.scala 27:72]
    node _T_2590 = or(_T_2589, _T_2535) @[Mux.scala 27:72]
    node _T_2591 = or(_T_2590, _T_2536) @[Mux.scala 27:72]
    node _T_2592 = or(_T_2591, _T_2537) @[Mux.scala 27:72]
    node _T_2593 = or(_T_2592, _T_2538) @[Mux.scala 27:72]
    node _T_2594 = or(_T_2593, _T_2539) @[Mux.scala 27:72]
    node _T_2595 = or(_T_2594, _T_2540) @[Mux.scala 27:72]
    node _T_2596 = or(_T_2595, _T_2541) @[Mux.scala 27:72]
    node _T_2597 = or(_T_2596, _T_2542) @[Mux.scala 27:72]
    node _T_2598 = or(_T_2597, _T_2543) @[Mux.scala 27:72]
    node _T_2599 = or(_T_2598, _T_2544) @[Mux.scala 27:72]
    node _T_2600 = or(_T_2599, _T_2545) @[Mux.scala 27:72]
    node _T_2601 = or(_T_2600, _T_2546) @[Mux.scala 27:72]
    node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72]
    node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72]
    node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72]
    node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72]
    node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72]
    node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72]
    node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72]
    node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72]
    wire _T_2610 : UInt @[Mux.scala 27:72]
    _T_2610 <= _T_2609 @[Mux.scala 27:72]
    io.dec_csr_rddata_d <= _T_2610 @[el2_dec_tlu_ctl.scala 2576:22]
    
  module el2_dec_decode_csr_read : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}}
    
    node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1 = eq(_T, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_3 = eq(_T_2, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_5 = eq(_T_4, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_9 = and(_T_1, _T_3) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_10 = and(_T_9, _T_5) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_11 = and(_T_10, _T_7) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_12 = and(_T_11, _T_8) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_misa <= _T_12 @[el2_dec_tlu_ctl.scala 2650:49]
    node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_17 = eq(_T_16, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_19 = and(_T_13, _T_15) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_20 = and(_T_19, _T_17) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_21 = and(_T_20, _T_18) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mvendorid <= _T_21 @[el2_dec_tlu_ctl.scala 2651:49]
    node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_28 = and(_T_22, _T_24) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_29 = and(_T_28, _T_25) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_30 = and(_T_29, _T_27) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_marchid <= _T_30 @[el2_dec_tlu_ctl.scala 2652:57]
    node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_36 = and(_T_31, _T_33) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_37 = and(_T_36, _T_34) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_38 = and(_T_37, _T_35) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mimpid <= _T_38 @[el2_dec_tlu_ctl.scala 2653:57]
    node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_43 = and(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_44 = and(_T_43, _T_42) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhartid <= _T_44 @[el2_dec_tlu_ctl.scala 2654:57]
    node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_50 = eq(_T_49, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_54 = eq(_T_53, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_55 = and(_T_46, _T_48) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_56 = and(_T_55, _T_50) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_57 = and(_T_56, _T_52) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_58 = and(_T_57, _T_54) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mstatus <= _T_58 @[el2_dec_tlu_ctl.scala 2655:57]
    node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_67 = and(_T_60, _T_62) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_68 = and(_T_67, _T_64) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_69 = and(_T_68, _T_65) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_70 = and(_T_69, _T_66) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mtvec <= _T_70 @[el2_dec_tlu_ctl.scala 2656:49]
    node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_75 = and(_T_72, _T_73) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_76 = and(_T_75, _T_74) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mip <= _T_76 @[el2_dec_tlu_ctl.scala 2657:57]
    node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_80 = eq(_T_79, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_86 = and(_T_78, _T_80) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_87 = and(_T_86, _T_82) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_88 = and(_T_87, _T_83) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_89 = and(_T_88, _T_85) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mie <= _T_89 @[el2_dec_tlu_ctl.scala 2658:57]
    node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_101 = and(_T_90, _T_92) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_102 = and(_T_101, _T_94) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_103 = and(_T_102, _T_96) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_104 = and(_T_103, _T_98) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_105 = and(_T_104, _T_100) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mcyclel <= _T_105 @[el2_dec_tlu_ctl.scala 2659:57]
    node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_108 = eq(_T_107, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_119 = and(_T_106, _T_108) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_120 = and(_T_119, _T_110) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_121 = and(_T_120, _T_112) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_122 = and(_T_121, _T_114) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_123 = and(_T_122, _T_116) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_124 = and(_T_123, _T_118) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mcycleh <= _T_124 @[el2_dec_tlu_ctl.scala 2660:57]
    node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_128 = eq(_T_127, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_138 = and(_T_126, _T_128) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_139 = and(_T_138, _T_130) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_140 = and(_T_139, _T_132) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_141 = and(_T_140, _T_134) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_142 = and(_T_141, _T_135) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_143 = and(_T_142, _T_137) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_minstretl <= _T_143 @[el2_dec_tlu_ctl.scala 2661:49]
    node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_145 = eq(_T_144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_155 = eq(_T_154, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_156 = and(_T_145, _T_146) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_157 = and(_T_156, _T_148) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_158 = and(_T_157, _T_150) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_159 = and(_T_158, _T_152) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_160 = and(_T_159, _T_153) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_161 = and(_T_160, _T_155) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_minstreth <= _T_161 @[el2_dec_tlu_ctl.scala 2662:49]
    node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_166 = eq(_T_165, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_171 = and(_T_163, _T_164) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_172 = and(_T_171, _T_166) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_173 = and(_T_172, _T_168) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_174 = and(_T_173, _T_170) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mscratch <= _T_174 @[el2_dec_tlu_ctl.scala 2663:49]
    node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_181 = and(_T_176, _T_177) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_182 = and(_T_181, _T_179) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_183 = and(_T_182, _T_180) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mepc <= _T_183 @[el2_dec_tlu_ctl.scala 2664:49]
    node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_190 = and(_T_185, _T_186) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_191 = and(_T_190, _T_187) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_192 = and(_T_191, _T_189) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mcause <= _T_192 @[el2_dec_tlu_ctl.scala 2665:57]
    node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_196 = and(_T_193, _T_194) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_197 = and(_T_196, _T_195) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mscause <= _T_197 @[el2_dec_tlu_ctl.scala 2666:57]
    node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_203 = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_204 = and(_T_203, _T_201) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_205 = and(_T_204, _T_202) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mtval <= _T_205 @[el2_dec_tlu_ctl.scala 2667:49]
    node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_217 = and(_T_207, _T_208) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_218 = and(_T_217, _T_210) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_219 = and(_T_218, _T_212) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_220 = and(_T_219, _T_214) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_221 = and(_T_220, _T_216) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mrac <= _T_221 @[el2_dec_tlu_ctl.scala 2668:49]
    node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_230 = and(_T_222, _T_224) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_231 = and(_T_230, _T_226) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_232 = and(_T_231, _T_227) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_233 = and(_T_232, _T_229) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dmst <= _T_233 @[el2_dec_tlu_ctl.scala 2669:49]
    node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_237 = eq(_T_236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_240 = and(_T_234, _T_235) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_241 = and(_T_240, _T_237) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_242 = and(_T_241, _T_239) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mdseac <= _T_242 @[el2_dec_tlu_ctl.scala 2670:57]
    node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_246 = and(_T_243, _T_244) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_247 = and(_T_246, _T_245) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_meihap <= _T_247 @[el2_dec_tlu_ctl.scala 2671:57]
    node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_258 = and(_T_249, _T_250) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_259 = and(_T_258, _T_251) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_260 = and(_T_259, _T_253) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_261 = and(_T_260, _T_255) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_262 = and(_T_261, _T_257) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_meivt <= _T_262 @[el2_dec_tlu_ctl.scala 2672:49]
    node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_266 = eq(_T_265, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_268 = and(_T_263, _T_264) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_269 = and(_T_268, _T_266) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_270 = and(_T_269, _T_267) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_meipt <= _T_270 @[el2_dec_tlu_ctl.scala 2673:49]
    node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_274 = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_275 = and(_T_274, _T_273) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_meicurpl <= _T_275 @[el2_dec_tlu_ctl.scala 2674:49]
    node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_280 = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_281 = and(_T_280, _T_278) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_282 = and(_T_281, _T_279) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_meicidpl <= _T_282 @[el2_dec_tlu_ctl.scala 2675:49]
    node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_290 = and(_T_283, _T_285) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_291 = and(_T_290, _T_286) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_292 = and(_T_291, _T_287) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_293 = and(_T_292, _T_289) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dcsr <= _T_293 @[el2_dec_tlu_ctl.scala 2676:49]
    node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_299 = and(_T_294, _T_295) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_300 = and(_T_299, _T_296) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_301 = and(_T_300, _T_298) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mcgc <= _T_301 @[el2_dec_tlu_ctl.scala 2677:49]
    node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_308 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_309 = and(_T_308, _T_304) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_310 = and(_T_309, _T_306) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_311 = and(_T_310, _T_307) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mfdc <= _T_311 @[el2_dec_tlu_ctl.scala 2678:49]
    node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_318 = and(_T_312, _T_314) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_319 = and(_T_318, _T_315) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_320 = and(_T_319, _T_316) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_321 = and(_T_320, _T_317) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dpc <= _T_321 @[el2_dec_tlu_ctl.scala 2679:57]
    node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_330 = and(_T_322, _T_323) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_331 = and(_T_330, _T_325) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_332 = and(_T_331, _T_327) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_333 = and(_T_332, _T_329) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mtsel <= _T_333 @[el2_dec_tlu_ctl.scala 2680:49]
    node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_336 = eq(_T_335, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_340 = and(_T_334, _T_336) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_341 = and(_T_340, _T_338) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_342 = and(_T_341, _T_339) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mtdata1 <= _T_342 @[el2_dec_tlu_ctl.scala 2681:57]
    node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_348 = and(_T_343, _T_344) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_349 = and(_T_348, _T_346) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_350 = and(_T_349, _T_347) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mtdata2 <= _T_350 @[el2_dec_tlu_ctl.scala 2682:57]
    node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_361 = and(_T_351, _T_353) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_362 = and(_T_361, _T_355) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_363 = and(_T_362, _T_357) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_364 = and(_T_363, _T_359) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_365 = and(_T_364, _T_360) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc3 <= _T_365 @[el2_dec_tlu_ctl.scala 2683:57]
    node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_368 = eq(_T_367, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_370 = eq(_T_369, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_372 = eq(_T_371, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_378 = and(_T_366, _T_368) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_379 = and(_T_378, _T_370) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_380 = and(_T_379, _T_372) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_381 = and(_T_380, _T_373) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_382 = and(_T_381, _T_375) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_383 = and(_T_382, _T_377) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc4 <= _T_383 @[el2_dec_tlu_ctl.scala 2684:57]
    node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_394 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_395 = and(_T_394, _T_388) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_396 = and(_T_395, _T_390) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_397 = and(_T_396, _T_392) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_398 = and(_T_397, _T_393) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc5 <= _T_398 @[el2_dec_tlu_ctl.scala 2685:57]
    node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_411 = and(_T_400, _T_402) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_412 = and(_T_411, _T_404) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_413 = and(_T_412, _T_406) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_414 = and(_T_413, _T_407) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_415 = and(_T_414, _T_408) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_416 = and(_T_415, _T_410) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc6 <= _T_416 @[el2_dec_tlu_ctl.scala 2686:57]
    node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_421 = eq(_T_420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_423 = eq(_T_422, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_426 = and(_T_417, _T_419) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_427 = and(_T_426, _T_421) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_428 = and(_T_427, _T_423) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_429 = and(_T_428, _T_424) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_430 = and(_T_429, _T_425) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc3h <= _T_430 @[el2_dec_tlu_ctl.scala 2687:57]
    node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_440 = eq(_T_439, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_443 = and(_T_431, _T_433) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_444 = and(_T_443, _T_435) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_445 = and(_T_444, _T_437) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_446 = and(_T_445, _T_438) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_447 = and(_T_446, _T_440) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_448 = and(_T_447, _T_442) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc4h <= _T_448 @[el2_dec_tlu_ctl.scala 2688:57]
    node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_456 = eq(_T_455, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_458 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_459 = and(_T_458, _T_453) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_460 = and(_T_459, _T_454) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_461 = and(_T_460, _T_456) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_462 = and(_T_461, _T_457) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc5h <= _T_462 @[el2_dec_tlu_ctl.scala 2689:57]
    node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_469 = eq(_T_468, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_474 = and(_T_463, _T_465) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_475 = and(_T_474, _T_467) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_476 = and(_T_475, _T_469) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_477 = and(_T_476, _T_470) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_478 = and(_T_477, _T_471) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_479 = and(_T_478, _T_473) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpmc6h <= _T_479 @[el2_dec_tlu_ctl.scala 2690:57]
    node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_488 = eq(_T_487, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_490 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_491 = and(_T_490, _T_484) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_492 = and(_T_491, _T_486) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_493 = and(_T_492, _T_488) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_494 = and(_T_493, _T_489) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpme3 <= _T_494 @[el2_dec_tlu_ctl.scala 2691:57]
    node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_504 = eq(_T_503, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_505 = and(_T_495, _T_497) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_506 = and(_T_505, _T_499) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_507 = and(_T_506, _T_500) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_508 = and(_T_507, _T_502) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_509 = and(_T_508, _T_504) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpme4 <= _T_509 @[el2_dec_tlu_ctl.scala 2692:57]
    node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_512 = eq(_T_511, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_517 = eq(_T_516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_519 = and(_T_510, _T_512) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_520 = and(_T_519, _T_514) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_521 = and(_T_520, _T_515) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_522 = and(_T_521, _T_517) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_523 = and(_T_522, _T_518) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpme5 <= _T_523 @[el2_dec_tlu_ctl.scala 2693:57]
    node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_528 = eq(_T_527, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_533 = and(_T_524, _T_526) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_534 = and(_T_533, _T_528) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_535 = and(_T_534, _T_529) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_536 = and(_T_535, _T_530) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_537 = and(_T_536, _T_532) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mhpme6 <= _T_537 @[el2_dec_tlu_ctl.scala 2694:57]
    node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_544 = eq(_T_543, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_549 = and(_T_539, _T_540) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_550 = and(_T_549, _T_542) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_551 = and(_T_550, _T_544) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_552 = and(_T_551, _T_546) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_553 = and(_T_552, _T_548) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mcountinhibit <= _T_553 @[el2_dec_tlu_ctl.scala 2695:41]
    node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_562 = and(_T_554, _T_556) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_563 = and(_T_562, _T_557) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_564 = and(_T_563, _T_559) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_565 = and(_T_564, _T_561) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mitctl0 <= _T_565 @[el2_dec_tlu_ctl.scala 2696:57]
    node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_572 = and(_T_566, _T_568) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_573 = and(_T_572, _T_569) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_574 = and(_T_573, _T_570) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_575 = and(_T_574, _T_571) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mitctl1 <= _T_575 @[el2_dec_tlu_ctl.scala 2697:57]
    node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_583 = and(_T_576, _T_578) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_584 = and(_T_583, _T_579) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_585 = and(_T_584, _T_581) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_586 = and(_T_585, _T_582) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mitb0 <= _T_586 @[el2_dec_tlu_ctl.scala 2698:49]
    node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_592 = eq(_T_591, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_593 = and(_T_587, _T_588) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_594 = and(_T_593, _T_589) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_595 = and(_T_594, _T_590) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_596 = and(_T_595, _T_592) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mitb1 <= _T_596 @[el2_dec_tlu_ctl.scala 2699:49]
    node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_599 = eq(_T_598, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_605 = and(_T_597, _T_599) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_606 = and(_T_605, _T_600) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_607 = and(_T_606, _T_602) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_608 = and(_T_607, _T_604) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mitcnt0 <= _T_608 @[el2_dec_tlu_ctl.scala 2700:57]
    node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_612 = eq(_T_611, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_614 = and(_T_609, _T_610) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_615 = and(_T_614, _T_612) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_616 = and(_T_615, _T_613) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mitcnt1 <= _T_616 @[el2_dec_tlu_ctl.scala 2701:57]
    node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_624 = and(_T_617, _T_619) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_625 = and(_T_624, _T_621) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_626 = and(_T_625, _T_622) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_627 = and(_T_626, _T_623) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mpmc <= _T_627 @[el2_dec_tlu_ctl.scala 2702:49]
    node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_637 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_638 = and(_T_637, _T_631) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_639 = and(_T_638, _T_633) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_640 = and(_T_639, _T_635) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_641 = and(_T_640, _T_636) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mcpc <= _T_641 @[el2_dec_tlu_ctl.scala 2703:49]
    node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_647 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_648 = and(_T_647, _T_644) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_649 = and(_T_648, _T_646) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_meicpct <= _T_649 @[el2_dec_tlu_ctl.scala 2704:57]
    node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_651 = eq(_T_650, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_656 = and(_T_651, _T_652) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_657 = and(_T_656, _T_653) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_658 = and(_T_657, _T_655) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mdeau <= _T_658 @[el2_dec_tlu_ctl.scala 2705:49]
    node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_664 = eq(_T_663, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_667 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_668 = and(_T_667, _T_662) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_669 = and(_T_668, _T_664) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_670 = and(_T_669, _T_666) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_micect <= _T_670 @[el2_dec_tlu_ctl.scala 2706:57]
    node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_676 = and(_T_671, _T_672) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_677 = and(_T_676, _T_674) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_678 = and(_T_677, _T_675) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_miccmect <= _T_678 @[el2_dec_tlu_ctl.scala 2707:49]
    node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_683 = eq(_T_682, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_684 = and(_T_679, _T_680) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_685 = and(_T_684, _T_681) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_686 = and(_T_685, _T_683) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mdccmect <= _T_686 @[el2_dec_tlu_ctl.scala 2708:49]
    node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_692 = eq(_T_691, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_693 = and(_T_687, _T_688) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_694 = and(_T_693, _T_689) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_695 = and(_T_694, _T_690) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_696 = and(_T_695, _T_692) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mfdht <= _T_696 @[el2_dec_tlu_ctl.scala 2709:49]
    node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_699 = eq(_T_698, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_702 = and(_T_697, _T_699) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_703 = and(_T_702, _T_700) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_704 = and(_T_703, _T_701) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_mfdhs <= _T_704 @[el2_dec_tlu_ctl.scala 2710:49]
    node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_708 = eq(_T_707, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_711 = eq(_T_710, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_713 = eq(_T_712, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_716 = and(_T_706, _T_708) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_717 = and(_T_716, _T_709) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_718 = and(_T_717, _T_711) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_719 = and(_T_718, _T_713) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_720 = and(_T_719, _T_715) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dicawics <= _T_720 @[el2_dec_tlu_ctl.scala 2711:49]
    node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_725 = eq(_T_724, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_726 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_727 = and(_T_726, _T_723) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_728 = and(_T_727, _T_725) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dicad0h <= _T_728 @[el2_dec_tlu_ctl.scala 2712:57]
    node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_731 = eq(_T_730, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_734 = eq(_T_733, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_736 = and(_T_729, _T_731) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_737 = and(_T_736, _T_732) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_738 = and(_T_737, _T_734) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_739 = and(_T_738, _T_735) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dicad0 <= _T_739 @[el2_dec_tlu_ctl.scala 2713:57]
    node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_743 = eq(_T_742, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_746 = eq(_T_745, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_747 = and(_T_740, _T_741) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_748 = and(_T_747, _T_743) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_749 = and(_T_748, _T_744) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_750 = and(_T_749, _T_746) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dicad1 <= _T_750 @[el2_dec_tlu_ctl.scala 2714:57]
    node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_754 = eq(_T_753, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_757 = and(_T_751, _T_752) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_758 = and(_T_757, _T_754) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_759 = and(_T_758, _T_755) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_760 = and(_T_759, _T_756) @[el2_dec_tlu_ctl.scala 2648:192]
    io.csr_pkt.csr_dicago <= _T_760 @[el2_dec_tlu_ctl.scala 2715:57]
    node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_765 = eq(_T_764, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_767 = and(_T_761, _T_762) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_768 = and(_T_767, _T_763) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_769 = and(_T_768, _T_765) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_770 = and(_T_769, _T_766) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_772 = eq(_T_771, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_779 = eq(_T_778, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_781 = eq(_T_780, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_782 = and(_T_772, _T_773) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_783 = and(_T_782, _T_775) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_784 = and(_T_783, _T_777) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_785 = and(_T_784, _T_779) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_786 = and(_T_785, _T_781) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_787 = or(_T_770, _T_786) @[el2_dec_tlu_ctl.scala 2716:73]
    node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_789 = eq(_T_788, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_795 = eq(_T_794, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_799 = and(_T_789, _T_791) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_800 = and(_T_799, _T_793) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_801 = and(_T_800, _T_795) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_802 = and(_T_801, _T_797) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_803 = and(_T_802, _T_798) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_804 = or(_T_787, _T_803) @[el2_dec_tlu_ctl.scala 2716:113]
    node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_807 = eq(_T_806, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_809 = eq(_T_808, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_812 = eq(_T_811, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_813 = and(_T_805, _T_807) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_814 = and(_T_813, _T_809) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_815 = and(_T_814, _T_810) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_816 = and(_T_815, _T_812) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_817 = or(_T_804, _T_816) @[el2_dec_tlu_ctl.scala 2716:147]
    node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_820 = eq(_T_819, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_825 = eq(_T_824, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_826 = and(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_827 = and(_T_826, _T_822) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_828 = and(_T_827, _T_823) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_829 = and(_T_828, _T_825) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_830 = or(_T_817, _T_829) @[el2_dec_tlu_ctl.scala 2717:41]
    node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_835 = eq(_T_834, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_837 = eq(_T_836, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_839 = eq(_T_838, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_841 = and(_T_831, _T_833) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_842 = and(_T_841, _T_835) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_843 = and(_T_842, _T_837) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_844 = and(_T_843, _T_839) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_845 = and(_T_844, _T_840) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_846 = or(_T_830, _T_845) @[el2_dec_tlu_ctl.scala 2717:81]
    io.csr_pkt.presync <= _T_846 @[el2_dec_tlu_ctl.scala 2716:26]
    node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_851 = eq(_T_850, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_853 = and(_T_847, _T_848) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_854 = and(_T_853, _T_849) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_855 = and(_T_854, _T_851) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_856 = and(_T_855, _T_852) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_862 = eq(_T_861, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_865 = and(_T_858, _T_860) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_866 = and(_T_865, _T_862) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_867 = and(_T_866, _T_863) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_868 = and(_T_867, _T_864) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_869 = or(_T_856, _T_868) @[el2_dec_tlu_ctl.scala 2718:73]
    node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_874 = eq(_T_873, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_876 = and(_T_871, _T_872) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_877 = and(_T_876, _T_874) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_878 = and(_T_877, _T_875) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_879 = or(_T_869, _T_878) @[el2_dec_tlu_ctl.scala 2718:113]
    node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_886 = and(_T_880, _T_882) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_887 = and(_T_886, _T_884) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_888 = and(_T_887, _T_885) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_889 = or(_T_879, _T_888) @[el2_dec_tlu_ctl.scala 2718:154]
    node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_893 = eq(_T_892, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_897 = eq(_T_896, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_903 = eq(_T_902, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_904 = and(_T_891, _T_893) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_905 = and(_T_904, _T_895) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_906 = and(_T_905, _T_897) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_907 = and(_T_906, _T_899) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_908 = and(_T_907, _T_901) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_909 = and(_T_908, _T_903) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_910 = or(_T_889, _T_909) @[el2_dec_tlu_ctl.scala 2719:41]
    node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_912 = eq(_T_911, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_918 = eq(_T_917, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_921 = and(_T_912, _T_913) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_922 = and(_T_921, _T_914) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_923 = and(_T_922, _T_916) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_924 = and(_T_923, _T_918) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_925 = and(_T_924, _T_920) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_926 = or(_T_910, _T_925) @[el2_dec_tlu_ctl.scala 2719:81]
    node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_929 = eq(_T_928, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_931 = eq(_T_930, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_935 = and(_T_927, _T_929) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_936 = and(_T_935, _T_931) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_937 = and(_T_936, _T_933) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_938 = and(_T_937, _T_934) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_939 = or(_T_926, _T_938) @[el2_dec_tlu_ctl.scala 2719:114]
    io.csr_pkt.postsync <= _T_939 @[el2_dec_tlu_ctl.scala 2718:24]
    node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_955 = and(_T_941, _T_942) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_956 = and(_T_955, _T_943) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_957 = and(_T_956, _T_944) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_958 = and(_T_957, _T_945) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_959 = and(_T_958, _T_946) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_960 = and(_T_959, _T_947) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_961 = and(_T_960, _T_949) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_962 = and(_T_961, _T_951) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_963 = and(_T_962, _T_952) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_964 = and(_T_963, _T_954) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_966 = eq(_T_965, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_972 = eq(_T_971, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_974 = eq(_T_973, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_976 = eq(_T_975, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_983 = and(_T_966, _T_968) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_984 = and(_T_983, _T_969) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_985 = and(_T_984, _T_970) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_986 = and(_T_985, _T_972) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_987 = and(_T_986, _T_974) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_988 = and(_T_987, _T_976) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_989 = and(_T_988, _T_978) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_990 = and(_T_989, _T_980) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_991 = and(_T_990, _T_982) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_992 = or(_T_964, _T_991) @[el2_dec_tlu_ctl.scala 2721:73]
    node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_996 = eq(_T_995, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1000 = eq(_T_999, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1008 = and(_T_994, _T_996) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1009 = and(_T_1008, _T_997) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1010 = and(_T_1009, _T_998) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1011 = and(_T_1010, _T_1000) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1012 = and(_T_1011, _T_1002) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1013 = and(_T_1012, _T_1003) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1014 = and(_T_1013, _T_1005) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1015 = and(_T_1014, _T_1007) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1016 = or(_T_992, _T_1015) @[el2_dec_tlu_ctl.scala 2721:121]
    node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1032 = and(_T_1017, _T_1018) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1033 = and(_T_1032, _T_1019) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1034 = and(_T_1033, _T_1020) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1035 = and(_T_1034, _T_1021) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1036 = and(_T_1035, _T_1023) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1037 = and(_T_1036, _T_1025) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1038 = and(_T_1037, _T_1027) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1039 = and(_T_1038, _T_1029) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1040 = and(_T_1039, _T_1031) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1041 = or(_T_1016, _T_1040) @[el2_dec_tlu_ctl.scala 2722:57]
    node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1053 = and(_T_1042, _T_1044) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1054 = and(_T_1053, _T_1045) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1055 = and(_T_1054, _T_1046) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1056 = and(_T_1055, _T_1048) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1057 = and(_T_1056, _T_1050) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1058 = and(_T_1057, _T_1052) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1059 = or(_T_1041, _T_1058) @[el2_dec_tlu_ctl.scala 2722:105]
    node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1073 = and(_T_1061, _T_1062) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1074 = and(_T_1073, _T_1063) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1075 = and(_T_1074, _T_1064) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1076 = and(_T_1075, _T_1065) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1077 = and(_T_1076, _T_1066) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1078 = and(_T_1077, _T_1067) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1079 = and(_T_1078, _T_1068) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1080 = and(_T_1079, _T_1069) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1081 = and(_T_1080, _T_1070) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1082 = and(_T_1081, _T_1071) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1083 = and(_T_1082, _T_1072) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1084 = or(_T_1059, _T_1083) @[el2_dec_tlu_ctl.scala 2723:65]
    node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1098 = and(_T_1086, _T_1087) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1099 = and(_T_1098, _T_1088) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1100 = and(_T_1099, _T_1089) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1101 = and(_T_1100, _T_1090) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1102 = and(_T_1101, _T_1091) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1103 = and(_T_1102, _T_1092) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1104 = and(_T_1103, _T_1093) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1105 = and(_T_1104, _T_1095) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1106 = and(_T_1105, _T_1097) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1107 = or(_T_1084, _T_1106) @[el2_dec_tlu_ctl.scala 2723:113]
    node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1123 = and(_T_1108, _T_1109) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1124 = and(_T_1123, _T_1110) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1125 = and(_T_1124, _T_1112) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1126 = and(_T_1125, _T_1114) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1127 = and(_T_1126, _T_1116) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1128 = and(_T_1127, _T_1117) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1129 = and(_T_1128, _T_1119) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1130 = and(_T_1129, _T_1121) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1131 = and(_T_1130, _T_1122) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1132 = or(_T_1107, _T_1131) @[el2_dec_tlu_ctl.scala 2724:57]
    node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1148 = and(_T_1134, _T_1135) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1149 = and(_T_1148, _T_1136) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1150 = and(_T_1149, _T_1137) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1151 = and(_T_1150, _T_1138) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1152 = and(_T_1151, _T_1140) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1153 = and(_T_1152, _T_1141) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1154 = and(_T_1153, _T_1143) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1155 = and(_T_1154, _T_1145) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1156 = and(_T_1155, _T_1147) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1157 = or(_T_1132, _T_1156) @[el2_dec_tlu_ctl.scala 2724:113]
    node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1170 = and(_T_1159, _T_1161) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1171 = and(_T_1170, _T_1162) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1172 = and(_T_1171, _T_1163) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1173 = and(_T_1172, _T_1165) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1174 = and(_T_1173, _T_1167) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1175 = and(_T_1174, _T_1168) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1176 = and(_T_1175, _T_1169) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1177 = or(_T_1157, _T_1176) @[el2_dec_tlu_ctl.scala 2725:57]
    node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1195 = and(_T_1178, _T_1179) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1196 = and(_T_1195, _T_1180) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1197 = and(_T_1196, _T_1182) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1198 = and(_T_1197, _T_1184) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1199 = and(_T_1198, _T_1186) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1200 = and(_T_1199, _T_1187) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1201 = and(_T_1200, _T_1189) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1202 = and(_T_1201, _T_1190) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1203 = and(_T_1202, _T_1192) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1204 = and(_T_1203, _T_1194) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1205 = or(_T_1177, _T_1204) @[el2_dec_tlu_ctl.scala 2725:113]
    node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1219 = and(_T_1207, _T_1208) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1220 = and(_T_1219, _T_1209) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1221 = and(_T_1220, _T_1210) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1222 = and(_T_1221, _T_1211) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1223 = and(_T_1222, _T_1212) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1224 = and(_T_1223, _T_1214) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1225 = and(_T_1224, _T_1216) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1226 = and(_T_1225, _T_1217) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1227 = and(_T_1226, _T_1218) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1228 = or(_T_1205, _T_1227) @[el2_dec_tlu_ctl.scala 2726:57]
    node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1242 = and(_T_1230, _T_1231) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1243 = and(_T_1242, _T_1232) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1244 = and(_T_1243, _T_1233) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1245 = and(_T_1244, _T_1234) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1246 = and(_T_1245, _T_1235) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1247 = and(_T_1246, _T_1237) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1248 = and(_T_1247, _T_1238) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1249 = and(_T_1248, _T_1240) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1250 = and(_T_1249, _T_1241) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1251 = or(_T_1228, _T_1250) @[el2_dec_tlu_ctl.scala 2726:113]
    node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1267 = and(_T_1252, _T_1253) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1268 = and(_T_1267, _T_1254) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1269 = and(_T_1268, _T_1256) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1270 = and(_T_1269, _T_1258) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1271 = and(_T_1270, _T_1260) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1272 = and(_T_1271, _T_1261) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1273 = and(_T_1272, _T_1263) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1274 = and(_T_1273, _T_1265) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1275 = and(_T_1274, _T_1266) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1276 = or(_T_1251, _T_1275) @[el2_dec_tlu_ctl.scala 2727:57]
    node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1290 = and(_T_1278, _T_1280) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1291 = and(_T_1290, _T_1281) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1292 = and(_T_1291, _T_1282) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1293 = and(_T_1292, _T_1284) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1294 = and(_T_1293, _T_1286) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1295 = and(_T_1294, _T_1287) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1296 = and(_T_1295, _T_1288) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1297 = and(_T_1296, _T_1289) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1298 = or(_T_1276, _T_1297) @[el2_dec_tlu_ctl.scala 2727:113]
    node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1312 = and(_T_1299, _T_1301) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1313 = and(_T_1312, _T_1302) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1314 = and(_T_1313, _T_1303) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1315 = and(_T_1314, _T_1304) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1316 = and(_T_1315, _T_1306) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1317 = and(_T_1316, _T_1308) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1318 = and(_T_1317, _T_1309) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1319 = and(_T_1318, _T_1311) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1320 = or(_T_1298, _T_1319) @[el2_dec_tlu_ctl.scala 2728:65]
    node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1336 = and(_T_1321, _T_1323) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1337 = and(_T_1336, _T_1324) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1338 = and(_T_1337, _T_1325) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1339 = and(_T_1338, _T_1326) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1340 = and(_T_1339, _T_1328) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1341 = and(_T_1340, _T_1330) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1342 = and(_T_1341, _T_1331) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1343 = and(_T_1342, _T_1333) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1344 = and(_T_1343, _T_1335) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1345 = or(_T_1320, _T_1344) @[el2_dec_tlu_ctl.scala 2728:121]
    node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1356 = and(_T_1346, _T_1348) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1357 = and(_T_1356, _T_1349) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1358 = and(_T_1357, _T_1350) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1359 = and(_T_1358, _T_1352) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1360 = and(_T_1359, _T_1354) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1361 = and(_T_1360, _T_1355) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1362 = or(_T_1345, _T_1361) @[el2_dec_tlu_ctl.scala 2729:57]
    node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1376 = and(_T_1364, _T_1365) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1377 = and(_T_1376, _T_1366) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1378 = and(_T_1377, _T_1367) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1379 = and(_T_1378, _T_1368) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1380 = and(_T_1379, _T_1369) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1381 = and(_T_1380, _T_1371) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1382 = and(_T_1381, _T_1372) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1383 = and(_T_1382, _T_1374) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1384 = and(_T_1383, _T_1375) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1385 = or(_T_1362, _T_1384) @[el2_dec_tlu_ctl.scala 2729:113]
    node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1399 = and(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1400 = and(_T_1399, _T_1389) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1401 = and(_T_1400, _T_1390) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1402 = and(_T_1401, _T_1391) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1403 = and(_T_1402, _T_1392) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1404 = and(_T_1403, _T_1394) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1405 = and(_T_1404, _T_1396) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1406 = and(_T_1405, _T_1398) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1407 = or(_T_1385, _T_1406) @[el2_dec_tlu_ctl.scala 2730:57]
    node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1422 = and(_T_1409, _T_1410) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1423 = and(_T_1422, _T_1411) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1424 = and(_T_1423, _T_1412) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1425 = and(_T_1424, _T_1413) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1426 = and(_T_1425, _T_1414) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1427 = and(_T_1426, _T_1416) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1428 = and(_T_1427, _T_1418) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1429 = and(_T_1428, _T_1419) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1430 = and(_T_1429, _T_1421) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1431 = or(_T_1407, _T_1430) @[el2_dec_tlu_ctl.scala 2730:113]
    node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1449 = and(_T_1433, _T_1434) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1450 = and(_T_1449, _T_1435) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1451 = and(_T_1450, _T_1436) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1452 = and(_T_1451, _T_1437) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1453 = and(_T_1452, _T_1439) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1454 = and(_T_1453, _T_1440) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1455 = and(_T_1454, _T_1442) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1456 = and(_T_1455, _T_1444) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1457 = and(_T_1456, _T_1446) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1458 = and(_T_1457, _T_1448) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1459 = or(_T_1431, _T_1458) @[el2_dec_tlu_ctl.scala 2731:57]
    node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1470 = and(_T_1460, _T_1462) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1471 = and(_T_1470, _T_1463) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1472 = and(_T_1471, _T_1464) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1473 = and(_T_1472, _T_1466) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1474 = and(_T_1473, _T_1468) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1475 = and(_T_1474, _T_1469) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1476 = or(_T_1459, _T_1475) @[el2_dec_tlu_ctl.scala 2731:105]
    node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1494 = and(_T_1478, _T_1480) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1495 = and(_T_1494, _T_1481) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1496 = and(_T_1495, _T_1482) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1497 = and(_T_1496, _T_1484) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1498 = and(_T_1497, _T_1485) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1499 = and(_T_1498, _T_1487) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1500 = and(_T_1499, _T_1489) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1501 = and(_T_1500, _T_1491) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1502 = and(_T_1501, _T_1493) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1503 = or(_T_1476, _T_1502) @[el2_dec_tlu_ctl.scala 2732:65]
    node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179]
    node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159]
    node _T_1522 = and(_T_1505, _T_1507) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1523 = and(_T_1522, _T_1508) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1524 = and(_T_1523, _T_1509) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1525 = and(_T_1524, _T_1511) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1526 = and(_T_1525, _T_1513) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1527 = and(_T_1526, _T_1515) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1528 = and(_T_1527, _T_1517) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1529 = and(_T_1528, _T_1519) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1530 = and(_T_1529, _T_1521) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1531 = or(_T_1503, _T_1530) @[el2_dec_tlu_ctl.scala 2732:113]
    node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1544 = and(_T_1533, _T_1535) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1545 = and(_T_1544, _T_1536) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1546 = and(_T_1545, _T_1537) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1547 = and(_T_1546, _T_1539) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1548 = and(_T_1547, _T_1541) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1549 = and(_T_1548, _T_1542) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1550 = and(_T_1549, _T_1543) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1551 = or(_T_1531, _T_1550) @[el2_dec_tlu_ctl.scala 2733:57]
    node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1562 = and(_T_1552, _T_1554) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1563 = and(_T_1562, _T_1555) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1564 = and(_T_1563, _T_1556) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1565 = and(_T_1564, _T_1558) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1566 = and(_T_1565, _T_1560) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1567 = and(_T_1566, _T_1561) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1568 = or(_T_1551, _T_1567) @[el2_dec_tlu_ctl.scala 2733:113]
    node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1581 = and(_T_1570, _T_1572) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1582 = and(_T_1581, _T_1573) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1583 = and(_T_1582, _T_1574) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1584 = and(_T_1583, _T_1576) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1585 = and(_T_1584, _T_1578) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1586 = and(_T_1585, _T_1579) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1587 = and(_T_1586, _T_1580) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1588 = or(_T_1568, _T_1587) @[el2_dec_tlu_ctl.scala 2734:65]
    node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143]
    node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123]
    node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100]
    node _T_1599 = and(_T_1589, _T_1591) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1600 = and(_T_1599, _T_1592) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1601 = and(_T_1600, _T_1593) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1602 = and(_T_1601, _T_1595) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1603 = and(_T_1602, _T_1597) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1604 = and(_T_1603, _T_1598) @[el2_dec_tlu_ctl.scala 2648:192]
    node _T_1605 = or(_T_1588, _T_1604) @[el2_dec_tlu_ctl.scala 2734:121]
    io.csr_pkt.legal <= _T_1605 @[el2_dec_tlu_ctl.scala 2721:20]
    
  module el2_dec_tlu_ctl : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>}
    
    wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59]
    wire pause_expired_wb : UInt<1>
    pause_expired_wb <= UInt<1>("h00")
    wire take_nmi_r_d1 : UInt<1>
    take_nmi_r_d1 <= UInt<1>("h00")
    wire exc_or_int_valid_r_d1 : UInt<1>
    exc_or_int_valid_r_d1 <= UInt<1>("h00")
    wire interrupt_valid_r_d1 : UInt<1>
    interrupt_valid_r_d1 <= UInt<1>("h00")
    wire tlu_flush_lower_r : UInt<1>
    tlu_flush_lower_r <= UInt<1>("h00")
    wire synchronous_flush_r : UInt<1>
    synchronous_flush_r <= UInt<1>("h00")
    wire interrupt_valid_r : UInt<1>
    interrupt_valid_r <= UInt<1>("h00")
    wire take_nmi : UInt<1>
    take_nmi <= UInt<1>("h00")
    wire take_reset : UInt<1>
    take_reset <= UInt<1>("h00")
    wire take_int_timer1_int : UInt<1>
    take_int_timer1_int <= UInt<1>("h00")
    wire take_int_timer0_int : UInt<1>
    take_int_timer0_int <= UInt<1>("h00")
    wire take_timer_int : UInt<1>
    take_timer_int <= UInt<1>("h00")
    wire take_soft_int : UInt<1>
    take_soft_int <= UInt<1>("h00")
    wire take_ce_int : UInt<1>
    take_ce_int <= UInt<1>("h00")
    wire take_ext_int_start : UInt<1>
    take_ext_int_start <= UInt<1>("h00")
    wire ext_int_freeze : UInt<1>
    ext_int_freeze <= UInt<1>("h00")
    wire ext_int_freeze_d1 : UInt<1>
    ext_int_freeze_d1 <= UInt<1>("h00")
    wire take_ext_int_start_d1 : UInt<1>
    take_ext_int_start_d1 <= UInt<1>("h00")
    wire take_ext_int_start_d2 : UInt<1>
    take_ext_int_start_d2 <= UInt<1>("h00")
    wire take_ext_int_start_d3 : UInt<1>
    take_ext_int_start_d3 <= UInt<1>("h00")
    wire fast_int_meicpct : UInt<1>
    fast_int_meicpct <= UInt<1>("h00")
    wire ignore_ext_int_due_to_lsu_stall : UInt<1>
    ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00")
    wire take_ext_int : UInt<1>
    take_ext_int <= UInt<1>("h00")
    wire internal_dbg_halt_timers : UInt<1>
    internal_dbg_halt_timers <= UInt<1>("h00")
    wire int_timer1_int_hold : UInt<1>
    int_timer1_int_hold <= UInt<1>("h00")
    wire int_timer0_int_hold : UInt<1>
    int_timer0_int_hold <= UInt<1>("h00")
    wire mhwakeup_ready : UInt<1>
    mhwakeup_ready <= UInt<1>("h00")
    wire ext_int_ready : UInt<1>
    ext_int_ready <= UInt<1>("h00")
    wire ce_int_ready : UInt<1>
    ce_int_ready <= UInt<1>("h00")
    wire soft_int_ready : UInt<1>
    soft_int_ready <= UInt<1>("h00")
    wire timer_int_ready : UInt<1>
    timer_int_ready <= UInt<1>("h00")
    wire ebreak_to_debug_mode_r_d1 : UInt<1>
    ebreak_to_debug_mode_r_d1 <= UInt<1>("h00")
    wire ebreak_to_debug_mode_r : UInt<1>
    ebreak_to_debug_mode_r <= UInt<1>("h00")
    wire inst_acc_r : UInt<1>
    inst_acc_r <= UInt<1>("h00")
    wire inst_acc_r_raw : UInt<1>
    inst_acc_r_raw <= UInt<1>("h00")
    wire iccm_sbecc_r : UInt<1>
    iccm_sbecc_r <= UInt<1>("h00")
    wire ic_perr_r : UInt<1>
    ic_perr_r <= UInt<1>("h00")
    wire fence_i_r : UInt<1>
    fence_i_r <= UInt<1>("h00")
    wire ebreak_r : UInt<1>
    ebreak_r <= UInt<1>("h00")
    wire ecall_r : UInt<1>
    ecall_r <= UInt<1>("h00")
    wire illegal_r : UInt<1>
    illegal_r <= UInt<1>("h00")
    wire mret_r : UInt<1>
    mret_r <= UInt<1>("h00")
    wire iccm_repair_state_ns : UInt<1>
    iccm_repair_state_ns <= UInt<1>("h00")
    wire rfpc_i0_r : UInt<1>
    rfpc_i0_r <= UInt<1>("h00")
    wire tlu_i0_kill_writeb_r : UInt<1>
    tlu_i0_kill_writeb_r <= UInt<1>("h00")
    wire lsu_exc_valid_r_d1 : UInt<1>
    lsu_exc_valid_r_d1 <= UInt<1>("h00")
    wire lsu_i0_exc_r_raw : UInt<1>
    lsu_i0_exc_r_raw <= UInt<1>("h00")
    wire mdseac_locked_f : UInt<1>
    mdseac_locked_f <= UInt<1>("h00")
    wire i_cpu_run_req_d1 : UInt<1>
    i_cpu_run_req_d1 <= UInt<1>("h00")
    wire cpu_run_ack : UInt<1>
    cpu_run_ack <= UInt<1>("h00")
    wire cpu_halt_status : UInt<1>
    cpu_halt_status <= UInt<1>("h00")
    wire cpu_halt_ack : UInt<1>
    cpu_halt_ack <= UInt<1>("h00")
    wire pmu_fw_tlu_halted : UInt<1>
    pmu_fw_tlu_halted <= UInt<1>("h00")
    wire internal_pmu_fw_halt_mode : UInt<1>
    internal_pmu_fw_halt_mode <= UInt<1>("h00")
    wire pmu_fw_halt_req_ns : UInt<1>
    pmu_fw_halt_req_ns <= UInt<1>("h00")
    wire pmu_fw_halt_req_f : UInt<1>
    pmu_fw_halt_req_f <= UInt<1>("h00")
    wire pmu_fw_tlu_halted_f : UInt<1>
    pmu_fw_tlu_halted_f <= UInt<1>("h00")
    wire int_timer0_int_hold_f : UInt<1>
    int_timer0_int_hold_f <= UInt<1>("h00")
    wire int_timer1_int_hold_f : UInt<1>
    int_timer1_int_hold_f <= UInt<1>("h00")
    wire trigger_hit_dmode_r : UInt<1>
    trigger_hit_dmode_r <= UInt<1>("h00")
    wire i0_trigger_hit_r : UInt<1>
    i0_trigger_hit_r <= UInt<1>("h00")
    wire pause_expired_r : UInt<1>
    pause_expired_r <= UInt<1>("h00")
    wire dec_tlu_pmu_fw_halted : UInt<1>
    dec_tlu_pmu_fw_halted <= UInt<1>("h00")
    wire dec_tlu_flush_noredir_r_d1 : UInt<1>
    dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00")
    wire halt_taken_f : UInt<1>
    halt_taken_f <= UInt<1>("h00")
    wire lsu_idle_any_f : UInt<1>
    lsu_idle_any_f <= UInt<1>("h00")
    wire ifu_miss_state_idle_f : UInt<1>
    ifu_miss_state_idle_f <= UInt<1>("h00")
    wire dbg_tlu_halted_f : UInt<1>
    dbg_tlu_halted_f <= UInt<1>("h00")
    wire debug_halt_req_f : UInt<1>
    debug_halt_req_f <= UInt<1>("h00")
    wire debug_resume_req_f : UInt<1>
    debug_resume_req_f <= UInt<1>("h00")
    wire trigger_hit_dmode_r_d1 : UInt<1>
    trigger_hit_dmode_r_d1 <= UInt<1>("h00")
    wire dcsr_single_step_done_f : UInt<1>
    dcsr_single_step_done_f <= UInt<1>("h00")
    wire debug_halt_req_d1 : UInt<1>
    debug_halt_req_d1 <= UInt<1>("h00")
    wire request_debug_mode_r_d1 : UInt<1>
    request_debug_mode_r_d1 <= UInt<1>("h00")
    wire request_debug_mode_done_f : UInt<1>
    request_debug_mode_done_f <= UInt<1>("h00")
    wire dcsr_single_step_running_f : UInt<1>
    dcsr_single_step_running_f <= UInt<1>("h00")
    wire dec_tlu_flush_pause_r_d1 : UInt<1>
    dec_tlu_flush_pause_r_d1 <= UInt<1>("h00")
    wire dbg_halt_req_held : UInt<1>
    dbg_halt_req_held <= UInt<1>("h00")
    wire debug_halt_req_ns : UInt<1>
    debug_halt_req_ns <= UInt<1>("h00")
    wire internal_dbg_halt_mode : UInt<1>
    internal_dbg_halt_mode <= UInt<1>("h00")
    wire core_empty : UInt<1>
    core_empty <= UInt<1>("h00")
    wire dbg_halt_req_final : UInt<1>
    dbg_halt_req_final <= UInt<1>("h00")
    wire debug_brkpt_status_ns : UInt<1>
    debug_brkpt_status_ns <= UInt<1>("h00")
    wire mpc_debug_halt_ack_ns : UInt<1>
    mpc_debug_halt_ack_ns <= UInt<1>("h00")
    wire mpc_debug_run_ack_ns : UInt<1>
    mpc_debug_run_ack_ns <= UInt<1>("h00")
    wire mpc_halt_state_ns : UInt<1>
    mpc_halt_state_ns <= UInt<1>("h00")
    wire mpc_run_state_ns : UInt<1>
    mpc_run_state_ns <= UInt<1>("h00")
    wire dbg_halt_state_ns : UInt<1>
    dbg_halt_state_ns <= UInt<1>("h00")
    wire dbg_run_state_ns : UInt<1>
    dbg_run_state_ns <= UInt<1>("h00")
    wire dbg_halt_state_f : UInt<1>
    dbg_halt_state_f <= UInt<1>("h00")
    wire mpc_halt_state_f : UInt<1>
    mpc_halt_state_f <= UInt<1>("h00")
    wire nmi_int_detected : UInt<1>
    nmi_int_detected <= UInt<1>("h00")
    wire nmi_lsu_load_type : UInt<1>
    nmi_lsu_load_type <= UInt<1>("h00")
    wire nmi_lsu_store_type : UInt<1>
    nmi_lsu_store_type <= UInt<1>("h00")
    wire reset_delayed : UInt<1>
    reset_delayed <= UInt<1>("h00")
    wire debug_mode_status : UInt<1>
    debug_mode_status <= UInt<1>("h00")
    wire e5_valid : UInt<1>
    e5_valid <= UInt<1>("h00")
    wire ic_perr_r_d1 : UInt<1>
    ic_perr_r_d1 <= UInt<1>("h00")
    wire iccm_sbecc_r_d1 : UInt<1>
    iccm_sbecc_r_d1 <= UInt<1>("h00")
    wire npc_r : UInt<31>
    npc_r <= UInt<1>("h00")
    wire npc_r_d1 : UInt<31>
    npc_r_d1 <= UInt<1>("h00")
    wire mie_ns : UInt<6>
    mie_ns <= UInt<1>("h00")
    wire mepc : UInt<31>
    mepc <= UInt<1>("h00")
    wire mdseac_locked_ns : UInt<1>
    mdseac_locked_ns <= UInt<1>("h00")
    wire force_halt : UInt<1>
    force_halt <= UInt<1>("h00")
    wire dpc : UInt<31>
    dpc <= UInt<1>("h00")
    wire mstatus_mie_ns : UInt<1>
    mstatus_mie_ns <= UInt<1>("h00")
    wire dec_csr_wen_r_mod : UInt<1>
    dec_csr_wen_r_mod <= UInt<1>("h00")
    wire fw_halt_req : UInt<1>
    fw_halt_req <= UInt<1>("h00")
    wire mstatus : UInt<2>
    mstatus <= UInt<1>("h00")
    wire dcsr : UInt<16>
    dcsr <= UInt<1>("h00")
    wire mtvec : UInt<31>
    mtvec <= UInt<1>("h00")
    wire mip : UInt<6>
    mip <= UInt<1>("h00")
    wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41]
    wire dec_tlu_mpc_halted_only_ns : UInt<1>
    dec_tlu_mpc_halted_only_ns <= UInt<1>("h00")
    node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33]
    node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51]
    dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30]
    inst int_timers of el2_dec_timer_ctl @[el2_dec_tlu_ctl.scala 355:24]
    int_timers.clock <= clock
    int_timers.reset <= reset
    int_timers.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 356:57]
    int_timers.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 357:57]
    int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 358:49]
    int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 359:49]
    int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 360:49]
    int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 361:49]
    int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 362:49]
    int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 363:49]
    int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 364:57]
    int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 365:57]
    int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 366:49]
    int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 367:49]
    int_timers.io.dec_pause_state <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 368:41]
    int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 369:41]
    int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[el2_dec_tlu_ctl.scala 370:41]
    node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58]
    node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58]
    node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58]
    node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58]
    node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58]
    node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58]
    reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:81]
    _T_8 <= _T_7 @[el2_lib.scala 177:81]
    reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:58]
    syncro_ff <= _T_8 @[el2_lib.scala 177:58]
    node nmi_int_sync = bits(syncro_ff, 6, 6) @[el2_dec_tlu_ctl.scala 382:67]
    node timer_int_sync = bits(syncro_ff, 5, 5) @[el2_dec_tlu_ctl.scala 383:59]
    node soft_int_sync = bits(syncro_ff, 4, 4) @[el2_dec_tlu_ctl.scala 384:59]
    node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[el2_dec_tlu_ctl.scala 385:59]
    node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[el2_dec_tlu_ctl.scala 386:59]
    node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[el2_dec_tlu_ctl.scala 387:51]
    node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[el2_dec_tlu_ctl.scala 388:51]
    node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 391:52]
    node _T_10 = bits(_T_9, 0, 0) @[el2_dec_tlu_ctl.scala 391:68]
    inst rvclkhdr of rvclkhdr_4 @[el2_lib.scala 483:22]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr.io.en <= _T_10 @[el2_lib.scala 485:16]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[el2_dec_tlu_ctl.scala 392:61]
    node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 392:82]
    node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 392:98]
    inst rvclkhdr_1 of rvclkhdr_5 @[el2_lib.scala 483:22]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr_1.io.en <= _T_13 @[el2_lib.scala 485:16]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[el2_dec_tlu_ctl.scala 395:29]
    node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 396:49]
    node _T_15 = or(_T_14, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 396:68]
    node _T_16 = or(_T_15, interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 396:88]
    node _T_17 = or(_T_16, reset_delayed) @[el2_dec_tlu_ctl.scala 396:111]
    node _T_18 = or(_T_17, pause_expired_r) @[el2_dec_tlu_ctl.scala 396:127]
    node _T_19 = or(_T_18, pause_expired_wb) @[el2_dec_tlu_ctl.scala 396:145]
    node _T_20 = or(_T_19, ic_perr_r) @[el2_dec_tlu_ctl.scala 396:164]
    node _T_21 = or(_T_20, ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 396:176]
    node _T_22 = or(_T_21, iccm_sbecc_r) @[el2_dec_tlu_ctl.scala 396:191]
    node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 396:206]
    node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 396:224]
    node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 398:43]
    node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 398:59]
    inst rvclkhdr_2 of rvclkhdr_6 @[el2_lib.scala 483:22]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr_2.io.en <= _T_25 @[el2_lib.scala 485:16]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    node _T_26 = or(e4e5_valid, flush_clkvalid) @[el2_dec_tlu_ctl.scala 399:47]
    node _T_27 = bits(_T_26, 0, 0) @[el2_dec_tlu_ctl.scala 399:65]
    inst rvclkhdr_3 of rvclkhdr_7 @[el2_lib.scala 483:22]
    rvclkhdr_3.clock <= clock
    rvclkhdr_3.reset <= reset
    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr_3.io.en <= _T_27 @[el2_lib.scala 485:16]
    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 401:72]
    iccm_repair_state_d1 <= iccm_repair_state_ns @[el2_dec_tlu_ctl.scala 401:72]
    reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 402:81]
    _T_28 <= ic_perr_r @[el2_dec_tlu_ctl.scala 402:81]
    ic_perr_r_d1 <= _T_28 @[el2_dec_tlu_ctl.scala 402:49]
    reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 403:89]
    _T_29 <= iccm_sbecc_r @[el2_dec_tlu_ctl.scala 403:89]
    iccm_sbecc_r_d1 <= _T_29 @[el2_dec_tlu_ctl.scala 403:57]
    reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 404:89]
    _T_30 <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 404:89]
    e5_valid <= _T_30 @[el2_dec_tlu_ctl.scala 404:57]
    reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 405:73]
    _T_31 <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 405:73]
    debug_mode_status <= _T_31 @[el2_dec_tlu_ctl.scala 405:41]
    reg lsu_pmu_load_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 406:72]
    lsu_pmu_load_external_r <= io.lsu_pmu_load_external_m @[el2_dec_tlu_ctl.scala 406:72]
    reg lsu_pmu_store_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 407:64]
    lsu_pmu_store_external_r <= io.lsu_pmu_store_external_m @[el2_dec_tlu_ctl.scala 407:64]
    reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 408:72]
    tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 408:72]
    reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 409:65]
    _T_32 <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 409:65]
    io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[el2_dec_tlu_ctl.scala 409:33]
    reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 410:64]
    internal_dbg_halt_mode_f2 <= debug_mode_status @[el2_dec_tlu_ctl.scala 410:64]
    reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 411:73]
    _T_33 <= force_halt @[el2_dec_tlu_ctl.scala 411:73]
    io.dec_tlu_force_halt <= _T_33 @[el2_dec_tlu_ctl.scala 411:41]
    io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 415:33]
    reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 416:80]
    reset_detect <= UInt<1>("h01") @[el2_dec_tlu_ctl.scala 416:80]
    reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 417:80]
    reset_detected <= reset_detect @[el2_dec_tlu_ctl.scala 417:80]
    node _T_34 = xor(reset_detect, reset_detected) @[el2_dec_tlu_ctl.scala 418:64]
    reset_delayed <= _T_34 @[el2_dec_tlu_ctl.scala 418:49]
    reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 420:64]
    nmi_int_delayed <= nmi_int_sync @[el2_dec_tlu_ctl.scala 420:64]
    reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 421:72]
    nmi_int_detected_f <= nmi_int_detected @[el2_dec_tlu_ctl.scala 421:72]
    reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 422:72]
    nmi_lsu_load_type_f <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 422:72]
    reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 423:64]
    nmi_lsu_store_type_f <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 423:64]
    node _T_35 = not(mdseac_locked_f) @[el2_dec_tlu_ctl.scala 427:26]
    node _T_36 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 427:78]
    node nmi_lsu_detected = and(_T_35, _T_36) @[el2_dec_tlu_ctl.scala 427:43]
    node _T_37 = not(nmi_int_delayed) @[el2_dec_tlu_ctl.scala 429:39]
    node _T_38 = and(nmi_int_sync, _T_37) @[el2_dec_tlu_ctl.scala 429:37]
    node _T_39 = or(_T_38, nmi_lsu_detected) @[el2_dec_tlu_ctl.scala 429:57]
    node _T_40 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 429:100]
    node _T_41 = and(nmi_int_detected_f, _T_40) @[el2_dec_tlu_ctl.scala 429:98]
    node _T_42 = or(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 429:76]
    node _T_43 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 429:159]
    node _T_44 = and(take_ext_int_start_d3, _T_43) @[el2_dec_tlu_ctl.scala 429:140]
    node _T_45 = or(_T_42, _T_44) @[el2_dec_tlu_ctl.scala 429:116]
    nmi_int_detected <= _T_45 @[el2_dec_tlu_ctl.scala 429:20]
    node _T_46 = and(nmi_lsu_detected, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 431:42]
    node _T_47 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:101]
    node _T_48 = and(nmi_int_detected_f, _T_47) @[el2_dec_tlu_ctl.scala 431:99]
    node _T_49 = not(_T_48) @[el2_dec_tlu_ctl.scala 431:78]
    node _T_50 = and(_T_46, _T_49) @[el2_dec_tlu_ctl.scala 431:76]
    node _T_51 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:143]
    node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[el2_dec_tlu_ctl.scala 431:141]
    node _T_53 = or(_T_50, _T_52) @[el2_dec_tlu_ctl.scala 431:118]
    nmi_lsu_load_type <= _T_53 @[el2_dec_tlu_ctl.scala 431:21]
    node _T_54 = and(nmi_lsu_detected, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 432:43]
    node _T_55 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:103]
    node _T_56 = and(nmi_int_detected_f, _T_55) @[el2_dec_tlu_ctl.scala 432:101]
    node _T_57 = not(_T_56) @[el2_dec_tlu_ctl.scala 432:80]
    node _T_58 = and(_T_54, _T_57) @[el2_dec_tlu_ctl.scala 432:78]
    node _T_59 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:146]
    node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[el2_dec_tlu_ctl.scala 432:144]
    node _T_61 = or(_T_58, _T_60) @[el2_dec_tlu_ctl.scala 432:120]
    nmi_lsu_store_type <= _T_61 @[el2_dec_tlu_ctl.scala 432:22]
    node _T_62 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 439:63]
    node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[el2_dec_tlu_ctl.scala 439:61]
    reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 440:64]
    mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[el2_dec_tlu_ctl.scala 440:64]
    reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 441:64]
    mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[el2_dec_tlu_ctl.scala 441:64]
    reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 442:81]
    _T_63 <= mpc_halt_state_ns @[el2_dec_tlu_ctl.scala 442:81]
    mpc_halt_state_f <= _T_63 @[el2_dec_tlu_ctl.scala 442:49]
    reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 443:80]
    mpc_run_state_f <= mpc_run_state_ns @[el2_dec_tlu_ctl.scala 443:80]
    reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 444:72]
    debug_brkpt_status_f <= debug_brkpt_status_ns @[el2_dec_tlu_ctl.scala 444:72]
    reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 445:72]
    mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[el2_dec_tlu_ctl.scala 445:72]
    reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 446:80]
    mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[el2_dec_tlu_ctl.scala 446:80]
    reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 447:81]
    _T_64 <= dbg_halt_state_ns @[el2_dec_tlu_ctl.scala 447:81]
    dbg_halt_state_f <= _T_64 @[el2_dec_tlu_ctl.scala 447:49]
    reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 448:80]
    dbg_run_state_f <= dbg_run_state_ns @[el2_dec_tlu_ctl.scala 448:80]
    reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 449:73]
    _T_65 <= dec_tlu_mpc_halted_only_ns @[el2_dec_tlu_ctl.scala 449:73]
    io.dec_tlu_mpc_halted_only <= _T_65 @[el2_dec_tlu_ctl.scala 449:41]
    node _T_66 = not(mpc_debug_halt_req_sync_f) @[el2_dec_tlu_ctl.scala 453:65]
    node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[el2_dec_tlu_ctl.scala 453:63]
    node _T_67 = not(mpc_debug_run_req_sync_f) @[el2_dec_tlu_ctl.scala 454:64]
    node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[el2_dec_tlu_ctl.scala 454:62]
    node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[el2_dec_tlu_ctl.scala 456:42]
    node _T_69 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 456:93]
    node _T_70 = and(reset_delayed, _T_69) @[el2_dec_tlu_ctl.scala 456:91]
    node _T_71 = or(_T_68, _T_70) @[el2_dec_tlu_ctl.scala 456:74]
    node _T_72 = not(mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 456:119]
    node _T_73 = and(_T_71, _T_72) @[el2_dec_tlu_ctl.scala 456:117]
    mpc_halt_state_ns <= _T_73 @[el2_dec_tlu_ctl.scala 456:21]
    node _T_74 = not(mpc_debug_run_ack_f) @[el2_dec_tlu_ctl.scala 457:74]
    node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[el2_dec_tlu_ctl.scala 457:72]
    node _T_76 = or(mpc_run_state_f, _T_75) @[el2_dec_tlu_ctl.scala 457:40]
    node _T_77 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 457:127]
    node _T_78 = and(debug_mode_status, _T_77) @[el2_dec_tlu_ctl.scala 457:125]
    node _T_79 = and(_T_76, _T_78) @[el2_dec_tlu_ctl.scala 457:97]
    mpc_run_state_ns <= _T_79 @[el2_dec_tlu_ctl.scala 457:20]
    node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 459:64]
    node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 459:90]
    node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 459:115]
    node _T_83 = or(dbg_halt_state_f, _T_82) @[el2_dec_tlu_ctl.scala 459:42]
    node _T_84 = not(io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 459:147]
    node _T_85 = and(_T_83, _T_84) @[el2_dec_tlu_ctl.scala 459:145]
    dbg_halt_state_ns <= _T_85 @[el2_dec_tlu_ctl.scala 459:21]
    node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 460:40]
    node _T_87 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 460:91]
    node _T_88 = and(debug_mode_status, _T_87) @[el2_dec_tlu_ctl.scala 460:89]
    node _T_89 = and(_T_86, _T_88) @[el2_dec_tlu_ctl.scala 460:61]
    dbg_run_state_ns <= _T_89 @[el2_dec_tlu_ctl.scala 460:20]
    node _T_90 = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 463:33]
    node _T_91 = and(_T_90, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 463:51]
    dec_tlu_mpc_halted_only_ns <= _T_91 @[el2_dec_tlu_ctl.scala 463:30]
    node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 466:53]
    node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[el2_dec_tlu_ctl.scala 467:47]
    node _T_93 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 467:99]
    node _T_94 = and(internal_dbg_halt_mode, _T_93) @[el2_dec_tlu_ctl.scala 467:97]
    node _T_95 = and(_T_92, _T_94) @[el2_dec_tlu_ctl.scala 467:71]
    debug_brkpt_status_ns <= _T_95 @[el2_dec_tlu_ctl.scala 467:25]
    node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[el2_dec_tlu_ctl.scala 470:45]
    node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 470:72]
    node _T_98 = and(_T_97, core_empty) @[el2_dec_tlu_ctl.scala 470:98]
    mpc_debug_halt_ack_ns <= _T_98 @[el2_dec_tlu_ctl.scala 470:25]
    node _T_99 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 471:53]
    node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[el2_dec_tlu_ctl.scala 471:51]
    node _T_101 = not(mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 471:74]
    node _T_102 = and(_T_100, _T_101) @[el2_dec_tlu_ctl.scala 471:72]
    node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 471:123]
    node _T_104 = or(_T_102, _T_103) @[el2_dec_tlu_ctl.scala 471:100]
    mpc_debug_run_ack_ns <= _T_104 @[el2_dec_tlu_ctl.scala 471:24]
    io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[el2_dec_tlu_ctl.scala 474:25]
    io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[el2_dec_tlu_ctl.scala 475:25]
    io.debug_brkpt_status <= debug_brkpt_status_f @[el2_dec_tlu_ctl.scala 476:25]
    node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 479:47]
    node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 479:68]
    node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 480:42]
    node _T_107 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 480:65]
    node _T_108 = and(_T_106, _T_107) @[el2_dec_tlu_ctl.scala 480:63]
    dbg_halt_req_final <= _T_108 @[el2_dec_tlu_ctl.scala 480:22]
    node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 483:44]
    node _T_110 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 483:89]
    node _T_111 = and(reset_delayed, _T_110) @[el2_dec_tlu_ctl.scala 483:87]
    node _T_112 = or(_T_109, _T_111) @[el2_dec_tlu_ctl.scala 483:70]
    node _T_113 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 483:115]
    node _T_114 = and(_T_112, _T_113) @[el2_dec_tlu_ctl.scala 483:113]
    node _T_115 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 483:143]
    node debug_halt_req = and(_T_114, _T_115) @[el2_dec_tlu_ctl.scala 483:141]
    node _T_116 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 485:26]
    node _T_117 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:69]
    node _T_118 = and(mpc_run_state_ns, _T_117) @[el2_dec_tlu_ctl.scala 485:67]
    node _T_119 = not(mpc_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:111]
    node _T_120 = and(dbg_run_state_ns, _T_119) @[el2_dec_tlu_ctl.scala 485:109]
    node _T_121 = or(_T_118, _T_120) @[el2_dec_tlu_ctl.scala 485:89]
    node debug_resume_req = and(_T_116, _T_121) @[el2_dec_tlu_ctl.scala 485:46]
    node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 490:37]
    node _T_123 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 490:60]
    node _T_124 = and(_T_122, _T_123) @[el2_dec_tlu_ctl.scala 490:58]
    node _T_125 = not(mret_r) @[el2_dec_tlu_ctl.scala 490:83]
    node _T_126 = and(_T_124, _T_125) @[el2_dec_tlu_ctl.scala 490:81]
    node _T_127 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 490:93]
    node _T_128 = and(_T_126, _T_127) @[el2_dec_tlu_ctl.scala 490:91]
    node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[el2_dec_tlu_ctl.scala 490:109]
    node _T_130 = and(_T_128, _T_129) @[el2_dec_tlu_ctl.scala 490:107]
    node _T_131 = not(take_reset) @[el2_dec_tlu_ctl.scala 490:139]
    node take_halt = and(_T_130, _T_131) @[el2_dec_tlu_ctl.scala 490:137]
    node _T_132 = not(dec_tlu_flush_pause_r_d1) @[el2_dec_tlu_ctl.scala 493:50]
    node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[el2_dec_tlu_ctl.scala 493:48]
    node _T_134 = not(take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 493:78]
    node _T_135 = and(_T_133, _T_134) @[el2_dec_tlu_ctl.scala 493:76]
    node _T_136 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:120]
    node _T_137 = and(halt_taken_f, _T_136) @[el2_dec_tlu_ctl.scala 493:118]
    node _T_138 = not(pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:140]
    node _T_139 = and(_T_137, _T_138) @[el2_dec_tlu_ctl.scala 493:138]
    node _T_140 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 493:163]
    node _T_141 = and(_T_139, _T_140) @[el2_dec_tlu_ctl.scala 493:161]
    node halt_taken = or(_T_135, _T_141) @[el2_dec_tlu_ctl.scala 493:102]
    node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 497:47]
    node _T_143 = and(_T_142, io.ifu_miss_state_idle) @[el2_dec_tlu_ctl.scala 497:64]
    node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 497:89]
    node _T_145 = not(debug_halt_req) @[el2_dec_tlu_ctl.scala 497:115]
    node _T_146 = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 497:113]
    node _T_147 = not(debug_halt_req_d1) @[el2_dec_tlu_ctl.scala 497:133]
    node _T_148 = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 497:131]
    node _T_149 = not(io.dec_div_active) @[el2_dec_tlu_ctl.scala 497:154]
    node _T_150 = and(_T_148, _T_149) @[el2_dec_tlu_ctl.scala 497:152]
    node _T_151 = or(force_halt, _T_150) @[el2_dec_tlu_ctl.scala 497:28]
    core_empty <= _T_151 @[el2_dec_tlu_ctl.scala 497:14]
    node _T_152 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 503:31]
    node _T_153 = and(_T_152, debug_halt_req) @[el2_dec_tlu_ctl.scala 503:57]
    node _T_154 = or(_T_153, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 503:75]
    node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 503:101]
    node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 503:126]
    node _T_156 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 506:105]
    node _T_157 = not(_T_156) @[el2_dec_tlu_ctl.scala 506:100]
    node _T_158 = and(debug_resume_req_f, _T_157) @[el2_dec_tlu_ctl.scala 506:98]
    node _T_159 = not(_T_158) @[el2_dec_tlu_ctl.scala 506:77]
    node _T_160 = and(debug_mode_status, _T_159) @[el2_dec_tlu_ctl.scala 506:75]
    node _T_161 = or(debug_halt_req_ns, _T_160) @[el2_dec_tlu_ctl.scala 506:47]
    internal_dbg_halt_mode <= _T_161 @[el2_dec_tlu_ctl.scala 506:26]
    node _T_162 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 508:61]
    node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[el2_dec_tlu_ctl.scala 508:59]
    node _T_163 = and(debug_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 513:42]
    node _T_164 = and(_T_163, halt_taken) @[el2_dec_tlu_ctl.scala 513:55]
    node _T_165 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 513:91]
    node _T_166 = and(dbg_tlu_halted_f, _T_165) @[el2_dec_tlu_ctl.scala 513:89]
    node dbg_tlu_halted = or(_T_164, _T_166) @[el2_dec_tlu_ctl.scala 513:69]
    node _T_167 = not(dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 514:67]
    node _T_168 = and(debug_halt_req_f, _T_167) @[el2_dec_tlu_ctl.scala 514:65]
    node _T_169 = or(enter_debug_halt_req, _T_168) @[el2_dec_tlu_ctl.scala 514:45]
    debug_halt_req_ns <= _T_169 @[el2_dec_tlu_ctl.scala 514:21]
    node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 515:43]
    node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[el2_dec_tlu_ctl.scala 515:62]
    node _T_171 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 517:55]
    node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[el2_dec_tlu_ctl.scala 517:53]
    node _T_173 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 517:84]
    node _T_174 = and(_T_172, _T_173) @[el2_dec_tlu_ctl.scala 517:78]
    node _T_175 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 517:98]
    node dcsr_single_step_done = and(_T_174, _T_175) @[el2_dec_tlu_ctl.scala 517:96]
    node _T_176 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 519:60]
    node _T_177 = and(debug_resume_req_f, _T_176) @[el2_dec_tlu_ctl.scala 519:54]
    node _T_178 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 519:105]
    node _T_179 = and(dcsr_single_step_running_f, _T_178) @[el2_dec_tlu_ctl.scala 519:103]
    node dcsr_single_step_running = or(_T_177, _T_179) @[el2_dec_tlu_ctl.scala 519:73]
    node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 521:47]
    node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 524:51]
    node _T_181 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 524:106]
    node _T_182 = and(request_debug_mode_r_d1, _T_181) @[el2_dec_tlu_ctl.scala 524:104]
    node request_debug_mode_r = or(_T_180, _T_182) @[el2_dec_tlu_ctl.scala 524:77]
    node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[el2_dec_tlu_ctl.scala 526:58]
    node _T_184 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 526:89]
    node request_debug_mode_done = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 526:87]
    reg _T_185 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 529:73]
    _T_185 <= io.dec_tlu_flush_noredir_r @[el2_dec_tlu_ctl.scala 529:73]
    dec_tlu_flush_noredir_r_d1 <= _T_185 @[el2_dec_tlu_ctl.scala 529:41]
    reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 530:81]
    _T_186 <= halt_taken @[el2_dec_tlu_ctl.scala 530:81]
    halt_taken_f <= _T_186 @[el2_dec_tlu_ctl.scala 530:49]
    reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 531:89]
    _T_187 <= io.lsu_idle_any @[el2_dec_tlu_ctl.scala 531:89]
    lsu_idle_any_f <= _T_187 @[el2_dec_tlu_ctl.scala 531:57]
    reg _T_188 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 532:73]
    _T_188 <= io.ifu_miss_state_idle @[el2_dec_tlu_ctl.scala 532:73]
    ifu_miss_state_idle_f <= _T_188 @[el2_dec_tlu_ctl.scala 532:41]
    reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 533:81]
    _T_189 <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 533:81]
    dbg_tlu_halted_f <= _T_189 @[el2_dec_tlu_ctl.scala 533:49]
    reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 534:73]
    _T_190 <= resume_ack_ns @[el2_dec_tlu_ctl.scala 534:73]
    io.dec_tlu_resume_ack <= _T_190 @[el2_dec_tlu_ctl.scala 534:41]
    reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 535:81]
    _T_191 <= debug_halt_req_ns @[el2_dec_tlu_ctl.scala 535:81]
    debug_halt_req_f <= _T_191 @[el2_dec_tlu_ctl.scala 535:49]
    reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 536:81]
    _T_192 <= debug_resume_req @[el2_dec_tlu_ctl.scala 536:81]
    debug_resume_req_f <= _T_192 @[el2_dec_tlu_ctl.scala 536:49]
    reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 537:81]
    _T_193 <= trigger_hit_dmode_r @[el2_dec_tlu_ctl.scala 537:81]
    trigger_hit_dmode_r_d1 <= _T_193 @[el2_dec_tlu_ctl.scala 537:49]
    reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 538:81]
    _T_194 <= dcsr_single_step_done @[el2_dec_tlu_ctl.scala 538:81]
    dcsr_single_step_done_f <= _T_194 @[el2_dec_tlu_ctl.scala 538:49]
    reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 539:81]
    _T_195 <= debug_halt_req @[el2_dec_tlu_ctl.scala 539:81]
    debug_halt_req_d1 <= _T_195 @[el2_dec_tlu_ctl.scala 539:49]
    reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 540:73]
    dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 540:73]
    reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 541:73]
    dec_pause_state_f <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 541:73]
    reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 542:81]
    _T_196 <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 542:81]
    request_debug_mode_r_d1 <= _T_196 @[el2_dec_tlu_ctl.scala 542:49]
    reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 543:73]
    _T_197 <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 543:73]
    request_debug_mode_done_f <= _T_197 @[el2_dec_tlu_ctl.scala 543:41]
    reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 544:73]
    _T_198 <= dcsr_single_step_running @[el2_dec_tlu_ctl.scala 544:73]
    dcsr_single_step_running_f <= _T_198 @[el2_dec_tlu_ctl.scala 544:41]
    reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 545:73]
    _T_199 <= io.dec_tlu_flush_pause_r @[el2_dec_tlu_ctl.scala 545:73]
    dec_tlu_flush_pause_r_d1 <= _T_199 @[el2_dec_tlu_ctl.scala 545:41]
    reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 546:81]
    _T_200 <= dbg_halt_req_held_ns @[el2_dec_tlu_ctl.scala 546:81]
    dbg_halt_req_held <= _T_200 @[el2_dec_tlu_ctl.scala 546:49]
    io.dec_tlu_debug_stall <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 549:41]
    io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 550:41]
    io.dec_tlu_debug_mode <= debug_mode_status @[el2_dec_tlu_ctl.scala 551:41]
    dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[el2_dec_tlu_ctl.scala 552:41]
    node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 555:56]
    node _T_202 = or(take_halt, _T_201) @[el2_dec_tlu_ctl.scala 555:43]
    node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[el2_dec_tlu_ctl.scala 555:82]
    node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 555:129]
    node _T_205 = or(_T_203, _T_204) @[el2_dec_tlu_ctl.scala 555:109]
    node _T_206 = or(_T_205, take_ext_int_start) @[el2_dec_tlu_ctl.scala 555:152]
    io.dec_tlu_flush_noredir_r <= _T_206 @[el2_dec_tlu_ctl.scala 555:30]
    io.dec_tlu_flush_extint <= take_ext_int_start @[el2_dec_tlu_ctl.scala 557:27]
    node _T_207 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 560:55]
    node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[el2_dec_tlu_ctl.scala 560:53]
    node _T_209 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 560:76]
    node _T_210 = and(_T_208, _T_209) @[el2_dec_tlu_ctl.scala 560:74]
    io.dec_tlu_flush_pause_r <= _T_210 @[el2_dec_tlu_ctl.scala 560:28]
    node _T_211 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 562:22]
    node _T_212 = and(_T_211, dec_pause_state_f) @[el2_dec_tlu_ctl.scala 562:42]
    node _T_213 = or(ext_int_ready, ce_int_ready) @[el2_dec_tlu_ctl.scala 562:80]
    node _T_214 = or(_T_213, timer_int_ready) @[el2_dec_tlu_ctl.scala 562:95]
    node _T_215 = or(_T_214, soft_int_ready) @[el2_dec_tlu_ctl.scala 562:113]
    node _T_216 = or(_T_215, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 562:130]
    node _T_217 = or(_T_216, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 562:154]
    node _T_218 = or(_T_217, nmi_int_detected) @[el2_dec_tlu_ctl.scala 562:178]
    node _T_219 = or(_T_218, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 562:197]
    node _T_220 = not(_T_219) @[el2_dec_tlu_ctl.scala 562:64]
    node _T_221 = and(_T_212, _T_220) @[el2_dec_tlu_ctl.scala 562:62]
    node _T_222 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 562:220]
    node _T_223 = and(_T_221, _T_222) @[el2_dec_tlu_ctl.scala 562:218]
    node _T_224 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 562:244]
    node _T_225 = and(_T_223, _T_224) @[el2_dec_tlu_ctl.scala 562:242]
    node _T_226 = not(pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 562:264]
    node _T_227 = and(_T_225, _T_226) @[el2_dec_tlu_ctl.scala 562:262]
    node _T_228 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 562:285]
    node _T_229 = and(_T_227, _T_228) @[el2_dec_tlu_ctl.scala 562:283]
    pause_expired_r <= _T_229 @[el2_dec_tlu_ctl.scala 562:19]
    node _T_230 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 564:66]
    node _T_231 = and(io.dec_tlu_flush_lower_r, _T_230) @[el2_dec_tlu_ctl.scala 564:60]
    node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 564:103]
    node _T_233 = and(_T_231, _T_232) @[el2_dec_tlu_ctl.scala 564:78]
    node _T_234 = not(io.dec_tlu_flush_noredir_r) @[el2_dec_tlu_ctl.scala 564:133]
    node _T_235 = and(_T_233, _T_234) @[el2_dec_tlu_ctl.scala 564:131]
    io.dec_tlu_flush_leak_one_r <= _T_235 @[el2_dec_tlu_ctl.scala 564:31]
    node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 565:70]
    node _T_237 = and(io.dec_tlu_flush_lower_r, _T_236) @[el2_dec_tlu_ctl.scala 565:54]
    io.dec_tlu_flush_err_r <= _T_237 @[el2_dec_tlu_ctl.scala 565:26]
    io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[el2_dec_tlu_ctl.scala 568:23]
    node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[el2_dec_tlu_ctl.scala 569:36]
    io.dec_dbg_cmd_fail <= _T_238 @[el2_dec_tlu_ctl.scala 569:23]
    node _T_239 = bits(mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 582:42]
    node _T_240 = bits(mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 582:69]
    node _T_241 = bits(mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 582:96]
    node _T_242 = bits(mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 582:123]
    node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58]
    node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58]
    node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58]
    node _T_245 = bits(mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 583:44]
    node _T_246 = bits(mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 583:71]
    node _T_247 = bits(mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 583:98]
    node _T_248 = bits(mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 583:125]
    node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
    node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58]
    node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58]
    node _T_251 = bits(mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 584:44]
    node _T_252 = bits(mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 584:71]
    node _T_253 = bits(mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 584:98]
    node _T_254 = bits(mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 584:125]
    node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58]
    node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58]
    node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58]
    node _T_257 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 587:45]
    node _T_258 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:71]
    node _T_259 = or(_T_257, _T_258) @[el2_dec_tlu_ctl.scala 587:62]
    node _T_260 = bits(mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 587:100]
    node _T_261 = and(_T_259, _T_260) @[el2_dec_tlu_ctl.scala 587:86]
    node _T_262 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 587:133]
    node _T_263 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:159]
    node _T_264 = or(_T_262, _T_263) @[el2_dec_tlu_ctl.scala 587:150]
    node _T_265 = bits(mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 587:188]
    node _T_266 = and(_T_264, _T_265) @[el2_dec_tlu_ctl.scala 587:174]
    node _T_267 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 587:222]
    node _T_268 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:248]
    node _T_269 = or(_T_267, _T_268) @[el2_dec_tlu_ctl.scala 587:239]
    node _T_270 = bits(mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 587:277]
    node _T_271 = and(_T_269, _T_270) @[el2_dec_tlu_ctl.scala 587:263]
    node _T_272 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 587:311]
    node _T_273 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:337]
    node _T_274 = or(_T_272, _T_273) @[el2_dec_tlu_ctl.scala 587:328]
    node _T_275 = bits(mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 587:366]
    node _T_276 = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 587:352]
    node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58]
    node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58]
    node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58]
    node _T_279 = and(trigger_execute, trigger_data) @[el2_dec_tlu_ctl.scala 590:56]
    node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15]
    node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_282 = and(_T_279, _T_281) @[el2_dec_tlu_ctl.scala 590:71]
    node _T_283 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 590:128]
    node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15]
    node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_286 = or(_T_282, _T_285) @[el2_dec_tlu_ctl.scala 590:97]
    node i0_iside_trigger_has_pri_r = not(_T_286) @[el2_dec_tlu_ctl.scala 590:37]
    node _T_287 = and(trigger_store, trigger_data) @[el2_dec_tlu_ctl.scala 593:50]
    node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15]
    node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_290 = and(_T_287, _T_289) @[el2_dec_tlu_ctl.scala 593:65]
    node i0_lsu_trigger_has_pri_r = not(_T_290) @[el2_dec_tlu_ctl.scala 593:34]
    node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15]
    node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[el2_dec_tlu_ctl.scala 598:83]
    node _T_294 = and(_T_292, _T_293) @[el2_dec_tlu_ctl.scala 598:52]
    node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:89]
    node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:118]
    node i0trigger_qual_r = and(_T_296, trigger_enabled) @[el2_dec_tlu_ctl.scala 598:145]
    node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 600:57]
    node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15]
    node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_300 = not(_T_299) @[el2_dec_tlu_ctl.scala 600:22]
    node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[el2_dec_tlu_ctl.scala 600:83]
    node _T_301 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:52]
    node _T_302 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:72]
    node _T_303 = not(_T_302) @[el2_dec_tlu_ctl.scala 603:59]
    node _T_304 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:102]
    node _T_305 = or(_T_303, _T_304) @[el2_dec_tlu_ctl.scala 603:88]
    node _T_306 = and(_T_301, _T_305) @[el2_dec_tlu_ctl.scala 603:56]
    node _T_307 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:120]
    node _T_308 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:140]
    node _T_309 = not(_T_308) @[el2_dec_tlu_ctl.scala 603:127]
    node _T_310 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:170]
    node _T_311 = or(_T_309, _T_310) @[el2_dec_tlu_ctl.scala 603:156]
    node _T_312 = and(_T_307, _T_311) @[el2_dec_tlu_ctl.scala 603:124]
    node _T_313 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:188]
    node _T_314 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:208]
    node _T_315 = not(_T_314) @[el2_dec_tlu_ctl.scala 603:195]
    node _T_316 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:238]
    node _T_317 = or(_T_315, _T_316) @[el2_dec_tlu_ctl.scala 603:224]
    node _T_318 = and(_T_313, _T_317) @[el2_dec_tlu_ctl.scala 603:192]
    node _T_319 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:256]
    node _T_320 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:276]
    node _T_321 = not(_T_320) @[el2_dec_tlu_ctl.scala 603:263]
    node _T_322 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:306]
    node _T_323 = or(_T_321, _T_322) @[el2_dec_tlu_ctl.scala 603:292]
    node _T_324 = and(_T_319, _T_323) @[el2_dec_tlu_ctl.scala 603:260]
    node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58]
    node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58]
    node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58]
    node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 606:56]
    i0_trigger_hit_r <= i0_trigger_hit_raw_r @[el2_dec_tlu_ctl.scala 608:25]
    node _T_327 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 612:44]
    node _T_328 = bits(mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 612:75]
    node _T_329 = and(_T_327, _T_328) @[el2_dec_tlu_ctl.scala 612:61]
    node _T_330 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 612:104]
    node _T_331 = bits(mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 612:135]
    node _T_332 = and(_T_330, _T_331) @[el2_dec_tlu_ctl.scala 612:121]
    node _T_333 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 612:164]
    node _T_334 = bits(mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 612:195]
    node _T_335 = and(_T_333, _T_334) @[el2_dec_tlu_ctl.scala 612:181]
    node _T_336 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 612:224]
    node _T_337 = bits(mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 612:255]
    node _T_338 = and(_T_336, _T_337) @[el2_dec_tlu_ctl.scala 612:241]
    node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58]
    node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58]
    node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58]
    node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15]
    node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 615:56]
    node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[el2_dec_tlu_ctl.scala 618:56]
    node i0_trigger_action_r = orr(_T_343) @[el2_dec_tlu_ctl.scala 618:74]
    node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[el2_dec_tlu_ctl.scala 620:44]
    trigger_hit_dmode_r <= _T_344 @[el2_dec_tlu_ctl.scala 620:23]
    node _T_345 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 622:54]
    node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[el2_dec_tlu_ctl.scala 622:52]
    node _T_346 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 649:56]
    node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[el2_dec_tlu_ctl.scala 649:54]
    node _T_348 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 649:81]
    node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[el2_dec_tlu_ctl.scala 649:79]
    node _T_349 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 650:54]
    node _T_350 = and(i_cpu_run_req_sync, _T_349) @[el2_dec_tlu_ctl.scala 650:52]
    node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 650:77]
    node _T_352 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 650:101]
    node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[el2_dec_tlu_ctl.scala 650:99]
    reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 652:80]
    i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[el2_dec_tlu_ctl.scala 652:80]
    reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 653:72]
    i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[el2_dec_tlu_ctl.scala 653:72]
    reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 654:73]
    _T_353 <= cpu_halt_status @[el2_dec_tlu_ctl.scala 654:73]
    io.o_cpu_halt_status <= _T_353 @[el2_dec_tlu_ctl.scala 654:41]
    reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 655:81]
    _T_354 <= cpu_halt_ack @[el2_dec_tlu_ctl.scala 655:81]
    io.o_cpu_halt_ack <= _T_354 @[el2_dec_tlu_ctl.scala 655:49]
    reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 656:81]
    _T_355 <= cpu_run_ack @[el2_dec_tlu_ctl.scala 656:81]
    io.o_cpu_run_ack <= _T_355 @[el2_dec_tlu_ctl.scala 656:49]
    reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 657:66]
    internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[el2_dec_tlu_ctl.scala 657:66]
    reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 658:73]
    _T_356 <= pmu_fw_halt_req_ns @[el2_dec_tlu_ctl.scala 658:73]
    pmu_fw_halt_req_f <= _T_356 @[el2_dec_tlu_ctl.scala 658:41]
    reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 659:73]
    _T_357 <= pmu_fw_tlu_halted @[el2_dec_tlu_ctl.scala 659:73]
    pmu_fw_tlu_halted_f <= _T_357 @[el2_dec_tlu_ctl.scala 659:41]
    reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 660:65]
    _T_358 <= int_timer0_int_hold @[el2_dec_tlu_ctl.scala 660:65]
    int_timer0_int_hold_f <= _T_358 @[el2_dec_tlu_ctl.scala 660:33]
    reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 661:65]
    _T_359 <= int_timer1_int_hold @[el2_dec_tlu_ctl.scala 661:65]
    int_timer1_int_hold_f <= _T_359 @[el2_dec_tlu_ctl.scala 661:33]
    node _T_360 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 665:51]
    node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[el2_dec_tlu_ctl.scala 665:49]
    node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[el2_dec_tlu_ctl.scala 666:47]
    node _T_361 = not(pmu_fw_tlu_halted) @[el2_dec_tlu_ctl.scala 667:71]
    node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[el2_dec_tlu_ctl.scala 667:69]
    node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[el2_dec_tlu_ctl.scala 667:48]
    node _T_364 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 667:94]
    node _T_365 = and(_T_363, _T_364) @[el2_dec_tlu_ctl.scala 667:92]
    pmu_fw_halt_req_ns <= _T_365 @[el2_dec_tlu_ctl.scala 667:22]
    node _T_366 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 668:84]
    node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[el2_dec_tlu_ctl.scala 668:82]
    node _T_368 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 668:104]
    node _T_369 = and(_T_367, _T_368) @[el2_dec_tlu_ctl.scala 668:102]
    node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[el2_dec_tlu_ctl.scala 668:51]
    internal_pmu_fw_halt_mode <= _T_370 @[el2_dec_tlu_ctl.scala 668:29]
    node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 671:44]
    node _T_372 = and(_T_371, halt_taken) @[el2_dec_tlu_ctl.scala 671:57]
    node _T_373 = not(enter_debug_halt_req) @[el2_dec_tlu_ctl.scala 671:72]
    node _T_374 = and(_T_372, _T_373) @[el2_dec_tlu_ctl.scala 671:70]
    node _T_375 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 671:120]
    node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[el2_dec_tlu_ctl.scala 671:118]
    node _T_377 = or(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 671:95]
    node _T_378 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 671:142]
    node _T_379 = and(_T_377, _T_378) @[el2_dec_tlu_ctl.scala 671:140]
    pmu_fw_tlu_halted <= _T_379 @[el2_dec_tlu_ctl.scala 671:21]
    node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 673:37]
    cpu_halt_ack <= _T_380 @[el2_dec_tlu_ctl.scala 673:16]
    node _T_381 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:45]
    node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[el2_dec_tlu_ctl.scala 674:43]
    node _T_383 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:90]
    node _T_384 = and(io.o_cpu_halt_status, _T_383) @[el2_dec_tlu_ctl.scala 674:88]
    node _T_385 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 674:110]
    node _T_386 = and(_T_384, _T_385) @[el2_dec_tlu_ctl.scala 674:108]
    node _T_387 = or(_T_382, _T_386) @[el2_dec_tlu_ctl.scala 674:64]
    cpu_halt_status <= _T_387 @[el2_dec_tlu_ctl.scala 674:19]
    node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:40]
    node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:87]
    node _T_390 = or(_T_388, _T_389) @[el2_dec_tlu_ctl.scala 675:67]
    cpu_run_ack <= _T_390 @[el2_dec_tlu_ctl.scala 675:15]
    io.o_debug_mode_status <= debug_mode_status @[el2_dec_tlu_ctl.scala 677:26]
    node _T_391 = or(nmi_int_detected, timer_int_ready) @[el2_dec_tlu_ctl.scala 680:65]
    node _T_392 = or(_T_391, soft_int_ready) @[el2_dec_tlu_ctl.scala 680:83]
    node _T_393 = or(_T_392, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 680:100]
    node _T_394 = or(_T_393, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 680:124]
    node _T_395 = and(io.mhwakeup, mhwakeup_ready) @[el2_dec_tlu_ctl.scala 680:163]
    node _T_396 = or(_T_394, _T_395) @[el2_dec_tlu_ctl.scala 680:148]
    node _T_397 = and(_T_396, io.o_cpu_halt_status) @[el2_dec_tlu_ctl.scala 680:182]
    node _T_398 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 680:207]
    node _T_399 = and(_T_397, _T_398) @[el2_dec_tlu_ctl.scala 680:205]
    node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[el2_dec_tlu_ctl.scala 680:44]
    i_cpu_run_req_d1 <= _T_400 @[el2_dec_tlu_ctl.scala 680:20]
    reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 686:89]
    _T_401 <= mdseac_locked_ns @[el2_dec_tlu_ctl.scala 686:89]
    mdseac_locked_f <= _T_401 @[el2_dec_tlu_ctl.scala 686:57]
    reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 687:64]
    lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[el2_dec_tlu_ctl.scala 687:64]
    node _T_402 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 689:56]
    node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[el2_dec_tlu_ctl.scala 689:54]
    lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 690:20]
    node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[el2_dec_tlu_ctl.scala 691:39]
    node _T_404 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 691:63]
    node _T_405 = and(_T_403, _T_404) @[el2_dec_tlu_ctl.scala 691:61]
    node _T_406 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 691:83]
    node lsu_exc_valid_r = and(_T_405, _T_406) @[el2_dec_tlu_ctl.scala 691:81]
    reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 693:74]
    _T_407 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 693:74]
    lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41]
    reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73]
    lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73]
    node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 695:39]
    node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37]
    node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 696:37]
    node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 697:37]
    node _T_409 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 701:48]
    node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[el2_dec_tlu_ctl.scala 701:46]
    node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 701:69]
    node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[el2_dec_tlu_ctl.scala 701:104]
    node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[el2_dec_tlu_ctl.scala 701:66]
    node _T_413 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 704:51]
    node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[el2_dec_tlu_ctl.scala 704:49]
    node _T_415 = not(lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 704:64]
    node _T_416 = and(_T_414, _T_415) @[el2_dec_tlu_ctl.scala 704:62]
    node _T_417 = not(inst_acc_r) @[el2_dec_tlu_ctl.scala 704:81]
    node _T_418 = and(_T_416, _T_417) @[el2_dec_tlu_ctl.scala 704:78]
    node _T_419 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 704:95]
    node _T_420 = and(_T_418, _T_419) @[el2_dec_tlu_ctl.scala 704:93]
    node _T_421 = not(request_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 704:120]
    node _T_422 = and(_T_420, _T_421) @[el2_dec_tlu_ctl.scala 704:118]
    node _T_423 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 704:147]
    node tlu_i0_commit_cmt = and(_T_422, _T_423) @[el2_dec_tlu_ctl.scala 704:145]
    node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 707:37]
    node _T_425 = or(_T_424, inst_acc_r) @[el2_dec_tlu_ctl.scala 707:52]
    node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 707:78]
    node _T_427 = or(_T_425, _T_426) @[el2_dec_tlu_ctl.scala 707:65]
    node _T_428 = or(_T_427, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 707:103]
    tlu_i0_kill_writeb_r <= _T_428 @[el2_dec_tlu_ctl.scala 707:24]
    io.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 708:28]
    node _T_429 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 713:43]
    node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[el2_dec_tlu_ctl.scala 713:41]
    node _T_431 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 713:89]
    node _T_432 = and(_T_430, _T_431) @[el2_dec_tlu_ctl.scala 713:65]
    node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 713:137]
    node _T_434 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 713:158]
    node _T_435 = and(_T_433, _T_434) @[el2_dec_tlu_ctl.scala 713:156]
    node _T_436 = or(_T_432, _T_435) @[el2_dec_tlu_ctl.scala 713:120]
    node _T_437 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 713:182]
    node _T_438 = and(_T_436, _T_437) @[el2_dec_tlu_ctl.scala 713:179]
    node _T_439 = not(lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 713:203]
    node _T_440 = and(_T_438, _T_439) @[el2_dec_tlu_ctl.scala 713:200]
    rfpc_i0_r <= _T_440 @[el2_dec_tlu_ctl.scala 713:13]
    node _T_441 = not(io.dec_tlu_flush_lower_r) @[el2_dec_tlu_ctl.scala 716:69]
    node _T_442 = and(iccm_repair_state_d1, _T_441) @[el2_dec_tlu_ctl.scala 716:67]
    node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[el2_dec_tlu_ctl.scala 716:43]
    iccm_repair_state_ns <= _T_443 @[el2_dec_tlu_ctl.scala 716:24]
    node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[el2_dec_tlu_ctl.scala 722:51]
    node _T_445 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 722:87]
    node _T_446 = or(_T_445, mret_r) @[el2_dec_tlu_ctl.scala 722:97]
    node _T_447 = or(_T_446, take_reset) @[el2_dec_tlu_ctl.scala 722:106]
    node _T_448 = or(_T_447, illegal_r) @[el2_dec_tlu_ctl.scala 722:119]
    node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 722:175]
    node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[el2_dec_tlu_ctl.scala 722:152]
    node _T_451 = or(_T_448, _T_450) @[el2_dec_tlu_ctl.scala 722:131]
    node _T_452 = not(_T_451) @[el2_dec_tlu_ctl.scala 722:76]
    node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[el2_dec_tlu_ctl.scala 722:74]
    node _T_453 = and(io.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 725:50]
    node _T_454 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 725:76]
    node dec_tlu_br0_error_r = and(_T_453, _T_454) @[el2_dec_tlu_ctl.scala 725:74]
    node _T_455 = and(io.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 726:62]
    node _T_456 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 726:88]
    node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[el2_dec_tlu_ctl.scala 726:86]
    node _T_457 = and(io.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 727:46]
    node _T_458 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 727:72]
    node _T_459 = and(_T_457, _T_458) @[el2_dec_tlu_ctl.scala 727:70]
    node _T_460 = not(io.exu_i0_br_mp_r) @[el2_dec_tlu_ctl.scala 727:97]
    node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118]
    node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116]
    node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94]
    io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57]
    io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49]
    io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49]
    io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49]
    io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57]
    io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57]
    node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51]
    node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64]
    node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90]
    node _T_466 = and(_T_464, _T_465) @[el2_dec_tlu_ctl.scala 738:88]
    node _T_467 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 738:115]
    node _T_468 = not(_T_467) @[el2_dec_tlu_ctl.scala 738:110]
    node _T_469 = and(_T_466, _T_468) @[el2_dec_tlu_ctl.scala 738:108]
    node _T_470 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 738:132]
    node _T_471 = and(_T_469, _T_470) @[el2_dec_tlu_ctl.scala 738:130]
    ebreak_r <= _T_471 @[el2_dec_tlu_ctl.scala 738:13]
    node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 739:51]
    node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 739:64]
    node _T_474 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 739:90]
    node _T_475 = and(_T_473, _T_474) @[el2_dec_tlu_ctl.scala 739:88]
    node _T_476 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 739:110]
    node _T_477 = and(_T_475, _T_476) @[el2_dec_tlu_ctl.scala 739:108]
    ecall_r <= _T_477 @[el2_dec_tlu_ctl.scala 739:13]
    node _T_478 = not(io.dec_tlu_packet_r.legal) @[el2_dec_tlu_ctl.scala 740:17]
    node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 740:46]
    node _T_480 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 740:72]
    node _T_481 = and(_T_479, _T_480) @[el2_dec_tlu_ctl.scala 740:70]
    node _T_482 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 740:92]
    node _T_483 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 740:90]
    illegal_r <= _T_483 @[el2_dec_tlu_ctl.scala 740:13]
    node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 741:51]
    node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 741:64]
    node _T_486 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 741:90]
    node _T_487 = and(_T_485, _T_486) @[el2_dec_tlu_ctl.scala 741:88]
    node _T_488 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 741:110]
    node _T_489 = and(_T_487, _T_488) @[el2_dec_tlu_ctl.scala 741:108]
    mret_r <= _T_489 @[el2_dec_tlu_ctl.scala 741:13]
    node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 743:49]
    node _T_491 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 743:75]
    node _T_492 = and(_T_490, _T_491) @[el2_dec_tlu_ctl.scala 743:73]
    node _T_493 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 743:96]
    node _T_494 = and(_T_492, _T_493) @[el2_dec_tlu_ctl.scala 743:94]
    fence_i_r <= _T_494 @[el2_dec_tlu_ctl.scala 743:16]
    node _T_495 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 744:44]
    node _T_496 = and(io.ifu_ic_error_start, _T_495) @[el2_dec_tlu_ctl.scala 744:42]
    node _T_497 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 744:66]
    node _T_498 = or(_T_497, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 744:92]
    node _T_499 = and(_T_496, _T_498) @[el2_dec_tlu_ctl.scala 744:63]
    node _T_500 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 744:122]
    node _T_501 = and(_T_499, _T_500) @[el2_dec_tlu_ctl.scala 744:120]
    ic_perr_r <= _T_501 @[el2_dec_tlu_ctl.scala 744:16]
    node _T_502 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 745:52]
    node _T_503 = and(io.ifu_iccm_rd_ecc_single_err, _T_502) @[el2_dec_tlu_ctl.scala 745:50]
    node _T_504 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 745:74]
    node _T_505 = or(_T_504, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 745:100]
    node _T_506 = and(_T_503, _T_505) @[el2_dec_tlu_ctl.scala 745:71]
    node _T_507 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 745:130]
    node _T_508 = and(_T_506, _T_507) @[el2_dec_tlu_ctl.scala 745:128]
    iccm_sbecc_r <= _T_508 @[el2_dec_tlu_ctl.scala 745:16]
    node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 746:48]
    inst_acc_r_raw <= _T_509 @[el2_dec_tlu_ctl.scala 746:19]
    node _T_510 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 747:34]
    node _T_511 = and(inst_acc_r_raw, _T_510) @[el2_dec_tlu_ctl.scala 747:32]
    node _T_512 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 747:47]
    node _T_513 = and(_T_511, _T_512) @[el2_dec_tlu_ctl.scala 747:45]
    inst_acc_r <= _T_513 @[el2_dec_tlu_ctl.scala 747:14]
    node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 750:63]
    node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 750:76]
    node _T_516 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 750:102]
    node _T_517 = and(_T_515, _T_516) @[el2_dec_tlu_ctl.scala 750:100]
    node _T_518 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 750:126]
    node _T_519 = and(_T_517, _T_518) @[el2_dec_tlu_ctl.scala 750:120]
    node _T_520 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 750:143]
    node _T_521 = and(_T_519, _T_520) @[el2_dec_tlu_ctl.scala 750:141]
    ebreak_to_debug_mode_r <= _T_521 @[el2_dec_tlu_ctl.scala 750:26]
    reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 752:58]
    _T_522 <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 752:58]
    ebreak_to_debug_mode_r_d1 <= _T_522 @[el2_dec_tlu_ctl.scala 752:28]
    io.dec_tlu_fence_i_r <= fence_i_r @[el2_dec_tlu_ctl.scala 753:24]
    node _T_523 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 766:40]
    node _T_524 = or(_T_523, illegal_r) @[el2_dec_tlu_ctl.scala 766:50]
    node _T_525 = or(_T_524, inst_acc_r) @[el2_dec_tlu_ctl.scala 766:62]
    node _T_526 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 766:78]
    node _T_527 = and(_T_525, _T_526) @[el2_dec_tlu_ctl.scala 766:76]
    node _T_528 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 766:91]
    node i0_exception_valid_r = and(_T_527, _T_528) @[el2_dec_tlu_ctl.scala 766:89]
    node _T_529 = not(take_nmi) @[el2_dec_tlu_ctl.scala 775:21]
    node _T_530 = and(take_ext_int, _T_529) @[el2_dec_tlu_ctl.scala 775:19]
    node _T_531 = bits(_T_530, 0, 0) @[el2_dec_tlu_ctl.scala 775:32]
    node _T_532 = not(take_nmi) @[el2_dec_tlu_ctl.scala 776:23]
    node _T_533 = and(take_timer_int, _T_532) @[el2_dec_tlu_ctl.scala 776:21]
    node _T_534 = bits(_T_533, 0, 0) @[el2_dec_tlu_ctl.scala 776:34]
    node _T_535 = not(take_nmi) @[el2_dec_tlu_ctl.scala 777:22]
    node _T_536 = and(take_soft_int, _T_535) @[el2_dec_tlu_ctl.scala 777:20]
    node _T_537 = bits(_T_536, 0, 0) @[el2_dec_tlu_ctl.scala 777:33]
    node _T_538 = not(take_nmi) @[el2_dec_tlu_ctl.scala 778:28]
    node _T_539 = and(take_int_timer0_int, _T_538) @[el2_dec_tlu_ctl.scala 778:26]
    node _T_540 = bits(_T_539, 0, 0) @[el2_dec_tlu_ctl.scala 778:39]
    node _T_541 = not(take_nmi) @[el2_dec_tlu_ctl.scala 779:28]
    node _T_542 = and(take_int_timer1_int, _T_541) @[el2_dec_tlu_ctl.scala 779:26]
    node _T_543 = bits(_T_542, 0, 0) @[el2_dec_tlu_ctl.scala 779:39]
    node _T_544 = not(take_nmi) @[el2_dec_tlu_ctl.scala 780:20]
    node _T_545 = and(take_ce_int, _T_544) @[el2_dec_tlu_ctl.scala 780:18]
    node _T_546 = bits(_T_545, 0, 0) @[el2_dec_tlu_ctl.scala 780:31]
    node _T_547 = not(take_nmi) @[el2_dec_tlu_ctl.scala 781:18]
    node _T_548 = and(illegal_r, _T_547) @[el2_dec_tlu_ctl.scala 781:16]
    node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 781:29]
    node _T_550 = not(take_nmi) @[el2_dec_tlu_ctl.scala 782:17]
    node _T_551 = and(ecall_r, _T_550) @[el2_dec_tlu_ctl.scala 782:15]
    node _T_552 = bits(_T_551, 0, 0) @[el2_dec_tlu_ctl.scala 782:28]
    node _T_553 = not(take_nmi) @[el2_dec_tlu_ctl.scala 783:20]
    node _T_554 = and(inst_acc_r, _T_553) @[el2_dec_tlu_ctl.scala 783:18]
    node _T_555 = bits(_T_554, 0, 0) @[el2_dec_tlu_ctl.scala 783:31]
    node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 784:16]
    node _T_557 = not(take_nmi) @[el2_dec_tlu_ctl.scala 784:38]
    node _T_558 = and(_T_556, _T_557) @[el2_dec_tlu_ctl.scala 784:36]
    node _T_559 = bits(_T_558, 0, 0) @[el2_dec_tlu_ctl.scala 784:49]
    node _T_560 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 785:21]
    node _T_561 = and(lsu_exc_ma_r, _T_560) @[el2_dec_tlu_ctl.scala 785:19]
    node _T_562 = not(take_nmi) @[el2_dec_tlu_ctl.scala 785:37]
    node _T_563 = and(_T_561, _T_562) @[el2_dec_tlu_ctl.scala 785:35]
    node _T_564 = bits(_T_563, 0, 0) @[el2_dec_tlu_ctl.scala 785:48]
    node _T_565 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 786:22]
    node _T_566 = and(lsu_exc_acc_r, _T_565) @[el2_dec_tlu_ctl.scala 786:20]
    node _T_567 = not(take_nmi) @[el2_dec_tlu_ctl.scala 786:38]
    node _T_568 = and(_T_566, _T_567) @[el2_dec_tlu_ctl.scala 786:36]
    node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 786:49]
    node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 787:19]
    node _T_571 = not(take_nmi) @[el2_dec_tlu_ctl.scala 787:36]
    node _T_572 = and(_T_570, _T_571) @[el2_dec_tlu_ctl.scala 787:34]
    node _T_573 = bits(_T_572, 0, 0) @[el2_dec_tlu_ctl.scala 787:47]
    node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 788:20]
    node _T_575 = not(take_nmi) @[el2_dec_tlu_ctl.scala 788:37]
    node _T_576 = and(_T_574, _T_575) @[el2_dec_tlu_ctl.scala 788:35]
    node _T_577 = bits(_T_576, 0, 0) @[el2_dec_tlu_ctl.scala 788:48]
    node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_581 = mux(_T_540, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_582 = mux(_T_543, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_583 = mux(_T_546, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_584 = mux(_T_549, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_585 = mux(_T_552, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_586 = mux(_T_555, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_587 = mux(_T_559, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_588 = mux(_T_564, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_589 = mux(_T_569, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_590 = mux(_T_573, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_591 = mux(_T_577, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_592 = or(_T_578, _T_579) @[Mux.scala 27:72]
    node _T_593 = or(_T_592, _T_580) @[Mux.scala 27:72]
    node _T_594 = or(_T_593, _T_581) @[Mux.scala 27:72]
    node _T_595 = or(_T_594, _T_582) @[Mux.scala 27:72]
    node _T_596 = or(_T_595, _T_583) @[Mux.scala 27:72]
    node _T_597 = or(_T_596, _T_584) @[Mux.scala 27:72]
    node _T_598 = or(_T_597, _T_585) @[Mux.scala 27:72]
    node _T_599 = or(_T_598, _T_586) @[Mux.scala 27:72]
    node _T_600 = or(_T_599, _T_587) @[Mux.scala 27:72]
    node _T_601 = or(_T_600, _T_588) @[Mux.scala 27:72]
    node _T_602 = or(_T_601, _T_589) @[Mux.scala 27:72]
    node _T_603 = or(_T_602, _T_590) @[Mux.scala 27:72]
    node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72]
    wire exc_cause_r : UInt<5> @[Mux.scala 27:72]
    exc_cause_r <= _T_604 @[Mux.scala 27:72]
    node _T_605 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 799:23]
    node _T_606 = and(_T_605, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 799:48]
    node _T_607 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 799:70]
    node _T_608 = and(_T_606, _T_607) @[el2_dec_tlu_ctl.scala 799:65]
    node _T_609 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 799:91]
    node _T_610 = and(_T_608, _T_609) @[el2_dec_tlu_ctl.scala 799:83]
    mhwakeup_ready <= _T_610 @[el2_dec_tlu_ctl.scala 799:19]
    node _T_611 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 800:22]
    node _T_612 = and(_T_611, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 800:47]
    node _T_613 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 800:69]
    node _T_614 = and(_T_612, _T_613) @[el2_dec_tlu_ctl.scala 800:64]
    node _T_615 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 800:90]
    node _T_616 = and(_T_614, _T_615) @[el2_dec_tlu_ctl.scala 800:82]
    node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[el2_dec_tlu_ctl.scala 800:103]
    node _T_618 = and(_T_616, _T_617) @[el2_dec_tlu_ctl.scala 800:101]
    ext_int_ready <= _T_618 @[el2_dec_tlu_ctl.scala 800:19]
    node _T_619 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 801:22]
    node _T_620 = and(_T_619, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 801:47]
    node _T_621 = bits(mip, 5, 5) @[el2_dec_tlu_ctl.scala 801:69]
    node _T_622 = and(_T_620, _T_621) @[el2_dec_tlu_ctl.scala 801:64]
    node _T_623 = bits(mie_ns, 5, 5) @[el2_dec_tlu_ctl.scala 801:90]
    node _T_624 = and(_T_622, _T_623) @[el2_dec_tlu_ctl.scala 801:82]
    ce_int_ready <= _T_624 @[el2_dec_tlu_ctl.scala 801:19]
    node _T_625 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 802:22]
    node _T_626 = and(_T_625, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 802:47]
    node _T_627 = bits(mip, 0, 0) @[el2_dec_tlu_ctl.scala 802:69]
    node _T_628 = and(_T_626, _T_627) @[el2_dec_tlu_ctl.scala 802:64]
    node _T_629 = bits(mie_ns, 0, 0) @[el2_dec_tlu_ctl.scala 802:90]
    node _T_630 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 802:82]
    soft_int_ready <= _T_630 @[el2_dec_tlu_ctl.scala 802:19]
    node _T_631 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 803:22]
    node _T_632 = and(_T_631, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 803:47]
    node _T_633 = bits(mip, 1, 1) @[el2_dec_tlu_ctl.scala 803:69]
    node _T_634 = and(_T_632, _T_633) @[el2_dec_tlu_ctl.scala 803:64]
    node _T_635 = bits(mie_ns, 1, 1) @[el2_dec_tlu_ctl.scala 803:90]
    node _T_636 = and(_T_634, _T_635) @[el2_dec_tlu_ctl.scala 803:82]
    timer_int_ready <= _T_636 @[el2_dec_tlu_ctl.scala 803:19]
    node _T_637 = bits(mie_ns, 4, 4) @[el2_dec_tlu_ctl.scala 806:56]
    node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[el2_dec_tlu_ctl.scala 806:48]
    node _T_638 = bits(mip, 4, 4) @[el2_dec_tlu_ctl.scala 807:33]
    node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 807:46]
    node _T_639 = bits(mie_ns, 3, 3) @[el2_dec_tlu_ctl.scala 808:56]
    node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[el2_dec_tlu_ctl.scala 808:48]
    node _T_640 = bits(mip, 3, 3) @[el2_dec_tlu_ctl.scala 809:33]
    node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 809:46]
    node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 813:51]
    node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 813:73]
    node int_timer_stalled = or(_T_642, mret_r) @[el2_dec_tlu_ctl.scala 813:97]
    node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 815:71]
    node _T_644 = and(int_timer0_int_ready, _T_643) @[el2_dec_tlu_ctl.scala 815:48]
    node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 815:120]
    node _T_646 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 815:146]
    node _T_647 = and(_T_645, _T_646) @[el2_dec_tlu_ctl.scala 815:144]
    node _T_648 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 815:167]
    node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 815:165]
    node _T_650 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 815:189]
    node _T_651 = and(_T_649, _T_650) @[el2_dec_tlu_ctl.scala 815:187]
    node _T_652 = or(_T_644, _T_651) @[el2_dec_tlu_ctl.scala 815:93]
    int_timer0_int_hold <= _T_652 @[el2_dec_tlu_ctl.scala 815:23]
    node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 816:71]
    node _T_654 = and(int_timer1_int_ready, _T_653) @[el2_dec_tlu_ctl.scala 816:48]
    node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 816:120]
    node _T_656 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 816:146]
    node _T_657 = and(_T_655, _T_656) @[el2_dec_tlu_ctl.scala 816:144]
    node _T_658 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 816:167]
    node _T_659 = and(_T_657, _T_658) @[el2_dec_tlu_ctl.scala 816:165]
    node _T_660 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 816:189]
    node _T_661 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 816:187]
    node _T_662 = or(_T_654, _T_661) @[el2_dec_tlu_ctl.scala 816:93]
    int_timer1_int_hold <= _T_662 @[el2_dec_tlu_ctl.scala 816:23]
    node _T_663 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 818:58]
    node _T_664 = and(debug_mode_status, _T_663) @[el2_dec_tlu_ctl.scala 818:56]
    internal_dbg_halt_timers <= _T_664 @[el2_dec_tlu_ctl.scala 818:28]
    node _T_665 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 820:54]
    node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 820:80]
    node _T_667 = and(internal_dbg_halt_mode, _T_666) @[el2_dec_tlu_ctl.scala 820:51]
    node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 820:106]
    node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 820:134]
    node _T_670 = or(_T_669, take_nmi) @[el2_dec_tlu_ctl.scala 820:154]
    node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 820:165]
    node _T_672 = or(_T_671, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 820:190]
    node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 820:213]
    node _T_674 = or(_T_673, mret_r) @[el2_dec_tlu_ctl.scala 820:237]
    node block_interrupts = or(_T_674, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 820:246]
    reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 824:58]
    _T_675 <= take_ext_int_start @[el2_dec_tlu_ctl.scala 824:58]
    take_ext_int_start_d1 <= _T_675 @[el2_dec_tlu_ctl.scala 824:26]
    reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 825:58]
    _T_676 <= take_ext_int_start_d1 @[el2_dec_tlu_ctl.scala 825:58]
    take_ext_int_start_d2 <= _T_676 @[el2_dec_tlu_ctl.scala 825:26]
    reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 826:58]
    _T_677 <= take_ext_int_start_d2 @[el2_dec_tlu_ctl.scala 826:58]
    take_ext_int_start_d3 <= _T_677 @[el2_dec_tlu_ctl.scala 826:26]
    reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 827:58]
    _T_678 <= ext_int_freeze @[el2_dec_tlu_ctl.scala 827:58]
    ext_int_freeze_d1 <= _T_678 @[el2_dec_tlu_ctl.scala 827:26]
    node _T_679 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 828:43]
    node _T_680 = and(ext_int_ready, _T_679) @[el2_dec_tlu_ctl.scala 828:41]
    take_ext_int_start <= _T_680 @[el2_dec_tlu_ctl.scala 828:24]
    node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 830:42]
    node _T_682 = or(_T_681, take_ext_int_start_d2) @[el2_dec_tlu_ctl.scala 830:66]
    node _T_683 = or(_T_682, take_ext_int_start_d3) @[el2_dec_tlu_ctl.scala 830:90]
    ext_int_freeze <= _T_683 @[el2_dec_tlu_ctl.scala 830:20]
    node _T_684 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 831:63]
    node _T_685 = not(_T_684) @[el2_dec_tlu_ctl.scala 831:45]
    node _T_686 = and(take_ext_int_start_d3, _T_685) @[el2_dec_tlu_ctl.scala 831:43]
    take_ext_int <= _T_686 @[el2_dec_tlu_ctl.scala 831:18]
    node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 832:45]
    fast_int_meicpct <= _T_687 @[el2_dec_tlu_ctl.scala 832:22]
    ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[el2_dec_tlu_ctl.scala 833:37]
    node _T_688 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 846:34]
    node _T_689 = and(ce_int_ready, _T_688) @[el2_dec_tlu_ctl.scala 846:32]
    node _T_690 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 846:51]
    node _T_691 = and(_T_689, _T_690) @[el2_dec_tlu_ctl.scala 846:49]
    take_ce_int <= _T_691 @[el2_dec_tlu_ctl.scala 846:16]
    node _T_692 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 847:37]
    node _T_693 = and(soft_int_ready, _T_692) @[el2_dec_tlu_ctl.scala 847:35]
    node _T_694 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 847:54]
    node _T_695 = and(_T_693, _T_694) @[el2_dec_tlu_ctl.scala 847:52]
    node _T_696 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 847:70]
    node _T_697 = and(_T_695, _T_696) @[el2_dec_tlu_ctl.scala 847:68]
    take_soft_int <= _T_697 @[el2_dec_tlu_ctl.scala 847:17]
    node _T_698 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 848:39]
    node _T_699 = and(timer_int_ready, _T_698) @[el2_dec_tlu_ctl.scala 848:37]
    node _T_700 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 848:57]
    node _T_701 = and(_T_699, _T_700) @[el2_dec_tlu_ctl.scala 848:55]
    node _T_702 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 848:74]
    node _T_703 = and(_T_701, _T_702) @[el2_dec_tlu_ctl.scala 848:72]
    node _T_704 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 848:90]
    node _T_705 = and(_T_703, _T_704) @[el2_dec_tlu_ctl.scala 848:88]
    take_timer_int <= _T_705 @[el2_dec_tlu_ctl.scala 848:18]
    node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 849:48]
    node _T_707 = and(_T_706, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 849:73]
    node _T_708 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 849:101]
    node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 849:99]
    node _T_710 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 849:128]
    node _T_711 = and(_T_709, _T_710) @[el2_dec_tlu_ctl.scala 849:126]
    node _T_712 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 849:147]
    node _T_713 = and(_T_711, _T_712) @[el2_dec_tlu_ctl.scala 849:145]
    node _T_714 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 849:165]
    node _T_715 = and(_T_713, _T_714) @[el2_dec_tlu_ctl.scala 849:163]
    node _T_716 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 849:182]
    node _T_717 = and(_T_715, _T_716) @[el2_dec_tlu_ctl.scala 849:180]
    node _T_718 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 849:198]
    node _T_719 = and(_T_717, _T_718) @[el2_dec_tlu_ctl.scala 849:196]
    take_int_timer0_int <= _T_719 @[el2_dec_tlu_ctl.scala 849:23]
    node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 850:48]
    node _T_721 = and(_T_720, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 850:73]
    node _T_722 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 850:101]
    node _T_723 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 850:99]
    node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 850:151]
    node _T_725 = not(_T_724) @[el2_dec_tlu_ctl.scala 850:128]
    node _T_726 = and(_T_723, _T_725) @[el2_dec_tlu_ctl.scala 850:126]
    node _T_727 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 850:178]
    node _T_728 = and(_T_726, _T_727) @[el2_dec_tlu_ctl.scala 850:176]
    node _T_729 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 850:197]
    node _T_730 = and(_T_728, _T_729) @[el2_dec_tlu_ctl.scala 850:195]
    node _T_731 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 850:215]
    node _T_732 = and(_T_730, _T_731) @[el2_dec_tlu_ctl.scala 850:213]
    node _T_733 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 850:232]
    node _T_734 = and(_T_732, _T_733) @[el2_dec_tlu_ctl.scala 850:230]
    node _T_735 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 850:248]
    node _T_736 = and(_T_734, _T_735) @[el2_dec_tlu_ctl.scala 850:246]
    take_int_timer1_int <= _T_736 @[el2_dec_tlu_ctl.scala 850:23]
    node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 851:31]
    take_reset <= _T_737 @[el2_dec_tlu_ctl.scala 851:14]
    node _T_738 = not(internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 852:34]
    node _T_739 = and(nmi_int_detected, _T_738) @[el2_dec_tlu_ctl.scala 852:32]
    node _T_740 = not(internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 852:64]
    node _T_741 = bits(dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 852:124]
    node _T_742 = and(dcsr_single_step_running_f, _T_741) @[el2_dec_tlu_ctl.scala 852:118]
    node _T_743 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 852:140]
    node _T_744 = and(_T_742, _T_743) @[el2_dec_tlu_ctl.scala 852:138]
    node _T_745 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 852:165]
    node _T_746 = and(_T_744, _T_745) @[el2_dec_tlu_ctl.scala 852:163]
    node _T_747 = or(_T_740, _T_746) @[el2_dec_tlu_ctl.scala 852:88]
    node _T_748 = and(_T_739, _T_747) @[el2_dec_tlu_ctl.scala 852:61]
    node _T_749 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 852:194]
    node _T_750 = and(_T_748, _T_749) @[el2_dec_tlu_ctl.scala 852:192]
    node _T_751 = not(mret_r) @[el2_dec_tlu_ctl.scala 852:217]
    node _T_752 = and(_T_750, _T_751) @[el2_dec_tlu_ctl.scala 852:215]
    node _T_753 = not(take_reset) @[el2_dec_tlu_ctl.scala 852:227]
    node _T_754 = and(_T_752, _T_753) @[el2_dec_tlu_ctl.scala 852:225]
    node _T_755 = not(ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 852:241]
    node _T_756 = and(_T_754, _T_755) @[el2_dec_tlu_ctl.scala 852:239]
    node _T_757 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 852:268]
    node _T_758 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 852:331]
    node _T_759 = and(take_ext_int_start_d3, _T_758) @[el2_dec_tlu_ctl.scala 852:312]
    node _T_760 = or(_T_757, _T_759) @[el2_dec_tlu_ctl.scala 852:287]
    node _T_761 = and(_T_756, _T_760) @[el2_dec_tlu_ctl.scala 852:265]
    take_nmi <= _T_761 @[el2_dec_tlu_ctl.scala 852:12]
    node _T_762 = or(take_ext_int, take_timer_int) @[el2_dec_tlu_ctl.scala 855:37]
    node _T_763 = or(_T_762, take_soft_int) @[el2_dec_tlu_ctl.scala 855:54]
    node _T_764 = or(_T_763, take_nmi) @[el2_dec_tlu_ctl.scala 855:70]
    node _T_765 = or(_T_764, take_ce_int) @[el2_dec_tlu_ctl.scala 855:81]
    node _T_766 = or(_T_765, take_int_timer0_int) @[el2_dec_tlu_ctl.scala 855:95]
    node _T_767 = or(_T_766, take_int_timer1_int) @[el2_dec_tlu_ctl.scala 855:117]
    interrupt_valid_r <= _T_767 @[el2_dec_tlu_ctl.scala 855:21]
    node _T_768 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 860:33]
    node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58]
    node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_772 = add(_T_769, _T_771) @[el2_dec_tlu_ctl.scala 860:50]
    node vectored_path = tail(_T_772, 1) @[el2_dec_tlu_ctl.scala 860:50]
    node _T_773 = bits(take_nmi, 0, 0) @[el2_dec_tlu_ctl.scala 861:37]
    node _T_774 = bits(mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 861:66]
    node _T_775 = eq(_T_774, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 861:70]
    node _T_776 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 861:103]
    node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_778 = mux(_T_775, vectored_path, _T_777) @[el2_dec_tlu_ctl.scala 861:60]
    node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[el2_dec_tlu_ctl.scala 861:27]
    node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[el2_dec_tlu_ctl.scala 862:35]
    node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 862:47]
    node _T_781 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 862:95]
    node _T_782 = and(i_cpu_run_req_d1, _T_781) @[el2_dec_tlu_ctl.scala 862:93]
    node _T_783 = or(_T_780, _T_782) @[el2_dec_tlu_ctl.scala 862:73]
    node _T_784 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 862:130]
    node _T_785 = and(rfpc_i0_r, _T_784) @[el2_dec_tlu_ctl.scala 862:128]
    node sel_npc_r = or(_T_783, _T_785) @[el2_dec_tlu_ctl.scala 862:115]
    node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 863:42]
    node sel_npc_resume = or(_T_786, pause_expired_r) @[el2_dec_tlu_ctl.scala 863:65]
    node _T_787 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 864:64]
    node _T_788 = not(_T_787) @[el2_dec_tlu_ctl.scala 864:46]
    node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[el2_dec_tlu_ctl.scala 864:44]
    node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[el2_dec_tlu_ctl.scala 865:48]
    node _T_790 = or(_T_789, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 865:60]
    node _T_791 = or(_T_790, fence_i_r) @[el2_dec_tlu_ctl.scala 865:78]
    node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 865:90]
    node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 865:107]
    node _T_794 = or(_T_793, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 865:134]
    node _T_795 = or(_T_794, sel_npc_resume) @[el2_dec_tlu_ctl.scala 865:156]
    node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[el2_dec_tlu_ctl.scala 865:174]
    node _T_797 = or(_T_796, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 865:200]
    synchronous_flush_r <= _T_797 @[el2_dec_tlu_ctl.scala 865:24]
    node _T_798 = or(interrupt_valid_r, mret_r) @[el2_dec_tlu_ctl.scala 866:42]
    node _T_799 = or(_T_798, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 866:51]
    node _T_800 = or(_T_799, take_halt) @[el2_dec_tlu_ctl.scala 866:73]
    node _T_801 = or(_T_800, take_reset) @[el2_dec_tlu_ctl.scala 866:85]
    node _T_802 = or(_T_801, take_ext_int_start) @[el2_dec_tlu_ctl.scala 866:98]
    tlu_flush_lower_r <= _T_802 @[el2_dec_tlu_ctl.scala 866:21]
    node _T_803 = bits(take_reset, 0, 0) @[el2_dec_tlu_ctl.scala 868:41]
    node _T_804 = bits(sel_fir_addr, 0, 0) @[el2_dec_tlu_ctl.scala 869:20]
    node _T_805 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 870:14]
    node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 870:32]
    node _T_807 = and(_T_805, _T_806) @[el2_dec_tlu_ctl.scala 870:21]
    node _T_808 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:14]
    node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:32]
    node _T_810 = and(_T_808, _T_809) @[el2_dec_tlu_ctl.scala 871:21]
    node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:62]
    node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 871:39]
    node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:80]
    node _T_814 = and(_T_812, _T_813) @[el2_dec_tlu_ctl.scala 871:69]
    node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 872:23]
    node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 872:44]
    node _T_817 = and(_T_815, _T_816) @[el2_dec_tlu_ctl.scala 872:30]
    node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 873:28]
    node _T_819 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 873:68]
    node _T_820 = and(i0_trigger_hit_r, _T_819) @[el2_dec_tlu_ctl.scala 873:66]
    node _T_821 = or(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 873:46]
    node _T_822 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 873:93]
    node _T_823 = and(_T_821, _T_822) @[el2_dec_tlu_ctl.scala 873:91]
    node _T_824 = not(sel_fir_addr) @[el2_dec_tlu_ctl.scala 873:114]
    node _T_825 = and(_T_823, _T_824) @[el2_dec_tlu_ctl.scala 873:112]
    node _T_826 = bits(_T_825, 0, 0) @[el2_dec_tlu_ctl.scala 873:129]
    node _T_827 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 873:149]
    node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_829 = not(take_nmi) @[el2_dec_tlu_ctl.scala 874:6]
    node _T_830 = and(_T_829, mret_r) @[el2_dec_tlu_ctl.scala 874:16]
    node _T_831 = bits(_T_830, 0, 0) @[el2_dec_tlu_ctl.scala 874:26]
    node _T_832 = not(take_nmi) @[el2_dec_tlu_ctl.scala 875:6]
    node _T_833 = and(_T_832, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 875:16]
    node _T_834 = bits(_T_833, 0, 0) @[el2_dec_tlu_ctl.scala 875:38]
    node _T_835 = not(take_nmi) @[el2_dec_tlu_ctl.scala 876:6]
    node _T_836 = and(_T_835, sel_npc_resume) @[el2_dec_tlu_ctl.scala 876:16]
    node _T_837 = bits(_T_836, 0, 0) @[el2_dec_tlu_ctl.scala 876:34]
    node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_841 = mux(_T_817, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_842 = mux(_T_826, _T_828, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_843 = mux(_T_831, mepc, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_844 = mux(_T_834, dpc, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_845 = mux(_T_837, npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_846 = or(_T_838, _T_839) @[Mux.scala 27:72]
    node _T_847 = or(_T_846, _T_840) @[Mux.scala 27:72]
    node _T_848 = or(_T_847, _T_841) @[Mux.scala 27:72]
    node _T_849 = or(_T_848, _T_842) @[Mux.scala 27:72]
    node _T_850 = or(_T_849, _T_843) @[Mux.scala 27:72]
    node _T_851 = or(_T_850, _T_844) @[Mux.scala 27:72]
    node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72]
    wire _T_853 : UInt<31> @[Mux.scala 27:72]
    _T_853 <= _T_852 @[Mux.scala 27:72]
    node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[el2_dec_tlu_ctl.scala 868:29]
    reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 879:58]
    tlu_flush_path_r_d1 <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 879:58]
    io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 881:33]
    io.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 882:33]
    io.dec_tlu_flush_path_r <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 883:33]
    node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[el2_dec_tlu_ctl.scala 886:44]
    node _T_855 = or(_T_854, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 886:67]
    node _T_856 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 886:109]
    node _T_857 = and(i0_trigger_hit_r, _T_856) @[el2_dec_tlu_ctl.scala 886:107]
    node exc_or_int_valid_r = or(_T_855, _T_857) @[el2_dec_tlu_ctl.scala 886:87]
    reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 888:82]
    _T_858 <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 888:82]
    interrupt_valid_r_d1 <= _T_858 @[el2_dec_tlu_ctl.scala 888:49]
    reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 889:81]
    i0_exception_valid_r_d1 <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 889:81]
    reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 890:82]
    _T_859 <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 890:82]
    exc_or_int_valid_r_d1 <= _T_859 @[el2_dec_tlu_ctl.scala 890:49]
    reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 891:89]
    exc_cause_wb <= exc_cause_r @[el2_dec_tlu_ctl.scala 891:89]
    node _T_860 = not(illegal_r) @[el2_dec_tlu_ctl.scala 892:119]
    node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[el2_dec_tlu_ctl.scala 892:117]
    reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 892:97]
    i0_valid_wb <= _T_861 @[el2_dec_tlu_ctl.scala 892:97]
    reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 893:81]
    trigger_hit_r_d1 <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 893:81]
    reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 894:90]
    _T_862 <= take_nmi @[el2_dec_tlu_ctl.scala 894:90]
    take_nmi_r_d1 <= _T_862 @[el2_dec_tlu_ctl.scala 894:57]
    reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 895:90]
    _T_863 <= pause_expired_r @[el2_dec_tlu_ctl.scala 895:90]
    pause_expired_wb <= _T_863 @[el2_dec_tlu_ctl.scala 895:57]
    inst csr of csr_tlu @[el2_dec_tlu_ctl.scala 897:17]
    csr.clock <= clock
    csr.reset <= reset
    csr.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 898:44]
    csr.io.active_clk <= io.active_clk @[el2_dec_tlu_ctl.scala 899:44]
    csr.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 900:44]
    csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 901:44]
    csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 902:44]
    csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 903:44]
    csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[el2_dec_tlu_ctl.scala 904:44]
    csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[el2_dec_tlu_ctl.scala 905:44]
    csr.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec_tlu_ctl.scala 906:44]
    csr.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 907:44]
    csr.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec_tlu_ctl.scala 908:44]
    csr.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec_tlu_ctl.scala 909:44]
    csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec_tlu_ctl.scala 910:44]
    csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[el2_dec_tlu_ctl.scala 911:44]
    csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[el2_dec_tlu_ctl.scala 912:44]
    csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[el2_dec_tlu_ctl.scala 913:44]
    csr.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec_tlu_ctl.scala 914:44]
    csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[el2_dec_tlu_ctl.scala 915:44]
    csr.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec_tlu_ctl.scala 916:44]
    csr.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec_tlu_ctl.scala 917:44]
    csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[el2_dec_tlu_ctl.scala 918:44]
    csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec_tlu_ctl.scala 919:44]
    csr.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec_tlu_ctl.scala 920:44]
    csr.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec_tlu_ctl.scala 921:44]
    csr.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec_tlu_ctl.scala 922:44]
    csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[el2_dec_tlu_ctl.scala 923:44]
    csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[el2_dec_tlu_ctl.scala 924:44]
    csr.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec_tlu_ctl.scala 925:44]
    csr.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec_tlu_ctl.scala 926:44]
    csr.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec_tlu_ctl.scala 927:44]
    csr.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec_tlu_ctl.scala 928:44]
    csr.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 929:44]
    csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[el2_dec_tlu_ctl.scala 930:44]
    csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 931:44]
    csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[el2_dec_tlu_ctl.scala 932:44]
    csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[el2_dec_tlu_ctl.scala 933:44]
    csr.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 934:44]
    csr.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec_tlu_ctl.scala 935:44]
    csr.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec_tlu_ctl.scala 936:44]
    csr.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec_tlu_ctl.scala 937:44]
    csr.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 938:44]
    csr.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec_tlu_ctl.scala 939:44]
    csr.io.pic_pl <= io.pic_pl @[el2_dec_tlu_ctl.scala 940:44]
    csr.io.pic_claimid <= io.pic_claimid @[el2_dec_tlu_ctl.scala 941:44]
    csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec_tlu_ctl.scala 942:44]
    csr.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec_tlu_ctl.scala 943:44]
    csr.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec_tlu_ctl.scala 944:44]
    csr.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec_tlu_ctl.scala 945:44]
    csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 946:44]
    csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 947:44]
    csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec_tlu_ctl.scala 947:44]
    csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec_tlu_ctl.scala 947:44]
    csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec_tlu_ctl.scala 947:44]
    csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec_tlu_ctl.scala 947:44]
    csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 947:44]
    csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 948:44]
    csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 949:44]
    csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 950:44]
    csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 951:44]
    csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 952:44]
    csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 953:44]
    csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 954:44]
    io.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[el2_dec_tlu_ctl.scala 955:44]
    io.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[el2_dec_tlu_ctl.scala 956:44]
    io.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[el2_dec_tlu_ctl.scala 957:44]
    io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[el2_dec_tlu_ctl.scala 958:44]
    io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec_tlu_ctl.scala 959:44]
    io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[el2_dec_tlu_ctl.scala 960:44]
    io.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec_tlu_ctl.scala 961:44]
    io.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec_tlu_ctl.scala 961:44]
    io.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec_tlu_ctl.scala 961:44]
    io.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec_tlu_ctl.scala 961:44]
    io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[el2_dec_tlu_ctl.scala 962:40]
    io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40]
    io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40]
    io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40]
    io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[el2_dec_tlu_ctl.scala 965:40]
    io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[el2_dec_tlu_ctl.scala 966:40]
    io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[el2_dec_tlu_ctl.scala 967:40]
    io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[el2_dec_tlu_ctl.scala 968:40]
    io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[el2_dec_tlu_ctl.scala 969:40]
    io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 970:40]
    io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[el2_dec_tlu_ctl.scala 971:40]
    io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[el2_dec_tlu_ctl.scala 972:40]
    io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[el2_dec_tlu_ctl.scala 973:40]
    io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[el2_dec_tlu_ctl.scala 974:40]
    io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[el2_dec_tlu_ctl.scala 975:40]
    io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[el2_dec_tlu_ctl.scala 976:40]
    io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[el2_dec_tlu_ctl.scala 977:40]
    io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[el2_dec_tlu_ctl.scala 978:40]
    io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 979:40]
    io.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[el2_dec_tlu_ctl.scala 980:40]
    io.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[el2_dec_tlu_ctl.scala 981:40]
    io.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[el2_dec_tlu_ctl.scala 982:40]
    io.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[el2_dec_tlu_ctl.scala 983:40]
    io.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[el2_dec_tlu_ctl.scala 984:40]
    io.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[el2_dec_tlu_ctl.scala 985:40]
    io.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[el2_dec_tlu_ctl.scala 986:40]
    csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 987:44]
    csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 988:44]
    csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec_tlu_ctl.scala 988:44]
    csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec_tlu_ctl.scala 988:44]
    csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec_tlu_ctl.scala 988:44]
    csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec_tlu_ctl.scala 988:44]
    csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 988:44]
    csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 989:44]
    csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 990:44]
    csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 991:44]
    csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 992:44]
    csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 993:44]
    csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 994:44]
    csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 995:44]
    csr.io.rfpc_i0_r <= rfpc_i0_r @[el2_dec_tlu_ctl.scala 998:39]
    csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 999:39]
    csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 1000:39]
    csr.io.mret_r <= mret_r @[el2_dec_tlu_ctl.scala 1001:39]
    csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[el2_dec_tlu_ctl.scala 1002:39]
    csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[el2_dec_tlu_ctl.scala 1003:39]
    csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[el2_dec_tlu_ctl.scala 1004:39]
    csr.io.timer_int_sync <= timer_int_sync @[el2_dec_tlu_ctl.scala 1005:39]
    csr.io.soft_int_sync <= soft_int_sync @[el2_dec_tlu_ctl.scala 1006:39]
    csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[el2_dec_tlu_ctl.scala 1007:39]
    csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 1008:39]
    csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 1009:39]
    csr.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec_tlu_ctl.scala 1010:39]
    csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 1011:39]
    csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[el2_dec_tlu_ctl.scala 1012:39]
    csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[el2_dec_tlu_ctl.scala 1013:39]
    csr.io.reset_delayed <= reset_delayed @[el2_dec_tlu_ctl.scala 1014:39]
    csr.io.interrupt_valid_r <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 1015:39]
    csr.io.i0_exception_valid_r <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 1016:39]
    csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1017:39]
    csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[el2_dec_tlu_ctl.scala 1018:39]
    csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[el2_dec_tlu_ctl.scala 1019:39]
    csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1020:39]
    csr.io.inst_acc_r <= inst_acc_r @[el2_dec_tlu_ctl.scala 1021:39]
    csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 1022:39]
    csr.io.take_nmi <= take_nmi @[el2_dec_tlu_ctl.scala 1023:39]
    csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 1024:39]
    csr.io.exc_cause_r <= exc_cause_r @[el2_dec_tlu_ctl.scala 1025:39]
    csr.io.i0_valid_wb <= i0_valid_wb @[el2_dec_tlu_ctl.scala 1026:39]
    csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[el2_dec_tlu_ctl.scala 1027:39]
    csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 1028:39]
    csr.io.clk_override <= io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 1029:39]
    csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[el2_dec_tlu_ctl.scala 1030:39]
    csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[el2_dec_tlu_ctl.scala 1031:39]
    csr.io.exc_cause_wb <= exc_cause_wb @[el2_dec_tlu_ctl.scala 1032:39]
    csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 1033:39]
    csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 1034:39]
    csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 1035:39]
    csr.io.ebreak_r <= ebreak_r @[el2_dec_tlu_ctl.scala 1036:39]
    csr.io.ecall_r <= ecall_r @[el2_dec_tlu_ctl.scala 1037:39]
    csr.io.illegal_r <= illegal_r @[el2_dec_tlu_ctl.scala 1038:39]
    csr.io.mdseac_locked_f <= mdseac_locked_f @[el2_dec_tlu_ctl.scala 1039:39]
    csr.io.nmi_int_detected_f <= nmi_int_detected_f @[el2_dec_tlu_ctl.scala 1040:39]
    csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[el2_dec_tlu_ctl.scala 1041:39]
    csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[el2_dec_tlu_ctl.scala 1042:39]
    csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[el2_dec_tlu_ctl.scala 1043:39]
    csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[el2_dec_tlu_ctl.scala 1044:39]
    csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[el2_dec_tlu_ctl.scala 1045:39]
    csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[el2_dec_tlu_ctl.scala 1046:39]
    csr.io.lsu_idle_any_f <= lsu_idle_any_f @[el2_dec_tlu_ctl.scala 1047:39]
    csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 1048:39]
    csr.io.dbg_tlu_halted <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 1049:39]
    csr.io.debug_halt_req_f <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 1050:51]
    csr.io.take_ext_int_start <= take_ext_int_start @[el2_dec_tlu_ctl.scala 1051:47]
    csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[el2_dec_tlu_ctl.scala 1052:43]
    csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[el2_dec_tlu_ctl.scala 1053:43]
    csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[el2_dec_tlu_ctl.scala 1054:43]
    csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[el2_dec_tlu_ctl.scala 1055:39]
    csr.io.debug_halt_req <= debug_halt_req @[el2_dec_tlu_ctl.scala 1056:51]
    csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[el2_dec_tlu_ctl.scala 1057:39]
    csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[el2_dec_tlu_ctl.scala 1058:39]
    csr.io.enter_debug_halt_req <= enter_debug_halt_req @[el2_dec_tlu_ctl.scala 1059:39]
    csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 1060:39]
    csr.io.request_debug_mode_done <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 1061:39]
    csr.io.request_debug_mode_r <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 1062:39]
    csr.io.update_hit_bit_r <= update_hit_bit_r @[el2_dec_tlu_ctl.scala 1063:39]
    csr.io.take_timer_int <= take_timer_int @[el2_dec_tlu_ctl.scala 1064:39]
    csr.io.take_int_timer0_int <= take_int_timer0_int @[el2_dec_tlu_ctl.scala 1065:39]
    csr.io.take_int_timer1_int <= take_int_timer1_int @[el2_dec_tlu_ctl.scala 1066:39]
    csr.io.take_ext_int <= take_ext_int @[el2_dec_tlu_ctl.scala 1067:39]
    csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 1068:39]
    csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 1069:39]
    csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 1070:39]
    csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[el2_dec_tlu_ctl.scala 1071:39]
    csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[el2_dec_tlu_ctl.scala 1072:39]
    csr.io.csr_pkt.legal <= csr_pkt.legal @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.postsync <= csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.presync <= csr_pkt.presync @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1073:39]
    csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1073:39]
    npc_r <= csr.io.npc_r @[el2_dec_tlu_ctl.scala 1075:31]
    npc_r_d1 <= csr.io.npc_r_d1 @[el2_dec_tlu_ctl.scala 1076:31]
    mie_ns <= csr.io.mie_ns @[el2_dec_tlu_ctl.scala 1077:31]
    mepc <= csr.io.mepc @[el2_dec_tlu_ctl.scala 1078:31]
    mdseac_locked_ns <= csr.io.mdseac_locked_ns @[el2_dec_tlu_ctl.scala 1079:31]
    force_halt <= csr.io.force_halt @[el2_dec_tlu_ctl.scala 1080:31]
    dpc <= csr.io.dpc @[el2_dec_tlu_ctl.scala 1081:31]
    mstatus_mie_ns <= csr.io.mstatus_mie_ns @[el2_dec_tlu_ctl.scala 1082:31]
    dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 1083:31]
    fw_halt_req <= csr.io.fw_halt_req @[el2_dec_tlu_ctl.scala 1084:31]
    mstatus <= csr.io.mstatus @[el2_dec_tlu_ctl.scala 1085:31]
    dcsr <= csr.io.dcsr @[el2_dec_tlu_ctl.scala 1086:31]
    mtvec <= csr.io.mtvec @[el2_dec_tlu_ctl.scala 1087:31]
    mip <= csr.io.mip @[el2_dec_tlu_ctl.scala 1088:31]
    mtdata1_t[0] <= csr.io.mtdata1_t[0] @[el2_dec_tlu_ctl.scala 1089:33]
    mtdata1_t[1] <= csr.io.mtdata1_t[1] @[el2_dec_tlu_ctl.scala 1089:33]
    mtdata1_t[2] <= csr.io.mtdata1_t[2] @[el2_dec_tlu_ctl.scala 1089:33]
    mtdata1_t[3] <= csr.io.mtdata1_t[3] @[el2_dec_tlu_ctl.scala 1089:33]
    inst csr_read of el2_dec_decode_csr_read @[el2_dec_tlu_ctl.scala 1090:22]
    csr_read.clock <= clock
    csr_read.reset <= reset
    csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 1091:31]
    csr_pkt.legal <= csr_read.io.csr_pkt.legal @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.presync <= csr_read.io.csr_pkt.presync @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1092:10]
    csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1092:10]
    node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1094:44]
    node _T_865 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 1094:69]
    node _T_866 = and(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 1094:67]
    io.dec_tlu_presync_d <= _T_866 @[el2_dec_tlu_ctl.scala 1094:25]
    node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1095:45]
    io.dec_tlu_postsync_d <= _T_867 @[el2_dec_tlu_ctl.scala 1095:25]
    node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[el2_dec_tlu_ctl.scala 1098:52]
    node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[el2_dec_tlu_ctl.scala 1098:74]
    node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[el2_dec_tlu_ctl.scala 1098:94]
    node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[el2_dec_tlu_ctl.scala 1098:114]
    node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[el2_dec_tlu_ctl.scala 1098:136]
    node _T_873 = not(UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 1098:161]
    node conditionally_illegal = and(_T_872, _T_873) @[el2_dec_tlu_ctl.scala 1098:159]
    node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[el2_dec_tlu_ctl.scala 1099:57]
    node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[el2_dec_tlu_ctl.scala 1099:75]
    node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[el2_dec_tlu_ctl.scala 1099:94]
    node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[el2_dec_tlu_ctl.scala 1099:117]
    node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[el2_dec_tlu_ctl.scala 1099:138]
    node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[el2_dec_tlu_ctl.scala 1099:160]
    node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[el2_dec_tlu_ctl.scala 1099:181]
    node _T_881 = not(_T_880) @[el2_dec_tlu_ctl.scala 1099:38]
    node _T_882 = or(_T_881, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 1099:203]
    node _T_883 = and(csr_pkt.legal, _T_882) @[el2_dec_tlu_ctl.scala 1099:35]
    node _T_884 = not(fast_int_meicpct) @[el2_dec_tlu_ctl.scala 1099:225]
    node _T_885 = and(_T_883, _T_884) @[el2_dec_tlu_ctl.scala 1099:223]
    node _T_886 = not(conditionally_illegal) @[el2_dec_tlu_ctl.scala 1099:245]
    node valid_csr = and(_T_885, _T_886) @[el2_dec_tlu_ctl.scala 1099:243]
    node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[el2_dec_tlu_ctl.scala 1101:48]
    node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[el2_dec_tlu_ctl.scala 1101:109]
    node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[el2_dec_tlu_ctl.scala 1101:131]
    node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[el2_dec_tlu_ctl.scala 1101:152]
    node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[el2_dec_tlu_ctl.scala 1101:174]
    node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[el2_dec_tlu_ctl.scala 1101:195]
    node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[el2_dec_tlu_ctl.scala 1101:84]
    node _T_894 = not(_T_893) @[el2_dec_tlu_ctl.scala 1101:61]
    node _T_895 = and(_T_887, _T_894) @[el2_dec_tlu_ctl.scala 1101:59]
    io.dec_csr_legal_d <= _T_895 @[el2_dec_tlu_ctl.scala 1101:22]
    
