;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_dec_decode_ctl : 
  extmodule gated_latch : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module el2_dec_dec_ctl : 
    input clock : Clock
    input reset : Reset
    output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}}
    
    node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 20:23]
    node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 20:35]
    node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 20:27]
    node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 20:49]
    node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:42]
    node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:60]
    node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 20:53]
    node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 20:39]
    node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 20:75]
    node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:68]
    node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:85]
    node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 20:78]
    node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 20:65]
    io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 20:14]
    node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 17:17]
    node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 17:17]
    node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34]
    node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 17:17]
    node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 17:17]
    node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 21:43]
    node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34]
    node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 17:17]
    node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 17:17]
    node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 21:70]
    node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34]
    node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 17:17]
    node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 17:17]
    node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 22:29]
    node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34]
    node _T_45 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_46 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_48 = and(_T_44, _T_45) @[el2_dec_dec_ctl.scala 17:17]
    node _T_49 = and(_T_48, _T_47) @[el2_dec_dec_ctl.scala 17:17]
    node _T_50 = or(_T_43, _T_49) @[el2_dec_dec_ctl.scala 22:56]
    node _T_51 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_53 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34]
    node _T_54 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_56 = and(_T_52, _T_53) @[el2_dec_dec_ctl.scala 17:17]
    node _T_57 = and(_T_56, _T_55) @[el2_dec_dec_ctl.scala 17:17]
    node _T_58 = or(_T_50, _T_57) @[el2_dec_dec_ctl.scala 23:29]
    node _T_59 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34]
    node _T_60 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_61 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_63 = and(_T_59, _T_60) @[el2_dec_dec_ctl.scala 17:17]
    node _T_64 = and(_T_63, _T_62) @[el2_dec_dec_ctl.scala 17:17]
    node _T_65 = or(_T_58, _T_64) @[el2_dec_dec_ctl.scala 23:55]
    node _T_66 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_68 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34]
    node _T_69 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_71 = and(_T_67, _T_68) @[el2_dec_dec_ctl.scala 17:17]
    node _T_72 = and(_T_71, _T_70) @[el2_dec_dec_ctl.scala 17:17]
    node _T_73 = or(_T_65, _T_72) @[el2_dec_dec_ctl.scala 24:29]
    node _T_74 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34]
    node _T_75 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_76 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_78 = and(_T_74, _T_75) @[el2_dec_dec_ctl.scala 17:17]
    node _T_79 = and(_T_78, _T_77) @[el2_dec_dec_ctl.scala 17:17]
    node _T_80 = or(_T_73, _T_79) @[el2_dec_dec_ctl.scala 24:55]
    node _T_81 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_83 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34]
    node _T_84 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_86 = and(_T_82, _T_83) @[el2_dec_dec_ctl.scala 17:17]
    node _T_87 = and(_T_86, _T_85) @[el2_dec_dec_ctl.scala 17:17]
    node _T_88 = or(_T_80, _T_87) @[el2_dec_dec_ctl.scala 25:29]
    node _T_89 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34]
    node _T_90 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_91 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_93 = and(_T_89, _T_90) @[el2_dec_dec_ctl.scala 17:17]
    node _T_94 = and(_T_93, _T_92) @[el2_dec_dec_ctl.scala 17:17]
    node _T_95 = or(_T_88, _T_94) @[el2_dec_dec_ctl.scala 25:55]
    node _T_96 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_97 = eq(_T_96, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_98 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_100 = and(_T_97, _T_99) @[el2_dec_dec_ctl.scala 17:17]
    node _T_101 = or(_T_95, _T_100) @[el2_dec_dec_ctl.scala 26:29]
    node _T_102 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_104 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_106 = and(_T_103, _T_105) @[el2_dec_dec_ctl.scala 17:17]
    node _T_107 = or(_T_101, _T_106) @[el2_dec_dec_ctl.scala 26:51]
    io.out.rs1 <= _T_107 @[el2_dec_dec_ctl.scala 21:14]
    node _T_108 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_109 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_111 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_113 = and(_T_108, _T_110) @[el2_dec_dec_ctl.scala 17:17]
    node _T_114 = and(_T_113, _T_112) @[el2_dec_dec_ctl.scala 17:17]
    node _T_115 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_117 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_118 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_119 = eq(_T_118, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_120 = and(_T_116, _T_117) @[el2_dec_dec_ctl.scala 17:17]
    node _T_121 = and(_T_120, _T_119) @[el2_dec_dec_ctl.scala 17:17]
    node _T_122 = or(_T_114, _T_121) @[el2_dec_dec_ctl.scala 27:40]
    io.out.rs2 <= _T_122 @[el2_dec_dec_ctl.scala 27:14]
    node _T_123 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_125 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_127 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_128 = and(_T_124, _T_126) @[el2_dec_dec_ctl.scala 17:17]
    node _T_129 = and(_T_128, _T_127) @[el2_dec_dec_ctl.scala 17:17]
    node _T_130 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_131 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_133 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_134 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_136 = and(_T_130, _T_132) @[el2_dec_dec_ctl.scala 17:17]
    node _T_137 = and(_T_136, _T_133) @[el2_dec_dec_ctl.scala 17:17]
    node _T_138 = and(_T_137, _T_135) @[el2_dec_dec_ctl.scala 17:17]
    node _T_139 = or(_T_129, _T_138) @[el2_dec_dec_ctl.scala 28:42]
    node _T_140 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_142 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_144 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_145 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_146 = and(_T_141, _T_143) @[el2_dec_dec_ctl.scala 17:17]
    node _T_147 = and(_T_146, _T_144) @[el2_dec_dec_ctl.scala 17:17]
    node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 17:17]
    node _T_149 = or(_T_139, _T_148) @[el2_dec_dec_ctl.scala 28:70]
    node _T_150 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_152 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_154 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_155 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_157 = and(_T_151, _T_153) @[el2_dec_dec_ctl.scala 17:17]
    node _T_158 = and(_T_157, _T_154) @[el2_dec_dec_ctl.scala 17:17]
    node _T_159 = and(_T_158, _T_156) @[el2_dec_dec_ctl.scala 17:17]
    node _T_160 = or(_T_149, _T_159) @[el2_dec_dec_ctl.scala 29:32]
    io.out.imm12 <= _T_160 @[el2_dec_dec_ctl.scala 28:16]
    node _T_161 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:24]
    node _T_162 = eq(_T_161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:17]
    node _T_163 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:37]
    node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:30]
    node _T_165 = and(_T_162, _T_164) @[el2_dec_dec_ctl.scala 30:28]
    node _T_166 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:51]
    node _T_167 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:63]
    node _T_168 = and(_T_166, _T_167) @[el2_dec_dec_ctl.scala 30:55]
    node _T_169 = or(_T_165, _T_168) @[el2_dec_dec_ctl.scala 30:42]
    node _T_170 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 30:76]
    node _T_171 = or(_T_169, _T_170) @[el2_dec_dec_ctl.scala 30:68]
    io.out.rd <= _T_171 @[el2_dec_dec_ctl.scala 30:13]
    node _T_172 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_174 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_175 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_177 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_178 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_180 = and(_T_173, _T_174) @[el2_dec_dec_ctl.scala 17:17]
    node _T_181 = and(_T_180, _T_176) @[el2_dec_dec_ctl.scala 17:17]
    node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 17:17]
    node _T_183 = and(_T_182, _T_179) @[el2_dec_dec_ctl.scala 17:17]
    io.out.shimm5 <= _T_183 @[el2_dec_dec_ctl.scala 31:17]
    node _T_184 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 32:26]
    node _T_185 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 32:36]
    node _T_186 = and(_T_184, _T_185) @[el2_dec_dec_ctl.scala 32:29]
    node _T_187 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 32:50]
    node _T_188 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 32:60]
    node _T_189 = and(_T_187, _T_188) @[el2_dec_dec_ctl.scala 32:53]
    node _T_190 = or(_T_186, _T_189) @[el2_dec_dec_ctl.scala 32:41]
    io.out.imm20 <= _T_190 @[el2_dec_dec_ctl.scala 32:16]
    node _T_191 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:24]
    node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:17]
    node _T_193 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:37]
    node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:30]
    node _T_195 = and(_T_192, _T_194) @[el2_dec_dec_ctl.scala 33:28]
    node _T_196 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 33:49]
    node _T_197 = and(_T_195, _T_196) @[el2_dec_dec_ctl.scala 33:41]
    node _T_198 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:63]
    node _T_199 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:75]
    node _T_200 = and(_T_198, _T_199) @[el2_dec_dec_ctl.scala 33:67]
    node _T_201 = or(_T_197, _T_200) @[el2_dec_dec_ctl.scala 33:54]
    io.out.pc <= _T_201 @[el2_dec_dec_ctl.scala 33:13]
    node _T_202 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_203 = eq(_T_202, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_204 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_206 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_208 = and(_T_203, _T_205) @[el2_dec_dec_ctl.scala 17:17]
    node _T_209 = and(_T_208, _T_207) @[el2_dec_dec_ctl.scala 17:17]
    io.out.load <= _T_209 @[el2_dec_dec_ctl.scala 34:15]
    node _T_210 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_212 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_213 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_215 = and(_T_211, _T_212) @[el2_dec_dec_ctl.scala 17:17]
    node _T_216 = and(_T_215, _T_214) @[el2_dec_dec_ctl.scala 17:17]
    io.out.store <= _T_216 @[el2_dec_dec_ctl.scala 35:16]
    node _T_217 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_218 = eq(_T_217, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_219 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_221 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_223 = and(_T_218, _T_220) @[el2_dec_dec_ctl.scala 17:17]
    node _T_224 = and(_T_223, _T_222) @[el2_dec_dec_ctl.scala 17:17]
    io.out.lsu <= _T_224 @[el2_dec_dec_ctl.scala 36:14]
    node _T_225 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_227 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_229 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_231 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_232 = eq(_T_231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_233 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_234 = and(_T_226, _T_228) @[el2_dec_dec_ctl.scala 17:17]
    node _T_235 = and(_T_234, _T_230) @[el2_dec_dec_ctl.scala 17:17]
    node _T_236 = and(_T_235, _T_232) @[el2_dec_dec_ctl.scala 17:17]
    node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 17:17]
    node _T_238 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_240 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_242 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_243 = and(_T_239, _T_241) @[el2_dec_dec_ctl.scala 17:17]
    node _T_244 = and(_T_243, _T_242) @[el2_dec_dec_ctl.scala 17:17]
    node _T_245 = or(_T_237, _T_244) @[el2_dec_dec_ctl.scala 37:49]
    node _T_246 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_247 = eq(_T_246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_248 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_252 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_254 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_256 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_258 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_259 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_261 = and(_T_247, _T_249) @[el2_dec_dec_ctl.scala 17:17]
    node _T_262 = and(_T_261, _T_251) @[el2_dec_dec_ctl.scala 17:17]
    node _T_263 = and(_T_262, _T_253) @[el2_dec_dec_ctl.scala 17:17]
    node _T_264 = and(_T_263, _T_255) @[el2_dec_dec_ctl.scala 17:17]
    node _T_265 = and(_T_264, _T_257) @[el2_dec_dec_ctl.scala 17:17]
    node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 17:17]
    node _T_267 = and(_T_266, _T_260) @[el2_dec_dec_ctl.scala 17:17]
    node _T_268 = or(_T_245, _T_267) @[el2_dec_dec_ctl.scala 37:74]
    io.out.add <= _T_268 @[el2_dec_dec_ctl.scala 37:14]
    node _T_269 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34]
    node _T_270 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_273 = eq(_T_272, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_274 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_275 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_276 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_277 = eq(_T_276, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_278 = and(_T_269, _T_271) @[el2_dec_dec_ctl.scala 17:17]
    node _T_279 = and(_T_278, _T_273) @[el2_dec_dec_ctl.scala 17:17]
    node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 17:17]
    node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 17:17]
    node _T_282 = and(_T_281, _T_277) @[el2_dec_dec_ctl.scala 17:17]
    node _T_283 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_285 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_286 = eq(_T_285, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_287 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_288 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_290 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_291 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_293 = and(_T_284, _T_286) @[el2_dec_dec_ctl.scala 17:17]
    node _T_294 = and(_T_293, _T_287) @[el2_dec_dec_ctl.scala 17:17]
    node _T_295 = and(_T_294, _T_289) @[el2_dec_dec_ctl.scala 17:17]
    node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 17:17]
    node _T_297 = and(_T_296, _T_292) @[el2_dec_dec_ctl.scala 17:17]
    node _T_298 = or(_T_282, _T_297) @[el2_dec_dec_ctl.scala 39:49]
    node _T_299 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_300 = eq(_T_299, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_301 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_302 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_304 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_305 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_307 = and(_T_300, _T_301) @[el2_dec_dec_ctl.scala 17:17]
    node _T_308 = and(_T_307, _T_303) @[el2_dec_dec_ctl.scala 17:17]
    node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 17:17]
    node _T_310 = and(_T_309, _T_306) @[el2_dec_dec_ctl.scala 17:17]
    node _T_311 = or(_T_298, _T_310) @[el2_dec_dec_ctl.scala 39:85]
    node _T_312 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_313 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_315 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_317 = and(_T_312, _T_314) @[el2_dec_dec_ctl.scala 17:17]
    node _T_318 = and(_T_317, _T_316) @[el2_dec_dec_ctl.scala 17:17]
    node _T_319 = or(_T_311, _T_318) @[el2_dec_dec_ctl.scala 40:35]
    io.out.sub <= _T_319 @[el2_dec_dec_ctl.scala 39:14]
    node _T_320 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_321 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_322 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_323 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_324 = eq(_T_323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_325 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_327 = and(_T_320, _T_321) @[el2_dec_dec_ctl.scala 17:17]
    node _T_328 = and(_T_327, _T_322) @[el2_dec_dec_ctl.scala 17:17]
    node _T_329 = and(_T_328, _T_324) @[el2_dec_dec_ctl.scala 17:17]
    node _T_330 = and(_T_329, _T_326) @[el2_dec_dec_ctl.scala 17:17]
    node _T_331 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_333 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_334 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_335 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_336 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_338 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_340 = and(_T_332, _T_333) @[el2_dec_dec_ctl.scala 17:17]
    node _T_341 = and(_T_340, _T_334) @[el2_dec_dec_ctl.scala 17:17]
    node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 17:17]
    node _T_343 = and(_T_342, _T_337) @[el2_dec_dec_ctl.scala 17:17]
    node _T_344 = and(_T_343, _T_339) @[el2_dec_dec_ctl.scala 17:17]
    node _T_345 = or(_T_330, _T_344) @[el2_dec_dec_ctl.scala 41:48]
    io.out.land <= _T_345 @[el2_dec_dec_ctl.scala 41:15]
    node _T_346 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_347 = eq(_T_346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_348 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_349 = and(_T_347, _T_348) @[el2_dec_dec_ctl.scala 17:17]
    node _T_350 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_351 = eq(_T_350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_352 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_353 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_354 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_356 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_358 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_360 = and(_T_351, _T_352) @[el2_dec_dec_ctl.scala 17:17]
    node _T_361 = and(_T_360, _T_353) @[el2_dec_dec_ctl.scala 17:17]
    node _T_362 = and(_T_361, _T_355) @[el2_dec_dec_ctl.scala 17:17]
    node _T_363 = and(_T_362, _T_357) @[el2_dec_dec_ctl.scala 17:17]
    node _T_364 = and(_T_363, _T_359) @[el2_dec_dec_ctl.scala 17:17]
    node _T_365 = or(_T_349, _T_364) @[el2_dec_dec_ctl.scala 42:37]
    node _T_366 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_367 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_368 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_369 = and(_T_366, _T_367) @[el2_dec_dec_ctl.scala 17:17]
    node _T_370 = and(_T_369, _T_368) @[el2_dec_dec_ctl.scala 17:17]
    node _T_371 = or(_T_365, _T_370) @[el2_dec_dec_ctl.scala 42:74]
    node _T_372 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_374 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_376 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_377 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_378 = and(_T_373, _T_375) @[el2_dec_dec_ctl.scala 17:17]
    node _T_379 = and(_T_378, _T_376) @[el2_dec_dec_ctl.scala 17:17]
    node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 17:17]
    node _T_381 = or(_T_371, _T_380) @[el2_dec_dec_ctl.scala 43:26]
    node _T_382 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_383 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_384 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_385 = eq(_T_384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_386 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_388 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_390 = and(_T_382, _T_383) @[el2_dec_dec_ctl.scala 17:17]
    node _T_391 = and(_T_390, _T_385) @[el2_dec_dec_ctl.scala 17:17]
    node _T_392 = and(_T_391, _T_387) @[el2_dec_dec_ctl.scala 17:17]
    node _T_393 = and(_T_392, _T_389) @[el2_dec_dec_ctl.scala 17:17]
    node _T_394 = or(_T_381, _T_393) @[el2_dec_dec_ctl.scala 43:55]
    io.out.lor <= _T_394 @[el2_dec_dec_ctl.scala 42:14]
    node _T_395 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_397 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_398 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_400 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_402 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_403 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_405 = and(_T_396, _T_397) @[el2_dec_dec_ctl.scala 17:17]
    node _T_406 = and(_T_405, _T_399) @[el2_dec_dec_ctl.scala 17:17]
    node _T_407 = and(_T_406, _T_401) @[el2_dec_dec_ctl.scala 17:17]
    node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 17:17]
    node _T_409 = and(_T_408, _T_404) @[el2_dec_dec_ctl.scala 17:17]
    node _T_410 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_411 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_412 = eq(_T_411, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_413 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_415 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_417 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_418 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_420 = and(_T_410, _T_412) @[el2_dec_dec_ctl.scala 17:17]
    node _T_421 = and(_T_420, _T_414) @[el2_dec_dec_ctl.scala 17:17]
    node _T_422 = and(_T_421, _T_416) @[el2_dec_dec_ctl.scala 17:17]
    node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 17:17]
    node _T_424 = and(_T_423, _T_419) @[el2_dec_dec_ctl.scala 17:17]
    node _T_425 = or(_T_409, _T_424) @[el2_dec_dec_ctl.scala 45:53]
    io.out.lxor <= _T_425 @[el2_dec_dec_ctl.scala 45:15]
    node _T_426 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_428 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_430 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_432 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_433 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_434 = eq(_T_433, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_435 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_436 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_438 = and(_T_427, _T_429) @[el2_dec_dec_ctl.scala 17:17]
    node _T_439 = and(_T_438, _T_431) @[el2_dec_dec_ctl.scala 17:17]
    node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 17:17]
    node _T_441 = and(_T_440, _T_434) @[el2_dec_dec_ctl.scala 17:17]
    node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 17:17]
    node _T_443 = and(_T_442, _T_437) @[el2_dec_dec_ctl.scala 17:17]
    io.out.sll <= _T_443 @[el2_dec_dec_ctl.scala 46:14]
    node _T_444 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34]
    node _T_445 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_447 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_448 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_449 = eq(_T_448, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_450 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_451 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_453 = and(_T_444, _T_446) @[el2_dec_dec_ctl.scala 17:17]
    node _T_454 = and(_T_453, _T_447) @[el2_dec_dec_ctl.scala 17:17]
    node _T_455 = and(_T_454, _T_449) @[el2_dec_dec_ctl.scala 17:17]
    node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 17:17]
    node _T_457 = and(_T_456, _T_452) @[el2_dec_dec_ctl.scala 17:17]
    io.out.sra <= _T_457 @[el2_dec_dec_ctl.scala 47:14]
    node _T_458 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_460 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_461 = eq(_T_460, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_462 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_463 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_464 = eq(_T_463, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_465 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_466 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_468 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_469 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_471 = and(_T_459, _T_461) @[el2_dec_dec_ctl.scala 17:17]
    node _T_472 = and(_T_471, _T_462) @[el2_dec_dec_ctl.scala 17:17]
    node _T_473 = and(_T_472, _T_464) @[el2_dec_dec_ctl.scala 17:17]
    node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 17:17]
    node _T_475 = and(_T_474, _T_467) @[el2_dec_dec_ctl.scala 17:17]
    node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 17:17]
    node _T_477 = and(_T_476, _T_470) @[el2_dec_dec_ctl.scala 17:17]
    io.out.srl <= _T_477 @[el2_dec_dec_ctl.scala 48:14]
    node _T_478 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_479 = eq(_T_478, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_480 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_482 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_483 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_485 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_486 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_487 = eq(_T_486, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_488 = and(_T_479, _T_481) @[el2_dec_dec_ctl.scala 17:17]
    node _T_489 = and(_T_488, _T_482) @[el2_dec_dec_ctl.scala 17:17]
    node _T_490 = and(_T_489, _T_484) @[el2_dec_dec_ctl.scala 17:17]
    node _T_491 = and(_T_490, _T_485) @[el2_dec_dec_ctl.scala 17:17]
    node _T_492 = and(_T_491, _T_487) @[el2_dec_dec_ctl.scala 17:17]
    node _T_493 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_495 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_496 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_498 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_499 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_501 = and(_T_494, _T_495) @[el2_dec_dec_ctl.scala 17:17]
    node _T_502 = and(_T_501, _T_497) @[el2_dec_dec_ctl.scala 17:17]
    node _T_503 = and(_T_502, _T_498) @[el2_dec_dec_ctl.scala 17:17]
    node _T_504 = and(_T_503, _T_500) @[el2_dec_dec_ctl.scala 17:17]
    node _T_505 = or(_T_492, _T_504) @[el2_dec_dec_ctl.scala 49:51]
    io.out.slt <= _T_505 @[el2_dec_dec_ctl.scala 49:14]
    node _T_506 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_507 = eq(_T_506, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_508 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_509 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_510 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_511 = eq(_T_510, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_512 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_513 = eq(_T_512, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_514 = and(_T_507, _T_508) @[el2_dec_dec_ctl.scala 17:17]
    node _T_515 = and(_T_514, _T_509) @[el2_dec_dec_ctl.scala 17:17]
    node _T_516 = and(_T_515, _T_511) @[el2_dec_dec_ctl.scala 17:17]
    node _T_517 = and(_T_516, _T_513) @[el2_dec_dec_ctl.scala 17:17]
    node _T_518 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_519 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_520 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_521 = eq(_T_520, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_522 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_523 = eq(_T_522, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_524 = and(_T_518, _T_519) @[el2_dec_dec_ctl.scala 17:17]
    node _T_525 = and(_T_524, _T_521) @[el2_dec_dec_ctl.scala 17:17]
    node _T_526 = and(_T_525, _T_523) @[el2_dec_dec_ctl.scala 17:17]
    node _T_527 = or(_T_517, _T_526) @[el2_dec_dec_ctl.scala 50:51]
    node _T_528 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_529 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_531 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_533 = and(_T_528, _T_530) @[el2_dec_dec_ctl.scala 17:17]
    node _T_534 = and(_T_533, _T_532) @[el2_dec_dec_ctl.scala 17:17]
    node _T_535 = or(_T_527, _T_534) @[el2_dec_dec_ctl.scala 50:79]
    node _T_536 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_537 = eq(_T_536, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_538 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_540 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_541 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_542 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_543 = eq(_T_542, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_544 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_545 = eq(_T_544, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_546 = and(_T_537, _T_539) @[el2_dec_dec_ctl.scala 17:17]
    node _T_547 = and(_T_546, _T_540) @[el2_dec_dec_ctl.scala 17:17]
    node _T_548 = and(_T_547, _T_541) @[el2_dec_dec_ctl.scala 17:17]
    node _T_549 = and(_T_548, _T_543) @[el2_dec_dec_ctl.scala 17:17]
    node _T_550 = and(_T_549, _T_545) @[el2_dec_dec_ctl.scala 17:17]
    node _T_551 = or(_T_535, _T_550) @[el2_dec_dec_ctl.scala 51:29]
    node _T_552 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_553 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_554 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_555 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_557 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_558 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_560 = and(_T_552, _T_553) @[el2_dec_dec_ctl.scala 17:17]
    node _T_561 = and(_T_560, _T_554) @[el2_dec_dec_ctl.scala 17:17]
    node _T_562 = and(_T_561, _T_556) @[el2_dec_dec_ctl.scala 17:17]
    node _T_563 = and(_T_562, _T_557) @[el2_dec_dec_ctl.scala 17:17]
    node _T_564 = and(_T_563, _T_559) @[el2_dec_dec_ctl.scala 17:17]
    node _T_565 = or(_T_551, _T_564) @[el2_dec_dec_ctl.scala 51:66]
    io.out.unsign <= _T_565 @[el2_dec_dec_ctl.scala 50:17]
    node _T_566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_567 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_569 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_571 = and(_T_566, _T_568) @[el2_dec_dec_ctl.scala 17:17]
    node _T_572 = and(_T_571, _T_570) @[el2_dec_dec_ctl.scala 17:17]
    io.out.condbr <= _T_572 @[el2_dec_dec_ctl.scala 53:17]
    node _T_573 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_575 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_576 = eq(_T_575, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_577 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_578 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_580 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_582 = and(_T_574, _T_576) @[el2_dec_dec_ctl.scala 17:17]
    node _T_583 = and(_T_582, _T_577) @[el2_dec_dec_ctl.scala 17:17]
    node _T_584 = and(_T_583, _T_579) @[el2_dec_dec_ctl.scala 17:17]
    node _T_585 = and(_T_584, _T_581) @[el2_dec_dec_ctl.scala 17:17]
    io.out.beq <= _T_585 @[el2_dec_dec_ctl.scala 54:14]
    node _T_586 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_588 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_589 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_590 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_591 = eq(_T_590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_592 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_593 = eq(_T_592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_594 = and(_T_587, _T_588) @[el2_dec_dec_ctl.scala 17:17]
    node _T_595 = and(_T_594, _T_589) @[el2_dec_dec_ctl.scala 17:17]
    node _T_596 = and(_T_595, _T_591) @[el2_dec_dec_ctl.scala 17:17]
    node _T_597 = and(_T_596, _T_593) @[el2_dec_dec_ctl.scala 17:17]
    io.out.bne <= _T_597 @[el2_dec_dec_ctl.scala 55:14]
    node _T_598 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_599 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_600 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_601 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_603 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_605 = and(_T_598, _T_599) @[el2_dec_dec_ctl.scala 17:17]
    node _T_606 = and(_T_605, _T_600) @[el2_dec_dec_ctl.scala 17:17]
    node _T_607 = and(_T_606, _T_602) @[el2_dec_dec_ctl.scala 17:17]
    node _T_608 = and(_T_607, _T_604) @[el2_dec_dec_ctl.scala 17:17]
    io.out.bge <= _T_608 @[el2_dec_dec_ctl.scala 56:14]
    node _T_609 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_610 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_612 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_613 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_615 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_616 = eq(_T_615, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_617 = and(_T_609, _T_611) @[el2_dec_dec_ctl.scala 17:17]
    node _T_618 = and(_T_617, _T_612) @[el2_dec_dec_ctl.scala 17:17]
    node _T_619 = and(_T_618, _T_614) @[el2_dec_dec_ctl.scala 17:17]
    node _T_620 = and(_T_619, _T_616) @[el2_dec_dec_ctl.scala 17:17]
    io.out.blt <= _T_620 @[el2_dec_dec_ctl.scala 57:14]
    node _T_621 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_622 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_623 = and(_T_621, _T_622) @[el2_dec_dec_ctl.scala 17:17]
    io.out.jal <= _T_623 @[el2_dec_dec_ctl.scala 58:14]
    node _T_624 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_625 = eq(_T_624, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_626 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_629 = eq(_T_628, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_632 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_634 = and(_T_625, _T_627) @[el2_dec_dec_ctl.scala 17:17]
    node _T_635 = and(_T_634, _T_629) @[el2_dec_dec_ctl.scala 17:17]
    node _T_636 = and(_T_635, _T_631) @[el2_dec_dec_ctl.scala 17:17]
    node _T_637 = and(_T_636, _T_633) @[el2_dec_dec_ctl.scala 17:17]
    io.out.by <= _T_637 @[el2_dec_dec_ctl.scala 59:13]
    node _T_638 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_639 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_641 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_643 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_644 = eq(_T_643, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_645 = and(_T_638, _T_640) @[el2_dec_dec_ctl.scala 17:17]
    node _T_646 = and(_T_645, _T_642) @[el2_dec_dec_ctl.scala 17:17]
    node _T_647 = and(_T_646, _T_644) @[el2_dec_dec_ctl.scala 17:17]
    io.out.half <= _T_647 @[el2_dec_dec_ctl.scala 60:15]
    node _T_648 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_649 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_650 = eq(_T_649, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_651 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_652 = eq(_T_651, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_653 = and(_T_648, _T_650) @[el2_dec_dec_ctl.scala 17:17]
    node _T_654 = and(_T_653, _T_652) @[el2_dec_dec_ctl.scala 17:17]
    io.out.word <= _T_654 @[el2_dec_dec_ctl.scala 61:15]
    node _T_655 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_656 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_657 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_658 = and(_T_655, _T_656) @[el2_dec_dec_ctl.scala 17:17]
    node _T_659 = and(_T_658, _T_657) @[el2_dec_dec_ctl.scala 17:17]
    node _T_660 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34]
    node _T_661 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_662 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_663 = and(_T_660, _T_661) @[el2_dec_dec_ctl.scala 17:17]
    node _T_664 = and(_T_663, _T_662) @[el2_dec_dec_ctl.scala 17:17]
    node _T_665 = or(_T_659, _T_664) @[el2_dec_dec_ctl.scala 62:44]
    node _T_666 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34]
    node _T_667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_668 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_669 = and(_T_666, _T_667) @[el2_dec_dec_ctl.scala 17:17]
    node _T_670 = and(_T_669, _T_668) @[el2_dec_dec_ctl.scala 17:17]
    node _T_671 = or(_T_665, _T_670) @[el2_dec_dec_ctl.scala 62:67]
    node _T_672 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34]
    node _T_673 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_674 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_675 = and(_T_672, _T_673) @[el2_dec_dec_ctl.scala 17:17]
    node _T_676 = and(_T_675, _T_674) @[el2_dec_dec_ctl.scala 17:17]
    node _T_677 = or(_T_671, _T_676) @[el2_dec_dec_ctl.scala 63:26]
    node _T_678 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34]
    node _T_679 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_680 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_681 = and(_T_678, _T_679) @[el2_dec_dec_ctl.scala 17:17]
    node _T_682 = and(_T_681, _T_680) @[el2_dec_dec_ctl.scala 17:17]
    node _T_683 = or(_T_677, _T_682) @[el2_dec_dec_ctl.scala 63:49]
    node _T_684 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34]
    node _T_685 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_686 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_687 = and(_T_684, _T_685) @[el2_dec_dec_ctl.scala 17:17]
    node _T_688 = and(_T_687, _T_686) @[el2_dec_dec_ctl.scala 17:17]
    node _T_689 = or(_T_683, _T_688) @[el2_dec_dec_ctl.scala 63:73]
    io.out.csr_read <= _T_689 @[el2_dec_dec_ctl.scala 62:19]
    node _T_690 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34]
    node _T_691 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_692 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_693 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_694 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_695 = and(_T_690, _T_691) @[el2_dec_dec_ctl.scala 17:17]
    node _T_696 = and(_T_695, _T_692) @[el2_dec_dec_ctl.scala 17:17]
    node _T_697 = and(_T_696, _T_693) @[el2_dec_dec_ctl.scala 17:17]
    node _T_698 = and(_T_697, _T_694) @[el2_dec_dec_ctl.scala 17:17]
    node _T_699 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34]
    node _T_700 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_701 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_702 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_703 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_704 = and(_T_699, _T_700) @[el2_dec_dec_ctl.scala 17:17]
    node _T_705 = and(_T_704, _T_701) @[el2_dec_dec_ctl.scala 17:17]
    node _T_706 = and(_T_705, _T_702) @[el2_dec_dec_ctl.scala 17:17]
    node _T_707 = and(_T_706, _T_703) @[el2_dec_dec_ctl.scala 17:17]
    node _T_708 = or(_T_698, _T_707) @[el2_dec_dec_ctl.scala 65:49]
    node _T_709 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34]
    node _T_710 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_711 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_712 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_713 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_714 = and(_T_709, _T_710) @[el2_dec_dec_ctl.scala 17:17]
    node _T_715 = and(_T_714, _T_711) @[el2_dec_dec_ctl.scala 17:17]
    node _T_716 = and(_T_715, _T_712) @[el2_dec_dec_ctl.scala 17:17]
    node _T_717 = and(_T_716, _T_713) @[el2_dec_dec_ctl.scala 17:17]
    node _T_718 = or(_T_708, _T_717) @[el2_dec_dec_ctl.scala 65:79]
    node _T_719 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34]
    node _T_720 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_721 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_722 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_723 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_724 = and(_T_719, _T_720) @[el2_dec_dec_ctl.scala 17:17]
    node _T_725 = and(_T_724, _T_721) @[el2_dec_dec_ctl.scala 17:17]
    node _T_726 = and(_T_725, _T_722) @[el2_dec_dec_ctl.scala 17:17]
    node _T_727 = and(_T_726, _T_723) @[el2_dec_dec_ctl.scala 17:17]
    node _T_728 = or(_T_718, _T_727) @[el2_dec_dec_ctl.scala 66:33]
    node _T_729 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34]
    node _T_730 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_731 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_732 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_733 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_734 = and(_T_729, _T_730) @[el2_dec_dec_ctl.scala 17:17]
    node _T_735 = and(_T_734, _T_731) @[el2_dec_dec_ctl.scala 17:17]
    node _T_736 = and(_T_735, _T_732) @[el2_dec_dec_ctl.scala 17:17]
    node _T_737 = and(_T_736, _T_733) @[el2_dec_dec_ctl.scala 17:17]
    node _T_738 = or(_T_728, _T_737) @[el2_dec_dec_ctl.scala 66:63]
    io.out.csr_clr <= _T_738 @[el2_dec_dec_ctl.scala 65:18]
    node _T_739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_740 = eq(_T_739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_741 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_742 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_743 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_744 = and(_T_740, _T_741) @[el2_dec_dec_ctl.scala 17:17]
    node _T_745 = and(_T_744, _T_742) @[el2_dec_dec_ctl.scala 17:17]
    node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 17:17]
    io.out.csr_write <= _T_746 @[el2_dec_dec_ctl.scala 68:20]
    node _T_747 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_748 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_749 = eq(_T_748, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_750 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_751 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_752 = and(_T_747, _T_749) @[el2_dec_dec_ctl.scala 17:17]
    node _T_753 = and(_T_752, _T_750) @[el2_dec_dec_ctl.scala 17:17]
    node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 17:17]
    node _T_755 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34]
    node _T_756 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_757 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_758 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_759 = and(_T_755, _T_756) @[el2_dec_dec_ctl.scala 17:17]
    node _T_760 = and(_T_759, _T_757) @[el2_dec_dec_ctl.scala 17:17]
    node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 17:17]
    node _T_762 = or(_T_754, _T_761) @[el2_dec_dec_ctl.scala 69:47]
    node _T_763 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34]
    node _T_764 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_765 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_766 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_767 = and(_T_763, _T_764) @[el2_dec_dec_ctl.scala 17:17]
    node _T_768 = and(_T_767, _T_765) @[el2_dec_dec_ctl.scala 17:17]
    node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 17:17]
    node _T_770 = or(_T_762, _T_769) @[el2_dec_dec_ctl.scala 69:74]
    node _T_771 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34]
    node _T_772 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_773 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_774 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_775 = and(_T_771, _T_772) @[el2_dec_dec_ctl.scala 17:17]
    node _T_776 = and(_T_775, _T_773) @[el2_dec_dec_ctl.scala 17:17]
    node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 17:17]
    node _T_778 = or(_T_770, _T_777) @[el2_dec_dec_ctl.scala 70:30]
    node _T_779 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34]
    node _T_780 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_781 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_782 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_783 = and(_T_779, _T_780) @[el2_dec_dec_ctl.scala 17:17]
    node _T_784 = and(_T_783, _T_781) @[el2_dec_dec_ctl.scala 17:17]
    node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 17:17]
    node _T_786 = or(_T_778, _T_785) @[el2_dec_dec_ctl.scala 70:57]
    node _T_787 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34]
    node _T_788 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_789 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_790 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_791 = and(_T_787, _T_788) @[el2_dec_dec_ctl.scala 17:17]
    node _T_792 = and(_T_791, _T_789) @[el2_dec_dec_ctl.scala 17:17]
    node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 17:17]
    node _T_794 = or(_T_786, _T_793) @[el2_dec_dec_ctl.scala 71:30]
    io.out.csr_imm <= _T_794 @[el2_dec_dec_ctl.scala 69:18]
    node _T_795 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34]
    node _T_796 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_798 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_799 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_800 = and(_T_795, _T_797) @[el2_dec_dec_ctl.scala 17:17]
    node _T_801 = and(_T_800, _T_798) @[el2_dec_dec_ctl.scala 17:17]
    node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 17:17]
    node _T_803 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34]
    node _T_804 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_805 = eq(_T_804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_806 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_807 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_808 = and(_T_803, _T_805) @[el2_dec_dec_ctl.scala 17:17]
    node _T_809 = and(_T_808, _T_806) @[el2_dec_dec_ctl.scala 17:17]
    node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 17:17]
    node _T_811 = or(_T_802, _T_810) @[el2_dec_dec_ctl.scala 72:47]
    node _T_812 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34]
    node _T_813 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_814 = eq(_T_813, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_815 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_816 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_817 = and(_T_812, _T_814) @[el2_dec_dec_ctl.scala 17:17]
    node _T_818 = and(_T_817, _T_815) @[el2_dec_dec_ctl.scala 17:17]
    node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 17:17]
    node _T_820 = or(_T_811, _T_819) @[el2_dec_dec_ctl.scala 72:75]
    node _T_821 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34]
    node _T_822 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_823 = eq(_T_822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_824 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_825 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_826 = and(_T_821, _T_823) @[el2_dec_dec_ctl.scala 17:17]
    node _T_827 = and(_T_826, _T_824) @[el2_dec_dec_ctl.scala 17:17]
    node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 17:17]
    node _T_829 = or(_T_820, _T_828) @[el2_dec_dec_ctl.scala 73:31]
    node _T_830 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34]
    node _T_831 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_832 = eq(_T_831, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_833 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_834 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_835 = and(_T_830, _T_832) @[el2_dec_dec_ctl.scala 17:17]
    node _T_836 = and(_T_835, _T_833) @[el2_dec_dec_ctl.scala 17:17]
    node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 17:17]
    node _T_838 = or(_T_829, _T_837) @[el2_dec_dec_ctl.scala 73:59]
    io.out.csr_set <= _T_838 @[el2_dec_dec_ctl.scala 72:18]
    node _T_839 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53]
    node _T_840 = eq(_T_839, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_841 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34]
    node _T_842 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_843 = eq(_T_842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_844 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_845 = eq(_T_844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_846 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_847 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_848 = and(_T_840, _T_841) @[el2_dec_dec_ctl.scala 17:17]
    node _T_849 = and(_T_848, _T_843) @[el2_dec_dec_ctl.scala 17:17]
    node _T_850 = and(_T_849, _T_845) @[el2_dec_dec_ctl.scala 17:17]
    node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 17:17]
    node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 17:17]
    io.out.ebreak <= _T_852 @[el2_dec_dec_ctl.scala 75:17]
    node _T_853 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53]
    node _T_854 = eq(_T_853, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_855 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53]
    node _T_856 = eq(_T_855, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_857 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_859 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_862 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_863 = and(_T_854, _T_856) @[el2_dec_dec_ctl.scala 17:17]
    node _T_864 = and(_T_863, _T_858) @[el2_dec_dec_ctl.scala 17:17]
    node _T_865 = and(_T_864, _T_860) @[el2_dec_dec_ctl.scala 17:17]
    node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 17:17]
    node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 17:17]
    io.out.ecall <= _T_867 @[el2_dec_dec_ctl.scala 76:16]
    node _T_868 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34]
    node _T_869 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_870 = eq(_T_869, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_871 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_872 = eq(_T_871, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_873 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_874 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_875 = and(_T_868, _T_870) @[el2_dec_dec_ctl.scala 17:17]
    node _T_876 = and(_T_875, _T_872) @[el2_dec_dec_ctl.scala 17:17]
    node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 17:17]
    node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 17:17]
    io.out.mret <= _T_878 @[el2_dec_dec_ctl.scala 77:15]
    node _T_879 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_880 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_881 = eq(_T_880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_882 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_883 = eq(_T_882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_884 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_885 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_886 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_887 = eq(_T_886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_888 = and(_T_879, _T_881) @[el2_dec_dec_ctl.scala 17:17]
    node _T_889 = and(_T_888, _T_883) @[el2_dec_dec_ctl.scala 17:17]
    node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 17:17]
    node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 17:17]
    node _T_892 = and(_T_891, _T_887) @[el2_dec_dec_ctl.scala 17:17]
    io.out.mul <= _T_892 @[el2_dec_dec_ctl.scala 78:14]
    node _T_893 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_894 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_896 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_897 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_898 = eq(_T_897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_899 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_900 = eq(_T_899, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_903 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_904 = eq(_T_903, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_905 = and(_T_893, _T_895) @[el2_dec_dec_ctl.scala 17:17]
    node _T_906 = and(_T_905, _T_896) @[el2_dec_dec_ctl.scala 17:17]
    node _T_907 = and(_T_906, _T_898) @[el2_dec_dec_ctl.scala 17:17]
    node _T_908 = and(_T_907, _T_900) @[el2_dec_dec_ctl.scala 17:17]
    node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 17:17]
    node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 17:17]
    node _T_911 = and(_T_910, _T_904) @[el2_dec_dec_ctl.scala 17:17]
    node _T_912 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_913 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_914 = eq(_T_913, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_917 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_918 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_919 = eq(_T_918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_921 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_922 = eq(_T_921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_923 = and(_T_912, _T_914) @[el2_dec_dec_ctl.scala 17:17]
    node _T_924 = and(_T_923, _T_916) @[el2_dec_dec_ctl.scala 17:17]
    node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 17:17]
    node _T_926 = and(_T_925, _T_919) @[el2_dec_dec_ctl.scala 17:17]
    node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 17:17]
    node _T_928 = and(_T_927, _T_922) @[el2_dec_dec_ctl.scala 17:17]
    node _T_929 = or(_T_911, _T_928) @[el2_dec_dec_ctl.scala 79:61]
    io.out.rs1_sign <= _T_929 @[el2_dec_dec_ctl.scala 79:19]
    node _T_930 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_931 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_932 = eq(_T_931, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_933 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_934 = eq(_T_933, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_935 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_937 = eq(_T_936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_939 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_941 = and(_T_930, _T_932) @[el2_dec_dec_ctl.scala 17:17]
    node _T_942 = and(_T_941, _T_934) @[el2_dec_dec_ctl.scala 17:17]
    node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 17:17]
    node _T_944 = and(_T_943, _T_937) @[el2_dec_dec_ctl.scala 17:17]
    node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 17:17]
    node _T_946 = and(_T_945, _T_940) @[el2_dec_dec_ctl.scala 17:17]
    io.out.rs2_sign <= _T_946 @[el2_dec_dec_ctl.scala 81:19]
    node _T_947 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_948 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_950 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_952 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_953 = eq(_T_952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_954 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_955 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_956 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_957 = eq(_T_956, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_958 = and(_T_947, _T_949) @[el2_dec_dec_ctl.scala 17:17]
    node _T_959 = and(_T_958, _T_951) @[el2_dec_dec_ctl.scala 17:17]
    node _T_960 = and(_T_959, _T_953) @[el2_dec_dec_ctl.scala 17:17]
    node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 17:17]
    node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 17:17]
    node _T_963 = and(_T_962, _T_957) @[el2_dec_dec_ctl.scala 17:17]
    io.out.low <= _T_963 @[el2_dec_dec_ctl.scala 82:14]
    node _T_964 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_965 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_966 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_967 = eq(_T_966, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_968 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_969 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_970 = eq(_T_969, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_971 = and(_T_964, _T_965) @[el2_dec_dec_ctl.scala 17:17]
    node _T_972 = and(_T_971, _T_967) @[el2_dec_dec_ctl.scala 17:17]
    node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 17:17]
    node _T_974 = and(_T_973, _T_970) @[el2_dec_dec_ctl.scala 17:17]
    io.out.div <= _T_974 @[el2_dec_dec_ctl.scala 83:14]
    node _T_975 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34]
    node _T_976 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_977 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_978 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_979 = eq(_T_978, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_980 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_981 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_983 = and(_T_975, _T_976) @[el2_dec_dec_ctl.scala 17:17]
    node _T_984 = and(_T_983, _T_977) @[el2_dec_dec_ctl.scala 17:17]
    node _T_985 = and(_T_984, _T_979) @[el2_dec_dec_ctl.scala 17:17]
    node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 17:17]
    node _T_987 = and(_T_986, _T_982) @[el2_dec_dec_ctl.scala 17:17]
    io.out.rem <= _T_987 @[el2_dec_dec_ctl.scala 84:14]
    node _T_988 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_989 = eq(_T_988, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_990 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_991 = and(_T_989, _T_990) @[el2_dec_dec_ctl.scala 17:17]
    io.out.fence <= _T_991 @[el2_dec_dec_ctl.scala 85:16]
    node _T_992 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_993 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_995 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_996 = and(_T_992, _T_994) @[el2_dec_dec_ctl.scala 17:17]
    node _T_997 = and(_T_996, _T_995) @[el2_dec_dec_ctl.scala 17:17]
    io.out.fence_i <= _T_997 @[el2_dec_dec_ctl.scala 86:18]
    node _T_998 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34]
    node _T_999 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1000 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1002 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1004 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1005 = and(_T_998, _T_999) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1006 = and(_T_1005, _T_1001) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1007 = and(_T_1006, _T_1003) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1009 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1010 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1011 = and(_T_1009, _T_1010) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1012 = or(_T_1008, _T_1011) @[el2_dec_dec_ctl.scala 87:51]
    node _T_1013 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1015 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1016 = eq(_T_1015, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1017 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1018 = and(_T_1014, _T_1016) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1019 = and(_T_1018, _T_1017) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1020 = or(_T_1012, _T_1019) @[el2_dec_dec_ctl.scala 87:72]
    node _T_1021 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1023 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1024 = and(_T_1022, _T_1023) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1025 = or(_T_1020, _T_1024) @[el2_dec_dec_ctl.scala 88:29]
    io.out.pm_alu <= _T_1025 @[el2_dec_dec_ctl.scala 87:17]
    node _T_1026 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1028 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1029 = and(_T_1027, _T_1028) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1030 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1032 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1033 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1034 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1035 = and(_T_1031, _T_1032) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1036 = and(_T_1035, _T_1033) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1038 = or(_T_1029, _T_1037) @[el2_dec_dec_ctl.scala 89:41]
    node _T_1039 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1041 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1042 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1043 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1044 = and(_T_1040, _T_1041) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1045 = and(_T_1044, _T_1042) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1047 = or(_T_1038, _T_1046) @[el2_dec_dec_ctl.scala 89:68]
    node _T_1048 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1050 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1051 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1052 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1053 = and(_T_1049, _T_1050) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1054 = and(_T_1053, _T_1051) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1056 = or(_T_1047, _T_1055) @[el2_dec_dec_ctl.scala 90:30]
    node _T_1057 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1059 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1060 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1061 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1062 = and(_T_1058, _T_1059) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1063 = and(_T_1062, _T_1060) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1065 = or(_T_1056, _T_1064) @[el2_dec_dec_ctl.scala 90:57]
    node _T_1066 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1068 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1069 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1070 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1071 = and(_T_1067, _T_1068) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1072 = and(_T_1071, _T_1069) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1074 = or(_T_1065, _T_1073) @[el2_dec_dec_ctl.scala 91:31]
    node _T_1075 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1077 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1078 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1079 = and(_T_1075, _T_1076) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1080 = and(_T_1079, _T_1077) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1081 = and(_T_1080, _T_1078) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1082 = or(_T_1074, _T_1081) @[el2_dec_dec_ctl.scala 91:59]
    node _T_1083 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1084 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1085 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1086 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1087 = and(_T_1083, _T_1084) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1088 = and(_T_1087, _T_1085) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1089 = and(_T_1088, _T_1086) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1090 = or(_T_1082, _T_1089) @[el2_dec_dec_ctl.scala 92:30]
    node _T_1091 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1092 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1093 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1094 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1095 = and(_T_1091, _T_1092) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1096 = and(_T_1095, _T_1093) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1097 = and(_T_1096, _T_1094) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1098 = or(_T_1090, _T_1097) @[el2_dec_dec_ctl.scala 92:57]
    node _T_1099 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1100 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1101 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1102 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1103 = and(_T_1099, _T_1100) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1104 = and(_T_1103, _T_1101) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1105 = and(_T_1104, _T_1102) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1106 = or(_T_1098, _T_1105) @[el2_dec_dec_ctl.scala 93:30]
    node _T_1107 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1108 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1109 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1111 = and(_T_1107, _T_1108) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1112 = and(_T_1111, _T_1109) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1113 = and(_T_1112, _T_1110) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1114 = or(_T_1106, _T_1113) @[el2_dec_dec_ctl.scala 93:57]
    io.out.presync <= _T_1114 @[el2_dec_dec_ctl.scala 89:18]
    node _T_1115 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1116 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1118 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1119 = and(_T_1115, _T_1117) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1120 = and(_T_1119, _T_1118) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1121 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1123 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1127 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1128 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1129 = and(_T_1122, _T_1124) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1130 = and(_T_1129, _T_1126) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1131 = and(_T_1130, _T_1127) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1132 = and(_T_1131, _T_1128) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1133 = or(_T_1120, _T_1132) @[el2_dec_dec_ctl.scala 95:45]
    node _T_1134 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1135 = eq(_T_1134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1136 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1139 = and(_T_1135, _T_1136) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1140 = and(_T_1139, _T_1137) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1141 = and(_T_1140, _T_1138) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1142 = or(_T_1133, _T_1141) @[el2_dec_dec_ctl.scala 95:78]
    node _T_1143 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1145 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1146 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1147 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1148 = and(_T_1144, _T_1145) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1149 = and(_T_1148, _T_1146) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1151 = or(_T_1142, _T_1150) @[el2_dec_dec_ctl.scala 96:30]
    node _T_1152 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1154 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1155 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1156 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1157 = and(_T_1153, _T_1154) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1158 = and(_T_1157, _T_1155) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1160 = or(_T_1151, _T_1159) @[el2_dec_dec_ctl.scala 96:57]
    node _T_1161 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1163 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1164 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1165 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1166 = and(_T_1162, _T_1163) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1167 = and(_T_1166, _T_1164) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1169 = or(_T_1160, _T_1168) @[el2_dec_dec_ctl.scala 97:30]
    node _T_1170 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1172 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1173 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1174 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1175 = and(_T_1171, _T_1172) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1176 = and(_T_1175, _T_1173) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1178 = or(_T_1169, _T_1177) @[el2_dec_dec_ctl.scala 97:58]
    node _T_1179 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1181 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1182 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1183 = and(_T_1179, _T_1180) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1184 = and(_T_1183, _T_1181) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1185 = and(_T_1184, _T_1182) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1186 = or(_T_1178, _T_1185) @[el2_dec_dec_ctl.scala 98:31]
    node _T_1187 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1188 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1189 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1190 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1191 = and(_T_1187, _T_1188) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1192 = and(_T_1191, _T_1189) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1193 = and(_T_1192, _T_1190) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1194 = or(_T_1186, _T_1193) @[el2_dec_dec_ctl.scala 98:58]
    node _T_1195 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1196 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1197 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1198 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1199 = and(_T_1195, _T_1196) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1200 = and(_T_1199, _T_1197) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1201 = and(_T_1200, _T_1198) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1202 = or(_T_1194, _T_1201) @[el2_dec_dec_ctl.scala 99:30]
    node _T_1203 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1204 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1205 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1206 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1207 = and(_T_1203, _T_1204) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1208 = and(_T_1207, _T_1205) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1209 = and(_T_1208, _T_1206) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1210 = or(_T_1202, _T_1209) @[el2_dec_dec_ctl.scala 99:57]
    node _T_1211 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1212 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1213 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1215 = and(_T_1211, _T_1212) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1216 = and(_T_1215, _T_1213) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1217 = and(_T_1216, _T_1214) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1218 = or(_T_1210, _T_1217) @[el2_dec_dec_ctl.scala 100:30]
    io.out.postsync <= _T_1218 @[el2_dec_dec_ctl.scala 95:19]
    node _T_1219 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1220 = eq(_T_1219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1221 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1223 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1224 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1225 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1227 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1228 = eq(_T_1227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1229 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1231 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1233 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1235 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1237 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1238 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1240 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1242 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1243 = eq(_T_1242, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1244 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1246 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1247 = eq(_T_1246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1248 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1252 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1254 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1256 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1258 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1260 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1262 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1263 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1264 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1265 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1266 = eq(_T_1265, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1267 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1269 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1270 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1271 = and(_T_1220, _T_1222) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1272 = and(_T_1271, _T_1223) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1273 = and(_T_1272, _T_1224) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1274 = and(_T_1273, _T_1226) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1275 = and(_T_1274, _T_1228) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1276 = and(_T_1275, _T_1230) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1277 = and(_T_1276, _T_1232) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1278 = and(_T_1277, _T_1234) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1279 = and(_T_1278, _T_1236) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1280 = and(_T_1279, _T_1237) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1281 = and(_T_1280, _T_1239) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1282 = and(_T_1281, _T_1241) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1283 = and(_T_1282, _T_1243) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1284 = and(_T_1283, _T_1245) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1285 = and(_T_1284, _T_1247) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1286 = and(_T_1285, _T_1249) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1287 = and(_T_1286, _T_1251) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1288 = and(_T_1287, _T_1253) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1289 = and(_T_1288, _T_1255) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1290 = and(_T_1289, _T_1257) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1291 = and(_T_1290, _T_1259) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1292 = and(_T_1291, _T_1261) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1293 = and(_T_1292, _T_1262) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1294 = and(_T_1293, _T_1263) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1295 = and(_T_1294, _T_1264) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1296 = and(_T_1295, _T_1266) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1297 = and(_T_1296, _T_1268) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1298 = and(_T_1297, _T_1269) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1299 = and(_T_1298, _T_1270) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1300 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1302 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1304 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1306 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1307 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1309 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1311 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1313 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1315 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1317 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1318 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1320 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1321 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1323 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1324 = eq(_T_1323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1325 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1326 = eq(_T_1325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1327 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1329 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1331 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1332 = eq(_T_1331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1333 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1334 = eq(_T_1333, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1335 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1337 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1338 = eq(_T_1337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1339 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1340 = eq(_T_1339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1341 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1342 = eq(_T_1341, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1343 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1344 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1345 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1346 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1348 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1350 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1351 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1352 = and(_T_1301, _T_1303) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1353 = and(_T_1352, _T_1305) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1354 = and(_T_1353, _T_1306) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1355 = and(_T_1354, _T_1308) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1356 = and(_T_1355, _T_1310) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1357 = and(_T_1356, _T_1312) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1358 = and(_T_1357, _T_1314) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1359 = and(_T_1358, _T_1316) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1360 = and(_T_1359, _T_1317) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1361 = and(_T_1360, _T_1319) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1362 = and(_T_1361, _T_1320) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1363 = and(_T_1362, _T_1322) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1364 = and(_T_1363, _T_1324) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1365 = and(_T_1364, _T_1326) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1366 = and(_T_1365, _T_1328) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1367 = and(_T_1366, _T_1330) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1368 = and(_T_1367, _T_1332) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1369 = and(_T_1368, _T_1334) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1370 = and(_T_1369, _T_1336) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1371 = and(_T_1370, _T_1338) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1372 = and(_T_1371, _T_1340) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1373 = and(_T_1372, _T_1342) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1374 = and(_T_1373, _T_1343) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1375 = and(_T_1374, _T_1344) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1376 = and(_T_1375, _T_1345) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1377 = and(_T_1376, _T_1347) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1378 = and(_T_1377, _T_1349) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1379 = and(_T_1378, _T_1350) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1380 = and(_T_1379, _T_1351) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1381 = or(_T_1299, _T_1380) @[el2_dec_dec_ctl.scala 101:136]
    node _T_1382 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1383 = eq(_T_1382, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1384 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1385 = eq(_T_1384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1386 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1388 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1390 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1391 = eq(_T_1390, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1392 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1394 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1396 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1398 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1400 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1402 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1404 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1406 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1408 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1410 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1412 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1414 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1416 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1418 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1420 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1422 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1424 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1426 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1427 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1428 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1430 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1432 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1433 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1434 = and(_T_1383, _T_1385) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1435 = and(_T_1434, _T_1387) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1436 = and(_T_1435, _T_1389) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1437 = and(_T_1436, _T_1391) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1438 = and(_T_1437, _T_1393) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1439 = and(_T_1438, _T_1395) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1440 = and(_T_1439, _T_1397) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1441 = and(_T_1440, _T_1399) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1442 = and(_T_1441, _T_1401) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1443 = and(_T_1442, _T_1403) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1444 = and(_T_1443, _T_1405) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1445 = and(_T_1444, _T_1407) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1446 = and(_T_1445, _T_1409) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1447 = and(_T_1446, _T_1411) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1448 = and(_T_1447, _T_1413) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1449 = and(_T_1448, _T_1415) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1450 = and(_T_1449, _T_1417) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1451 = and(_T_1450, _T_1419) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1452 = and(_T_1451, _T_1421) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1453 = and(_T_1452, _T_1423) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1454 = and(_T_1453, _T_1425) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1455 = and(_T_1454, _T_1426) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1456 = and(_T_1455, _T_1427) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1457 = and(_T_1456, _T_1429) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1458 = and(_T_1457, _T_1431) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1459 = and(_T_1458, _T_1432) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1460 = and(_T_1459, _T_1433) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1461 = or(_T_1381, _T_1460) @[el2_dec_dec_ctl.scala 102:122]
    node _T_1462 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1464 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1465 = eq(_T_1464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1466 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1467 = eq(_T_1466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1468 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1469 = eq(_T_1468, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1470 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1472 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1473 = eq(_T_1472, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1474 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1475 = eq(_T_1474, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1476 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1478 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1479 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1481 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1482 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1483 = and(_T_1463, _T_1465) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1484 = and(_T_1483, _T_1467) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1485 = and(_T_1484, _T_1469) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1486 = and(_T_1485, _T_1471) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1487 = and(_T_1486, _T_1473) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1488 = and(_T_1487, _T_1475) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1489 = and(_T_1488, _T_1477) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1490 = and(_T_1489, _T_1478) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1491 = and(_T_1490, _T_1480) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1492 = and(_T_1491, _T_1481) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1493 = and(_T_1492, _T_1482) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1494 = or(_T_1461, _T_1493) @[el2_dec_dec_ctl.scala 103:119]
    node _T_1495 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1497 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1499 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1500 = eq(_T_1499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1501 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1502 = eq(_T_1501, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1503 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1504 = eq(_T_1503, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1505 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1507 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1509 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1511 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1513 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1515 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1517 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1519 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1520 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1521 = and(_T_1496, _T_1498) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1522 = and(_T_1521, _T_1500) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1523 = and(_T_1522, _T_1502) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1524 = and(_T_1523, _T_1504) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1525 = and(_T_1524, _T_1506) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1526 = and(_T_1525, _T_1508) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1527 = and(_T_1526, _T_1510) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1528 = and(_T_1527, _T_1512) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1529 = and(_T_1528, _T_1514) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1530 = and(_T_1529, _T_1516) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1531 = and(_T_1530, _T_1518) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1532 = and(_T_1531, _T_1519) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1533 = and(_T_1532, _T_1520) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1534 = or(_T_1494, _T_1533) @[el2_dec_dec_ctl.scala 104:60]
    node _T_1535 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1536 = eq(_T_1535, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1537 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1539 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1541 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1542 = eq(_T_1541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1543 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1544 = eq(_T_1543, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1545 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1547 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1548 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1550 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1551 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1552 = eq(_T_1551, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1553 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1554 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1556 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1557 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1558 = and(_T_1536, _T_1538) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1559 = and(_T_1558, _T_1540) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1560 = and(_T_1559, _T_1542) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1561 = and(_T_1560, _T_1544) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1562 = and(_T_1561, _T_1546) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1563 = and(_T_1562, _T_1547) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1564 = and(_T_1563, _T_1549) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1565 = and(_T_1564, _T_1550) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1566 = and(_T_1565, _T_1552) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1567 = and(_T_1566, _T_1553) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1568 = and(_T_1567, _T_1555) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1569 = and(_T_1568, _T_1556) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1570 = and(_T_1569, _T_1557) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1571 = or(_T_1534, _T_1570) @[el2_dec_dec_ctl.scala 105:69]
    node _T_1572 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1574 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1575 = eq(_T_1574, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1576 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1578 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1579 = eq(_T_1578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1580 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1581 = eq(_T_1580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1582 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1584 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1586 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1587 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1588 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1590 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1591 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1592 = and(_T_1573, _T_1575) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1593 = and(_T_1592, _T_1577) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1594 = and(_T_1593, _T_1579) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1595 = and(_T_1594, _T_1581) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1596 = and(_T_1595, _T_1583) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1597 = and(_T_1596, _T_1585) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1598 = and(_T_1597, _T_1586) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1599 = and(_T_1598, _T_1587) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1600 = and(_T_1599, _T_1589) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1601 = and(_T_1600, _T_1590) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1602 = and(_T_1601, _T_1591) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1603 = or(_T_1571, _T_1602) @[el2_dec_dec_ctl.scala 106:66]
    node _T_1604 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1606 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1607 = eq(_T_1606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1608 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1609 = eq(_T_1608, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1610 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1611 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1612 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1614 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1615 = eq(_T_1614, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1616 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1617 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1618 = and(_T_1605, _T_1607) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1619 = and(_T_1618, _T_1609) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1620 = and(_T_1619, _T_1610) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1621 = and(_T_1620, _T_1611) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1622 = and(_T_1621, _T_1613) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1623 = and(_T_1622, _T_1615) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1624 = and(_T_1623, _T_1616) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1625 = and(_T_1624, _T_1617) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1626 = or(_T_1603, _T_1625) @[el2_dec_dec_ctl.scala 107:58]
    node _T_1627 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1629 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1632 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1633 = eq(_T_1632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1634 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1636 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1637 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1638 = and(_T_1627, _T_1628) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1639 = and(_T_1638, _T_1629) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1640 = and(_T_1639, _T_1631) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1641 = and(_T_1640, _T_1633) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1642 = and(_T_1641, _T_1635) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1643 = and(_T_1642, _T_1636) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1644 = and(_T_1643, _T_1637) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1645 = or(_T_1626, _T_1644) @[el2_dec_dec_ctl.scala 108:46]
    node _T_1646 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1647 = eq(_T_1646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1648 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1650 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1652 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1653 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1655 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1656 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1657 = and(_T_1647, _T_1649) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1658 = and(_T_1657, _T_1651) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1659 = and(_T_1658, _T_1652) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1660 = and(_T_1659, _T_1654) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1661 = and(_T_1660, _T_1655) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1662 = and(_T_1661, _T_1656) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1663 = or(_T_1645, _T_1662) @[el2_dec_dec_ctl.scala 109:40]
    node _T_1664 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1666 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1668 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1669 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1671 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1672 = eq(_T_1671, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1673 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1675 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1676 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1677 = and(_T_1665, _T_1667) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1678 = and(_T_1677, _T_1668) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1679 = and(_T_1678, _T_1670) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1680 = and(_T_1679, _T_1672) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1682 = and(_T_1681, _T_1675) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1683 = and(_T_1682, _T_1676) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1684 = or(_T_1663, _T_1683) @[el2_dec_dec_ctl.scala 110:39]
    node _T_1685 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1686 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1687 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1688 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1689 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1691 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1693 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1694 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1695 = and(_T_1685, _T_1686) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1696 = and(_T_1695, _T_1687) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1697 = and(_T_1696, _T_1688) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1698 = and(_T_1697, _T_1690) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1699 = and(_T_1698, _T_1692) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1700 = and(_T_1699, _T_1693) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1701 = and(_T_1700, _T_1694) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1702 = or(_T_1684, _T_1701) @[el2_dec_dec_ctl.scala 111:43]
    node _T_1703 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1704 = eq(_T_1703, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1705 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1706 = eq(_T_1705, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1707 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1708 = eq(_T_1707, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1709 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1711 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1712 = eq(_T_1711, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1713 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1715 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1717 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1718 = eq(_T_1717, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1719 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1720 = eq(_T_1719, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1721 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1722 = eq(_T_1721, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1723 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1725 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1727 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1729 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1731 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1733 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1735 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1737 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1741 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1743 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1745 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1747 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1749 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1753 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1755 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1757 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1758 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1759 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1760 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1761 = and(_T_1704, _T_1706) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1762 = and(_T_1761, _T_1708) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1763 = and(_T_1762, _T_1710) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1764 = and(_T_1763, _T_1712) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1765 = and(_T_1764, _T_1714) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1766 = and(_T_1765, _T_1716) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1767 = and(_T_1766, _T_1718) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1768 = and(_T_1767, _T_1720) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1769 = and(_T_1768, _T_1722) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1770 = and(_T_1769, _T_1724) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1771 = and(_T_1770, _T_1726) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1772 = and(_T_1771, _T_1728) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1773 = and(_T_1772, _T_1730) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1774 = and(_T_1773, _T_1732) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1775 = and(_T_1774, _T_1734) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1776 = and(_T_1775, _T_1736) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1777 = and(_T_1776, _T_1738) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1778 = and(_T_1777, _T_1740) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1779 = and(_T_1778, _T_1742) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1780 = and(_T_1779, _T_1744) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1781 = and(_T_1780, _T_1746) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1782 = and(_T_1781, _T_1748) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1783 = and(_T_1782, _T_1750) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1784 = and(_T_1783, _T_1752) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1785 = and(_T_1784, _T_1754) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1786 = and(_T_1785, _T_1756) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1787 = and(_T_1786, _T_1757) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1788 = and(_T_1787, _T_1758) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1789 = and(_T_1788, _T_1759) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1790 = and(_T_1789, _T_1760) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1791 = or(_T_1702, _T_1790) @[el2_dec_dec_ctl.scala 112:39]
    node _T_1792 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1793 = eq(_T_1792, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1794 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1796 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1798 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1799 = eq(_T_1798, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1800 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1802 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1803 = eq(_T_1802, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1804 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1806 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1807 = eq(_T_1806, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1808 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1809 = eq(_T_1808, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1810 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1811 = eq(_T_1810, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1812 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1813 = eq(_T_1812, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1815 = eq(_T_1814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1816 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1817 = eq(_T_1816, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1818 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1820 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1822 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1824 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1826 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1828 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1830 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1832 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1833 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1834 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1835 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1836 = and(_T_1793, _T_1795) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1837 = and(_T_1836, _T_1797) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1838 = and(_T_1837, _T_1799) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1839 = and(_T_1838, _T_1801) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1840 = and(_T_1839, _T_1803) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1841 = and(_T_1840, _T_1805) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1842 = and(_T_1841, _T_1807) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1843 = and(_T_1842, _T_1809) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1844 = and(_T_1843, _T_1811) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1845 = and(_T_1844, _T_1813) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1846 = and(_T_1845, _T_1815) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1847 = and(_T_1846, _T_1817) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1848 = and(_T_1847, _T_1819) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1849 = and(_T_1848, _T_1821) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1850 = and(_T_1849, _T_1823) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1851 = and(_T_1850, _T_1825) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1852 = and(_T_1851, _T_1827) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1853 = and(_T_1852, _T_1829) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1854 = and(_T_1853, _T_1831) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1855 = and(_T_1854, _T_1832) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1856 = and(_T_1855, _T_1833) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1857 = and(_T_1856, _T_1834) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1858 = and(_T_1857, _T_1835) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1859 = or(_T_1791, _T_1858) @[el2_dec_dec_ctl.scala 113:130]
    node _T_1860 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1862 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1864 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1866 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1867 = eq(_T_1866, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1868 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1869 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1870 = and(_T_1860, _T_1861) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1871 = and(_T_1870, _T_1862) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1872 = and(_T_1871, _T_1863) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1873 = and(_T_1872, _T_1865) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1874 = and(_T_1873, _T_1867) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1875 = and(_T_1874, _T_1868) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1876 = and(_T_1875, _T_1869) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1877 = or(_T_1859, _T_1876) @[el2_dec_dec_ctl.scala 114:102]
    node _T_1878 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1879 = eq(_T_1878, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1880 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1881 = eq(_T_1880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1882 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1884 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1885 = eq(_T_1884, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1886 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1887 = eq(_T_1886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1888 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1889 = eq(_T_1888, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1890 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1891 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1892 = and(_T_1879, _T_1881) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1893 = and(_T_1892, _T_1883) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1894 = and(_T_1893, _T_1885) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1895 = and(_T_1894, _T_1887) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1896 = and(_T_1895, _T_1889) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1897 = and(_T_1896, _T_1890) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1898 = and(_T_1897, _T_1891) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1899 = or(_T_1877, _T_1898) @[el2_dec_dec_ctl.scala 115:39]
    node _T_1900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1903 = eq(_T_1902, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1904 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1905 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1906 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1907 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1908 = and(_T_1900, _T_1901) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1909 = and(_T_1908, _T_1903) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1910 = and(_T_1909, _T_1904) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1911 = and(_T_1910, _T_1905) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1912 = and(_T_1911, _T_1906) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1913 = and(_T_1912, _T_1907) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1914 = or(_T_1899, _T_1913) @[el2_dec_dec_ctl.scala 116:43]
    node _T_1915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1916 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1917 = eq(_T_1916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1918 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1921 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1922 = eq(_T_1921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1923 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1924 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1925 = and(_T_1915, _T_1917) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1926 = and(_T_1925, _T_1919) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1927 = and(_T_1926, _T_1920) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1928 = and(_T_1927, _T_1922) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1929 = and(_T_1928, _T_1923) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1930 = and(_T_1929, _T_1924) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1931 = or(_T_1914, _T_1930) @[el2_dec_dec_ctl.scala 117:35]
    node _T_1932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1934 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1937 = eq(_T_1936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1940 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1942 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1943 = eq(_T_1942, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1944 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1945 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1946 = and(_T_1933, _T_1935) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1947 = and(_T_1946, _T_1937) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1948 = and(_T_1947, _T_1939) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1949 = and(_T_1948, _T_1941) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1950 = and(_T_1949, _T_1943) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1951 = and(_T_1950, _T_1944) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1952 = and(_T_1951, _T_1945) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1953 = or(_T_1931, _T_1952) @[el2_dec_dec_ctl.scala 118:38]
    node _T_1954 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1957 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53]
    node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46]
    node _T_1959 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1960 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1961 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34]
    node _T_1962 = and(_T_1955, _T_1956) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1963 = and(_T_1962, _T_1958) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1964 = and(_T_1963, _T_1959) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1965 = and(_T_1964, _T_1960) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1966 = and(_T_1965, _T_1961) @[el2_dec_dec_ctl.scala 17:17]
    node _T_1967 = or(_T_1953, _T_1966) @[el2_dec_dec_ctl.scala 119:44]
    io.out.legal <= _T_1967 @[el2_dec_dec_ctl.scala 101:16]
    
  extmodule gated_latch_1 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_1 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_2 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_2 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_3 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_3 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_4 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_4 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_5 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_5 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_6 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_6 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_7 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_7 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_8 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_8 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_9 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_9 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_10 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_10 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_11 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_11 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_12 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_12 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_13 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_13 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_14 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_14 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_15 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_15 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_16 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_16 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_17 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_17 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_18 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_18 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_19 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_19 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module el2_dec_decode_ctl : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
    
    wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.crc32c_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.crc32c_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.crc32c_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.crc32_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.crc32_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.crc32_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.unshfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.shfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.grev <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.clmulr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.clmulh <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.clmul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.bdep <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.bext <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.bits.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    _T.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
    io.mul_p.bits.bfp <= _T.bits.bfp @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.crc32_w <= _T.bits.crc32_w @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.crc32_h <= _T.bits.crc32_h @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.crc32_b <= _T.bits.crc32_b @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.unshfl <= _T.bits.unshfl @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.shfl <= _T.bits.shfl @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.grev <= _T.bits.grev @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.clmulr <= _T.bits.clmulr @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.clmulh <= _T.bits.clmulh @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.clmul <= _T.bits.clmul @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.bdep <= _T.bits.bdep @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.bext <= _T.bits.bext @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.low <= _T.bits.low @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[el2_dec_decode_ctl.scala 126:12]
    io.mul_p.valid <= _T.valid @[el2_dec_decode_ctl.scala 126:12]
    wire leak1_i1_stall_in : UInt<1>
    leak1_i1_stall_in <= UInt<1>("h00")
    wire leak1_i0_stall_in : UInt<1>
    leak1_i0_stall_in <= UInt<1>("h00")
    wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 130:17]
    wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 131:17]
    wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 132:17]
    wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20]
    wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17]
    wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23]
    wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17]
    wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17]
    wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17]
    wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20]
    wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17]
    wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20]
    wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28]
    wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28]
    wire i0_rs1_depth_d : UInt<2>
    i0_rs1_depth_d <= UInt<1>("h00")
    wire i0_rs2_depth_d : UInt<2>
    i0_rs2_depth_d <= UInt<1>("h00")
    wire cam_wen : UInt<4>
    cam_wen <= UInt<1>("h00")
    wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 147:17]
    wire cam_write : UInt<1>
    cam_write <= UInt<1>("h00")
    wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29]
    wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30]
    wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31]
    wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 152:20]
    wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 153:20]
    wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18]
    wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22]
    wire i0_rs1bypass : UInt<3>
    i0_rs1bypass <= UInt<1>("h00")
    wire i0_rs2bypass : UInt<3>
    i0_rs2bypass <= UInt<1>("h00")
    wire illegal_lockout : UInt<1>
    illegal_lockout <= UInt<1>("h00")
    wire postsync_stall : UInt<1>
    postsync_stall <= UInt<1>("h00")
    wire ps_stall_in : UInt<1>
    ps_stall_in <= UInt<1>("h00")
    wire i0_pipe_en : UInt<4>
    i0_pipe_en <= UInt<1>("h00")
    wire i0_load_block_d : UInt<1>
    i0_load_block_d <= UInt<1>("h00")
    wire load_ldst_bypass_d : UInt<1>
    load_ldst_bypass_d <= UInt<1>("h00")
    wire store_data_bypass_d : UInt<1>
    store_data_bypass_d <= UInt<1>("h00")
    wire store_data_bypass_m : UInt<1>
    store_data_bypass_m <= UInt<1>("h00")
    wire tlu_wr_pause_r1 : UInt<1>
    tlu_wr_pause_r1 <= UInt<1>("h00")
    wire tlu_wr_pause_r2 : UInt<1>
    tlu_wr_pause_r2 <= UInt<1>("h00")
    wire leak1_i1_stall : UInt<1>
    leak1_i1_stall <= UInt<1>("h00")
    wire leak1_i0_stall : UInt<1>
    leak1_i0_stall <= UInt<1>("h00")
    wire pause_stall : UInt<1>
    pause_stall <= UInt<1>("h00")
    wire flush_final_r : UInt<1>
    flush_final_r <= UInt<1>("h00")
    wire illegal_lockout_in : UInt<1>
    illegal_lockout_in <= UInt<1>("h00")
    wire lsu_idle : UInt<1>
    lsu_idle <= UInt<1>("h00")
    wire pause_state_in : UInt<1>
    pause_state_in <= UInt<1>("h00")
    wire leak1_mode : UInt<1>
    leak1_mode <= UInt<1>("h00")
    wire i0_pcall : UInt<1>
    i0_pcall <= UInt<1>("h00")
    wire i0_pja : UInt<1>
    i0_pja <= UInt<1>("h00")
    wire i0_pret : UInt<1>
    i0_pret <= UInt<1>("h00")
    wire i0_legal_decode_d : UInt<1>
    i0_legal_decode_d <= UInt<1>("h00")
    wire i0_pcall_raw : UInt<1>
    i0_pcall_raw <= UInt<1>("h00")
    wire i0_pja_raw : UInt<1>
    i0_pja_raw <= UInt<1>("h00")
    wire i0_pret_raw : UInt<1>
    i0_pret_raw <= UInt<1>("h00")
    wire i0_br_offset : UInt<12>
    i0_br_offset <= UInt<1>("h00")
    wire i0_csr_write_only_d : UInt<1>
    i0_csr_write_only_d <= UInt<1>("h00")
    wire i0_jal : UInt<1>
    i0_jal <= UInt<1>("h00")
    wire i0_wen_r : UInt<1>
    i0_wen_r <= UInt<1>("h00")
    wire i0_x_ctl_en : UInt<1>
    i0_x_ctl_en <= UInt<1>("h00")
    wire i0_r_ctl_en : UInt<1>
    i0_r_ctl_en <= UInt<1>("h00")
    wire i0_wb_ctl_en : UInt<1>
    i0_wb_ctl_en <= UInt<1>("h00")
    wire i0_x_data_en : UInt<1>
    i0_x_data_en <= UInt<1>("h00")
    wire i0_r_data_en : UInt<1>
    i0_r_data_en <= UInt<1>("h00")
    wire i0_wb_data_en : UInt<1>
    i0_wb_data_en <= UInt<1>("h00")
    wire i0_wb1_data_en : UInt<1>
    i0_wb1_data_en <= UInt<1>("h00")
    wire i0_nonblock_load_stall : UInt<1>
    i0_nonblock_load_stall <= UInt<1>("h00")
    wire csr_read : UInt<1>
    csr_read <= UInt<1>("h00")
    wire lsu_decode_d : UInt<1>
    lsu_decode_d <= UInt<1>("h00")
    wire mul_decode_d : UInt<1>
    mul_decode_d <= UInt<1>("h00")
    wire div_decode_d : UInt<1>
    div_decode_d <= UInt<1>("h00")
    wire write_csr_data : UInt<32>
    write_csr_data <= UInt<1>("h00")
    wire i0_result_corr_r : UInt<32>
    i0_result_corr_r <= UInt<1>("h00")
    wire presync_stall : UInt<1>
    presync_stall <= UInt<1>("h00")
    wire i0_nonblock_div_stall : UInt<1>
    i0_nonblock_div_stall <= UInt<1>("h00")
    wire debug_fence : UInt<1>
    debug_fence <= UInt<1>("h00")
    wire i0_immed_d : UInt<32>
    i0_immed_d <= UInt<1>("h00")
    wire i0_result_x : UInt<32>
    i0_result_x <= UInt<1>("h00")
    wire i0_result_r : UInt<32>
    i0_result_r <= UInt<1>("h00")
    node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[el2_dec_decode_ctl.scala 211:51]
    node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[el2_dec_decode_ctl.scala 212:32]
    node _T_3 = or(_T_1, _T_2) @[el2_dec_decode_ctl.scala 211:73]
    node _T_4 = xor(io.dec_tlu_flush_extint, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 213:32]
    node _T_5 = or(_T_3, _T_4) @[el2_dec_decode_ctl.scala 212:56]
    node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[el2_dec_decode_ctl.scala 214:32]
    node _T_7 = or(_T_5, _T_6) @[el2_dec_decode_ctl.scala 213:56]
    node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[el2_dec_decode_ctl.scala 215:32]
    node _T_9 = or(_T_7, _T_8) @[el2_dec_decode_ctl.scala 214:56]
    node _T_10 = xor(pause_state_in, pause_stall) @[el2_dec_decode_ctl.scala 216:32]
    node _T_11 = or(_T_9, _T_10) @[el2_dec_decode_ctl.scala 215:56]
    node _T_12 = xor(ps_stall_in, postsync_stall) @[el2_dec_decode_ctl.scala 217:32]
    node _T_13 = or(_T_11, _T_12) @[el2_dec_decode_ctl.scala 216:56]
    node _T_14 = xor(io.exu_flush_final, flush_final_r) @[el2_dec_decode_ctl.scala 218:32]
    node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56]
    node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32]
    node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56]
    node _T_17 = bits(data_gate_en, 0, 0) @[el2_dec_decode_ctl.scala 222:56]
    inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr.io.en <= _T_17 @[el2_lib.scala 485:16]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 226:62]
    node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[el2_dec_decode_ctl.scala 226:60]
    io.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 227:43]
    io.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 228:43]
    io.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 229:43]
    io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43]
    io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43]
    io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43]
    io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 233:43]
    io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43]
    io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 235:43]
    node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55]
    io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38]
    node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75]
    node _T_21 = or(_T_20, i0_pja_raw) @[el2_dec_decode_ctl.scala 237:90]
    node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103]
    node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56]
    node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54]
    node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:72]
    node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47]
    node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:106]
    node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:76]
    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:126]
    node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:124]
    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 241:47]
    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:74]
    node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:72]
    node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:62]
    node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:79]
    node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:101]
    node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72]
    node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94]
    node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92]
    io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56]
    node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:94]
    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116]
    node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:114]
    io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56]
    io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32]
    io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32]
    node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 247:47]
    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:86]
    node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:84]
    io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49]
    io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32]
    io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 250:56]
    node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36]
    i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 259:9]
    i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 259:9]
    node _T_41 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 260:25]
    node _T_42 = bits(_T_41, 0, 0) @[el2_dec_decode_ctl.scala 260:43]
    when _T_42 : @[el2_dec_decode_ctl.scala 260:50]
      wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 261:35]
      _T_43.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      _T_43.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35]
      i0_dp.legal <= _T_43.legal @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.pm_alu <= _T_43.pm_alu @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.fence_i <= _T_43.fence_i @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.fence <= _T_43.fence @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.rem <= _T_43.rem @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.div <= _T_43.div @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.low <= _T_43.low @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.rs2_sign <= _T_43.rs2_sign @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.rs1_sign <= _T_43.rs1_sign @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.mul <= _T_43.mul @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.mret <= _T_43.mret @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.ecall <= _T_43.ecall @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.ebreak <= _T_43.ebreak @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.postsync <= _T_43.postsync @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.presync <= _T_43.presync @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.csr_imm <= _T_43.csr_imm @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.csr_write <= _T_43.csr_write @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.csr_set <= _T_43.csr_set @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.csr_clr <= _T_43.csr_clr @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.csr_read <= _T_43.csr_read @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.word <= _T_43.word @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.half <= _T_43.half @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.by <= _T_43.by @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.jal <= _T_43.jal @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.blt <= _T_43.blt @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.bge <= _T_43.bge @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.bne <= _T_43.bne @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.beq <= _T_43.beq @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.condbr <= _T_43.condbr @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.unsign <= _T_43.unsign @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.slt <= _T_43.slt @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.srl <= _T_43.srl @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.sra <= _T_43.sra @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.sll <= _T_43.sll @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.lxor <= _T_43.lxor @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.lor <= _T_43.lor @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.land <= _T_43.land @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.sub <= _T_43.sub @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.add <= _T_43.add @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.lsu <= _T_43.lsu @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.store <= _T_43.store @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.load <= _T_43.load @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.pc <= _T_43.pc @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.imm20 <= _T_43.imm20 @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.shimm5 <= _T_43.shimm5 @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.rd <= _T_43.rd @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.imm12 <= _T_43.imm12 @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.rs2 <= _T_43.rs2 @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.rs1 <= _T_43.rs1 @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.alu <= _T_43.alu @[el2_dec_decode_ctl.scala 261:20]
      i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 262:20]
      i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 263:20]
      i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 264:20]
      i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 265:20]
      i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20]
      i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20]
      skip @[el2_dec_decode_ctl.scala 260:50]
    io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 271:25]
    node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38]
    node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49]
    node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58]
    node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:51]
    node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:55]
    node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26]
    node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:71]
    node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:51]
    node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:55]
    node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:71]
    node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20]
    io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26]
    io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26]
    io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 283:20]
    io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 284:20]
    io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 285:20]
    io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 286:20]
    io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 287:20]
    io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 288:20]
    io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 289:20]
    io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 290:20]
    io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 291:20]
    io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 292:20]
    io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 293:20]
    io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 294:20]
    io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 295:20]
    io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 296:20]
    io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 297:22]
    io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 298:22]
    io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 299:22]
    node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78]
    node _T_52 = bits(_T_51, 0, 0) @[el2_dec_decode_ctl.scala 303:137]
    node _T_53 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 303:158]
    node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78]
    node _T_55 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120]
    node _T_56 = bits(_T_54, 0, 0) @[el2_dec_decode_ctl.scala 303:129]
    node _T_57 = and(_T_55, _T_56) @[el2_dec_decode_ctl.scala 303:126]
    node _T_58 = bits(_T_57, 0, 0) @[el2_dec_decode_ctl.scala 303:137]
    node _T_59 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 303:158]
    node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78]
    node _T_61 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120]
    node _T_62 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129]
    node _T_63 = and(_T_61, _T_62) @[el2_dec_decode_ctl.scala 303:126]
    node _T_64 = bits(_T_63, 0, 0) @[el2_dec_decode_ctl.scala 303:120]
    node _T_65 = bits(_T_60, 0, 0) @[el2_dec_decode_ctl.scala 303:129]
    node _T_66 = and(_T_64, _T_65) @[el2_dec_decode_ctl.scala 303:126]
    node _T_67 = bits(_T_66, 0, 0) @[el2_dec_decode_ctl.scala 303:137]
    node _T_68 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 303:158]
    node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78]
    node _T_70 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120]
    node _T_71 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129]
    node _T_72 = and(_T_70, _T_71) @[el2_dec_decode_ctl.scala 303:126]
    node _T_73 = bits(_T_72, 0, 0) @[el2_dec_decode_ctl.scala 303:120]
    node _T_74 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129]
    node _T_75 = and(_T_73, _T_74) @[el2_dec_decode_ctl.scala 303:126]
    node _T_76 = bits(_T_75, 0, 0) @[el2_dec_decode_ctl.scala 303:120]
    node _T_77 = bits(_T_69, 0, 0) @[el2_dec_decode_ctl.scala 303:129]
    node _T_78 = and(_T_76, _T_77) @[el2_dec_decode_ctl.scala 303:126]
    node _T_79 = bits(_T_78, 0, 0) @[el2_dec_decode_ctl.scala 303:137]
    node _T_80 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 303:158]
    node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_84 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_85 = or(_T_81, _T_82) @[Mux.scala 27:72]
    node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72]
    node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72]
    wire _T_88 : UInt<4> @[Mux.scala 27:72]
    _T_88 <= _T_87 @[Mux.scala 27:72]
    cam_wen <= _T_88 @[el2_dec_decode_ctl.scala 303:11]
    cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25]
    node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54]
    node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63]
    node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48]
    node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31]
    node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116]
    reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_90 : @[Reg.scala 28:19]
      nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56]
    node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
    node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45]
    node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87]
    cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26]
    node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
    node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45]
    node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:88]
    cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27]
    wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
    _T_97.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_97.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_97.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    cam_in[0].bits.rd <= _T_97.bits.rd @[el2_dec_decode_ctl.scala 323:14]
    cam_in[0].bits.tag <= _T_97.bits.tag @[el2_dec_decode_ctl.scala 323:14]
    cam_in[0].bits.wb <= _T_97.bits.wb @[el2_dec_decode_ctl.scala 323:14]
    cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14]
    cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 324:11]
    cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 324:11]
    cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 324:11]
    cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11]
    node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
    when _T_98 : @[el2_dec_decode_ctl.scala 326:39]
      cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20]
      skip @[el2_dec_decode_ctl.scala 326:39]
    node _T_99 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 329:17]
    node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
    when _T_100 : @[el2_dec_decode_ctl.scala 329:28]
      cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
      cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
      cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
      cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
      skip @[el2_dec_decode_ctl.scala 329:28]
    else : @[el2_dec_decode_ctl.scala 334:131]
      node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
      node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
      node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
      node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64]
      node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
      node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105]
      node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44]
      when _T_107 : @[el2_dec_decode_ctl.scala 334:131]
        cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
        skip @[el2_dec_decode_ctl.scala 334:131]
      else : @[el2_dec_decode_ctl.scala 336:16]
        cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22]
        cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22]
        cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 337:22]
        cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22]
        skip @[el2_dec_decode_ctl.scala 336:16]
    node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
    node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
    node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44]
    node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
    node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:100]
    when _T_112 : @[el2_dec_decode_ctl.scala 339:122]
      cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
      skip @[el2_dec_decode_ctl.scala 339:122]
    when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
      cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
      skip @[el2_dec_decode_ctl.scala 343:32]
    wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
    _T_113.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_113.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_113.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47]
    _T_114.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 347:47]
    _T_114.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 347:47]
    _T_114.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 347:47]
    _T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47]
    cam_raw[0].bits.rd <= _T_114.bits.rd @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[0].bits.tag <= _T_114.bits.tag @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[0].bits.wb <= _T_114.bits.wb @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15]
    node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
    node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:71]
    nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28]
    node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
    node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45]
    node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:87]
    cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26]
    node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
    node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45]
    node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:88]
    cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27]
    wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
    _T_123.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_123.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_123.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    cam_in[1].bits.rd <= _T_123.bits.rd @[el2_dec_decode_ctl.scala 323:14]
    cam_in[1].bits.tag <= _T_123.bits.tag @[el2_dec_decode_ctl.scala 323:14]
    cam_in[1].bits.wb <= _T_123.bits.wb @[el2_dec_decode_ctl.scala 323:14]
    cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14]
    cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 324:11]
    cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 324:11]
    cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 324:11]
    cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11]
    node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
    when _T_124 : @[el2_dec_decode_ctl.scala 326:39]
      cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20]
      skip @[el2_dec_decode_ctl.scala 326:39]
    node _T_125 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 329:17]
    node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
    when _T_126 : @[el2_dec_decode_ctl.scala 329:28]
      cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
      cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
      cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
      cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
      skip @[el2_dec_decode_ctl.scala 329:28]
    else : @[el2_dec_decode_ctl.scala 334:131]
      node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
      node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
      node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
      node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64]
      node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
      node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105]
      node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44]
      when _T_133 : @[el2_dec_decode_ctl.scala 334:131]
        cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
        skip @[el2_dec_decode_ctl.scala 334:131]
      else : @[el2_dec_decode_ctl.scala 336:16]
        cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22]
        cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22]
        cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 337:22]
        cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22]
        skip @[el2_dec_decode_ctl.scala 336:16]
    node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
    node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
    node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44]
    node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
    node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:100]
    when _T_138 : @[el2_dec_decode_ctl.scala 339:122]
      cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
      skip @[el2_dec_decode_ctl.scala 339:122]
    when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
      cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
      skip @[el2_dec_decode_ctl.scala 343:32]
    wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
    _T_139.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_139.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_139.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47]
    _T_140.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 347:47]
    _T_140.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 347:47]
    _T_140.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 347:47]
    _T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47]
    cam_raw[1].bits.rd <= _T_140.bits.rd @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[1].bits.tag <= _T_140.bits.tag @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[1].bits.wb <= _T_140.bits.wb @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15]
    node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
    node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:71]
    nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28]
    node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
    node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45]
    node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:87]
    cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26]
    node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
    node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45]
    node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:88]
    cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27]
    wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
    _T_149.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_149.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_149.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    cam_in[2].bits.rd <= _T_149.bits.rd @[el2_dec_decode_ctl.scala 323:14]
    cam_in[2].bits.tag <= _T_149.bits.tag @[el2_dec_decode_ctl.scala 323:14]
    cam_in[2].bits.wb <= _T_149.bits.wb @[el2_dec_decode_ctl.scala 323:14]
    cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14]
    cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 324:11]
    cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 324:11]
    cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 324:11]
    cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11]
    node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
    when _T_150 : @[el2_dec_decode_ctl.scala 326:39]
      cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20]
      skip @[el2_dec_decode_ctl.scala 326:39]
    node _T_151 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 329:17]
    node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
    when _T_152 : @[el2_dec_decode_ctl.scala 329:28]
      cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
      cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
      cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
      cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
      skip @[el2_dec_decode_ctl.scala 329:28]
    else : @[el2_dec_decode_ctl.scala 334:131]
      node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
      node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
      node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
      node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64]
      node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
      node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105]
      node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44]
      when _T_159 : @[el2_dec_decode_ctl.scala 334:131]
        cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
        skip @[el2_dec_decode_ctl.scala 334:131]
      else : @[el2_dec_decode_ctl.scala 336:16]
        cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22]
        cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22]
        cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 337:22]
        cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22]
        skip @[el2_dec_decode_ctl.scala 336:16]
    node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
    node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
    node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44]
    node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
    node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:100]
    when _T_164 : @[el2_dec_decode_ctl.scala 339:122]
      cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
      skip @[el2_dec_decode_ctl.scala 339:122]
    when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
      cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
      skip @[el2_dec_decode_ctl.scala 343:32]
    wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
    _T_165.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_165.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_165.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47]
    _T_166.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 347:47]
    _T_166.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 347:47]
    _T_166.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 347:47]
    _T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47]
    cam_raw[2].bits.rd <= _T_166.bits.rd @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[2].bits.tag <= _T_166.bits.tag @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[2].bits.wb <= _T_166.bits.wb @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15]
    node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
    node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:71]
    nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28]
    node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
    node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45]
    node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:87]
    cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26]
    node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
    node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45]
    node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:88]
    cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27]
    wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
    _T_175.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_175.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_175.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    _T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
    cam_in[3].bits.rd <= _T_175.bits.rd @[el2_dec_decode_ctl.scala 323:14]
    cam_in[3].bits.tag <= _T_175.bits.tag @[el2_dec_decode_ctl.scala 323:14]
    cam_in[3].bits.wb <= _T_175.bits.wb @[el2_dec_decode_ctl.scala 323:14]
    cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14]
    cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 324:11]
    cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 324:11]
    cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 324:11]
    cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11]
    node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
    when _T_176 : @[el2_dec_decode_ctl.scala 326:39]
      cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20]
      skip @[el2_dec_decode_ctl.scala 326:39]
    node _T_177 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 329:17]
    node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
    when _T_178 : @[el2_dec_decode_ctl.scala 329:28]
      cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
      cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
      cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
      cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
      skip @[el2_dec_decode_ctl.scala 329:28]
    else : @[el2_dec_decode_ctl.scala 334:131]
      node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
      node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
      node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
      node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64]
      node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
      node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105]
      node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44]
      when _T_185 : @[el2_dec_decode_ctl.scala 334:131]
        cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
        skip @[el2_dec_decode_ctl.scala 334:131]
      else : @[el2_dec_decode_ctl.scala 336:16]
        cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22]
        cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22]
        cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 337:22]
        cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22]
        skip @[el2_dec_decode_ctl.scala 336:16]
    node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
    node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
    node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44]
    node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
    node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:100]
    when _T_190 : @[el2_dec_decode_ctl.scala 339:122]
      cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
      skip @[el2_dec_decode_ctl.scala 339:122]
    when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
      cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
      skip @[el2_dec_decode_ctl.scala 343:32]
    wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
    _T_191.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_191.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_191.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    _T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
    reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47]
    _T_192.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 347:47]
    _T_192.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 347:47]
    _T_192.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 347:47]
    _T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47]
    cam_raw[3].bits.rd <= _T_192.bits.rd @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[3].bits.tag <= _T_192.bits.tag @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[3].bits.wb <= _T_192.bits.wb @[el2_dec_decode_ctl.scala 347:15]
    cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15]
    node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
    node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71]
    nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28]
    io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29]
    node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49]
    node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81]
    node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95]
    node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95]
    node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95]
    node _T_199 = bits(_T_198, 0, 0) @[el2_dec_decode_ctl.scala 354:99]
    node _T_200 = and(io.lsu_nonblock_load_data_valid, _T_199) @[el2_dec_decode_ctl.scala 354:64]
    node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 354:109]
    node _T_202 = and(_T_200, _T_201) @[el2_dec_decode_ctl.scala 354:106]
    io.dec_nonblock_load_wen <= _T_202 @[el2_dec_decode_ctl.scala 354:28]
    node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 355:54]
    node _T_204 = and(_T_203, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 355:66]
    node _T_205 = and(_T_204, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 355:97]
    node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 355:137]
    node _T_207 = and(_T_206, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 355:149]
    node _T_208 = and(_T_207, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 355:180]
    node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[el2_dec_decode_ctl.scala 355:118]
    i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26]
    node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
    node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
    node _T_211 = and(_T_210, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
    node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:126]
    node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
    node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:141]
    node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:192]
    node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
    node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:207]
    node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
    node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
    node _T_220 = and(_T_219, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
    node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:126]
    node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
    node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:141]
    node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:192]
    node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
    node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:207]
    node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
    node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
    node _T_229 = and(_T_228, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
    node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:126]
    node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
    node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:141]
    node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:192]
    node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
    node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:207]
    node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
    node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
    node _T_238 = and(_T_237, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
    node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:126]
    node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
    node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:141]
    node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:192]
    node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
    node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:207]
    node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69]
    node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69]
    node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69]
    node _T_247 = or(_T_214, _T_223) @[el2_dec_decode_ctl.scala 360:102]
    node _T_248 = or(_T_247, _T_232) @[el2_dec_decode_ctl.scala 360:102]
    node ld_stall_1 = or(_T_248, _T_241) @[el2_dec_decode_ctl.scala 360:102]
    node _T_249 = or(_T_217, _T_226) @[el2_dec_decode_ctl.scala 360:134]
    node _T_250 = or(_T_249, _T_235) @[el2_dec_decode_ctl.scala 360:134]
    node ld_stall_2 = or(_T_250, _T_244) @[el2_dec_decode_ctl.scala 360:134]
    io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 361:29]
    node _T_251 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 362:38]
    node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 362:51]
    i0_nonblock_load_stall <= _T_252 @[el2_dec_decode_ctl.scala 362:25]
    node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 371:34]
    node i0_br_unpred = and(i0_dp.jal, _T_253) @[el2_dec_decode_ctl.scala 371:32]
    node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15]
    node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 383:16]
    node _T_257 = bits(_T_256, 0, 0) @[el2_dec_decode_ctl.scala 383:30]
    node _T_258 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 384:6]
    node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 384:16]
    node _T_260 = bits(_T_259, 0, 0) @[el2_dec_decode_ctl.scala 384:30]
    node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 385:18]
    node _T_262 = and(csr_read, _T_261) @[el2_dec_decode_ctl.scala 385:16]
    node _T_263 = bits(_T_262, 0, 0) @[el2_dec_decode_ctl.scala 385:30]
    node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16]
    node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16]
    node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16]
    node _T_267 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_266) @[Mux.scala 98:16]
    node _T_268 = mux(_T_263, UInt<4>("h05"), _T_267) @[Mux.scala 98:16]
    node _T_269 = mux(_T_260, UInt<4>("h06"), _T_268) @[Mux.scala 98:16]
    node _T_270 = mux(_T_257, UInt<4>("h07"), _T_269) @[Mux.scala 98:16]
    node _T_271 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_270) @[Mux.scala 98:16]
    node _T_272 = mux(i0_dp.ecall, UInt<4>("h09"), _T_271) @[Mux.scala 98:16]
    node _T_273 = mux(i0_dp.fence, UInt<4>("h0a"), _T_272) @[Mux.scala 98:16]
    node _T_274 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_273) @[Mux.scala 98:16]
    node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16]
    node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16]
    node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16]
    node _T_278 = and(_T_255, _T_277) @[el2_dec_decode_ctl.scala 375:49]
    d_t.pmu_i0_itype <= _T_278 @[el2_dec_decode_ctl.scala 375:21]
    inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 392:22]
    i0_dec.clock <= clock
    i0_dec.reset <= reset
    i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 393:16]
    i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 394:12]
    i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 394:12]
    reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 396:45]
    _T_279 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 396:45]
    lsu_idle <= _T_279 @[el2_dec_decode_ctl.scala 396:11]
    node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 399:73]
    node _T_281 = and(leak1_i1_stall, _T_280) @[el2_dec_decode_ctl.scala 399:71]
    node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[el2_dec_decode_ctl.scala 399:53]
    leak1_i1_stall_in <= _T_282 @[el2_dec_decode_ctl.scala 399:21]
    reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:56]
    _T_283 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 400:56]
    leak1_i1_stall <= _T_283 @[el2_dec_decode_ctl.scala 400:21]
    leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 401:14]
    node _T_284 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 402:45]
    node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 402:83]
    node _T_286 = and(leak1_i0_stall, _T_285) @[el2_dec_decode_ctl.scala 402:81]
    node _T_287 = or(_T_284, _T_286) @[el2_dec_decode_ctl.scala 402:63]
    leak1_i0_stall_in <= _T_287 @[el2_dec_decode_ctl.scala 402:21]
    reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 403:56]
    _T_288 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 403:56]
    leak1_i0_stall <= _T_288 @[el2_dec_decode_ctl.scala 403:21]
    node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 407:29]
    node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 407:36]
    node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 407:46]
    node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 407:53]
    node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58]
    node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58]
    node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58]
    node _T_295 = bits(i0_pcall_imm, 11, 11) @[el2_dec_decode_ctl.scala 408:46]
    node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 408:51]
    node _T_297 = bits(i0_pcall_imm, 19, 12) @[el2_dec_decode_ctl.scala 408:71]
    node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 408:79]
    node _T_299 = bits(i0_pcall_imm, 19, 12) @[el2_dec_decode_ctl.scala 408:104]
    node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 408:112]
    node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 408:33]
    node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 409:47]
    node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 409:76]
    node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 409:98]
    node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 409:89]
    node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 409:65]
    node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 410:47]
    node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 410:76]
    node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 410:98]
    node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 410:89]
    node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 410:67]
    node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 410:65]
    node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 411:38]
    i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 411:20]
    node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 412:38]
    i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 412:20]
    node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 413:38]
    i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 413:20]
    node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 414:38]
    i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 414:20]
    node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 415:41]
    node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 415:55]
    node _T_316 = bits(i0_pcall_imm, 11, 0) @[el2_dec_decode_ctl.scala 415:75]
    node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 415:90]
    node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 415:97]
    node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 415:103]
    node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 415:113]
    node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58]
    node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58]
    node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58]
    node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 415:26]
    i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 415:20]
    node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 417:37]
    node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 417:65]
    node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 417:55]
    node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 417:89]
    node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 417:111]
    node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 417:101]
    node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 417:79]
    node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 418:32]
    i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 418:15]
    node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 419:32]
    i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 419:15]
    node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:35]
    node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 420:32]
    node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:52]
    node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 420:50]
    node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:67]
    node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 420:65]
    i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 420:15]
    io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 423:21]
    io.div_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 424:26]
    io.div_p.bits.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 425:26]
    io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 427:21]
    io.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 428:26]
    io.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 429:26]
    io.mul_p.bits.low <= i0_dp.low @[el2_dec_decode_ctl.scala 430:26]
    reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 432:58]
    _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 432:58]
    io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 432:23]
    wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.bits.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27]
    io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.dma <= _T_340.bits.dma @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.unsign <= _T_340.bits.unsign @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.store <= _T_340.bits.store @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.load <= _T_340.bits.load @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.dword <= _T_340.bits.dword @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.word <= _T_340.bits.word @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.half <= _T_340.bits.half @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.by <= _T_340.bits.by @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[el2_dec_decode_ctl.scala 434:12]
    io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 434:12]
    when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 435:29]
      io.lsu_p.bits.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 436:29]
      io.lsu_p.bits.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 437:29]
      io.lsu_p.bits.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 438:29]
      io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 439:24]
      skip @[el2_dec_decode_ctl.scala 435:29]
    else : @[el2_dec_decode_ctl.scala 440:15]
      io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 441:35]
      io.lsu_p.bits.load <= i0_dp.load @[el2_dec_decode_ctl.scala 442:40]
      io.lsu_p.bits.store <= i0_dp.store @[el2_dec_decode_ctl.scala 443:40]
      io.lsu_p.bits.by <= i0_dp.by @[el2_dec_decode_ctl.scala 444:40]
      io.lsu_p.bits.half <= i0_dp.half @[el2_dec_decode_ctl.scala 445:40]
      io.lsu_p.bits.word <= i0_dp.word @[el2_dec_decode_ctl.scala 446:40]
      io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 447:40]
      io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 448:40]
      io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 449:40]
      io.lsu_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 450:40]
      skip @[el2_dec_decode_ctl.scala 440:15]
    io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 454:21]
    node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 455:56]
    node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 455:36]
    csr_read <= _T_342 @[el2_dec_decode_ctl.scala 455:18]
    node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 457:42]
    node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 457:40]
    node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 458:61]
    node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 458:41]
    node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:59]
    node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 459:39]
    node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 460:59]
    node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 460:39]
    node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 462:41]
    node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 462:39]
    i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 462:23]
    node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 463:42]
    node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 463:58]
    io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24]
    node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30]
    io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24]
    io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23]
    node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39]
    node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53]
    node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51]
    io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20]
    node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50]
    node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85]
    node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64]
    node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100]
    node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118]
    node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132]
    node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130]
    io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27]
    reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52]
    csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52]
    reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 477:51]
    csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 477:51]
    reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 478:51]
    csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 478:51]
    reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 479:53]
    csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 479:53]
    reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:51]
    csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 480:51]
    node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 483:27]
    node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 483:48]
    inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_1.io.en <= _T_363 @[el2_lib.scala 511:17]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    csrimm_x <= _T_362 @[el2_lib.scala 514:16]
    node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 484:62]
    inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_2.io.en <= _T_364 @[el2_lib.scala 511:17]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 514:16]
    node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 487:15]
    wire _T_366 : UInt<1>[27] @[el2_lib.scala 162:48]
    _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[10] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[11] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[12] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[13] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[14] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[15] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[16] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[17] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[18] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[19] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[20] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[21] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[22] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[23] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[24] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[25] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_366[26] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58]
    node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58]
    node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58]
    node _T_370 = cat(_T_369, _T_366[4]) @[Cat.scala 29:58]
    node _T_371 = cat(_T_370, _T_366[5]) @[Cat.scala 29:58]
    node _T_372 = cat(_T_371, _T_366[6]) @[Cat.scala 29:58]
    node _T_373 = cat(_T_372, _T_366[7]) @[Cat.scala 29:58]
    node _T_374 = cat(_T_373, _T_366[8]) @[Cat.scala 29:58]
    node _T_375 = cat(_T_374, _T_366[9]) @[Cat.scala 29:58]
    node _T_376 = cat(_T_375, _T_366[10]) @[Cat.scala 29:58]
    node _T_377 = cat(_T_376, _T_366[11]) @[Cat.scala 29:58]
    node _T_378 = cat(_T_377, _T_366[12]) @[Cat.scala 29:58]
    node _T_379 = cat(_T_378, _T_366[13]) @[Cat.scala 29:58]
    node _T_380 = cat(_T_379, _T_366[14]) @[Cat.scala 29:58]
    node _T_381 = cat(_T_380, _T_366[15]) @[Cat.scala 29:58]
    node _T_382 = cat(_T_381, _T_366[16]) @[Cat.scala 29:58]
    node _T_383 = cat(_T_382, _T_366[17]) @[Cat.scala 29:58]
    node _T_384 = cat(_T_383, _T_366[18]) @[Cat.scala 29:58]
    node _T_385 = cat(_T_384, _T_366[19]) @[Cat.scala 29:58]
    node _T_386 = cat(_T_385, _T_366[20]) @[Cat.scala 29:58]
    node _T_387 = cat(_T_386, _T_366[21]) @[Cat.scala 29:58]
    node _T_388 = cat(_T_387, _T_366[22]) @[Cat.scala 29:58]
    node _T_389 = cat(_T_388, _T_366[23]) @[Cat.scala 29:58]
    node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58]
    node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58]
    node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58]
    node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 487:53]
    node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58]
    node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 488:16]
    node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 488:5]
    node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72]
    wire csr_mask_x : UInt<32> @[Mux.scala 27:72]
    csr_mask_x <= _T_399 @[Mux.scala 27:72]
    node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 491:38]
    node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 491:35]
    node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 492:35]
    node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_406 = or(_T_403, _T_404) @[Mux.scala 27:72]
    node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72]
    wire write_csr_data_x : UInt @[Mux.scala 27:72]
    write_csr_data_x <= _T_407 @[Mux.scala 27:72]
    node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 495:49]
    node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 495:47]
    node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 495:109]
    node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 495:91]
    node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 495:76]
    node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 496:44]
    node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 496:61]
    node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 496:59]
    pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 496:18]
    reg _T_415 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 497:50]
    _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 497:50]
    pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 497:15]
    io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 498:22]
    reg _T_416 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 499:55]
    _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 499:55]
    tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 499:19]
    reg _T_417 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 500:55]
    _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 500:55]
    tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 500:19]
    node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 502:44]
    node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 502:64]
    node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 502:61]
    node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 502:41]
    io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 502:25]
    node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 505:59]
    node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 505:59]
    node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 506:8]
    node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 505:30]
    node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 507:34]
    node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 507:46]
    node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 507:61]
    node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 507:75]
    node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 507:99]
    inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
    rvclkhdr_3.clock <= clock
    rvclkhdr_3.reset <= reset
    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_3.io.en <= csr_data_wen @[el2_lib.scala 511:17]
    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_429 <= write_csr_data_in @[el2_lib.scala 514:16]
    write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18]
    node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49]
    node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30]
    io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24]
    node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43]
    node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63]
    node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67]
    node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48]
    node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67]
    node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 519:48]
    node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 520:40]
    debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 520:21]
    node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 523:34]
    node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 523:57]
    node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 523:73]
    node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 523:91]
    node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 526:36]
    node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 526:60]
    node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 526:104]
    node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 526:112]
    node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 526:99]
    node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 526:76]
    node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 528:34]
    io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 529:24]
    node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 530:40]
    node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 530:51]
    node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 530:37]
    wire _T_446 : UInt<1>[16] @[el2_lib.scala 162:48]
    _T_446[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[10] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[11] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[12] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[13] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[14] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_446[15] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_447 = cat(_T_446[0], _T_446[1]) @[Cat.scala 29:58]
    node _T_448 = cat(_T_447, _T_446[2]) @[Cat.scala 29:58]
    node _T_449 = cat(_T_448, _T_446[3]) @[Cat.scala 29:58]
    node _T_450 = cat(_T_449, _T_446[4]) @[Cat.scala 29:58]
    node _T_451 = cat(_T_450, _T_446[5]) @[Cat.scala 29:58]
    node _T_452 = cat(_T_451, _T_446[6]) @[Cat.scala 29:58]
    node _T_453 = cat(_T_452, _T_446[7]) @[Cat.scala 29:58]
    node _T_454 = cat(_T_453, _T_446[8]) @[Cat.scala 29:58]
    node _T_455 = cat(_T_454, _T_446[9]) @[Cat.scala 29:58]
    node _T_456 = cat(_T_455, _T_446[10]) @[Cat.scala 29:58]
    node _T_457 = cat(_T_456, _T_446[11]) @[Cat.scala 29:58]
    node _T_458 = cat(_T_457, _T_446[12]) @[Cat.scala 29:58]
    node _T_459 = cat(_T_458, _T_446[13]) @[Cat.scala 29:58]
    node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58]
    node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58]
    node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58]
    node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 531:27]
    node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:49]
    node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 534:47]
    node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 535:44]
    node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 535:42]
    inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
    rvclkhdr_4.clock <= clock
    rvclkhdr_4.reset <= reset
    rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_4.io.en <= illegal_inst_en @[el2_lib.scala 511:17]
    rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_465 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_465 <= i0_inst_d @[el2_lib.scala 514:16]
    io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 536:23]
    node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 537:40]
    node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 537:61]
    node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 537:59]
    illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 537:22]
    reg _T_469 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 538:54]
    _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 538:54]
    illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 538:19]
    node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 539:42]
    node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 541:40]
    node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 541:59]
    node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 541:81]
    node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 541:95]
    node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 542:20]
    node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 542:45]
    node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 542:62]
    node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 543:19]
    node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 543:36]
    node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 543:34]
    node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 542:79]
    node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 543:47]
    node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 543:72]
    node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 544:21]
    node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 544:45]
    node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 546:65]
    node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 546:39]
    node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 547:63]
    node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 547:38]
    node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 548:38]
    node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 548:57]
    node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:46]
    node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 552:44]
    node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:63]
    node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 552:61]
    node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:91]
    node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 552:89]
    io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 552:22]
    node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:46]
    node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 553:44]
    node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:63]
    node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 553:61]
    node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:91]
    node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 553:89]
    node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 554:46]
    io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 557:28]
    node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 558:51]
    node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 558:49]
    io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 558:27]
    node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 559:47]
    io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29]
    node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46]
    io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29]
    node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41]
    node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31]
    node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37]
    presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22]
    reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53]
    _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 568:53]
    postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 568:18]
    node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56]
    node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54]
    node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39]
    node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88]
    node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69]
    ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15]
    node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50]
    io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 572:26]
    node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 574:40]
    lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 574:16]
    node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 575:40]
    mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16]
    node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40]
    div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16]
    node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45]
    node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43]
    io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29]
    d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26]
    node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40]
    d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 582:26]
    node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 583:50]
    d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 583:26]
    d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 584:26]
    node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 586:44]
    node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:61]
    d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 586:26]
    d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 589:26]
    d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 590:26]
    d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 591:26]
    wire _T_519 : UInt<1>[4] @[el2_lib.scala 162:48]
    _T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 162:48]
    _T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 162:48]
    _T_519[2] <= io.dec_i0_decode_d @[el2_lib.scala 162:48]
    _T_519[3] <= io.dec_i0_decode_d @[el2_lib.scala 162:48]
    node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58]
    node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58]
    node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58]
    node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 593:56]
    d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 593:26]
    node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 596:33]
    inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 518:23]
    rvclkhdr_5.clock <= clock
    rvclkhdr_5.reset <= reset
    rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_5.io.en <= _T_524 @[el2_lib.scala 521:17]
    rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33]
    _T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_525.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_525.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33]
    _T_525.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33]
    _T_525.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_525.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33]
    _T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_525.legal <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16]
    _T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 524:16]
    _T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 524:16]
    _T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 524:16]
    _T_526.pmu_i0_itype <= d_t.pmu_i0_itype @[el2_lib.scala 524:16]
    _T_526.i0trigger <= d_t.i0trigger @[el2_lib.scala 524:16]
    _T_526.fence_i <= d_t.fence_i @[el2_lib.scala 524:16]
    _T_526.icaf_type <= d_t.icaf_type @[el2_lib.scala 524:16]
    _T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 524:16]
    _T_526.icaf <= d_t.icaf @[el2_lib.scala 524:16]
    _T_526.legal <= d_t.legal @[el2_lib.scala 524:16]
    x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 596:7]
    x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 596:7]
    x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 596:7]
    x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 596:7]
    x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 596:7]
    x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 596:7]
    x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 596:7]
    x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 596:7]
    x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 596:7]
    x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 596:7]
    x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 598:10]
    x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 598:10]
    wire _T_527 : UInt<1>[4] @[el2_lib.scala 162:48]
    _T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48]
    _T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48]
    _T_527[2] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48]
    _T_527[3] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48]
    node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58]
    node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58]
    node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58]
    node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 599:39]
    node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 599:37]
    x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 599:20]
    node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 601:36]
    inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 518:23]
    rvclkhdr_6.clock <= clock
    rvclkhdr_6.reset <= reset
    rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_6.io.en <= _T_533 @[el2_lib.scala 521:17]
    rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33]
    _T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_534.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_534.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33]
    _T_534.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33]
    _T_534.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_534.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33]
    _T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_534.legal <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16]
    _T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 524:16]
    _T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 524:16]
    _T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 524:16]
    _T_535.pmu_i0_itype <= x_t_in.pmu_i0_itype @[el2_lib.scala 524:16]
    _T_535.i0trigger <= x_t_in.i0trigger @[el2_lib.scala 524:16]
    _T_535.fence_i <= x_t_in.fence_i @[el2_lib.scala 524:16]
    _T_535.icaf_type <= x_t_in.icaf_type @[el2_lib.scala 524:16]
    _T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 524:16]
    _T_535.icaf <= x_t_in.icaf @[el2_lib.scala 524:16]
    _T_535.legal <= x_t_in.legal @[el2_lib.scala 524:16]
    r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 601:7]
    r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 601:7]
    r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 601:7]
    r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 601:7]
    r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 601:7]
    r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 601:7]
    r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 601:7]
    r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 601:7]
    r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 601:7]
    r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 601:7]
    reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 602:36]
    lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 602:36]
    reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 603:37]
    lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 603:37]
    r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10]
    r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10]
    node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61]
    wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48]
    _T_537[0] <= _T_536 @[el2_lib.scala 162:48]
    _T_537[1] <= _T_536 @[el2_lib.scala 162:48]
    _T_537[2] <= _T_536 @[el2_lib.scala 162:48]
    _T_537[3] <= _T_536 @[el2_lib.scala 162:48]
    node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58]
    node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58]
    node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58]
    node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82]
    node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105]
    r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33]
    r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33]
    node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35]
    when _T_543 : @[el2_dec_decode_ctl.scala 610:43]
      wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 610:66]
      _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66]
      r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 610:51]
      r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 610:51]
      skip @[el2_dec_decode_ctl.scala 610:43]
    io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39]
    io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39]
    node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58]
    io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39]
    reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52]
    _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52]
    flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 616:17]
    node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:46]
    node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 618:44]
    node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:60]
    node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 618:58]
    node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:88]
    node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 618:86]
    io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 618:22]
    node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 620:16]
    i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 620:11]
    node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 621:16]
    i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 621:11]
    node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 622:16]
    i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 622:11]
    node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 624:49]
    node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 624:38]
    io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 624:24]
    node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 625:49]
    node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 625:38]
    io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 625:24]
    node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 626:48]
    node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 626:37]
    io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 627:19]
    io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 628:19]
    node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 630:38]
    node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 631:27]
    node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 631:38]
    node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:5]
    node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72]
    wire _T_566 : UInt<32> @[Mux.scala 27:72]
    _T_566 <= _T_565 @[Mux.scala 27:72]
    io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 633:21]
    node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 638:38]
    wire _T_568 : UInt<1>[20] @[el2_lib.scala 162:48]
    _T_568[0] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[1] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[2] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[3] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[4] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[5] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[6] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[7] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[8] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[9] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[10] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[11] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[12] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[13] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[14] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[15] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[16] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[17] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[18] <= _T_567 @[el2_lib.scala 162:48]
    _T_568[19] <= _T_567 @[el2_lib.scala 162:48]
    node _T_569 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58]
    node _T_570 = cat(_T_569, _T_568[2]) @[Cat.scala 29:58]
    node _T_571 = cat(_T_570, _T_568[3]) @[Cat.scala 29:58]
    node _T_572 = cat(_T_571, _T_568[4]) @[Cat.scala 29:58]
    node _T_573 = cat(_T_572, _T_568[5]) @[Cat.scala 29:58]
    node _T_574 = cat(_T_573, _T_568[6]) @[Cat.scala 29:58]
    node _T_575 = cat(_T_574, _T_568[7]) @[Cat.scala 29:58]
    node _T_576 = cat(_T_575, _T_568[8]) @[Cat.scala 29:58]
    node _T_577 = cat(_T_576, _T_568[9]) @[Cat.scala 29:58]
    node _T_578 = cat(_T_577, _T_568[10]) @[Cat.scala 29:58]
    node _T_579 = cat(_T_578, _T_568[11]) @[Cat.scala 29:58]
    node _T_580 = cat(_T_579, _T_568[12]) @[Cat.scala 29:58]
    node _T_581 = cat(_T_580, _T_568[13]) @[Cat.scala 29:58]
    node _T_582 = cat(_T_581, _T_568[14]) @[Cat.scala 29:58]
    node _T_583 = cat(_T_582, _T_568[15]) @[Cat.scala 29:58]
    node _T_584 = cat(_T_583, _T_568[16]) @[Cat.scala 29:58]
    node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58]
    node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58]
    node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58]
    node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 638:46]
    node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58]
    wire _T_590 : UInt<1>[27] @[el2_lib.scala 162:48]
    _T_590[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[10] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[11] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[12] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[13] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[14] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[15] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[16] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[17] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[18] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[19] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[20] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[21] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[22] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[23] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[24] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[25] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_590[26] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_591 = cat(_T_590[0], _T_590[1]) @[Cat.scala 29:58]
    node _T_592 = cat(_T_591, _T_590[2]) @[Cat.scala 29:58]
    node _T_593 = cat(_T_592, _T_590[3]) @[Cat.scala 29:58]
    node _T_594 = cat(_T_593, _T_590[4]) @[Cat.scala 29:58]
    node _T_595 = cat(_T_594, _T_590[5]) @[Cat.scala 29:58]
    node _T_596 = cat(_T_595, _T_590[6]) @[Cat.scala 29:58]
    node _T_597 = cat(_T_596, _T_590[7]) @[Cat.scala 29:58]
    node _T_598 = cat(_T_597, _T_590[8]) @[Cat.scala 29:58]
    node _T_599 = cat(_T_598, _T_590[9]) @[Cat.scala 29:58]
    node _T_600 = cat(_T_599, _T_590[10]) @[Cat.scala 29:58]
    node _T_601 = cat(_T_600, _T_590[11]) @[Cat.scala 29:58]
    node _T_602 = cat(_T_601, _T_590[12]) @[Cat.scala 29:58]
    node _T_603 = cat(_T_602, _T_590[13]) @[Cat.scala 29:58]
    node _T_604 = cat(_T_603, _T_590[14]) @[Cat.scala 29:58]
    node _T_605 = cat(_T_604, _T_590[15]) @[Cat.scala 29:58]
    node _T_606 = cat(_T_605, _T_590[16]) @[Cat.scala 29:58]
    node _T_607 = cat(_T_606, _T_590[17]) @[Cat.scala 29:58]
    node _T_608 = cat(_T_607, _T_590[18]) @[Cat.scala 29:58]
    node _T_609 = cat(_T_608, _T_590[19]) @[Cat.scala 29:58]
    node _T_610 = cat(_T_609, _T_590[20]) @[Cat.scala 29:58]
    node _T_611 = cat(_T_610, _T_590[21]) @[Cat.scala 29:58]
    node _T_612 = cat(_T_611, _T_590[22]) @[Cat.scala 29:58]
    node _T_613 = cat(_T_612, _T_590[23]) @[Cat.scala 29:58]
    node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58]
    node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58]
    node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58]
    node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 639:43]
    node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58]
    node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 640:38]
    wire _T_620 : UInt<1>[12] @[el2_lib.scala 162:48]
    _T_620[0] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[1] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[2] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[3] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[4] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[5] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[6] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[7] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[8] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[9] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[10] <= _T_619 @[el2_lib.scala 162:48]
    _T_620[11] <= _T_619 @[el2_lib.scala 162:48]
    node _T_621 = cat(_T_620[0], _T_620[1]) @[Cat.scala 29:58]
    node _T_622 = cat(_T_621, _T_620[2]) @[Cat.scala 29:58]
    node _T_623 = cat(_T_622, _T_620[3]) @[Cat.scala 29:58]
    node _T_624 = cat(_T_623, _T_620[4]) @[Cat.scala 29:58]
    node _T_625 = cat(_T_624, _T_620[5]) @[Cat.scala 29:58]
    node _T_626 = cat(_T_625, _T_620[6]) @[Cat.scala 29:58]
    node _T_627 = cat(_T_626, _T_620[7]) @[Cat.scala 29:58]
    node _T_628 = cat(_T_627, _T_620[8]) @[Cat.scala 29:58]
    node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58]
    node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58]
    node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58]
    node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 640:46]
    node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 640:56]
    node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 640:63]
    node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58]
    node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58]
    node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58]
    node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 641:30]
    wire _T_640 : UInt<1>[12] @[el2_lib.scala 162:48]
    _T_640[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[10] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_640[11] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58]
    node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58]
    node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58]
    node _T_644 = cat(_T_643, _T_640[4]) @[Cat.scala 29:58]
    node _T_645 = cat(_T_644, _T_640[5]) @[Cat.scala 29:58]
    node _T_646 = cat(_T_645, _T_640[6]) @[Cat.scala 29:58]
    node _T_647 = cat(_T_646, _T_640[7]) @[Cat.scala 29:58]
    node _T_648 = cat(_T_647, _T_640[8]) @[Cat.scala 29:58]
    node _T_649 = cat(_T_648, _T_640[9]) @[Cat.scala 29:58]
    node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58]
    node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58]
    node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58]
    node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 642:26]
    node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 642:43]
    wire _T_655 : UInt<1>[27] @[el2_lib.scala 162:48]
    _T_655[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[10] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[11] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[12] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[13] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[14] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[15] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[16] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[17] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[18] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[19] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[20] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[21] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[22] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[23] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[24] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[25] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_655[26] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_656 = cat(_T_655[0], _T_655[1]) @[Cat.scala 29:58]
    node _T_657 = cat(_T_656, _T_655[2]) @[Cat.scala 29:58]
    node _T_658 = cat(_T_657, _T_655[3]) @[Cat.scala 29:58]
    node _T_659 = cat(_T_658, _T_655[4]) @[Cat.scala 29:58]
    node _T_660 = cat(_T_659, _T_655[5]) @[Cat.scala 29:58]
    node _T_661 = cat(_T_660, _T_655[6]) @[Cat.scala 29:58]
    node _T_662 = cat(_T_661, _T_655[7]) @[Cat.scala 29:58]
    node _T_663 = cat(_T_662, _T_655[8]) @[Cat.scala 29:58]
    node _T_664 = cat(_T_663, _T_655[9]) @[Cat.scala 29:58]
    node _T_665 = cat(_T_664, _T_655[10]) @[Cat.scala 29:58]
    node _T_666 = cat(_T_665, _T_655[11]) @[Cat.scala 29:58]
    node _T_667 = cat(_T_666, _T_655[12]) @[Cat.scala 29:58]
    node _T_668 = cat(_T_667, _T_655[13]) @[Cat.scala 29:58]
    node _T_669 = cat(_T_668, _T_655[14]) @[Cat.scala 29:58]
    node _T_670 = cat(_T_669, _T_655[15]) @[Cat.scala 29:58]
    node _T_671 = cat(_T_670, _T_655[16]) @[Cat.scala 29:58]
    node _T_672 = cat(_T_671, _T_655[17]) @[Cat.scala 29:58]
    node _T_673 = cat(_T_672, _T_655[18]) @[Cat.scala 29:58]
    node _T_674 = cat(_T_673, _T_655[19]) @[Cat.scala 29:58]
    node _T_675 = cat(_T_674, _T_655[20]) @[Cat.scala 29:58]
    node _T_676 = cat(_T_675, _T_655[21]) @[Cat.scala 29:58]
    node _T_677 = cat(_T_676, _T_655[22]) @[Cat.scala 29:58]
    node _T_678 = cat(_T_677, _T_655[23]) @[Cat.scala 29:58]
    node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58]
    node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58]
    node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58]
    node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 642:72]
    node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58]
    node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_686 = mux(i0_jalimm20, _T_638, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_687 = mux(i0_uiimm20, _T_652, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_688 = mux(_T_654, _T_683, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_689 = or(_T_684, _T_685) @[Mux.scala 27:72]
    node _T_690 = or(_T_689, _T_686) @[Mux.scala 27:72]
    node _T_691 = or(_T_690, _T_687) @[Mux.scala 27:72]
    node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72]
    wire _T_693 : UInt<32> @[Mux.scala 27:72]
    _T_693 <= _T_692 @[Mux.scala 27:72]
    i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 637:14]
    node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 644:46]
    i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 644:24]
    node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 646:44]
    i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 646:29]
    node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 647:44]
    i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 647:29]
    node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 648:44]
    i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 648:29]
    node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 650:71]
    reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16]
    when _T_698 : @[Reg.scala 16:19]
      i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23]
      i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23]
      i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23]
      skip @[Reg.scala 16:19]
    node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 651:71]
    reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16]
    when _T_699 : @[Reg.scala 16:19]
      i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23]
      i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23]
      i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23]
      skip @[Reg.scala 16:19]
    node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 652:83]
    reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 652:72]
    _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 652:72]
    node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58]
    i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 652:14]
    node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 654:43]
    node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 654:49]
    node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 654:53]
    i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 654:29]
    node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 655:43]
    node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 655:49]
    node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 655:53]
    i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 655:29]
    node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 656:43]
    node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 656:49]
    node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 656:53]
    i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 656:29]
    node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 657:44]
    node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 657:50]
    i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 657:29]
    node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 658:44]
    node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 658:50]
    i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 658:29]
    node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 659:44]
    node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 659:50]
    i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 659:29]
    node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 660:44]
    node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 660:50]
    i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 660:29]
    node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
    io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27]
    node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
    io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27]
    d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34]
    node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50]
    d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34]
    d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27]
    node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50]
    d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34]
    node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50]
    d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34]
    node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50]
    d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34]
    node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61]
    d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34]
    node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58]
    d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34]
    node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40]
    d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34]
    node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34]
    inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 518:23]
    rvclkhdr_7.clock <= clock
    rvclkhdr_7.reset <= reset
    rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17]
    rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33]
    _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
    _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16]
    _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16]
    _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16]
    _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16]
    _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16]
    _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16]
    _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16]
    _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16]
    _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16]
    _T_731.valid <= d_d.valid @[el2_lib.scala 524:16]
    x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7]
    x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7]
    x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7]
    wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20]
    x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10]
    x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10]
    node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49]
    node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47]
    node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78]
    node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76]
    x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27]
    node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35]
    node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33]
    node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64]
    node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62]
    x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20]
    node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36]
    inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 518:23]
    rvclkhdr_8.clock <= clock
    rvclkhdr_8.reset <= reset
    rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17]
    rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33]
    _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
    _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16]
    _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16]
    _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16]
    _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16]
    _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16]
    _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16]
    _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16]
    _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16]
    _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16]
    _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16]
    r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7]
    r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7]
    r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7]
    r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10]
    r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22]
    node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51]
    node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49]
    r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27]
    node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37]
    node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35]
    r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20]
    node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51]
    node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49]
    r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27]
    node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51]
    node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49]
    r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27]
    node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37]
    inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 518:23]
    rvclkhdr_9.clock <= clock
    rvclkhdr_9.reset <= reset
    rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17]
    rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33]
    _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
    _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16]
    _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16]
    _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16]
    _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16]
    _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16]
    _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16]
    _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16]
    _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16]
    _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16]
    _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16]
    wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7]
    wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7]
    wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7]
    io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27]
    node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47]
    node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45]
    i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25]
    node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49]
    node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47]
    node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70]
    node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68]
    io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32]
    io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26]
    node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57]
    inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 508:23]
    rvclkhdr_10.clock <= clock
    rvclkhdr_10.reset <= reset
    rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_10.io.en <= _T_760 @[el2_lib.scala 511:17]
    rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16]
    node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47]
    node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66]
    node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32]
    i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26]
    i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26]
    node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42]
    node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61]
    node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27]
    i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21]
    node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54]
    node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 711:52]
    node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 711:66]
    wire _T_770 : UInt<1>[10] @[el2_lib.scala 162:48]
    _T_770[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_770[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_771 = cat(_T_770[0], _T_770[1]) @[Cat.scala 29:58]
    node _T_772 = cat(_T_771, _T_770[2]) @[Cat.scala 29:58]
    node _T_773 = cat(_T_772, _T_770[3]) @[Cat.scala 29:58]
    node _T_774 = cat(_T_773, _T_770[4]) @[Cat.scala 29:58]
    node _T_775 = cat(_T_774, _T_770[5]) @[Cat.scala 29:58]
    node _T_776 = cat(_T_775, _T_770[6]) @[Cat.scala 29:58]
    node _T_777 = cat(_T_776, _T_770[7]) @[Cat.scala 29:58]
    node _T_778 = cat(_T_777, _T_770[8]) @[Cat.scala 29:58]
    node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58]
    node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58]
    node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58]
    node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 711:30]
    io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 711:24]
    wire last_br_immed_d : UInt<12>
    last_br_immed_d <= UInt<1>("h00")
    node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 713:48]
    wire _T_784 : UInt<1>[10] @[el2_lib.scala 162:48]
    _T_784[0] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[1] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[2] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[3] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[4] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[5] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[6] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[7] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[8] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    _T_784[9] <= UInt<1>("h00") @[el2_lib.scala 162:48]
    node _T_785 = cat(_T_784[0], _T_784[1]) @[Cat.scala 29:58]
    node _T_786 = cat(_T_785, _T_784[2]) @[Cat.scala 29:58]
    node _T_787 = cat(_T_786, _T_784[3]) @[Cat.scala 29:58]
    node _T_788 = cat(_T_787, _T_784[4]) @[Cat.scala 29:58]
    node _T_789 = cat(_T_788, _T_784[5]) @[Cat.scala 29:58]
    node _T_790 = cat(_T_789, _T_784[6]) @[Cat.scala 29:58]
    node _T_791 = cat(_T_790, _T_784[7]) @[Cat.scala 29:58]
    node _T_792 = cat(_T_791, _T_784[8]) @[Cat.scala 29:58]
    node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58]
    node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58]
    node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58]
    node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 713:25]
    last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 713:19]
    wire last_br_immed_x : UInt<12>
    last_br_immed_x <= UInt<1>("h00")
    node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 715:58]
    inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23]
    rvclkhdr_11.clock <= clock
    rvclkhdr_11.reset <= reset
    rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_11.io.en <= _T_797 @[el2_lib.scala 511:17]
    rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_798 <= last_br_immed_d @[el2_lib.scala 514:16]
    last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19]
    node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45]
    node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76]
    node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58]
    node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48]
    node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77]
    node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60]
    node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21]
    node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33]
    node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94]
    node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21]
    node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33]
    node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60]
    node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62]
    node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51]
    node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26]
    node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24]
    node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56]
    node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39]
    node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77]
    node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65]
    node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53]
    io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29]
    node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 731:55]
    node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 733:62]
    node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 733:60]
    node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 733:81]
    node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 733:79]
    node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 733:39]
    reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 735:54]
    _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 735:54]
    io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 735:21]
    node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 738:49]
    node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 738:88]
    node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 738:69]
    node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 739:25]
    node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 739:64]
    node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 739:45]
    node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 738:102]
    i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 738:26]
    node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 741:59]
    reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_829 : @[Reg.scala 28:19]
      _T_830 <= i0r.rd @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 741:19]
    node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 748:34]
    node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 748:57]
    inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 508:23]
    rvclkhdr_12.clock <= clock
    rvclkhdr_12.reset <= reset
    rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_12.io.en <= _T_832 @[el2_lib.scala 511:17]
    rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    div_inst <= _T_831 @[el2_lib.scala 514:16]
    node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 749:49]
    inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 508:23]
    rvclkhdr_13.clock <= clock
    rvclkhdr_13.reset <= reset
    rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_13.io.en <= _T_833 @[el2_lib.scala 511:17]
    rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16]
    node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 750:49]
    inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 508:23]
    rvclkhdr_14.clock <= clock
    rvclkhdr_14.reset <= reset
    rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_14.io.en <= _T_834 @[el2_lib.scala 511:17]
    rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16]
    node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 752:50]
    inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 508:23]
    rvclkhdr_15.clock <= clock
    rvclkhdr_15.reset <= reset
    rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_15.io.en <= _T_835 @[el2_lib.scala 511:17]
    rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16]
    node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:53]
    inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 508:23]
    rvclkhdr_16.clock <= clock
    rvclkhdr_16.reset <= reset
    rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_16.io.en <= _T_836 @[el2_lib.scala 511:17]
    rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_837 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_837 <= i0_inst_wb @[el2_lib.scala 514:16]
    io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 753:22]
    node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:53]
    inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 508:23]
    rvclkhdr_17.clock <= clock
    rvclkhdr_17.reset <= reset
    rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_17.io.en <= _T_838 @[el2_lib.scala 511:17]
    rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16]
    node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:49]
    inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 508:23]
    rvclkhdr_18.clock <= clock
    rvclkhdr_18.reset <= reset
    rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_18.io.en <= _T_839 @[el2_lib.scala 511:17]
    rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_840 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_840 <= i0_pc_wb @[el2_lib.scala 514:16]
    io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 756:20]
    node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:56]
    inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 508:23]
    rvclkhdr_19.clock <= clock
    rvclkhdr_19.reset <= reset
    rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_19.io.en <= _T_841 @[el2_lib.scala 511:17]
    rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 514:16]
    io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 759:27]
    node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 208:24]
    node _T_845 = bits(_T_843, 12, 1) @[el2_lib.scala 208:40]
    node _T_846 = add(_T_844, _T_845) @[el2_lib.scala 208:31]
    node _T_847 = bits(_T_842, 31, 13) @[el2_lib.scala 209:20]
    node _T_848 = add(_T_847, UInt<1>("h01")) @[el2_lib.scala 209:27]
    node _T_849 = tail(_T_848, 1) @[el2_lib.scala 209:27]
    node _T_850 = bits(_T_842, 31, 13) @[el2_lib.scala 210:20]
    node _T_851 = sub(_T_850, UInt<1>("h01")) @[el2_lib.scala 210:27]
    node _T_852 = tail(_T_851, 1) @[el2_lib.scala 210:27]
    node _T_853 = bits(_T_843, 12, 12) @[el2_lib.scala 211:22]
    node _T_854 = bits(_T_846, 12, 12) @[el2_lib.scala 212:39]
    node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_lib.scala 212:28]
    node _T_856 = xor(_T_853, _T_855) @[el2_lib.scala 212:26]
    node _T_857 = bits(_T_856, 0, 0) @[el2_lib.scala 212:64]
    node _T_858 = bits(_T_842, 31, 13) @[el2_lib.scala 212:76]
    node _T_859 = eq(_T_853, UInt<1>("h00")) @[el2_lib.scala 213:20]
    node _T_860 = bits(_T_846, 12, 12) @[el2_lib.scala 213:39]
    node _T_861 = and(_T_859, _T_860) @[el2_lib.scala 213:26]
    node _T_862 = bits(_T_861, 0, 0) @[el2_lib.scala 213:64]
    node _T_863 = bits(_T_846, 12, 12) @[el2_lib.scala 214:39]
    node _T_864 = eq(_T_863, UInt<1>("h00")) @[el2_lib.scala 214:28]
    node _T_865 = and(_T_853, _T_864) @[el2_lib.scala 214:26]
    node _T_866 = bits(_T_865, 0, 0) @[el2_lib.scala 214:64]
    node _T_867 = mux(_T_857, _T_858, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_868 = mux(_T_862, _T_849, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_869 = mux(_T_866, _T_852, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_870 = or(_T_867, _T_868) @[Mux.scala 27:72]
    node _T_871 = or(_T_870, _T_869) @[Mux.scala 27:72]
    wire _T_872 : UInt<19> @[Mux.scala 27:72]
    _T_872 <= _T_871 @[Mux.scala 27:72]
    node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 214:94]
    node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58]
    node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51]
    io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25]
    node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48]
    node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80]
    node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63]
    node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48]
    node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80]
    node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63]
    node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48]
    node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80]
    node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63]
    node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48]
    node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80]
    node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63]
    node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44]
    node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81]
    wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109]
    _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109]
    _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109]
    _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109]
    node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 774:61]
    node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 774:24]
    i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 774:18]
    i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 774:18]
    i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 774:18]
    node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 775:44]
    node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 775:83]
    node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 775:63]
    node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 775:24]
    i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 775:18]
    node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 776:44]
    node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 776:81]
    wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 776:109]
    _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109]
    _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109]
    _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109]
    node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 776:61]
    node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 776:24]
    i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 776:18]
    i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 776:18]
    i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 776:18]
    node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 777:44]
    node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 777:83]
    node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 777:63]
    node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 777:24]
    i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 777:18]
    i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 787:21]
    node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 788:43]
    node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 788:74]
    node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 788:58]
    node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 788:78]
    load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 788:27]
    node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 789:59]
    node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 789:43]
    node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 789:63]
    store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 789:25]
    store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 790:25]
    node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 794:62]
    node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 794:119]
    node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 794:89]
    node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 796:62]
    node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 796:119]
    node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 796:89]
    node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 799:41]
    node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 799:66]
    node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 799:45]
    node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 799:104]
    node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 799:108]
    node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 799:149]
    node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 799:175]
    node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 799:196]
    node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 799:153]
    node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58]
    node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58]
    i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 799:18]
    node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 801:41]
    node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 801:67]
    node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 801:45]
    node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 801:105]
    node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 801:109]
    node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 801:149]
    node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 801:175]
    node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 801:196]
    node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 801:153]
    node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58]
    node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58]
    i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 801:18]
    node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 803:54]
    node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 803:71]
    node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 803:89]
    node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 803:75]
    node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 803:109]
    node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 803:96]
    node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 803:113]
    node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 803:93]
    node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58]
    io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 803:34]
    node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 804:54]
    node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 804:71]
    node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 804:89]
    node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 804:75]
    node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 804:109]
    node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 804:96]
    node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 804:113]
    node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 804:93]
    node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58]
    io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 804:34]
    node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:17]
    node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 808:21]
    node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 809:17]
    node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 809:21]
    node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 810:19]
    node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 810:6]
    node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 810:38]
    node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 810:25]
    node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 810:23]
    node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 810:42]
    node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 810:78]
    node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_967 = or(_T_964, _T_965) @[Mux.scala 27:72]
    node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72]
    wire _T_969 : UInt<32> @[Mux.scala 27:72]
    _T_969 <= _T_968 @[Mux.scala 27:72]
    io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 807:31]
    node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:17]
    node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 813:21]
    node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 814:17]
    node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 814:21]
    node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 815:19]
    node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 815:6]
    node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 815:38]
    node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 815:25]
    node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 815:23]
    node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 815:42]
    node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 815:78]
    node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_984 = or(_T_981, _T_982) @[Mux.scala 27:72]
    node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72]
    wire _T_986 : UInt<32> @[Mux.scala 27:72]
    _T_986 <= _T_985 @[Mux.scala 27:72]
    io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 812:31]
    node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 817:68]
    node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 817:50]
    node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:89]
    node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 817:87]
    node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:114]
    node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 817:112]
    node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 817:131]
    io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 817:26]
    node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:6]
    node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 819:27]
    node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 819:39]
    node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 819:53]
    node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 819:70]
    node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:6]
    node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 820:27]
    node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 820:39]
    node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 820:54]
    node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 820:74]
    node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 820:84]
    node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58]
    node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72]
    wire _T_1009 : UInt<12> @[Mux.scala 27:72]
    _T_1009 <= _T_1008 @[Mux.scala 27:72]
    io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 818:23]
    
