;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu : 
  extmodule gated_latch : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_1 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_1 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_2 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_2 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_3 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_3 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_4 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_4 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_5 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_5 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_6 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_6 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_7 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_7 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_8 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_8 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_9 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_9 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_10 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_10 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_11 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_11 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_12 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_12 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_13 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_13 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_14 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_14 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_15 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_15 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_16 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_16 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_17 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_17 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_18 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_18 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_19 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_19 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module el2_exu_alu_ctl : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}}
    
    node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60]
    inst rvclkhdr of rvclkhdr_18 @[el2_lib.scala 508:23]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17]
    rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24]
    reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1 <= io.pc_in @[el2_lib.scala 514:16]
    io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12]
    wire result : UInt<32>
    result <= UInt<1>("h00")
    node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62]
    inst rvclkhdr_1 of rvclkhdr_19 @[el2_lib.scala 508:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17]
    rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24]
    reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_3 <= result @[el2_lib.scala 514:16]
    io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16]
    node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29]
    node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37]
    node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17]
    wire aout : UInt<33>
    aout <= UInt<1>("h00")
    node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25]
    node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58]
    node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
    node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70]
    node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58]
    node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55]
    node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55]
    node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
    node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80]
    node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80]
    node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58]
    node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58]
    node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58]
    node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132]
    node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132]
    node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
    node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157]
    node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157]
    node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14]
    aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8]
    node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18]
    node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22]
    node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:14]
    node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32]
    node _T_28 = eq(_T_27, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:29]
    node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27]
    node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44]
    node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37]
    node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61]
    node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71]
    node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66]
    node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83]
    node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:78]
    node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76]
    node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50]
    node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50]
    node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38]
    node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29]
    node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34]
    node _T_39 = eq(io.ap.unsign, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:30]
    node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51]
    node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44]
    node _T_42 = eq(cout, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:78]
    node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76]
    node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58]
    node ge = eq(lt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 51:29]
    node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19]
    node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50]
    node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16]
    node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50]
    node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39]
    node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39]
    node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15]
    node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50]
    node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39]
    node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39]
    node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16]
    node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50]
    node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39]
    node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39]
    wire _T_58 : SInt<32> @[Mux.scala 27:72]
    node _T_59 = asUInt(_T_45) @[Mux.scala 27:72]
    node _T_60 = asSInt(_T_59) @[Mux.scala 27:72]
    _T_58 <= _T_60 @[Mux.scala 27:72]
    wire _T_61 : SInt<32> @[Mux.scala 27:72]
    node _T_62 = asUInt(_T_49) @[Mux.scala 27:72]
    node _T_63 = asSInt(_T_62) @[Mux.scala 27:72]
    _T_61 <= _T_63 @[Mux.scala 27:72]
    wire _T_64 : SInt<32> @[Mux.scala 27:72]
    node _T_65 = asUInt(_T_53) @[Mux.scala 27:72]
    node _T_66 = asSInt(_T_65) @[Mux.scala 27:72]
    _T_64 <= _T_66 @[Mux.scala 27:72]
    wire _T_67 : SInt<32> @[Mux.scala 27:72]
    node _T_68 = asUInt(_T_57) @[Mux.scala 27:72]
    node _T_69 = asSInt(_T_68) @[Mux.scala 27:72]
    _T_67 <= _T_69 @[Mux.scala 27:72]
    node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
    node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
    node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
    node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
    node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72]
    node _T_75 = asSInt(_T_74) @[Mux.scala 27:72]
    node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72]
    node _T_77 = asSInt(_T_76) @[Mux.scala 27:72]
    node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72]
    node _T_79 = asSInt(_T_78) @[Mux.scala 27:72]
    wire lout : SInt<32> @[Mux.scala 27:72]
    node _T_80 = asUInt(_T_79) @[Mux.scala 27:72]
    node _T_81 = asSInt(_T_80) @[Mux.scala 27:72]
    lout <= _T_81 @[Mux.scala 27:72]
    node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15]
    node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60]
    node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58]
    node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38]
    node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38]
    node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15]
    node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60]
    node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58]
    node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15]
    node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60]
    node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58]
    node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72]
    node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72]
    wire shift_amount : UInt<6> @[Mux.scala 27:72]
    shift_amount <= _T_97 @[Mux.scala 27:72]
    wire shift_mask : UInt<32>
    shift_mask <= UInt<1>("h00")
    wire _T_98 : UInt<1>[5] @[el2_lib.scala 162:48]
    _T_98[0] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_98[1] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_98[2] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_98[3] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_98[4] <= io.ap.sll @[el2_lib.scala 162:48]
    node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58]
    node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58]
    node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58]
    node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58]
    node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70]
    node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61]
    node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39]
    shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14]
    wire shift_extend : UInt<63>
    shift_extend <= UInt<1>("h00")
    wire _T_106 : UInt<1>[31] @[el2_lib.scala 162:48]
    _T_106[0] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[1] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[2] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[3] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[4] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[5] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[6] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[7] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[8] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[9] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[10] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[11] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[12] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[13] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[14] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[15] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[16] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[17] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[18] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[19] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[20] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[21] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[22] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[23] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[24] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[25] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[26] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[27] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[28] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[29] <= io.ap.sra @[el2_lib.scala 162:48]
    _T_106[30] <= io.ap.sra @[el2_lib.scala 162:48]
    node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58]
    node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58]
    node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58]
    node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58]
    node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58]
    node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58]
    node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58]
    node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58]
    node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58]
    node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58]
    node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58]
    node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58]
    node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58]
    node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58]
    node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58]
    node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58]
    node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58]
    node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58]
    node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58]
    node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58]
    node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58]
    node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58]
    node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58]
    node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58]
    node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58]
    node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58]
    node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58]
    node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58]
    node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58]
    node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58]
    node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61]
    wire _T_138 : UInt<1>[31] @[el2_lib.scala 162:48]
    _T_138[0] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[1] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[2] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[3] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[4] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[5] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[6] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[7] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[8] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[9] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[10] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[11] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[12] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[13] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[14] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[15] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[16] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[17] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[18] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[19] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[20] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[21] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[22] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[23] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[24] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[25] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[26] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[27] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[28] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[29] <= _T_137 @[el2_lib.scala 162:48]
    _T_138[30] <= _T_137 @[el2_lib.scala 162:48]
    node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58]
    node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58]
    node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58]
    node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58]
    node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58]
    node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58]
    node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58]
    node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58]
    node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58]
    node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58]
    node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58]
    node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58]
    node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58]
    node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58]
    node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58]
    node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58]
    node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58]
    node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58]
    node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58]
    node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58]
    node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58]
    node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58]
    node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58]
    node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58]
    node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58]
    node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58]
    node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58]
    node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58]
    node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58]
    node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58]
    node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44]
    wire _T_170 : UInt<1>[31] @[el2_lib.scala 162:48]
    _T_170[0] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[1] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[2] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[3] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[4] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[5] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[6] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[7] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[8] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[9] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[10] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[11] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[12] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[13] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[14] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[15] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[16] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[17] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[18] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[19] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[20] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[21] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[22] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[23] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[24] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[25] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[26] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[27] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[28] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[29] <= io.ap.sll @[el2_lib.scala 162:48]
    _T_170[30] <= io.ap.sll @[el2_lib.scala 162:48]
    node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58]
    node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58]
    node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58]
    node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58]
    node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58]
    node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58]
    node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58]
    node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58]
    node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58]
    node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58]
    node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58]
    node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58]
    node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58]
    node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58]
    node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58]
    node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58]
    node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58]
    node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58]
    node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58]
    node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58]
    node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58]
    node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58]
    node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58]
    node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58]
    node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58]
    node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58]
    node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58]
    node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58]
    node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58]
    node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58]
    node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99]
    node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90]
    node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68]
    node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58]
    node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58]
    shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16]
    wire shift_long : UInt<63>
    shift_long <= UInt<1>("h00")
    node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47]
    node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32]
    shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14]
    node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27]
    node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46]
    node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34]
    node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41]
    node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53]
    node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41]
    node _T_212 = eq(io.ap.slt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 78:56]
    node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54]
    node _T_213 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 79:41]
    node _T_214 = or(_T_213, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 79:63]
    node sel_pc = or(_T_214, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 79:83]
    node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47]
    node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63]
    node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32]
    node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40]
    node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24]
    node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40]
    node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31]
    node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20]
    node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27]
    node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27]
    node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20]
    node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27]
    node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27]
    node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22]
    node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39]
    node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28]
    node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26]
    node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64]
    node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76]
    node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20]
    node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39]
    node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26]
    node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64]
    node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39]
    node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28]
    node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26]
    node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64]
    node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72]
    node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72]
    wire _T_247 : UInt<19> @[Mux.scala 27:72]
    _T_247 <= _T_246 @[Mux.scala 27:72]
    node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94]
    node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
    node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24]
    node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58]
    node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31]
    node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15]
    node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41]
    node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15]
    node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41]
    node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12]
    node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21]
    node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51]
    node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72]
    node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72]
    node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72]
    wire _T_267 : UInt<32> @[Mux.scala 27:72]
    _T_267 <= _T_266 @[Mux.scala 27:72]
    node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56]
    result <= _T_268 @[el2_exu_alu_ctl.scala 88:16]
    node _T_269 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 96:45]
    node _T_270 = or(_T_269, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 97:25]
    node any_jal = or(_T_270, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 98:25]
    node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40]
    node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59]
    node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46]
    node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85]
    node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72]
    node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104]
    node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91]
    node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110]
    node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42]
    node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63]
    node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61]
    node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79]
    node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77]
    node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104]
    node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123]
    node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141]
    node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139]
    node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89]
    io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26]
    node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37]
    node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49]
    node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62]
    node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28]
    io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22]
    node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47]
    node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45]
    node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82]
    node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62]
    node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:80]
    node _T_296 = neq(io.pp_in.bits.prett, _T_295) @[el2_exu_alu_ctl.scala 114:72]
    node target_mispredict = and(io.pp_in.bits.pret, _T_296) @[el2_exu_alu_ctl.scala 114:49]
    node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42]
    node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60]
    node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81]
    node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97]
    node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95]
    node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119]
    node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117]
    io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26]
    node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42]
    node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60]
    node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81]
    node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97]
    node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95]
    node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117]
    io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26]
    wire newhist : UInt<2>
    newhist <= UInt<1>("h00")
    node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:40]
    node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:65]
    node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:44]
    node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:92]
    node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:73]
    node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:96]
    node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:70]
    node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:25]
    node _T_318 = eq(_T_317, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:6]
    node _T_319 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:31]
    node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:29]
    node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:68]
    node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:72]
    node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:47]
    node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
    newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14]
    io.predict_p_out.bits.way <= io.pp_in.bits.way @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[el2_exu_alu_ctl.scala 125:30]
    io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30]
    node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:38]
    node _T_326 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:58]
    node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:56]
    node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:95]
    node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:76]
    io.predict_p_out.bits.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:35]
    io.predict_p_out.bits.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:35]
    io.predict_p_out.bits.hist <= newhist @[el2_exu_alu_ctl.scala 128:35]
    
  extmodule gated_latch_20 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_20 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_21 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_21 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_22 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_22 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module el2_exu_mul_ctl : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
    
    wire rs1_ext_in : SInt<33>
    rs1_ext_in <= asSInt(UInt<1>("h00"))
    wire rs2_ext_in : SInt<33>
    rs2_ext_in <= asSInt(UInt<1>("h00"))
    wire rs1_x : SInt<33>
    rs1_x <= asSInt(UInt<1>("h00"))
    wire rs2_x : SInt<33>
    rs2_x <= asSInt(UInt<1>("h00"))
    wire prod_x : SInt<66>
    prod_x <= asSInt(UInt<1>("h00"))
    wire low_x : UInt<1>
    low_x <= UInt<1>("h00")
    node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:55]
    node _T_1 = and(io.mul_p.bits.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:44]
    node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
    node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:71]
    rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14]
    node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:55]
    node _T_5 = and(io.mul_p.bits.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:44]
    node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
    node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:71]
    rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
    node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 29:52]
    inst rvclkhdr of rvclkhdr_20 @[el2_lib.scala 508:23]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr.io.en <= _T_8 @[el2_lib.scala 511:17]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16]
    low_x <= _T_9 @[el2_exu_mul_ctl.scala 29:9]
    node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 30:44]
    inst rvclkhdr_1 of rvclkhdr_21 @[el2_lib.scala 528:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 530:18]
    rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 531:17]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
    reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
    _T_11 <= rs1_ext_in @[el2_lib.scala 534:16]
    rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 30:9]
    node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 31:45]
    inst rvclkhdr_2 of rvclkhdr_22 @[el2_lib.scala 528:23]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 530:18]
    rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 531:17]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
    reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
    _T_13 <= rs2_ext_in @[el2_lib.scala 534:16]
    rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 31:9]
    node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 33:20]
    prod_x <= _T_14 @[el2_exu_mul_ctl.scala 33:10]
    node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:36]
    node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 34:29]
    node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 34:52]
    node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:67]
    node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 34:83]
    node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
    wire _T_23 : UInt<32> @[Mux.scala 27:72]
    _T_23 <= _T_22 @[Mux.scala 27:72]
    io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 34:15]
    
  extmodule gated_latch_23 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_23 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_24 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_24 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_25 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_25 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  extmodule gated_latch_26 : 
    output Q : Clock
    input CK : Clock
    input EN : UInt<1>
    input SE : UInt<1>
    
    defname = gated_latch
    
    
  module rvclkhdr_26 : 
    input clock : Clock
    input reset : Reset
    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
    
    inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26]
    clkhdr.SE is invalid
    clkhdr.EN is invalid
    clkhdr.CK is invalid
    clkhdr.Q is invalid
    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
    
  module el2_exu_div_ctl : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip scan_mode : UInt<1>, flip dp : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dividend : UInt<32>, flip divisor : UInt<32>, flip cancel : UInt<1>, out : UInt<32>, finish_dly : UInt<1>}
    
    wire run_state : UInt<1>
    run_state <= UInt<1>("h00")
    wire count : UInt<6>
    count <= UInt<6>("h00")
    wire m_ff : UInt<33>
    m_ff <= UInt<33>("h00")
    wire q_in : UInt<33>
    q_in <= UInt<33>("h00")
    wire q_ff : UInt<33>
    q_ff <= UInt<33>("h00")
    wire a_in : UInt<33>
    a_in <= UInt<33>("h00")
    wire a_ff : UInt<33>
    a_ff <= UInt<33>("h00")
    wire m_eff : UInt<33>
    m_eff <= UInt<33>("h00")
    wire dividend_neg_ff : UInt<1>
    dividend_neg_ff <= UInt<1>("h00")
    wire divisor_neg_ff : UInt<1>
    divisor_neg_ff <= UInt<1>("h00")
    wire dividend_comp : UInt<32>
    dividend_comp <= UInt<32>("h00")
    wire q_ff_comp : UInt<32>
    q_ff_comp <= UInt<32>("h00")
    wire a_ff_comp : UInt<32>
    a_ff_comp <= UInt<32>("h00")
    wire sign_ff : UInt<1>
    sign_ff <= UInt<1>("h00")
    wire rem_ff : UInt<1>
    rem_ff <= UInt<1>("h00")
    wire add : UInt<1>
    add <= UInt<1>("h00")
    wire a_eff : UInt<33>
    a_eff <= UInt<33>("h00")
    wire a_eff_shift : UInt<56>
    a_eff_shift <= UInt<56>("h00")
    wire rem_correct : UInt<1>
    rem_correct <= UInt<1>("h00")
    wire valid_ff_x : UInt<1>
    valid_ff_x <= UInt<1>("h00")
    wire finish_ff : UInt<1>
    finish_ff <= UInt<1>("h00")
    wire smallnum_case_ff : UInt<1>
    smallnum_case_ff <= UInt<1>("h00")
    wire smallnum_ff : UInt<4>
    smallnum_ff <= UInt<4>("h00")
    wire smallnum_case : UInt<1>
    smallnum_case <= UInt<1>("h00")
    wire count_in : UInt<6>
    count_in <= UInt<6>("h00")
    wire dividend_eff : UInt<32>
    dividend_eff <= UInt<32>("h00")
    wire a_shift : UInt<33>
    a_shift <= UInt<33>("h00")
    io.out <= UInt<1>("h00") @[el2_exu_div_ctl.scala 50:10]
    io.finish_dly <= UInt<1>("h00") @[el2_exu_div_ctl.scala 51:17]
    node _T = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 54:30]
    node valid_x = and(valid_ff_x, _T) @[el2_exu_div_ctl.scala 54:28]
    node _T_1 = bits(q_ff, 31, 4) @[el2_exu_div_ctl.scala 60:27]
    node _T_2 = eq(_T_1, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:34]
    node _T_3 = bits(m_ff, 31, 4) @[el2_exu_div_ctl.scala 60:50]
    node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:57]
    node _T_5 = and(_T_2, _T_4) @[el2_exu_div_ctl.scala 60:43]
    node _T_6 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 60:73]
    node _T_7 = neq(_T_6, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:80]
    node _T_8 = and(_T_5, _T_7) @[el2_exu_div_ctl.scala 60:66]
    node _T_9 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:91]
    node _T_10 = and(_T_8, _T_9) @[el2_exu_div_ctl.scala 60:89]
    node _T_11 = and(_T_10, valid_x) @[el2_exu_div_ctl.scala 60:99]
    node _T_12 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 61:11]
    node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:18]
    node _T_14 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 61:34]
    node _T_15 = neq(_T_14, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:41]
    node _T_16 = and(_T_13, _T_15) @[el2_exu_div_ctl.scala 61:27]
    node _T_17 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:52]
    node _T_18 = and(_T_16, _T_17) @[el2_exu_div_ctl.scala 61:50]
    node _T_19 = and(_T_18, valid_x) @[el2_exu_div_ctl.scala 61:60]
    node _T_20 = or(_T_11, _T_19) @[el2_exu_div_ctl.scala 60:110]
    smallnum_case <= _T_20 @[el2_exu_div_ctl.scala 60:17]
    node _T_21 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_22 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_24 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_26 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_28 = and(_T_23, _T_25) @[el2_exu_div_ctl.scala 65:94]
    node _T_29 = and(_T_28, _T_27) @[el2_exu_div_ctl.scala 65:94]
    node _T_30 = and(_T_21, _T_29) @[el2_exu_div_ctl.scala 66:10]
    node _T_31 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_32 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_34 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_36 = and(_T_33, _T_35) @[el2_exu_div_ctl.scala 65:94]
    node _T_37 = and(_T_31, _T_36) @[el2_exu_div_ctl.scala 66:10]
    node _T_38 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 72:37]
    node _T_39 = eq(_T_38, UInt<1>("h00")) @[el2_exu_div_ctl.scala 72:32]
    node _T_40 = and(_T_37, _T_39) @[el2_exu_div_ctl.scala 72:30]
    node _T_41 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_42 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_43 = eq(_T_42, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_44 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_46 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_48 = and(_T_43, _T_45) @[el2_exu_div_ctl.scala 65:94]
    node _T_49 = and(_T_48, _T_47) @[el2_exu_div_ctl.scala 65:94]
    node _T_50 = and(_T_41, _T_49) @[el2_exu_div_ctl.scala 66:10]
    node _T_51 = or(_T_40, _T_50) @[el2_exu_div_ctl.scala 72:41]
    node _T_52 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_53 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_54 = and(_T_52, _T_53) @[el2_exu_div_ctl.scala 64:94]
    node _T_55 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_57 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_58 = eq(_T_57, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_59 = and(_T_56, _T_58) @[el2_exu_div_ctl.scala 65:94]
    node _T_60 = and(_T_54, _T_59) @[el2_exu_div_ctl.scala 66:10]
    node _T_61 = or(_T_51, _T_60) @[el2_exu_div_ctl.scala 72:73]
    node _T_62 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_63 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_65 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_67 = and(_T_64, _T_66) @[el2_exu_div_ctl.scala 65:94]
    node _T_68 = and(_T_62, _T_67) @[el2_exu_div_ctl.scala 66:10]
    node _T_69 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 74:37]
    node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_exu_div_ctl.scala 74:32]
    node _T_71 = and(_T_68, _T_70) @[el2_exu_div_ctl.scala 74:30]
    node _T_72 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_73 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_74 = eq(_T_73, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_75 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_77 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_79 = and(_T_74, _T_76) @[el2_exu_div_ctl.scala 65:94]
    node _T_80 = and(_T_79, _T_78) @[el2_exu_div_ctl.scala 65:94]
    node _T_81 = and(_T_72, _T_80) @[el2_exu_div_ctl.scala 66:10]
    node _T_82 = or(_T_71, _T_81) @[el2_exu_div_ctl.scala 74:41]
    node _T_83 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_84 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_86 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_87 = eq(_T_86, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_88 = and(_T_85, _T_87) @[el2_exu_div_ctl.scala 65:94]
    node _T_89 = and(_T_83, _T_88) @[el2_exu_div_ctl.scala 66:10]
    node _T_90 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 74:110]
    node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_exu_div_ctl.scala 74:105]
    node _T_92 = and(_T_89, _T_91) @[el2_exu_div_ctl.scala 74:103]
    node _T_93 = or(_T_82, _T_92) @[el2_exu_div_ctl.scala 74:76]
    node _T_94 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_95 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74]
    node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_97 = and(_T_94, _T_96) @[el2_exu_div_ctl.scala 64:94]
    node _T_98 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_100 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_101 = eq(_T_100, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_102 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57]
    node _T_103 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57]
    node _T_104 = and(_T_99, _T_101) @[el2_exu_div_ctl.scala 65:94]
    node _T_105 = and(_T_104, _T_102) @[el2_exu_div_ctl.scala 65:94]
    node _T_106 = and(_T_105, _T_103) @[el2_exu_div_ctl.scala 65:94]
    node _T_107 = and(_T_97, _T_106) @[el2_exu_div_ctl.scala 66:10]
    node _T_108 = or(_T_93, _T_107) @[el2_exu_div_ctl.scala 74:114]
    node _T_109 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74]
    node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_111 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_112 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_113 = and(_T_110, _T_111) @[el2_exu_div_ctl.scala 64:94]
    node _T_114 = and(_T_113, _T_112) @[el2_exu_div_ctl.scala 64:94]
    node _T_115 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_117 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_119 = and(_T_116, _T_118) @[el2_exu_div_ctl.scala 65:94]
    node _T_120 = and(_T_114, _T_119) @[el2_exu_div_ctl.scala 66:10]
    node _T_121 = or(_T_108, _T_120) @[el2_exu_div_ctl.scala 75:43]
    node _T_122 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_123 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_124 = and(_T_122, _T_123) @[el2_exu_div_ctl.scala 64:94]
    node _T_125 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_127 = and(_T_124, _T_126) @[el2_exu_div_ctl.scala 66:10]
    node _T_128 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 75:111]
    node _T_129 = eq(_T_128, UInt<1>("h00")) @[el2_exu_div_ctl.scala 75:106]
    node _T_130 = and(_T_127, _T_129) @[el2_exu_div_ctl.scala 75:104]
    node _T_131 = or(_T_121, _T_130) @[el2_exu_div_ctl.scala 75:78]
    node _T_132 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_133 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_134 = and(_T_132, _T_133) @[el2_exu_div_ctl.scala 64:94]
    node _T_135 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_137 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_138 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_140 = and(_T_136, _T_137) @[el2_exu_div_ctl.scala 65:94]
    node _T_141 = and(_T_140, _T_139) @[el2_exu_div_ctl.scala 65:94]
    node _T_142 = and(_T_134, _T_141) @[el2_exu_div_ctl.scala 66:10]
    node _T_143 = or(_T_131, _T_142) @[el2_exu_div_ctl.scala 75:116]
    node _T_144 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_145 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_146 = and(_T_144, _T_145) @[el2_exu_div_ctl.scala 64:94]
    node _T_147 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_149 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_151 = and(_T_148, _T_150) @[el2_exu_div_ctl.scala 65:94]
    node _T_152 = and(_T_146, _T_151) @[el2_exu_div_ctl.scala 66:10]
    node _T_153 = or(_T_143, _T_152) @[el2_exu_div_ctl.scala 76:43]
    node _T_154 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_155 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_156 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_157 = and(_T_154, _T_155) @[el2_exu_div_ctl.scala 64:94]
    node _T_158 = and(_T_157, _T_156) @[el2_exu_div_ctl.scala 64:94]
    node _T_159 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_160 = eq(_T_159, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_161 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_162 = and(_T_160, _T_161) @[el2_exu_div_ctl.scala 65:94]
    node _T_163 = and(_T_158, _T_162) @[el2_exu_div_ctl.scala 66:10]
    node _T_164 = or(_T_153, _T_163) @[el2_exu_div_ctl.scala 76:77]
    node _T_165 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_166 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_167 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_168 = and(_T_165, _T_166) @[el2_exu_div_ctl.scala 64:94]
    node _T_169 = and(_T_168, _T_167) @[el2_exu_div_ctl.scala 64:94]
    node _T_170 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_171 = eq(_T_170, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_172 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_174 = and(_T_171, _T_173) @[el2_exu_div_ctl.scala 65:94]
    node _T_175 = and(_T_169, _T_174) @[el2_exu_div_ctl.scala 66:10]
    node _T_176 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_177 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74]
    node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_179 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_180 = and(_T_176, _T_178) @[el2_exu_div_ctl.scala 64:94]
    node _T_181 = and(_T_180, _T_179) @[el2_exu_div_ctl.scala 64:94]
    node _T_182 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_183 = eq(_T_182, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_184 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57]
    node _T_185 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57]
    node _T_186 = and(_T_183, _T_184) @[el2_exu_div_ctl.scala 65:94]
    node _T_187 = and(_T_186, _T_185) @[el2_exu_div_ctl.scala 65:94]
    node _T_188 = and(_T_181, _T_187) @[el2_exu_div_ctl.scala 66:10]
    node _T_189 = or(_T_175, _T_188) @[el2_exu_div_ctl.scala 78:44]
    node _T_190 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_191 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_193 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_195 = and(_T_192, _T_194) @[el2_exu_div_ctl.scala 65:94]
    node _T_196 = and(_T_190, _T_195) @[el2_exu_div_ctl.scala 66:10]
    node _T_197 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 78:118]
    node _T_198 = eq(_T_197, UInt<1>("h00")) @[el2_exu_div_ctl.scala 78:113]
    node _T_199 = and(_T_196, _T_198) @[el2_exu_div_ctl.scala 78:111]
    node _T_200 = or(_T_189, _T_199) @[el2_exu_div_ctl.scala 78:84]
    node _T_201 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_202 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_203 = eq(_T_202, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_204 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_206 = and(_T_203, _T_205) @[el2_exu_div_ctl.scala 65:94]
    node _T_207 = and(_T_201, _T_206) @[el2_exu_div_ctl.scala 66:10]
    node _T_208 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 79:39]
    node _T_209 = eq(_T_208, UInt<1>("h00")) @[el2_exu_div_ctl.scala 79:34]
    node _T_210 = and(_T_207, _T_209) @[el2_exu_div_ctl.scala 79:32]
    node _T_211 = or(_T_200, _T_210) @[el2_exu_div_ctl.scala 78:126]
    node _T_212 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_213 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_215 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_217 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_218 = eq(_T_217, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_219 = and(_T_214, _T_216) @[el2_exu_div_ctl.scala 65:94]
    node _T_220 = and(_T_219, _T_218) @[el2_exu_div_ctl.scala 65:94]
    node _T_221 = and(_T_212, _T_220) @[el2_exu_div_ctl.scala 66:10]
    node _T_222 = or(_T_211, _T_221) @[el2_exu_div_ctl.scala 79:46]
    node _T_223 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74]
    node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_225 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_226 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74]
    node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_228 = and(_T_224, _T_225) @[el2_exu_div_ctl.scala 64:94]
    node _T_229 = and(_T_228, _T_227) @[el2_exu_div_ctl.scala 64:94]
    node _T_230 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_232 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_234 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57]
    node _T_235 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57]
    node _T_236 = and(_T_231, _T_233) @[el2_exu_div_ctl.scala 65:94]
    node _T_237 = and(_T_236, _T_234) @[el2_exu_div_ctl.scala 65:94]
    node _T_238 = and(_T_237, _T_235) @[el2_exu_div_ctl.scala 65:94]
    node _T_239 = and(_T_229, _T_238) @[el2_exu_div_ctl.scala 66:10]
    node _T_240 = or(_T_222, _T_239) @[el2_exu_div_ctl.scala 79:86]
    node _T_241 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74]
    node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_243 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_244 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_245 = and(_T_242, _T_243) @[el2_exu_div_ctl.scala 64:94]
    node _T_246 = and(_T_245, _T_244) @[el2_exu_div_ctl.scala 64:94]
    node _T_247 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_249 = and(_T_246, _T_248) @[el2_exu_div_ctl.scala 66:10]
    node _T_250 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 80:42]
    node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_exu_div_ctl.scala 80:37]
    node _T_252 = and(_T_249, _T_251) @[el2_exu_div_ctl.scala 80:35]
    node _T_253 = or(_T_240, _T_252) @[el2_exu_div_ctl.scala 79:128]
    node _T_254 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_255 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_257 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_259 = and(_T_256, _T_258) @[el2_exu_div_ctl.scala 65:94]
    node _T_260 = and(_T_254, _T_259) @[el2_exu_div_ctl.scala 66:10]
    node _T_261 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 80:81]
    node _T_262 = eq(_T_261, UInt<1>("h00")) @[el2_exu_div_ctl.scala 80:76]
    node _T_263 = and(_T_260, _T_262) @[el2_exu_div_ctl.scala 80:74]
    node _T_264 = or(_T_253, _T_263) @[el2_exu_div_ctl.scala 80:46]
    node _T_265 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_266 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74]
    node _T_267 = eq(_T_266, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_268 = and(_T_265, _T_267) @[el2_exu_div_ctl.scala 64:94]
    node _T_269 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_270 = eq(_T_269, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_271 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_272 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57]
    node _T_273 = and(_T_270, _T_271) @[el2_exu_div_ctl.scala 65:94]
    node _T_274 = and(_T_273, _T_272) @[el2_exu_div_ctl.scala 65:94]
    node _T_275 = and(_T_268, _T_274) @[el2_exu_div_ctl.scala 66:10]
    node _T_276 = or(_T_264, _T_275) @[el2_exu_div_ctl.scala 80:86]
    node _T_277 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74]
    node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_279 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_280 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_281 = and(_T_278, _T_279) @[el2_exu_div_ctl.scala 64:94]
    node _T_282 = and(_T_281, _T_280) @[el2_exu_div_ctl.scala 64:94]
    node _T_283 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_285 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_286 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_288 = and(_T_284, _T_285) @[el2_exu_div_ctl.scala 65:94]
    node _T_289 = and(_T_288, _T_287) @[el2_exu_div_ctl.scala 65:94]
    node _T_290 = and(_T_282, _T_289) @[el2_exu_div_ctl.scala 66:10]
    node _T_291 = or(_T_276, _T_290) @[el2_exu_div_ctl.scala 80:128]
    node _T_292 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74]
    node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_294 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_295 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_296 = and(_T_293, _T_294) @[el2_exu_div_ctl.scala 64:94]
    node _T_297 = and(_T_296, _T_295) @[el2_exu_div_ctl.scala 64:94]
    node _T_298 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_299 = eq(_T_298, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_300 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_302 = and(_T_299, _T_301) @[el2_exu_div_ctl.scala 65:94]
    node _T_303 = and(_T_297, _T_302) @[el2_exu_div_ctl.scala 66:10]
    node _T_304 = or(_T_291, _T_303) @[el2_exu_div_ctl.scala 81:46]
    node _T_305 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_306 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74]
    node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_308 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74]
    node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_310 = and(_T_305, _T_307) @[el2_exu_div_ctl.scala 64:94]
    node _T_311 = and(_T_310, _T_309) @[el2_exu_div_ctl.scala 64:94]
    node _T_312 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_313 = eq(_T_312, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_314 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_315 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57]
    node _T_316 = and(_T_313, _T_314) @[el2_exu_div_ctl.scala 65:94]
    node _T_317 = and(_T_316, _T_315) @[el2_exu_div_ctl.scala 65:94]
    node _T_318 = and(_T_311, _T_317) @[el2_exu_div_ctl.scala 66:10]
    node _T_319 = or(_T_304, _T_318) @[el2_exu_div_ctl.scala 81:86]
    node _T_320 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74]
    node _T_321 = eq(_T_320, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_322 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_323 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_324 = and(_T_321, _T_322) @[el2_exu_div_ctl.scala 64:94]
    node _T_325 = and(_T_324, _T_323) @[el2_exu_div_ctl.scala 64:94]
    node _T_326 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_328 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_330 = and(_T_327, _T_329) @[el2_exu_div_ctl.scala 65:94]
    node _T_331 = and(_T_325, _T_330) @[el2_exu_div_ctl.scala 66:10]
    node _T_332 = or(_T_319, _T_331) @[el2_exu_div_ctl.scala 81:128]
    node _T_333 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_334 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_335 = and(_T_333, _T_334) @[el2_exu_div_ctl.scala 64:94]
    node _T_336 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_338 = and(_T_335, _T_337) @[el2_exu_div_ctl.scala 66:10]
    node _T_339 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 82:80]
    node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_exu_div_ctl.scala 82:75]
    node _T_341 = and(_T_338, _T_340) @[el2_exu_div_ctl.scala 82:73]
    node _T_342 = or(_T_332, _T_341) @[el2_exu_div_ctl.scala 82:46]
    node _T_343 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74]
    node _T_344 = eq(_T_343, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_345 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_346 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_347 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_348 = and(_T_344, _T_345) @[el2_exu_div_ctl.scala 64:94]
    node _T_349 = and(_T_348, _T_346) @[el2_exu_div_ctl.scala 64:94]
    node _T_350 = and(_T_349, _T_347) @[el2_exu_div_ctl.scala 64:94]
    node _T_351 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_353 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_354 = and(_T_352, _T_353) @[el2_exu_div_ctl.scala 65:94]
    node _T_355 = and(_T_350, _T_354) @[el2_exu_div_ctl.scala 66:10]
    node _T_356 = or(_T_342, _T_355) @[el2_exu_div_ctl.scala 82:86]
    node _T_357 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_358 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_359 = and(_T_357, _T_358) @[el2_exu_div_ctl.scala 64:94]
    node _T_360 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57]
    node _T_361 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_363 = and(_T_360, _T_362) @[el2_exu_div_ctl.scala 65:94]
    node _T_364 = and(_T_359, _T_363) @[el2_exu_div_ctl.scala 66:10]
    node _T_365 = or(_T_356, _T_364) @[el2_exu_div_ctl.scala 82:128]
    node _T_366 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_367 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_368 = and(_T_366, _T_367) @[el2_exu_div_ctl.scala 64:94]
    node _T_369 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57]
    node _T_370 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_372 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_374 = and(_T_369, _T_371) @[el2_exu_div_ctl.scala 65:94]
    node _T_375 = and(_T_374, _T_373) @[el2_exu_div_ctl.scala 65:94]
    node _T_376 = and(_T_368, _T_375) @[el2_exu_div_ctl.scala 66:10]
    node _T_377 = or(_T_365, _T_376) @[el2_exu_div_ctl.scala 83:46]
    node _T_378 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_379 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_380 = and(_T_378, _T_379) @[el2_exu_div_ctl.scala 64:94]
    node _T_381 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_382 = eq(_T_381, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_383 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_385 = and(_T_382, _T_384) @[el2_exu_div_ctl.scala 65:94]
    node _T_386 = and(_T_380, _T_385) @[el2_exu_div_ctl.scala 66:10]
    node _T_387 = or(_T_377, _T_386) @[el2_exu_div_ctl.scala 83:86]
    node _T_388 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_389 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74]
    node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_391 = and(_T_388, _T_390) @[el2_exu_div_ctl.scala 64:94]
    node _T_392 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_393 = eq(_T_392, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_394 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57]
    node _T_395 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57]
    node _T_396 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57]
    node _T_397 = and(_T_393, _T_394) @[el2_exu_div_ctl.scala 65:94]
    node _T_398 = and(_T_397, _T_395) @[el2_exu_div_ctl.scala 65:94]
    node _T_399 = and(_T_398, _T_396) @[el2_exu_div_ctl.scala 65:94]
    node _T_400 = and(_T_391, _T_399) @[el2_exu_div_ctl.scala 66:10]
    node _T_401 = or(_T_387, _T_400) @[el2_exu_div_ctl.scala 83:128]
    node _T_402 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_403 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_404 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_405 = and(_T_402, _T_403) @[el2_exu_div_ctl.scala 64:94]
    node _T_406 = and(_T_405, _T_404) @[el2_exu_div_ctl.scala 64:94]
    node _T_407 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57]
    node _T_408 = and(_T_406, _T_407) @[el2_exu_div_ctl.scala 66:10]
    node _T_409 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 84:82]
    node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_exu_div_ctl.scala 84:77]
    node _T_411 = and(_T_408, _T_410) @[el2_exu_div_ctl.scala 84:75]
    node _T_412 = or(_T_401, _T_411) @[el2_exu_div_ctl.scala 84:46]
    node _T_413 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_414 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_415 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_416 = and(_T_413, _T_414) @[el2_exu_div_ctl.scala 64:94]
    node _T_417 = and(_T_416, _T_415) @[el2_exu_div_ctl.scala 64:94]
    node _T_418 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57]
    node _T_419 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_421 = and(_T_418, _T_420) @[el2_exu_div_ctl.scala 65:94]
    node _T_422 = and(_T_417, _T_421) @[el2_exu_div_ctl.scala 66:10]
    node _T_423 = or(_T_412, _T_422) @[el2_exu_div_ctl.scala 84:86]
    node _T_424 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_425 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_426 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_427 = and(_T_424, _T_425) @[el2_exu_div_ctl.scala 64:94]
    node _T_428 = and(_T_427, _T_426) @[el2_exu_div_ctl.scala 64:94]
    node _T_429 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57]
    node _T_430 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74]
    node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_432 = and(_T_429, _T_431) @[el2_exu_div_ctl.scala 65:94]
    node _T_433 = and(_T_428, _T_432) @[el2_exu_div_ctl.scala 66:10]
    node _T_434 = or(_T_423, _T_433) @[el2_exu_div_ctl.scala 84:128]
    node _T_435 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_436 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74]
    node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69]
    node _T_438 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_439 = and(_T_435, _T_437) @[el2_exu_div_ctl.scala 64:94]
    node _T_440 = and(_T_439, _T_438) @[el2_exu_div_ctl.scala 64:94]
    node _T_441 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74]
    node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_443 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57]
    node _T_444 = and(_T_442, _T_443) @[el2_exu_div_ctl.scala 65:94]
    node _T_445 = and(_T_440, _T_444) @[el2_exu_div_ctl.scala 66:10]
    node _T_446 = or(_T_434, _T_445) @[el2_exu_div_ctl.scala 85:46]
    node _T_447 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_448 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_449 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_450 = and(_T_447, _T_448) @[el2_exu_div_ctl.scala 64:94]
    node _T_451 = and(_T_450, _T_449) @[el2_exu_div_ctl.scala 64:94]
    node _T_452 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_454 = and(_T_451, _T_453) @[el2_exu_div_ctl.scala 66:10]
    node _T_455 = or(_T_446, _T_454) @[el2_exu_div_ctl.scala 85:86]
    node _T_456 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_457 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57]
    node _T_458 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_459 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57]
    node _T_460 = and(_T_456, _T_457) @[el2_exu_div_ctl.scala 64:94]
    node _T_461 = and(_T_460, _T_458) @[el2_exu_div_ctl.scala 64:94]
    node _T_462 = and(_T_461, _T_459) @[el2_exu_div_ctl.scala 64:94]
    node _T_463 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57]
    node _T_464 = and(_T_462, _T_463) @[el2_exu_div_ctl.scala 66:10]
    node _T_465 = or(_T_455, _T_464) @[el2_exu_div_ctl.scala 85:128]
    node _T_466 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57]
    node _T_467 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57]
    node _T_468 = and(_T_466, _T_467) @[el2_exu_div_ctl.scala 64:94]
    node _T_469 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74]
    node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69]
    node _T_471 = and(_T_468, _T_470) @[el2_exu_div_ctl.scala 66:10]
    node _T_472 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 86:79]
    node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_exu_div_ctl.scala 86:74]
    node _T_474 = and(_T_471, _T_473) @[el2_exu_div_ctl.scala 86:72]
    node _T_475 = or(_T_465, _T_474) @[el2_exu_div_ctl.scala 86:46]
    node _T_476 = cat(_T_164, _T_475) @[Cat.scala 29:58]
    node _T_477 = cat(_T_30, _T_61) @[Cat.scala 29:58]
    node smallnum = cat(_T_477, _T_476) @[Cat.scala 29:58]
    wire shortq_enable_ff : UInt<1>
    shortq_enable_ff <= UInt<1>("h00")
    wire short_dividend : UInt<33>
    short_dividend <= UInt<33>("h00")
    wire shortq_shift_xx : UInt<4>
    shortq_shift_xx <= UInt<4>("h00")
    node _T_478 = bits(q_ff, 31, 31) @[el2_exu_div_ctl.scala 96:40]
    node _T_479 = and(sign_ff, _T_478) @[el2_exu_div_ctl.scala 96:34]
    node _T_480 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 96:49]
    node _T_481 = cat(_T_479, _T_480) @[Cat.scala 29:58]
    short_dividend <= _T_481 @[el2_exu_div_ctl.scala 96:18]
    node _T_482 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 101:22]
    node _T_483 = bits(_T_482, 0, 0) @[el2_exu_div_ctl.scala 101:27]
    node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_exu_div_ctl.scala 101:7]
    node _T_485 = bits(short_dividend, 31, 24) @[el2_exu_div_ctl.scala 101:52]
    node _T_486 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_487 = neq(_T_485, _T_486) @[el2_exu_div_ctl.scala 101:60]
    node _T_488 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 102:21]
    node _T_489 = bits(_T_488, 0, 0) @[el2_exu_div_ctl.scala 102:26]
    node _T_490 = bits(short_dividend, 31, 23) @[el2_exu_div_ctl.scala 102:51]
    node _T_491 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
    node _T_492 = neq(_T_490, _T_491) @[el2_exu_div_ctl.scala 102:59]
    node _T_493 = mux(_T_484, _T_487, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_494 = mux(_T_489, _T_492, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_495 = or(_T_493, _T_494) @[Mux.scala 27:72]
    wire _T_496 : UInt<1> @[Mux.scala 27:72]
    _T_496 <= _T_495 @[Mux.scala 27:72]
    node _T_497 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 105:22]
    node _T_498 = bits(_T_497, 0, 0) @[el2_exu_div_ctl.scala 105:27]
    node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_exu_div_ctl.scala 105:7]
    node _T_500 = bits(short_dividend, 23, 16) @[el2_exu_div_ctl.scala 105:52]
    node _T_501 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_502 = neq(_T_500, _T_501) @[el2_exu_div_ctl.scala 105:60]
    node _T_503 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 106:21]
    node _T_504 = bits(_T_503, 0, 0) @[el2_exu_div_ctl.scala 106:26]
    node _T_505 = bits(short_dividend, 22, 15) @[el2_exu_div_ctl.scala 106:51]
    node _T_506 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_507 = neq(_T_505, _T_506) @[el2_exu_div_ctl.scala 106:59]
    node _T_508 = mux(_T_499, _T_502, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_509 = mux(_T_504, _T_507, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_510 = or(_T_508, _T_509) @[Mux.scala 27:72]
    wire _T_511 : UInt<1> @[Mux.scala 27:72]
    _T_511 <= _T_510 @[Mux.scala 27:72]
    node _T_512 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 109:22]
    node _T_513 = bits(_T_512, 0, 0) @[el2_exu_div_ctl.scala 109:27]
    node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_exu_div_ctl.scala 109:7]
    node _T_515 = bits(short_dividend, 15, 8) @[el2_exu_div_ctl.scala 109:52]
    node _T_516 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_517 = neq(_T_515, _T_516) @[el2_exu_div_ctl.scala 109:59]
    node _T_518 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 110:21]
    node _T_519 = bits(_T_518, 0, 0) @[el2_exu_div_ctl.scala 110:26]
    node _T_520 = bits(short_dividend, 14, 7) @[el2_exu_div_ctl.scala 110:51]
    node _T_521 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_522 = neq(_T_520, _T_521) @[el2_exu_div_ctl.scala 110:58]
    node _T_523 = mux(_T_514, _T_517, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_524 = mux(_T_519, _T_522, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_525 = or(_T_523, _T_524) @[Mux.scala 27:72]
    wire _T_526 : UInt<1> @[Mux.scala 27:72]
    _T_526 <= _T_525 @[Mux.scala 27:72]
    node _T_527 = cat(_T_496, _T_511) @[Cat.scala 29:58]
    node a_cls = cat(_T_527, _T_526) @[Cat.scala 29:58]
    node _T_528 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 115:12]
    node _T_529 = bits(_T_528, 0, 0) @[el2_exu_div_ctl.scala 115:17]
    node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_exu_div_ctl.scala 115:7]
    node _T_531 = bits(m_ff, 31, 24) @[el2_exu_div_ctl.scala 115:32]
    node _T_532 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_533 = neq(_T_531, _T_532) @[el2_exu_div_ctl.scala 115:40]
    node _T_534 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 116:11]
    node _T_535 = bits(_T_534, 0, 0) @[el2_exu_div_ctl.scala 116:16]
    node _T_536 = bits(m_ff, 31, 24) @[el2_exu_div_ctl.scala 116:31]
    node _T_537 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_538 = neq(_T_536, _T_537) @[el2_exu_div_ctl.scala 116:39]
    node _T_539 = mux(_T_530, _T_533, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_540 = mux(_T_535, _T_538, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_541 = or(_T_539, _T_540) @[Mux.scala 27:72]
    wire _T_542 : UInt<1> @[Mux.scala 27:72]
    _T_542 <= _T_541 @[Mux.scala 27:72]
    node _T_543 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 119:12]
    node _T_544 = bits(_T_543, 0, 0) @[el2_exu_div_ctl.scala 119:17]
    node _T_545 = eq(_T_544, UInt<1>("h00")) @[el2_exu_div_ctl.scala 119:7]
    node _T_546 = bits(m_ff, 23, 16) @[el2_exu_div_ctl.scala 119:32]
    node _T_547 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_548 = neq(_T_546, _T_547) @[el2_exu_div_ctl.scala 119:40]
    node _T_549 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 120:11]
    node _T_550 = bits(_T_549, 0, 0) @[el2_exu_div_ctl.scala 120:16]
    node _T_551 = bits(m_ff, 23, 16) @[el2_exu_div_ctl.scala 120:31]
    node _T_552 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_553 = neq(_T_551, _T_552) @[el2_exu_div_ctl.scala 120:39]
    node _T_554 = mux(_T_545, _T_548, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_555 = mux(_T_550, _T_553, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_556 = or(_T_554, _T_555) @[Mux.scala 27:72]
    wire _T_557 : UInt<1> @[Mux.scala 27:72]
    _T_557 <= _T_556 @[Mux.scala 27:72]
    node _T_558 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 123:12]
    node _T_559 = bits(_T_558, 0, 0) @[el2_exu_div_ctl.scala 123:17]
    node _T_560 = eq(_T_559, UInt<1>("h00")) @[el2_exu_div_ctl.scala 123:7]
    node _T_561 = bits(m_ff, 15, 8) @[el2_exu_div_ctl.scala 123:32]
    node _T_562 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_563 = neq(_T_561, _T_562) @[el2_exu_div_ctl.scala 123:39]
    node _T_564 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 124:11]
    node _T_565 = bits(_T_564, 0, 0) @[el2_exu_div_ctl.scala 124:16]
    node _T_566 = bits(m_ff, 15, 8) @[el2_exu_div_ctl.scala 124:31]
    node _T_567 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
    node _T_568 = neq(_T_566, _T_567) @[el2_exu_div_ctl.scala 124:38]
    node _T_569 = mux(_T_560, _T_563, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_570 = mux(_T_565, _T_568, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_571 = or(_T_569, _T_570) @[Mux.scala 27:72]
    wire _T_572 : UInt<1> @[Mux.scala 27:72]
    _T_572 <= _T_571 @[Mux.scala 27:72]
    node _T_573 = cat(_T_542, _T_557) @[Cat.scala 29:58]
    node b_cls = cat(_T_573, _T_572) @[Cat.scala 29:58]
    node _T_574 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 128:13]
    node _T_575 = eq(_T_574, UInt<1>("h01")) @[el2_exu_div_ctl.scala 128:19]
    node _T_576 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 128:42]
    node _T_577 = eq(_T_576, UInt<1>("h01")) @[el2_exu_div_ctl.scala 128:48]
    node _T_578 = and(_T_575, _T_577) @[el2_exu_div_ctl.scala 128:34]
    node _T_579 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 129:15]
    node _T_580 = eq(_T_579, UInt<1>("h01")) @[el2_exu_div_ctl.scala 129:21]
    node _T_581 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 129:44]
    node _T_582 = eq(_T_581, UInt<1>("h01")) @[el2_exu_div_ctl.scala 129:50]
    node _T_583 = and(_T_580, _T_582) @[el2_exu_div_ctl.scala 129:36]
    node _T_584 = or(_T_578, _T_583) @[el2_exu_div_ctl.scala 128:65]
    node _T_585 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 130:15]
    node _T_586 = eq(_T_585, UInt<1>("h00")) @[el2_exu_div_ctl.scala 130:21]
    node _T_587 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 130:44]
    node _T_588 = eq(_T_587, UInt<1>("h01")) @[el2_exu_div_ctl.scala 130:50]
    node _T_589 = and(_T_586, _T_588) @[el2_exu_div_ctl.scala 130:36]
    node _T_590 = or(_T_584, _T_589) @[el2_exu_div_ctl.scala 129:67]
    node _T_591 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 131:15]
    node _T_592 = eq(_T_591, UInt<1>("h01")) @[el2_exu_div_ctl.scala 131:21]
    node _T_593 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 131:44]
    node _T_594 = eq(_T_593, UInt<1>("h01")) @[el2_exu_div_ctl.scala 131:50]
    node _T_595 = and(_T_592, _T_594) @[el2_exu_div_ctl.scala 131:36]
    node _T_596 = or(_T_590, _T_595) @[el2_exu_div_ctl.scala 130:67]
    node _T_597 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 132:15]
    node _T_598 = eq(_T_597, UInt<1>("h00")) @[el2_exu_div_ctl.scala 132:21]
    node _T_599 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 132:44]
    node _T_600 = eq(_T_599, UInt<1>("h01")) @[el2_exu_div_ctl.scala 132:50]
    node _T_601 = and(_T_598, _T_600) @[el2_exu_div_ctl.scala 132:36]
    node _T_602 = or(_T_596, _T_601) @[el2_exu_div_ctl.scala 131:67]
    node _T_603 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 133:15]
    node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_exu_div_ctl.scala 133:21]
    node _T_605 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 133:44]
    node _T_606 = eq(_T_605, UInt<1>("h01")) @[el2_exu_div_ctl.scala 133:50]
    node _T_607 = and(_T_604, _T_606) @[el2_exu_div_ctl.scala 133:36]
    node _T_608 = or(_T_602, _T_607) @[el2_exu_div_ctl.scala 132:67]
    node _T_609 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 135:13]
    node _T_610 = eq(_T_609, UInt<1>("h01")) @[el2_exu_div_ctl.scala 135:19]
    node _T_611 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 135:42]
    node _T_612 = eq(_T_611, UInt<1>("h01")) @[el2_exu_div_ctl.scala 135:48]
    node _T_613 = and(_T_610, _T_612) @[el2_exu_div_ctl.scala 135:34]
    node _T_614 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 136:15]
    node _T_615 = eq(_T_614, UInt<1>("h01")) @[el2_exu_div_ctl.scala 136:21]
    node _T_616 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 136:44]
    node _T_617 = eq(_T_616, UInt<1>("h01")) @[el2_exu_div_ctl.scala 136:50]
    node _T_618 = and(_T_615, _T_617) @[el2_exu_div_ctl.scala 136:36]
    node _T_619 = or(_T_613, _T_618) @[el2_exu_div_ctl.scala 135:65]
    node _T_620 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 137:15]
    node _T_621 = eq(_T_620, UInt<1>("h01")) @[el2_exu_div_ctl.scala 137:21]
    node _T_622 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 137:44]
    node _T_623 = eq(_T_622, UInt<1>("h01")) @[el2_exu_div_ctl.scala 137:50]
    node _T_624 = and(_T_621, _T_623) @[el2_exu_div_ctl.scala 137:36]
    node _T_625 = or(_T_619, _T_624) @[el2_exu_div_ctl.scala 136:67]
    node _T_626 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 138:15]
    node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_exu_div_ctl.scala 138:21]
    node _T_628 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 138:44]
    node _T_629 = eq(_T_628, UInt<1>("h00")) @[el2_exu_div_ctl.scala 138:50]
    node _T_630 = and(_T_627, _T_629) @[el2_exu_div_ctl.scala 138:36]
    node _T_631 = or(_T_625, _T_630) @[el2_exu_div_ctl.scala 137:67]
    node _T_632 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 140:13]
    node _T_633 = eq(_T_632, UInt<1>("h01")) @[el2_exu_div_ctl.scala 140:19]
    node _T_634 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 140:42]
    node _T_635 = eq(_T_634, UInt<1>("h01")) @[el2_exu_div_ctl.scala 140:48]
    node _T_636 = and(_T_633, _T_635) @[el2_exu_div_ctl.scala 140:34]
    node _T_637 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 141:15]
    node _T_638 = eq(_T_637, UInt<1>("h01")) @[el2_exu_div_ctl.scala 141:21]
    node _T_639 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 141:44]
    node _T_640 = eq(_T_639, UInt<1>("h01")) @[el2_exu_div_ctl.scala 141:50]
    node _T_641 = and(_T_638, _T_640) @[el2_exu_div_ctl.scala 141:36]
    node _T_642 = or(_T_636, _T_641) @[el2_exu_div_ctl.scala 140:65]
    node _T_643 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 142:15]
    node _T_644 = eq(_T_643, UInt<1>("h01")) @[el2_exu_div_ctl.scala 142:21]
    node _T_645 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 142:44]
    node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_exu_div_ctl.scala 142:50]
    node _T_647 = and(_T_644, _T_646) @[el2_exu_div_ctl.scala 142:36]
    node _T_648 = or(_T_642, _T_647) @[el2_exu_div_ctl.scala 141:67]
    node _T_649 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 144:13]
    node _T_650 = eq(_T_649, UInt<1>("h01")) @[el2_exu_div_ctl.scala 144:19]
    node _T_651 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 144:42]
    node _T_652 = eq(_T_651, UInt<1>("h01")) @[el2_exu_div_ctl.scala 144:48]
    node _T_653 = and(_T_650, _T_652) @[el2_exu_div_ctl.scala 144:34]
    node _T_654 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 145:15]
    node _T_655 = eq(_T_654, UInt<1>("h01")) @[el2_exu_div_ctl.scala 145:21]
    node _T_656 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 145:44]
    node _T_657 = eq(_T_656, UInt<1>("h00")) @[el2_exu_div_ctl.scala 145:50]
    node _T_658 = and(_T_655, _T_657) @[el2_exu_div_ctl.scala 145:36]
    node _T_659 = or(_T_653, _T_658) @[el2_exu_div_ctl.scala 144:65]
    node _T_660 = cat(_T_648, _T_659) @[Cat.scala 29:58]
    node _T_661 = cat(_T_608, _T_631) @[Cat.scala 29:58]
    node shortq_raw = cat(_T_661, _T_660) @[Cat.scala 29:58]
    node _T_662 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 148:42]
    node _T_663 = neq(_T_662, UInt<32>("h00")) @[el2_exu_div_ctl.scala 148:49]
    node _T_664 = and(valid_ff_x, _T_663) @[el2_exu_div_ctl.scala 148:35]
    node _T_665 = neq(shortq_raw, UInt<4>("h00")) @[el2_exu_div_ctl.scala 148:78]
    node shortq_enable = and(_T_664, _T_665) @[el2_exu_div_ctl.scala 148:64]
    node _T_666 = bits(shortq_enable, 0, 0) @[Bitwise.scala 72:15]
    node _T_667 = mux(_T_666, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
    node shortq_shift = and(_T_667, shortq_raw) @[el2_exu_div_ctl.scala 149:44]
    node _T_668 = bits(shortq_shift_xx, 3, 3) @[el2_exu_div_ctl.scala 152:20]
    node _T_669 = bits(_T_668, 0, 0) @[el2_exu_div_ctl.scala 152:24]
    node _T_670 = bits(shortq_shift_xx, 2, 2) @[el2_exu_div_ctl.scala 153:20]
    node _T_671 = bits(_T_670, 0, 0) @[el2_exu_div_ctl.scala 153:24]
    node _T_672 = bits(shortq_shift_xx, 1, 1) @[el2_exu_div_ctl.scala 154:20]
    node _T_673 = bits(_T_672, 0, 0) @[el2_exu_div_ctl.scala 154:24]
    node _T_674 = bits(shortq_shift_xx, 0, 0) @[el2_exu_div_ctl.scala 155:20]
    node _T_675 = bits(_T_674, 0, 0) @[el2_exu_div_ctl.scala 155:24]
    node _T_676 = mux(_T_669, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_677 = mux(_T_671, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_678 = mux(_T_673, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_679 = mux(_T_675, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_680 = or(_T_676, _T_677) @[Mux.scala 27:72]
    node _T_681 = or(_T_680, _T_678) @[Mux.scala 27:72]
    node _T_682 = or(_T_681, _T_679) @[Mux.scala 27:72]
    wire shortq_shift_ff : UInt<5> @[Mux.scala 27:72]
    shortq_shift_ff <= _T_682 @[Mux.scala 27:72]
    node _T_683 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 159:40]
    node _T_684 = eq(count, UInt<6>("h020")) @[el2_exu_div_ctl.scala 159:55]
    node _T_685 = eq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 159:76]
    node _T_686 = mux(_T_683, _T_684, _T_685) @[el2_exu_div_ctl.scala 159:39]
    node finish = or(smallnum_case, _T_686) @[el2_exu_div_ctl.scala 159:34]
    node _T_687 = or(io.dp.valid, run_state) @[el2_exu_div_ctl.scala 160:32]
    node _T_688 = or(_T_687, finish) @[el2_exu_div_ctl.scala 160:44]
    node div_clken = or(_T_688, finish_ff) @[el2_exu_div_ctl.scala 160:53]
    node _T_689 = or(io.dp.valid, run_state) @[el2_exu_div_ctl.scala 161:33]
    node _T_690 = eq(finish, UInt<1>("h00")) @[el2_exu_div_ctl.scala 161:48]
    node _T_691 = and(_T_689, _T_690) @[el2_exu_div_ctl.scala 161:46]
    node _T_692 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 161:58]
    node run_in = and(_T_691, _T_692) @[el2_exu_div_ctl.scala 161:56]
    node _T_693 = eq(finish, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:37]
    node _T_694 = and(run_state, _T_693) @[el2_exu_div_ctl.scala 162:35]
    node _T_695 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:47]
    node _T_696 = and(_T_694, _T_695) @[el2_exu_div_ctl.scala 162:45]
    node _T_697 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:60]
    node _T_698 = and(_T_696, _T_697) @[el2_exu_div_ctl.scala 162:58]
    node _T_699 = bits(_T_698, 0, 0) @[Bitwise.scala 72:15]
    node _T_700 = mux(_T_699, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
    node _T_701 = cat(UInt<1>("h00"), shortq_shift_ff) @[Cat.scala 29:58]
    node _T_702 = add(count, _T_701) @[el2_exu_div_ctl.scala 162:86]
    node _T_703 = tail(_T_702, 1) @[el2_exu_div_ctl.scala 162:86]
    node _T_704 = add(_T_703, UInt<6>("h01")) @[el2_exu_div_ctl.scala 162:113]
    node _T_705 = tail(_T_704, 1) @[el2_exu_div_ctl.scala 162:113]
    node _T_706 = and(_T_700, _T_705) @[el2_exu_div_ctl.scala 162:77]
    count_in <= _T_706 @[el2_exu_div_ctl.scala 162:14]
    node _T_707 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 165:34]
    node _T_708 = and(finish_ff, _T_707) @[el2_exu_div_ctl.scala 165:32]
    io.finish_dly <= _T_708 @[el2_exu_div_ctl.scala 165:18]
    node _T_709 = eq(io.dp.bits.unsign, UInt<1>("h00")) @[el2_exu_div_ctl.scala 166:20]
    node _T_710 = neq(io.divisor, UInt<32>("h00")) @[el2_exu_div_ctl.scala 166:53]
    node sign_eff = and(_T_709, _T_710) @[el2_exu_div_ctl.scala 166:39]
    node _T_711 = eq(run_state, UInt<1>("h00")) @[el2_exu_div_ctl.scala 170:6]
    node _T_712 = bits(_T_711, 0, 0) @[el2_exu_div_ctl.scala 170:18]
    node _T_713 = cat(UInt<1>("h00"), io.dividend) @[Cat.scala 29:58]
    node _T_714 = or(valid_ff_x, shortq_enable_ff) @[el2_exu_div_ctl.scala 171:30]
    node _T_715 = and(run_state, _T_714) @[el2_exu_div_ctl.scala 171:16]
    node _T_716 = bits(_T_715, 0, 0) @[el2_exu_div_ctl.scala 171:51]
    node _T_717 = bits(dividend_eff, 31, 0) @[el2_exu_div_ctl.scala 171:78]
    node _T_718 = bits(a_in, 32, 32) @[el2_exu_div_ctl.scala 171:90]
    node _T_719 = eq(_T_718, UInt<1>("h00")) @[el2_exu_div_ctl.scala 171:85]
    node _T_720 = cat(_T_717, _T_719) @[Cat.scala 29:58]
    node _T_721 = dshl(_T_720, shortq_shift_ff) @[el2_exu_div_ctl.scala 171:96]
    node _T_722 = or(valid_ff_x, shortq_enable_ff) @[el2_exu_div_ctl.scala 172:31]
    node _T_723 = eq(_T_722, UInt<1>("h00")) @[el2_exu_div_ctl.scala 172:18]
    node _T_724 = and(run_state, _T_723) @[el2_exu_div_ctl.scala 172:16]
    node _T_725 = bits(_T_724, 0, 0) @[el2_exu_div_ctl.scala 172:52]
    node _T_726 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 172:70]
    node _T_727 = bits(a_in, 32, 32) @[el2_exu_div_ctl.scala 172:82]
    node _T_728 = eq(_T_727, UInt<1>("h00")) @[el2_exu_div_ctl.scala 172:77]
    node _T_729 = cat(_T_726, _T_728) @[Cat.scala 29:58]
    node _T_730 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_731 = mux(_T_716, _T_721, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_732 = mux(_T_725, _T_729, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_733 = or(_T_730, _T_731) @[Mux.scala 27:72]
    node _T_734 = or(_T_733, _T_732) @[Mux.scala 27:72]
    wire _T_735 : UInt<64> @[Mux.scala 27:72]
    _T_735 <= _T_734 @[Mux.scala 27:72]
    q_in <= _T_735 @[el2_exu_div_ctl.scala 169:8]
    node _T_736 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 174:50]
    node _T_737 = and(run_state, _T_736) @[el2_exu_div_ctl.scala 174:48]
    node qff_enable = or(io.dp.valid, _T_737) @[el2_exu_div_ctl.scala 174:35]
    node _T_738 = and(sign_ff, dividend_neg_ff) @[el2_exu_div_ctl.scala 175:32]
    node _T_739 = bits(_T_738, 0, 0) @[el2_exu_div_ctl.scala 175:51]
    node _T_740 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 175:74]
    wire _T_741 : UInt<1>[31] @[el2_lib.scala 541:20]
    node _T_742 = bits(_T_740, 0, 0) @[el2_lib.scala 543:27]
    node _T_743 = orr(_T_742) @[el2_lib.scala 543:35]
    node _T_744 = bits(_T_740, 1, 1) @[el2_lib.scala 543:44]
    node _T_745 = not(_T_744) @[el2_lib.scala 543:40]
    node _T_746 = bits(_T_740, 1, 1) @[el2_lib.scala 543:51]
    node _T_747 = mux(_T_743, _T_745, _T_746) @[el2_lib.scala 543:23]
    _T_741[0] <= _T_747 @[el2_lib.scala 543:17]
    node _T_748 = bits(_T_740, 1, 0) @[el2_lib.scala 543:27]
    node _T_749 = orr(_T_748) @[el2_lib.scala 543:35]
    node _T_750 = bits(_T_740, 2, 2) @[el2_lib.scala 543:44]
    node _T_751 = not(_T_750) @[el2_lib.scala 543:40]
    node _T_752 = bits(_T_740, 2, 2) @[el2_lib.scala 543:51]
    node _T_753 = mux(_T_749, _T_751, _T_752) @[el2_lib.scala 543:23]
    _T_741[1] <= _T_753 @[el2_lib.scala 543:17]
    node _T_754 = bits(_T_740, 2, 0) @[el2_lib.scala 543:27]
    node _T_755 = orr(_T_754) @[el2_lib.scala 543:35]
    node _T_756 = bits(_T_740, 3, 3) @[el2_lib.scala 543:44]
    node _T_757 = not(_T_756) @[el2_lib.scala 543:40]
    node _T_758 = bits(_T_740, 3, 3) @[el2_lib.scala 543:51]
    node _T_759 = mux(_T_755, _T_757, _T_758) @[el2_lib.scala 543:23]
    _T_741[2] <= _T_759 @[el2_lib.scala 543:17]
    node _T_760 = bits(_T_740, 3, 0) @[el2_lib.scala 543:27]
    node _T_761 = orr(_T_760) @[el2_lib.scala 543:35]
    node _T_762 = bits(_T_740, 4, 4) @[el2_lib.scala 543:44]
    node _T_763 = not(_T_762) @[el2_lib.scala 543:40]
    node _T_764 = bits(_T_740, 4, 4) @[el2_lib.scala 543:51]
    node _T_765 = mux(_T_761, _T_763, _T_764) @[el2_lib.scala 543:23]
    _T_741[3] <= _T_765 @[el2_lib.scala 543:17]
    node _T_766 = bits(_T_740, 4, 0) @[el2_lib.scala 543:27]
    node _T_767 = orr(_T_766) @[el2_lib.scala 543:35]
    node _T_768 = bits(_T_740, 5, 5) @[el2_lib.scala 543:44]
    node _T_769 = not(_T_768) @[el2_lib.scala 543:40]
    node _T_770 = bits(_T_740, 5, 5) @[el2_lib.scala 543:51]
    node _T_771 = mux(_T_767, _T_769, _T_770) @[el2_lib.scala 543:23]
    _T_741[4] <= _T_771 @[el2_lib.scala 543:17]
    node _T_772 = bits(_T_740, 5, 0) @[el2_lib.scala 543:27]
    node _T_773 = orr(_T_772) @[el2_lib.scala 543:35]
    node _T_774 = bits(_T_740, 6, 6) @[el2_lib.scala 543:44]
    node _T_775 = not(_T_774) @[el2_lib.scala 543:40]
    node _T_776 = bits(_T_740, 6, 6) @[el2_lib.scala 543:51]
    node _T_777 = mux(_T_773, _T_775, _T_776) @[el2_lib.scala 543:23]
    _T_741[5] <= _T_777 @[el2_lib.scala 543:17]
    node _T_778 = bits(_T_740, 6, 0) @[el2_lib.scala 543:27]
    node _T_779 = orr(_T_778) @[el2_lib.scala 543:35]
    node _T_780 = bits(_T_740, 7, 7) @[el2_lib.scala 543:44]
    node _T_781 = not(_T_780) @[el2_lib.scala 543:40]
    node _T_782 = bits(_T_740, 7, 7) @[el2_lib.scala 543:51]
    node _T_783 = mux(_T_779, _T_781, _T_782) @[el2_lib.scala 543:23]
    _T_741[6] <= _T_783 @[el2_lib.scala 543:17]
    node _T_784 = bits(_T_740, 7, 0) @[el2_lib.scala 543:27]
    node _T_785 = orr(_T_784) @[el2_lib.scala 543:35]
    node _T_786 = bits(_T_740, 8, 8) @[el2_lib.scala 543:44]
    node _T_787 = not(_T_786) @[el2_lib.scala 543:40]
    node _T_788 = bits(_T_740, 8, 8) @[el2_lib.scala 543:51]
    node _T_789 = mux(_T_785, _T_787, _T_788) @[el2_lib.scala 543:23]
    _T_741[7] <= _T_789 @[el2_lib.scala 543:17]
    node _T_790 = bits(_T_740, 8, 0) @[el2_lib.scala 543:27]
    node _T_791 = orr(_T_790) @[el2_lib.scala 543:35]
    node _T_792 = bits(_T_740, 9, 9) @[el2_lib.scala 543:44]
    node _T_793 = not(_T_792) @[el2_lib.scala 543:40]
    node _T_794 = bits(_T_740, 9, 9) @[el2_lib.scala 543:51]
    node _T_795 = mux(_T_791, _T_793, _T_794) @[el2_lib.scala 543:23]
    _T_741[8] <= _T_795 @[el2_lib.scala 543:17]
    node _T_796 = bits(_T_740, 9, 0) @[el2_lib.scala 543:27]
    node _T_797 = orr(_T_796) @[el2_lib.scala 543:35]
    node _T_798 = bits(_T_740, 10, 10) @[el2_lib.scala 543:44]
    node _T_799 = not(_T_798) @[el2_lib.scala 543:40]
    node _T_800 = bits(_T_740, 10, 10) @[el2_lib.scala 543:51]
    node _T_801 = mux(_T_797, _T_799, _T_800) @[el2_lib.scala 543:23]
    _T_741[9] <= _T_801 @[el2_lib.scala 543:17]
    node _T_802 = bits(_T_740, 10, 0) @[el2_lib.scala 543:27]
    node _T_803 = orr(_T_802) @[el2_lib.scala 543:35]
    node _T_804 = bits(_T_740, 11, 11) @[el2_lib.scala 543:44]
    node _T_805 = not(_T_804) @[el2_lib.scala 543:40]
    node _T_806 = bits(_T_740, 11, 11) @[el2_lib.scala 543:51]
    node _T_807 = mux(_T_803, _T_805, _T_806) @[el2_lib.scala 543:23]
    _T_741[10] <= _T_807 @[el2_lib.scala 543:17]
    node _T_808 = bits(_T_740, 11, 0) @[el2_lib.scala 543:27]
    node _T_809 = orr(_T_808) @[el2_lib.scala 543:35]
    node _T_810 = bits(_T_740, 12, 12) @[el2_lib.scala 543:44]
    node _T_811 = not(_T_810) @[el2_lib.scala 543:40]
    node _T_812 = bits(_T_740, 12, 12) @[el2_lib.scala 543:51]
    node _T_813 = mux(_T_809, _T_811, _T_812) @[el2_lib.scala 543:23]
    _T_741[11] <= _T_813 @[el2_lib.scala 543:17]
    node _T_814 = bits(_T_740, 12, 0) @[el2_lib.scala 543:27]
    node _T_815 = orr(_T_814) @[el2_lib.scala 543:35]
    node _T_816 = bits(_T_740, 13, 13) @[el2_lib.scala 543:44]
    node _T_817 = not(_T_816) @[el2_lib.scala 543:40]
    node _T_818 = bits(_T_740, 13, 13) @[el2_lib.scala 543:51]
    node _T_819 = mux(_T_815, _T_817, _T_818) @[el2_lib.scala 543:23]
    _T_741[12] <= _T_819 @[el2_lib.scala 543:17]
    node _T_820 = bits(_T_740, 13, 0) @[el2_lib.scala 543:27]
    node _T_821 = orr(_T_820) @[el2_lib.scala 543:35]
    node _T_822 = bits(_T_740, 14, 14) @[el2_lib.scala 543:44]
    node _T_823 = not(_T_822) @[el2_lib.scala 543:40]
    node _T_824 = bits(_T_740, 14, 14) @[el2_lib.scala 543:51]
    node _T_825 = mux(_T_821, _T_823, _T_824) @[el2_lib.scala 543:23]
    _T_741[13] <= _T_825 @[el2_lib.scala 543:17]
    node _T_826 = bits(_T_740, 14, 0) @[el2_lib.scala 543:27]
    node _T_827 = orr(_T_826) @[el2_lib.scala 543:35]
    node _T_828 = bits(_T_740, 15, 15) @[el2_lib.scala 543:44]
    node _T_829 = not(_T_828) @[el2_lib.scala 543:40]
    node _T_830 = bits(_T_740, 15, 15) @[el2_lib.scala 543:51]
    node _T_831 = mux(_T_827, _T_829, _T_830) @[el2_lib.scala 543:23]
    _T_741[14] <= _T_831 @[el2_lib.scala 543:17]
    node _T_832 = bits(_T_740, 15, 0) @[el2_lib.scala 543:27]
    node _T_833 = orr(_T_832) @[el2_lib.scala 543:35]
    node _T_834 = bits(_T_740, 16, 16) @[el2_lib.scala 543:44]
    node _T_835 = not(_T_834) @[el2_lib.scala 543:40]
    node _T_836 = bits(_T_740, 16, 16) @[el2_lib.scala 543:51]
    node _T_837 = mux(_T_833, _T_835, _T_836) @[el2_lib.scala 543:23]
    _T_741[15] <= _T_837 @[el2_lib.scala 543:17]
    node _T_838 = bits(_T_740, 16, 0) @[el2_lib.scala 543:27]
    node _T_839 = orr(_T_838) @[el2_lib.scala 543:35]
    node _T_840 = bits(_T_740, 17, 17) @[el2_lib.scala 543:44]
    node _T_841 = not(_T_840) @[el2_lib.scala 543:40]
    node _T_842 = bits(_T_740, 17, 17) @[el2_lib.scala 543:51]
    node _T_843 = mux(_T_839, _T_841, _T_842) @[el2_lib.scala 543:23]
    _T_741[16] <= _T_843 @[el2_lib.scala 543:17]
    node _T_844 = bits(_T_740, 17, 0) @[el2_lib.scala 543:27]
    node _T_845 = orr(_T_844) @[el2_lib.scala 543:35]
    node _T_846 = bits(_T_740, 18, 18) @[el2_lib.scala 543:44]
    node _T_847 = not(_T_846) @[el2_lib.scala 543:40]
    node _T_848 = bits(_T_740, 18, 18) @[el2_lib.scala 543:51]
    node _T_849 = mux(_T_845, _T_847, _T_848) @[el2_lib.scala 543:23]
    _T_741[17] <= _T_849 @[el2_lib.scala 543:17]
    node _T_850 = bits(_T_740, 18, 0) @[el2_lib.scala 543:27]
    node _T_851 = orr(_T_850) @[el2_lib.scala 543:35]
    node _T_852 = bits(_T_740, 19, 19) @[el2_lib.scala 543:44]
    node _T_853 = not(_T_852) @[el2_lib.scala 543:40]
    node _T_854 = bits(_T_740, 19, 19) @[el2_lib.scala 543:51]
    node _T_855 = mux(_T_851, _T_853, _T_854) @[el2_lib.scala 543:23]
    _T_741[18] <= _T_855 @[el2_lib.scala 543:17]
    node _T_856 = bits(_T_740, 19, 0) @[el2_lib.scala 543:27]
    node _T_857 = orr(_T_856) @[el2_lib.scala 543:35]
    node _T_858 = bits(_T_740, 20, 20) @[el2_lib.scala 543:44]
    node _T_859 = not(_T_858) @[el2_lib.scala 543:40]
    node _T_860 = bits(_T_740, 20, 20) @[el2_lib.scala 543:51]
    node _T_861 = mux(_T_857, _T_859, _T_860) @[el2_lib.scala 543:23]
    _T_741[19] <= _T_861 @[el2_lib.scala 543:17]
    node _T_862 = bits(_T_740, 20, 0) @[el2_lib.scala 543:27]
    node _T_863 = orr(_T_862) @[el2_lib.scala 543:35]
    node _T_864 = bits(_T_740, 21, 21) @[el2_lib.scala 543:44]
    node _T_865 = not(_T_864) @[el2_lib.scala 543:40]
    node _T_866 = bits(_T_740, 21, 21) @[el2_lib.scala 543:51]
    node _T_867 = mux(_T_863, _T_865, _T_866) @[el2_lib.scala 543:23]
    _T_741[20] <= _T_867 @[el2_lib.scala 543:17]
    node _T_868 = bits(_T_740, 21, 0) @[el2_lib.scala 543:27]
    node _T_869 = orr(_T_868) @[el2_lib.scala 543:35]
    node _T_870 = bits(_T_740, 22, 22) @[el2_lib.scala 543:44]
    node _T_871 = not(_T_870) @[el2_lib.scala 543:40]
    node _T_872 = bits(_T_740, 22, 22) @[el2_lib.scala 543:51]
    node _T_873 = mux(_T_869, _T_871, _T_872) @[el2_lib.scala 543:23]
    _T_741[21] <= _T_873 @[el2_lib.scala 543:17]
    node _T_874 = bits(_T_740, 22, 0) @[el2_lib.scala 543:27]
    node _T_875 = orr(_T_874) @[el2_lib.scala 543:35]
    node _T_876 = bits(_T_740, 23, 23) @[el2_lib.scala 543:44]
    node _T_877 = not(_T_876) @[el2_lib.scala 543:40]
    node _T_878 = bits(_T_740, 23, 23) @[el2_lib.scala 543:51]
    node _T_879 = mux(_T_875, _T_877, _T_878) @[el2_lib.scala 543:23]
    _T_741[22] <= _T_879 @[el2_lib.scala 543:17]
    node _T_880 = bits(_T_740, 23, 0) @[el2_lib.scala 543:27]
    node _T_881 = orr(_T_880) @[el2_lib.scala 543:35]
    node _T_882 = bits(_T_740, 24, 24) @[el2_lib.scala 543:44]
    node _T_883 = not(_T_882) @[el2_lib.scala 543:40]
    node _T_884 = bits(_T_740, 24, 24) @[el2_lib.scala 543:51]
    node _T_885 = mux(_T_881, _T_883, _T_884) @[el2_lib.scala 543:23]
    _T_741[23] <= _T_885 @[el2_lib.scala 543:17]
    node _T_886 = bits(_T_740, 24, 0) @[el2_lib.scala 543:27]
    node _T_887 = orr(_T_886) @[el2_lib.scala 543:35]
    node _T_888 = bits(_T_740, 25, 25) @[el2_lib.scala 543:44]
    node _T_889 = not(_T_888) @[el2_lib.scala 543:40]
    node _T_890 = bits(_T_740, 25, 25) @[el2_lib.scala 543:51]
    node _T_891 = mux(_T_887, _T_889, _T_890) @[el2_lib.scala 543:23]
    _T_741[24] <= _T_891 @[el2_lib.scala 543:17]
    node _T_892 = bits(_T_740, 25, 0) @[el2_lib.scala 543:27]
    node _T_893 = orr(_T_892) @[el2_lib.scala 543:35]
    node _T_894 = bits(_T_740, 26, 26) @[el2_lib.scala 543:44]
    node _T_895 = not(_T_894) @[el2_lib.scala 543:40]
    node _T_896 = bits(_T_740, 26, 26) @[el2_lib.scala 543:51]
    node _T_897 = mux(_T_893, _T_895, _T_896) @[el2_lib.scala 543:23]
    _T_741[25] <= _T_897 @[el2_lib.scala 543:17]
    node _T_898 = bits(_T_740, 26, 0) @[el2_lib.scala 543:27]
    node _T_899 = orr(_T_898) @[el2_lib.scala 543:35]
    node _T_900 = bits(_T_740, 27, 27) @[el2_lib.scala 543:44]
    node _T_901 = not(_T_900) @[el2_lib.scala 543:40]
    node _T_902 = bits(_T_740, 27, 27) @[el2_lib.scala 543:51]
    node _T_903 = mux(_T_899, _T_901, _T_902) @[el2_lib.scala 543:23]
    _T_741[26] <= _T_903 @[el2_lib.scala 543:17]
    node _T_904 = bits(_T_740, 27, 0) @[el2_lib.scala 543:27]
    node _T_905 = orr(_T_904) @[el2_lib.scala 543:35]
    node _T_906 = bits(_T_740, 28, 28) @[el2_lib.scala 543:44]
    node _T_907 = not(_T_906) @[el2_lib.scala 543:40]
    node _T_908 = bits(_T_740, 28, 28) @[el2_lib.scala 543:51]
    node _T_909 = mux(_T_905, _T_907, _T_908) @[el2_lib.scala 543:23]
    _T_741[27] <= _T_909 @[el2_lib.scala 543:17]
    node _T_910 = bits(_T_740, 28, 0) @[el2_lib.scala 543:27]
    node _T_911 = orr(_T_910) @[el2_lib.scala 543:35]
    node _T_912 = bits(_T_740, 29, 29) @[el2_lib.scala 543:44]
    node _T_913 = not(_T_912) @[el2_lib.scala 543:40]
    node _T_914 = bits(_T_740, 29, 29) @[el2_lib.scala 543:51]
    node _T_915 = mux(_T_911, _T_913, _T_914) @[el2_lib.scala 543:23]
    _T_741[28] <= _T_915 @[el2_lib.scala 543:17]
    node _T_916 = bits(_T_740, 29, 0) @[el2_lib.scala 543:27]
    node _T_917 = orr(_T_916) @[el2_lib.scala 543:35]
    node _T_918 = bits(_T_740, 30, 30) @[el2_lib.scala 543:44]
    node _T_919 = not(_T_918) @[el2_lib.scala 543:40]
    node _T_920 = bits(_T_740, 30, 30) @[el2_lib.scala 543:51]
    node _T_921 = mux(_T_917, _T_919, _T_920) @[el2_lib.scala 543:23]
    _T_741[29] <= _T_921 @[el2_lib.scala 543:17]
    node _T_922 = bits(_T_740, 30, 0) @[el2_lib.scala 543:27]
    node _T_923 = orr(_T_922) @[el2_lib.scala 543:35]
    node _T_924 = bits(_T_740, 31, 31) @[el2_lib.scala 543:44]
    node _T_925 = not(_T_924) @[el2_lib.scala 543:40]
    node _T_926 = bits(_T_740, 31, 31) @[el2_lib.scala 543:51]
    node _T_927 = mux(_T_923, _T_925, _T_926) @[el2_lib.scala 543:23]
    _T_741[30] <= _T_927 @[el2_lib.scala 543:17]
    node _T_928 = cat(_T_741[2], _T_741[1]) @[el2_lib.scala 545:14]
    node _T_929 = cat(_T_928, _T_741[0]) @[el2_lib.scala 545:14]
    node _T_930 = cat(_T_741[4], _T_741[3]) @[el2_lib.scala 545:14]
    node _T_931 = cat(_T_741[6], _T_741[5]) @[el2_lib.scala 545:14]
    node _T_932 = cat(_T_931, _T_930) @[el2_lib.scala 545:14]
    node _T_933 = cat(_T_932, _T_929) @[el2_lib.scala 545:14]
    node _T_934 = cat(_T_741[8], _T_741[7]) @[el2_lib.scala 545:14]
    node _T_935 = cat(_T_741[10], _T_741[9]) @[el2_lib.scala 545:14]
    node _T_936 = cat(_T_935, _T_934) @[el2_lib.scala 545:14]
    node _T_937 = cat(_T_741[12], _T_741[11]) @[el2_lib.scala 545:14]
    node _T_938 = cat(_T_741[14], _T_741[13]) @[el2_lib.scala 545:14]
    node _T_939 = cat(_T_938, _T_937) @[el2_lib.scala 545:14]
    node _T_940 = cat(_T_939, _T_936) @[el2_lib.scala 545:14]
    node _T_941 = cat(_T_940, _T_933) @[el2_lib.scala 545:14]
    node _T_942 = cat(_T_741[16], _T_741[15]) @[el2_lib.scala 545:14]
    node _T_943 = cat(_T_741[18], _T_741[17]) @[el2_lib.scala 545:14]
    node _T_944 = cat(_T_943, _T_942) @[el2_lib.scala 545:14]
    node _T_945 = cat(_T_741[20], _T_741[19]) @[el2_lib.scala 545:14]
    node _T_946 = cat(_T_741[22], _T_741[21]) @[el2_lib.scala 545:14]
    node _T_947 = cat(_T_946, _T_945) @[el2_lib.scala 545:14]
    node _T_948 = cat(_T_947, _T_944) @[el2_lib.scala 545:14]
    node _T_949 = cat(_T_741[24], _T_741[23]) @[el2_lib.scala 545:14]
    node _T_950 = cat(_T_741[26], _T_741[25]) @[el2_lib.scala 545:14]
    node _T_951 = cat(_T_950, _T_949) @[el2_lib.scala 545:14]
    node _T_952 = cat(_T_741[28], _T_741[27]) @[el2_lib.scala 545:14]
    node _T_953 = cat(_T_741[30], _T_741[29]) @[el2_lib.scala 545:14]
    node _T_954 = cat(_T_953, _T_952) @[el2_lib.scala 545:14]
    node _T_955 = cat(_T_954, _T_951) @[el2_lib.scala 545:14]
    node _T_956 = cat(_T_955, _T_948) @[el2_lib.scala 545:14]
    node _T_957 = cat(_T_956, _T_941) @[el2_lib.scala 545:14]
    node _T_958 = bits(_T_740, 0, 0) @[el2_lib.scala 545:24]
    node _T_959 = cat(_T_957, _T_958) @[Cat.scala 29:58]
    node _T_960 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 175:86]
    node _T_961 = mux(_T_739, _T_959, _T_960) @[el2_exu_div_ctl.scala 175:22]
    dividend_eff <= _T_961 @[el2_exu_div_ctl.scala 175:16]
    node _T_962 = bits(add, 0, 0) @[el2_exu_div_ctl.scala 178:20]
    node _T_963 = not(m_ff) @[el2_exu_div_ctl.scala 178:35]
    node _T_964 = mux(_T_962, m_ff, _T_963) @[el2_exu_div_ctl.scala 178:15]
    m_eff <= _T_964 @[el2_exu_div_ctl.scala 178:9]
    node _T_965 = cat(UInt<24>("h00"), dividend_eff) @[Cat.scala 29:58]
    node _T_966 = dshl(_T_965, shortq_shift_ff) @[el2_exu_div_ctl.scala 179:47]
    a_eff_shift <= _T_966 @[el2_exu_div_ctl.scala 179:15]
    node _T_967 = bits(rem_correct, 0, 0) @[el2_exu_div_ctl.scala 181:17]
    node _T_968 = eq(rem_correct, UInt<1>("h00")) @[el2_exu_div_ctl.scala 182:6]
    node _T_969 = eq(shortq_enable_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 182:21]
    node _T_970 = and(_T_968, _T_969) @[el2_exu_div_ctl.scala 182:19]
    node _T_971 = bits(_T_970, 0, 0) @[el2_exu_div_ctl.scala 182:40]
    node _T_972 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 182:58]
    node _T_973 = bits(q_ff, 32, 32) @[el2_exu_div_ctl.scala 182:70]
    node _T_974 = cat(_T_972, _T_973) @[Cat.scala 29:58]
    node _T_975 = eq(rem_correct, UInt<1>("h00")) @[el2_exu_div_ctl.scala 183:6]
    node _T_976 = and(_T_975, shortq_enable_ff) @[el2_exu_div_ctl.scala 183:19]
    node _T_977 = bits(_T_976, 0, 0) @[el2_exu_div_ctl.scala 183:40]
    node _T_978 = bits(a_eff_shift, 55, 32) @[el2_exu_div_ctl.scala 183:74]
    node _T_979 = cat(UInt<9>("h00"), _T_978) @[Cat.scala 29:58]
    node _T_980 = mux(_T_967, a_ff, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_981 = mux(_T_971, _T_974, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_982 = mux(_T_977, _T_979, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_983 = or(_T_980, _T_981) @[Mux.scala 27:72]
    node _T_984 = or(_T_983, _T_982) @[Mux.scala 27:72]
    wire _T_985 : UInt<33> @[Mux.scala 27:72]
    _T_985 <= _T_984 @[Mux.scala 27:72]
    a_eff <= _T_985 @[el2_exu_div_ctl.scala 180:9]
    node _T_986 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 185:49]
    node _T_987 = and(run_state, _T_986) @[el2_exu_div_ctl.scala 185:47]
    node _T_988 = neq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 185:73]
    node _T_989 = and(_T_987, _T_988) @[el2_exu_div_ctl.scala 185:64]
    node _T_990 = or(io.dp.valid, _T_989) @[el2_exu_div_ctl.scala 185:34]
    node aff_enable = or(_T_990, rem_correct) @[el2_exu_div_ctl.scala 185:89]
    node _T_991 = bits(run_state, 0, 0) @[Bitwise.scala 72:15]
    node _T_992 = mux(_T_991, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12]
    node _T_993 = and(_T_992, a_eff) @[el2_exu_div_ctl.scala 186:33]
    a_shift <= _T_993 @[el2_exu_div_ctl.scala 186:11]
    node _T_994 = bits(run_state, 0, 0) @[Bitwise.scala 72:15]
    node _T_995 = mux(_T_994, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12]
    node _T_996 = add(a_shift, m_eff) @[el2_exu_div_ctl.scala 187:41]
    node _T_997 = tail(_T_996, 1) @[el2_exu_div_ctl.scala 187:41]
    node _T_998 = eq(add, UInt<1>("h00")) @[el2_exu_div_ctl.scala 187:65]
    node _T_999 = cat(UInt<32>("h00"), _T_998) @[Cat.scala 29:58]
    node _T_1000 = add(_T_997, _T_999) @[el2_exu_div_ctl.scala 187:49]
    node _T_1001 = tail(_T_1000, 1) @[el2_exu_div_ctl.scala 187:49]
    node _T_1002 = and(_T_995, _T_1001) @[el2_exu_div_ctl.scala 187:30]
    a_in <= _T_1002 @[el2_exu_div_ctl.scala 187:8]
    node m_already_comp = and(divisor_neg_ff, sign_ff) @[el2_exu_div_ctl.scala 188:48]
    node _T_1003 = bits(a_ff, 32, 32) @[el2_exu_div_ctl.scala 190:16]
    node _T_1004 = or(_T_1003, rem_correct) @[el2_exu_div_ctl.scala 190:21]
    node _T_1005 = xor(_T_1004, m_already_comp) @[el2_exu_div_ctl.scala 190:36]
    add <= _T_1005 @[el2_exu_div_ctl.scala 190:8]
    node _T_1006 = eq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 191:26]
    node _T_1007 = and(_T_1006, rem_ff) @[el2_exu_div_ctl.scala 191:41]
    node _T_1008 = bits(a_ff, 32, 32) @[el2_exu_div_ctl.scala 191:56]
    node _T_1009 = and(_T_1007, _T_1008) @[el2_exu_div_ctl.scala 191:50]
    rem_correct <= _T_1009 @[el2_exu_div_ctl.scala 191:16]
    node _T_1010 = xor(dividend_neg_ff, divisor_neg_ff) @[el2_exu_div_ctl.scala 192:50]
    node _T_1011 = and(sign_ff, _T_1010) @[el2_exu_div_ctl.scala 192:31]
    node _T_1012 = bits(_T_1011, 0, 0) @[el2_exu_div_ctl.scala 192:69]
    node _T_1013 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 192:91]
    wire _T_1014 : UInt<1>[31] @[el2_lib.scala 541:20]
    node _T_1015 = bits(_T_1013, 0, 0) @[el2_lib.scala 543:27]
    node _T_1016 = orr(_T_1015) @[el2_lib.scala 543:35]
    node _T_1017 = bits(_T_1013, 1, 1) @[el2_lib.scala 543:44]
    node _T_1018 = not(_T_1017) @[el2_lib.scala 543:40]
    node _T_1019 = bits(_T_1013, 1, 1) @[el2_lib.scala 543:51]
    node _T_1020 = mux(_T_1016, _T_1018, _T_1019) @[el2_lib.scala 543:23]
    _T_1014[0] <= _T_1020 @[el2_lib.scala 543:17]
    node _T_1021 = bits(_T_1013, 1, 0) @[el2_lib.scala 543:27]
    node _T_1022 = orr(_T_1021) @[el2_lib.scala 543:35]
    node _T_1023 = bits(_T_1013, 2, 2) @[el2_lib.scala 543:44]
    node _T_1024 = not(_T_1023) @[el2_lib.scala 543:40]
    node _T_1025 = bits(_T_1013, 2, 2) @[el2_lib.scala 543:51]
    node _T_1026 = mux(_T_1022, _T_1024, _T_1025) @[el2_lib.scala 543:23]
    _T_1014[1] <= _T_1026 @[el2_lib.scala 543:17]
    node _T_1027 = bits(_T_1013, 2, 0) @[el2_lib.scala 543:27]
    node _T_1028 = orr(_T_1027) @[el2_lib.scala 543:35]
    node _T_1029 = bits(_T_1013, 3, 3) @[el2_lib.scala 543:44]
    node _T_1030 = not(_T_1029) @[el2_lib.scala 543:40]
    node _T_1031 = bits(_T_1013, 3, 3) @[el2_lib.scala 543:51]
    node _T_1032 = mux(_T_1028, _T_1030, _T_1031) @[el2_lib.scala 543:23]
    _T_1014[2] <= _T_1032 @[el2_lib.scala 543:17]
    node _T_1033 = bits(_T_1013, 3, 0) @[el2_lib.scala 543:27]
    node _T_1034 = orr(_T_1033) @[el2_lib.scala 543:35]
    node _T_1035 = bits(_T_1013, 4, 4) @[el2_lib.scala 543:44]
    node _T_1036 = not(_T_1035) @[el2_lib.scala 543:40]
    node _T_1037 = bits(_T_1013, 4, 4) @[el2_lib.scala 543:51]
    node _T_1038 = mux(_T_1034, _T_1036, _T_1037) @[el2_lib.scala 543:23]
    _T_1014[3] <= _T_1038 @[el2_lib.scala 543:17]
    node _T_1039 = bits(_T_1013, 4, 0) @[el2_lib.scala 543:27]
    node _T_1040 = orr(_T_1039) @[el2_lib.scala 543:35]
    node _T_1041 = bits(_T_1013, 5, 5) @[el2_lib.scala 543:44]
    node _T_1042 = not(_T_1041) @[el2_lib.scala 543:40]
    node _T_1043 = bits(_T_1013, 5, 5) @[el2_lib.scala 543:51]
    node _T_1044 = mux(_T_1040, _T_1042, _T_1043) @[el2_lib.scala 543:23]
    _T_1014[4] <= _T_1044 @[el2_lib.scala 543:17]
    node _T_1045 = bits(_T_1013, 5, 0) @[el2_lib.scala 543:27]
    node _T_1046 = orr(_T_1045) @[el2_lib.scala 543:35]
    node _T_1047 = bits(_T_1013, 6, 6) @[el2_lib.scala 543:44]
    node _T_1048 = not(_T_1047) @[el2_lib.scala 543:40]
    node _T_1049 = bits(_T_1013, 6, 6) @[el2_lib.scala 543:51]
    node _T_1050 = mux(_T_1046, _T_1048, _T_1049) @[el2_lib.scala 543:23]
    _T_1014[5] <= _T_1050 @[el2_lib.scala 543:17]
    node _T_1051 = bits(_T_1013, 6, 0) @[el2_lib.scala 543:27]
    node _T_1052 = orr(_T_1051) @[el2_lib.scala 543:35]
    node _T_1053 = bits(_T_1013, 7, 7) @[el2_lib.scala 543:44]
    node _T_1054 = not(_T_1053) @[el2_lib.scala 543:40]
    node _T_1055 = bits(_T_1013, 7, 7) @[el2_lib.scala 543:51]
    node _T_1056 = mux(_T_1052, _T_1054, _T_1055) @[el2_lib.scala 543:23]
    _T_1014[6] <= _T_1056 @[el2_lib.scala 543:17]
    node _T_1057 = bits(_T_1013, 7, 0) @[el2_lib.scala 543:27]
    node _T_1058 = orr(_T_1057) @[el2_lib.scala 543:35]
    node _T_1059 = bits(_T_1013, 8, 8) @[el2_lib.scala 543:44]
    node _T_1060 = not(_T_1059) @[el2_lib.scala 543:40]
    node _T_1061 = bits(_T_1013, 8, 8) @[el2_lib.scala 543:51]
    node _T_1062 = mux(_T_1058, _T_1060, _T_1061) @[el2_lib.scala 543:23]
    _T_1014[7] <= _T_1062 @[el2_lib.scala 543:17]
    node _T_1063 = bits(_T_1013, 8, 0) @[el2_lib.scala 543:27]
    node _T_1064 = orr(_T_1063) @[el2_lib.scala 543:35]
    node _T_1065 = bits(_T_1013, 9, 9) @[el2_lib.scala 543:44]
    node _T_1066 = not(_T_1065) @[el2_lib.scala 543:40]
    node _T_1067 = bits(_T_1013, 9, 9) @[el2_lib.scala 543:51]
    node _T_1068 = mux(_T_1064, _T_1066, _T_1067) @[el2_lib.scala 543:23]
    _T_1014[8] <= _T_1068 @[el2_lib.scala 543:17]
    node _T_1069 = bits(_T_1013, 9, 0) @[el2_lib.scala 543:27]
    node _T_1070 = orr(_T_1069) @[el2_lib.scala 543:35]
    node _T_1071 = bits(_T_1013, 10, 10) @[el2_lib.scala 543:44]
    node _T_1072 = not(_T_1071) @[el2_lib.scala 543:40]
    node _T_1073 = bits(_T_1013, 10, 10) @[el2_lib.scala 543:51]
    node _T_1074 = mux(_T_1070, _T_1072, _T_1073) @[el2_lib.scala 543:23]
    _T_1014[9] <= _T_1074 @[el2_lib.scala 543:17]
    node _T_1075 = bits(_T_1013, 10, 0) @[el2_lib.scala 543:27]
    node _T_1076 = orr(_T_1075) @[el2_lib.scala 543:35]
    node _T_1077 = bits(_T_1013, 11, 11) @[el2_lib.scala 543:44]
    node _T_1078 = not(_T_1077) @[el2_lib.scala 543:40]
    node _T_1079 = bits(_T_1013, 11, 11) @[el2_lib.scala 543:51]
    node _T_1080 = mux(_T_1076, _T_1078, _T_1079) @[el2_lib.scala 543:23]
    _T_1014[10] <= _T_1080 @[el2_lib.scala 543:17]
    node _T_1081 = bits(_T_1013, 11, 0) @[el2_lib.scala 543:27]
    node _T_1082 = orr(_T_1081) @[el2_lib.scala 543:35]
    node _T_1083 = bits(_T_1013, 12, 12) @[el2_lib.scala 543:44]
    node _T_1084 = not(_T_1083) @[el2_lib.scala 543:40]
    node _T_1085 = bits(_T_1013, 12, 12) @[el2_lib.scala 543:51]
    node _T_1086 = mux(_T_1082, _T_1084, _T_1085) @[el2_lib.scala 543:23]
    _T_1014[11] <= _T_1086 @[el2_lib.scala 543:17]
    node _T_1087 = bits(_T_1013, 12, 0) @[el2_lib.scala 543:27]
    node _T_1088 = orr(_T_1087) @[el2_lib.scala 543:35]
    node _T_1089 = bits(_T_1013, 13, 13) @[el2_lib.scala 543:44]
    node _T_1090 = not(_T_1089) @[el2_lib.scala 543:40]
    node _T_1091 = bits(_T_1013, 13, 13) @[el2_lib.scala 543:51]
    node _T_1092 = mux(_T_1088, _T_1090, _T_1091) @[el2_lib.scala 543:23]
    _T_1014[12] <= _T_1092 @[el2_lib.scala 543:17]
    node _T_1093 = bits(_T_1013, 13, 0) @[el2_lib.scala 543:27]
    node _T_1094 = orr(_T_1093) @[el2_lib.scala 543:35]
    node _T_1095 = bits(_T_1013, 14, 14) @[el2_lib.scala 543:44]
    node _T_1096 = not(_T_1095) @[el2_lib.scala 543:40]
    node _T_1097 = bits(_T_1013, 14, 14) @[el2_lib.scala 543:51]
    node _T_1098 = mux(_T_1094, _T_1096, _T_1097) @[el2_lib.scala 543:23]
    _T_1014[13] <= _T_1098 @[el2_lib.scala 543:17]
    node _T_1099 = bits(_T_1013, 14, 0) @[el2_lib.scala 543:27]
    node _T_1100 = orr(_T_1099) @[el2_lib.scala 543:35]
    node _T_1101 = bits(_T_1013, 15, 15) @[el2_lib.scala 543:44]
    node _T_1102 = not(_T_1101) @[el2_lib.scala 543:40]
    node _T_1103 = bits(_T_1013, 15, 15) @[el2_lib.scala 543:51]
    node _T_1104 = mux(_T_1100, _T_1102, _T_1103) @[el2_lib.scala 543:23]
    _T_1014[14] <= _T_1104 @[el2_lib.scala 543:17]
    node _T_1105 = bits(_T_1013, 15, 0) @[el2_lib.scala 543:27]
    node _T_1106 = orr(_T_1105) @[el2_lib.scala 543:35]
    node _T_1107 = bits(_T_1013, 16, 16) @[el2_lib.scala 543:44]
    node _T_1108 = not(_T_1107) @[el2_lib.scala 543:40]
    node _T_1109 = bits(_T_1013, 16, 16) @[el2_lib.scala 543:51]
    node _T_1110 = mux(_T_1106, _T_1108, _T_1109) @[el2_lib.scala 543:23]
    _T_1014[15] <= _T_1110 @[el2_lib.scala 543:17]
    node _T_1111 = bits(_T_1013, 16, 0) @[el2_lib.scala 543:27]
    node _T_1112 = orr(_T_1111) @[el2_lib.scala 543:35]
    node _T_1113 = bits(_T_1013, 17, 17) @[el2_lib.scala 543:44]
    node _T_1114 = not(_T_1113) @[el2_lib.scala 543:40]
    node _T_1115 = bits(_T_1013, 17, 17) @[el2_lib.scala 543:51]
    node _T_1116 = mux(_T_1112, _T_1114, _T_1115) @[el2_lib.scala 543:23]
    _T_1014[16] <= _T_1116 @[el2_lib.scala 543:17]
    node _T_1117 = bits(_T_1013, 17, 0) @[el2_lib.scala 543:27]
    node _T_1118 = orr(_T_1117) @[el2_lib.scala 543:35]
    node _T_1119 = bits(_T_1013, 18, 18) @[el2_lib.scala 543:44]
    node _T_1120 = not(_T_1119) @[el2_lib.scala 543:40]
    node _T_1121 = bits(_T_1013, 18, 18) @[el2_lib.scala 543:51]
    node _T_1122 = mux(_T_1118, _T_1120, _T_1121) @[el2_lib.scala 543:23]
    _T_1014[17] <= _T_1122 @[el2_lib.scala 543:17]
    node _T_1123 = bits(_T_1013, 18, 0) @[el2_lib.scala 543:27]
    node _T_1124 = orr(_T_1123) @[el2_lib.scala 543:35]
    node _T_1125 = bits(_T_1013, 19, 19) @[el2_lib.scala 543:44]
    node _T_1126 = not(_T_1125) @[el2_lib.scala 543:40]
    node _T_1127 = bits(_T_1013, 19, 19) @[el2_lib.scala 543:51]
    node _T_1128 = mux(_T_1124, _T_1126, _T_1127) @[el2_lib.scala 543:23]
    _T_1014[18] <= _T_1128 @[el2_lib.scala 543:17]
    node _T_1129 = bits(_T_1013, 19, 0) @[el2_lib.scala 543:27]
    node _T_1130 = orr(_T_1129) @[el2_lib.scala 543:35]
    node _T_1131 = bits(_T_1013, 20, 20) @[el2_lib.scala 543:44]
    node _T_1132 = not(_T_1131) @[el2_lib.scala 543:40]
    node _T_1133 = bits(_T_1013, 20, 20) @[el2_lib.scala 543:51]
    node _T_1134 = mux(_T_1130, _T_1132, _T_1133) @[el2_lib.scala 543:23]
    _T_1014[19] <= _T_1134 @[el2_lib.scala 543:17]
    node _T_1135 = bits(_T_1013, 20, 0) @[el2_lib.scala 543:27]
    node _T_1136 = orr(_T_1135) @[el2_lib.scala 543:35]
    node _T_1137 = bits(_T_1013, 21, 21) @[el2_lib.scala 543:44]
    node _T_1138 = not(_T_1137) @[el2_lib.scala 543:40]
    node _T_1139 = bits(_T_1013, 21, 21) @[el2_lib.scala 543:51]
    node _T_1140 = mux(_T_1136, _T_1138, _T_1139) @[el2_lib.scala 543:23]
    _T_1014[20] <= _T_1140 @[el2_lib.scala 543:17]
    node _T_1141 = bits(_T_1013, 21, 0) @[el2_lib.scala 543:27]
    node _T_1142 = orr(_T_1141) @[el2_lib.scala 543:35]
    node _T_1143 = bits(_T_1013, 22, 22) @[el2_lib.scala 543:44]
    node _T_1144 = not(_T_1143) @[el2_lib.scala 543:40]
    node _T_1145 = bits(_T_1013, 22, 22) @[el2_lib.scala 543:51]
    node _T_1146 = mux(_T_1142, _T_1144, _T_1145) @[el2_lib.scala 543:23]
    _T_1014[21] <= _T_1146 @[el2_lib.scala 543:17]
    node _T_1147 = bits(_T_1013, 22, 0) @[el2_lib.scala 543:27]
    node _T_1148 = orr(_T_1147) @[el2_lib.scala 543:35]
    node _T_1149 = bits(_T_1013, 23, 23) @[el2_lib.scala 543:44]
    node _T_1150 = not(_T_1149) @[el2_lib.scala 543:40]
    node _T_1151 = bits(_T_1013, 23, 23) @[el2_lib.scala 543:51]
    node _T_1152 = mux(_T_1148, _T_1150, _T_1151) @[el2_lib.scala 543:23]
    _T_1014[22] <= _T_1152 @[el2_lib.scala 543:17]
    node _T_1153 = bits(_T_1013, 23, 0) @[el2_lib.scala 543:27]
    node _T_1154 = orr(_T_1153) @[el2_lib.scala 543:35]
    node _T_1155 = bits(_T_1013, 24, 24) @[el2_lib.scala 543:44]
    node _T_1156 = not(_T_1155) @[el2_lib.scala 543:40]
    node _T_1157 = bits(_T_1013, 24, 24) @[el2_lib.scala 543:51]
    node _T_1158 = mux(_T_1154, _T_1156, _T_1157) @[el2_lib.scala 543:23]
    _T_1014[23] <= _T_1158 @[el2_lib.scala 543:17]
    node _T_1159 = bits(_T_1013, 24, 0) @[el2_lib.scala 543:27]
    node _T_1160 = orr(_T_1159) @[el2_lib.scala 543:35]
    node _T_1161 = bits(_T_1013, 25, 25) @[el2_lib.scala 543:44]
    node _T_1162 = not(_T_1161) @[el2_lib.scala 543:40]
    node _T_1163 = bits(_T_1013, 25, 25) @[el2_lib.scala 543:51]
    node _T_1164 = mux(_T_1160, _T_1162, _T_1163) @[el2_lib.scala 543:23]
    _T_1014[24] <= _T_1164 @[el2_lib.scala 543:17]
    node _T_1165 = bits(_T_1013, 25, 0) @[el2_lib.scala 543:27]
    node _T_1166 = orr(_T_1165) @[el2_lib.scala 543:35]
    node _T_1167 = bits(_T_1013, 26, 26) @[el2_lib.scala 543:44]
    node _T_1168 = not(_T_1167) @[el2_lib.scala 543:40]
    node _T_1169 = bits(_T_1013, 26, 26) @[el2_lib.scala 543:51]
    node _T_1170 = mux(_T_1166, _T_1168, _T_1169) @[el2_lib.scala 543:23]
    _T_1014[25] <= _T_1170 @[el2_lib.scala 543:17]
    node _T_1171 = bits(_T_1013, 26, 0) @[el2_lib.scala 543:27]
    node _T_1172 = orr(_T_1171) @[el2_lib.scala 543:35]
    node _T_1173 = bits(_T_1013, 27, 27) @[el2_lib.scala 543:44]
    node _T_1174 = not(_T_1173) @[el2_lib.scala 543:40]
    node _T_1175 = bits(_T_1013, 27, 27) @[el2_lib.scala 543:51]
    node _T_1176 = mux(_T_1172, _T_1174, _T_1175) @[el2_lib.scala 543:23]
    _T_1014[26] <= _T_1176 @[el2_lib.scala 543:17]
    node _T_1177 = bits(_T_1013, 27, 0) @[el2_lib.scala 543:27]
    node _T_1178 = orr(_T_1177) @[el2_lib.scala 543:35]
    node _T_1179 = bits(_T_1013, 28, 28) @[el2_lib.scala 543:44]
    node _T_1180 = not(_T_1179) @[el2_lib.scala 543:40]
    node _T_1181 = bits(_T_1013, 28, 28) @[el2_lib.scala 543:51]
    node _T_1182 = mux(_T_1178, _T_1180, _T_1181) @[el2_lib.scala 543:23]
    _T_1014[27] <= _T_1182 @[el2_lib.scala 543:17]
    node _T_1183 = bits(_T_1013, 28, 0) @[el2_lib.scala 543:27]
    node _T_1184 = orr(_T_1183) @[el2_lib.scala 543:35]
    node _T_1185 = bits(_T_1013, 29, 29) @[el2_lib.scala 543:44]
    node _T_1186 = not(_T_1185) @[el2_lib.scala 543:40]
    node _T_1187 = bits(_T_1013, 29, 29) @[el2_lib.scala 543:51]
    node _T_1188 = mux(_T_1184, _T_1186, _T_1187) @[el2_lib.scala 543:23]
    _T_1014[28] <= _T_1188 @[el2_lib.scala 543:17]
    node _T_1189 = bits(_T_1013, 29, 0) @[el2_lib.scala 543:27]
    node _T_1190 = orr(_T_1189) @[el2_lib.scala 543:35]
    node _T_1191 = bits(_T_1013, 30, 30) @[el2_lib.scala 543:44]
    node _T_1192 = not(_T_1191) @[el2_lib.scala 543:40]
    node _T_1193 = bits(_T_1013, 30, 30) @[el2_lib.scala 543:51]
    node _T_1194 = mux(_T_1190, _T_1192, _T_1193) @[el2_lib.scala 543:23]
    _T_1014[29] <= _T_1194 @[el2_lib.scala 543:17]
    node _T_1195 = bits(_T_1013, 30, 0) @[el2_lib.scala 543:27]
    node _T_1196 = orr(_T_1195) @[el2_lib.scala 543:35]
    node _T_1197 = bits(_T_1013, 31, 31) @[el2_lib.scala 543:44]
    node _T_1198 = not(_T_1197) @[el2_lib.scala 543:40]
    node _T_1199 = bits(_T_1013, 31, 31) @[el2_lib.scala 543:51]
    node _T_1200 = mux(_T_1196, _T_1198, _T_1199) @[el2_lib.scala 543:23]
    _T_1014[30] <= _T_1200 @[el2_lib.scala 543:17]
    node _T_1201 = cat(_T_1014[2], _T_1014[1]) @[el2_lib.scala 545:14]
    node _T_1202 = cat(_T_1201, _T_1014[0]) @[el2_lib.scala 545:14]
    node _T_1203 = cat(_T_1014[4], _T_1014[3]) @[el2_lib.scala 545:14]
    node _T_1204 = cat(_T_1014[6], _T_1014[5]) @[el2_lib.scala 545:14]
    node _T_1205 = cat(_T_1204, _T_1203) @[el2_lib.scala 545:14]
    node _T_1206 = cat(_T_1205, _T_1202) @[el2_lib.scala 545:14]
    node _T_1207 = cat(_T_1014[8], _T_1014[7]) @[el2_lib.scala 545:14]
    node _T_1208 = cat(_T_1014[10], _T_1014[9]) @[el2_lib.scala 545:14]
    node _T_1209 = cat(_T_1208, _T_1207) @[el2_lib.scala 545:14]
    node _T_1210 = cat(_T_1014[12], _T_1014[11]) @[el2_lib.scala 545:14]
    node _T_1211 = cat(_T_1014[14], _T_1014[13]) @[el2_lib.scala 545:14]
    node _T_1212 = cat(_T_1211, _T_1210) @[el2_lib.scala 545:14]
    node _T_1213 = cat(_T_1212, _T_1209) @[el2_lib.scala 545:14]
    node _T_1214 = cat(_T_1213, _T_1206) @[el2_lib.scala 545:14]
    node _T_1215 = cat(_T_1014[16], _T_1014[15]) @[el2_lib.scala 545:14]
    node _T_1216 = cat(_T_1014[18], _T_1014[17]) @[el2_lib.scala 545:14]
    node _T_1217 = cat(_T_1216, _T_1215) @[el2_lib.scala 545:14]
    node _T_1218 = cat(_T_1014[20], _T_1014[19]) @[el2_lib.scala 545:14]
    node _T_1219 = cat(_T_1014[22], _T_1014[21]) @[el2_lib.scala 545:14]
    node _T_1220 = cat(_T_1219, _T_1218) @[el2_lib.scala 545:14]
    node _T_1221 = cat(_T_1220, _T_1217) @[el2_lib.scala 545:14]
    node _T_1222 = cat(_T_1014[24], _T_1014[23]) @[el2_lib.scala 545:14]
    node _T_1223 = cat(_T_1014[26], _T_1014[25]) @[el2_lib.scala 545:14]
    node _T_1224 = cat(_T_1223, _T_1222) @[el2_lib.scala 545:14]
    node _T_1225 = cat(_T_1014[28], _T_1014[27]) @[el2_lib.scala 545:14]
    node _T_1226 = cat(_T_1014[30], _T_1014[29]) @[el2_lib.scala 545:14]
    node _T_1227 = cat(_T_1226, _T_1225) @[el2_lib.scala 545:14]
    node _T_1228 = cat(_T_1227, _T_1224) @[el2_lib.scala 545:14]
    node _T_1229 = cat(_T_1228, _T_1221) @[el2_lib.scala 545:14]
    node _T_1230 = cat(_T_1229, _T_1214) @[el2_lib.scala 545:14]
    node _T_1231 = bits(_T_1013, 0, 0) @[el2_lib.scala 545:24]
    node _T_1232 = cat(_T_1230, _T_1231) @[Cat.scala 29:58]
    node _T_1233 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 192:104]
    node q_ff_eff = mux(_T_1012, _T_1232, _T_1233) @[el2_exu_div_ctl.scala 192:21]
    node _T_1234 = and(sign_ff, dividend_neg_ff) @[el2_exu_div_ctl.scala 193:31]
    node _T_1235 = bits(_T_1234, 0, 0) @[el2_exu_div_ctl.scala 193:51]
    node _T_1236 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 193:74]
    wire _T_1237 : UInt<1>[31] @[el2_lib.scala 541:20]
    node _T_1238 = bits(_T_1236, 0, 0) @[el2_lib.scala 543:27]
    node _T_1239 = orr(_T_1238) @[el2_lib.scala 543:35]
    node _T_1240 = bits(_T_1236, 1, 1) @[el2_lib.scala 543:44]
    node _T_1241 = not(_T_1240) @[el2_lib.scala 543:40]
    node _T_1242 = bits(_T_1236, 1, 1) @[el2_lib.scala 543:51]
    node _T_1243 = mux(_T_1239, _T_1241, _T_1242) @[el2_lib.scala 543:23]
    _T_1237[0] <= _T_1243 @[el2_lib.scala 543:17]
    node _T_1244 = bits(_T_1236, 1, 0) @[el2_lib.scala 543:27]
    node _T_1245 = orr(_T_1244) @[el2_lib.scala 543:35]
    node _T_1246 = bits(_T_1236, 2, 2) @[el2_lib.scala 543:44]
    node _T_1247 = not(_T_1246) @[el2_lib.scala 543:40]
    node _T_1248 = bits(_T_1236, 2, 2) @[el2_lib.scala 543:51]
    node _T_1249 = mux(_T_1245, _T_1247, _T_1248) @[el2_lib.scala 543:23]
    _T_1237[1] <= _T_1249 @[el2_lib.scala 543:17]
    node _T_1250 = bits(_T_1236, 2, 0) @[el2_lib.scala 543:27]
    node _T_1251 = orr(_T_1250) @[el2_lib.scala 543:35]
    node _T_1252 = bits(_T_1236, 3, 3) @[el2_lib.scala 543:44]
    node _T_1253 = not(_T_1252) @[el2_lib.scala 543:40]
    node _T_1254 = bits(_T_1236, 3, 3) @[el2_lib.scala 543:51]
    node _T_1255 = mux(_T_1251, _T_1253, _T_1254) @[el2_lib.scala 543:23]
    _T_1237[2] <= _T_1255 @[el2_lib.scala 543:17]
    node _T_1256 = bits(_T_1236, 3, 0) @[el2_lib.scala 543:27]
    node _T_1257 = orr(_T_1256) @[el2_lib.scala 543:35]
    node _T_1258 = bits(_T_1236, 4, 4) @[el2_lib.scala 543:44]
    node _T_1259 = not(_T_1258) @[el2_lib.scala 543:40]
    node _T_1260 = bits(_T_1236, 4, 4) @[el2_lib.scala 543:51]
    node _T_1261 = mux(_T_1257, _T_1259, _T_1260) @[el2_lib.scala 543:23]
    _T_1237[3] <= _T_1261 @[el2_lib.scala 543:17]
    node _T_1262 = bits(_T_1236, 4, 0) @[el2_lib.scala 543:27]
    node _T_1263 = orr(_T_1262) @[el2_lib.scala 543:35]
    node _T_1264 = bits(_T_1236, 5, 5) @[el2_lib.scala 543:44]
    node _T_1265 = not(_T_1264) @[el2_lib.scala 543:40]
    node _T_1266 = bits(_T_1236, 5, 5) @[el2_lib.scala 543:51]
    node _T_1267 = mux(_T_1263, _T_1265, _T_1266) @[el2_lib.scala 543:23]
    _T_1237[4] <= _T_1267 @[el2_lib.scala 543:17]
    node _T_1268 = bits(_T_1236, 5, 0) @[el2_lib.scala 543:27]
    node _T_1269 = orr(_T_1268) @[el2_lib.scala 543:35]
    node _T_1270 = bits(_T_1236, 6, 6) @[el2_lib.scala 543:44]
    node _T_1271 = not(_T_1270) @[el2_lib.scala 543:40]
    node _T_1272 = bits(_T_1236, 6, 6) @[el2_lib.scala 543:51]
    node _T_1273 = mux(_T_1269, _T_1271, _T_1272) @[el2_lib.scala 543:23]
    _T_1237[5] <= _T_1273 @[el2_lib.scala 543:17]
    node _T_1274 = bits(_T_1236, 6, 0) @[el2_lib.scala 543:27]
    node _T_1275 = orr(_T_1274) @[el2_lib.scala 543:35]
    node _T_1276 = bits(_T_1236, 7, 7) @[el2_lib.scala 543:44]
    node _T_1277 = not(_T_1276) @[el2_lib.scala 543:40]
    node _T_1278 = bits(_T_1236, 7, 7) @[el2_lib.scala 543:51]
    node _T_1279 = mux(_T_1275, _T_1277, _T_1278) @[el2_lib.scala 543:23]
    _T_1237[6] <= _T_1279 @[el2_lib.scala 543:17]
    node _T_1280 = bits(_T_1236, 7, 0) @[el2_lib.scala 543:27]
    node _T_1281 = orr(_T_1280) @[el2_lib.scala 543:35]
    node _T_1282 = bits(_T_1236, 8, 8) @[el2_lib.scala 543:44]
    node _T_1283 = not(_T_1282) @[el2_lib.scala 543:40]
    node _T_1284 = bits(_T_1236, 8, 8) @[el2_lib.scala 543:51]
    node _T_1285 = mux(_T_1281, _T_1283, _T_1284) @[el2_lib.scala 543:23]
    _T_1237[7] <= _T_1285 @[el2_lib.scala 543:17]
    node _T_1286 = bits(_T_1236, 8, 0) @[el2_lib.scala 543:27]
    node _T_1287 = orr(_T_1286) @[el2_lib.scala 543:35]
    node _T_1288 = bits(_T_1236, 9, 9) @[el2_lib.scala 543:44]
    node _T_1289 = not(_T_1288) @[el2_lib.scala 543:40]
    node _T_1290 = bits(_T_1236, 9, 9) @[el2_lib.scala 543:51]
    node _T_1291 = mux(_T_1287, _T_1289, _T_1290) @[el2_lib.scala 543:23]
    _T_1237[8] <= _T_1291 @[el2_lib.scala 543:17]
    node _T_1292 = bits(_T_1236, 9, 0) @[el2_lib.scala 543:27]
    node _T_1293 = orr(_T_1292) @[el2_lib.scala 543:35]
    node _T_1294 = bits(_T_1236, 10, 10) @[el2_lib.scala 543:44]
    node _T_1295 = not(_T_1294) @[el2_lib.scala 543:40]
    node _T_1296 = bits(_T_1236, 10, 10) @[el2_lib.scala 543:51]
    node _T_1297 = mux(_T_1293, _T_1295, _T_1296) @[el2_lib.scala 543:23]
    _T_1237[9] <= _T_1297 @[el2_lib.scala 543:17]
    node _T_1298 = bits(_T_1236, 10, 0) @[el2_lib.scala 543:27]
    node _T_1299 = orr(_T_1298) @[el2_lib.scala 543:35]
    node _T_1300 = bits(_T_1236, 11, 11) @[el2_lib.scala 543:44]
    node _T_1301 = not(_T_1300) @[el2_lib.scala 543:40]
    node _T_1302 = bits(_T_1236, 11, 11) @[el2_lib.scala 543:51]
    node _T_1303 = mux(_T_1299, _T_1301, _T_1302) @[el2_lib.scala 543:23]
    _T_1237[10] <= _T_1303 @[el2_lib.scala 543:17]
    node _T_1304 = bits(_T_1236, 11, 0) @[el2_lib.scala 543:27]
    node _T_1305 = orr(_T_1304) @[el2_lib.scala 543:35]
    node _T_1306 = bits(_T_1236, 12, 12) @[el2_lib.scala 543:44]
    node _T_1307 = not(_T_1306) @[el2_lib.scala 543:40]
    node _T_1308 = bits(_T_1236, 12, 12) @[el2_lib.scala 543:51]
    node _T_1309 = mux(_T_1305, _T_1307, _T_1308) @[el2_lib.scala 543:23]
    _T_1237[11] <= _T_1309 @[el2_lib.scala 543:17]
    node _T_1310 = bits(_T_1236, 12, 0) @[el2_lib.scala 543:27]
    node _T_1311 = orr(_T_1310) @[el2_lib.scala 543:35]
    node _T_1312 = bits(_T_1236, 13, 13) @[el2_lib.scala 543:44]
    node _T_1313 = not(_T_1312) @[el2_lib.scala 543:40]
    node _T_1314 = bits(_T_1236, 13, 13) @[el2_lib.scala 543:51]
    node _T_1315 = mux(_T_1311, _T_1313, _T_1314) @[el2_lib.scala 543:23]
    _T_1237[12] <= _T_1315 @[el2_lib.scala 543:17]
    node _T_1316 = bits(_T_1236, 13, 0) @[el2_lib.scala 543:27]
    node _T_1317 = orr(_T_1316) @[el2_lib.scala 543:35]
    node _T_1318 = bits(_T_1236, 14, 14) @[el2_lib.scala 543:44]
    node _T_1319 = not(_T_1318) @[el2_lib.scala 543:40]
    node _T_1320 = bits(_T_1236, 14, 14) @[el2_lib.scala 543:51]
    node _T_1321 = mux(_T_1317, _T_1319, _T_1320) @[el2_lib.scala 543:23]
    _T_1237[13] <= _T_1321 @[el2_lib.scala 543:17]
    node _T_1322 = bits(_T_1236, 14, 0) @[el2_lib.scala 543:27]
    node _T_1323 = orr(_T_1322) @[el2_lib.scala 543:35]
    node _T_1324 = bits(_T_1236, 15, 15) @[el2_lib.scala 543:44]
    node _T_1325 = not(_T_1324) @[el2_lib.scala 543:40]
    node _T_1326 = bits(_T_1236, 15, 15) @[el2_lib.scala 543:51]
    node _T_1327 = mux(_T_1323, _T_1325, _T_1326) @[el2_lib.scala 543:23]
    _T_1237[14] <= _T_1327 @[el2_lib.scala 543:17]
    node _T_1328 = bits(_T_1236, 15, 0) @[el2_lib.scala 543:27]
    node _T_1329 = orr(_T_1328) @[el2_lib.scala 543:35]
    node _T_1330 = bits(_T_1236, 16, 16) @[el2_lib.scala 543:44]
    node _T_1331 = not(_T_1330) @[el2_lib.scala 543:40]
    node _T_1332 = bits(_T_1236, 16, 16) @[el2_lib.scala 543:51]
    node _T_1333 = mux(_T_1329, _T_1331, _T_1332) @[el2_lib.scala 543:23]
    _T_1237[15] <= _T_1333 @[el2_lib.scala 543:17]
    node _T_1334 = bits(_T_1236, 16, 0) @[el2_lib.scala 543:27]
    node _T_1335 = orr(_T_1334) @[el2_lib.scala 543:35]
    node _T_1336 = bits(_T_1236, 17, 17) @[el2_lib.scala 543:44]
    node _T_1337 = not(_T_1336) @[el2_lib.scala 543:40]
    node _T_1338 = bits(_T_1236, 17, 17) @[el2_lib.scala 543:51]
    node _T_1339 = mux(_T_1335, _T_1337, _T_1338) @[el2_lib.scala 543:23]
    _T_1237[16] <= _T_1339 @[el2_lib.scala 543:17]
    node _T_1340 = bits(_T_1236, 17, 0) @[el2_lib.scala 543:27]
    node _T_1341 = orr(_T_1340) @[el2_lib.scala 543:35]
    node _T_1342 = bits(_T_1236, 18, 18) @[el2_lib.scala 543:44]
    node _T_1343 = not(_T_1342) @[el2_lib.scala 543:40]
    node _T_1344 = bits(_T_1236, 18, 18) @[el2_lib.scala 543:51]
    node _T_1345 = mux(_T_1341, _T_1343, _T_1344) @[el2_lib.scala 543:23]
    _T_1237[17] <= _T_1345 @[el2_lib.scala 543:17]
    node _T_1346 = bits(_T_1236, 18, 0) @[el2_lib.scala 543:27]
    node _T_1347 = orr(_T_1346) @[el2_lib.scala 543:35]
    node _T_1348 = bits(_T_1236, 19, 19) @[el2_lib.scala 543:44]
    node _T_1349 = not(_T_1348) @[el2_lib.scala 543:40]
    node _T_1350 = bits(_T_1236, 19, 19) @[el2_lib.scala 543:51]
    node _T_1351 = mux(_T_1347, _T_1349, _T_1350) @[el2_lib.scala 543:23]
    _T_1237[18] <= _T_1351 @[el2_lib.scala 543:17]
    node _T_1352 = bits(_T_1236, 19, 0) @[el2_lib.scala 543:27]
    node _T_1353 = orr(_T_1352) @[el2_lib.scala 543:35]
    node _T_1354 = bits(_T_1236, 20, 20) @[el2_lib.scala 543:44]
    node _T_1355 = not(_T_1354) @[el2_lib.scala 543:40]
    node _T_1356 = bits(_T_1236, 20, 20) @[el2_lib.scala 543:51]
    node _T_1357 = mux(_T_1353, _T_1355, _T_1356) @[el2_lib.scala 543:23]
    _T_1237[19] <= _T_1357 @[el2_lib.scala 543:17]
    node _T_1358 = bits(_T_1236, 20, 0) @[el2_lib.scala 543:27]
    node _T_1359 = orr(_T_1358) @[el2_lib.scala 543:35]
    node _T_1360 = bits(_T_1236, 21, 21) @[el2_lib.scala 543:44]
    node _T_1361 = not(_T_1360) @[el2_lib.scala 543:40]
    node _T_1362 = bits(_T_1236, 21, 21) @[el2_lib.scala 543:51]
    node _T_1363 = mux(_T_1359, _T_1361, _T_1362) @[el2_lib.scala 543:23]
    _T_1237[20] <= _T_1363 @[el2_lib.scala 543:17]
    node _T_1364 = bits(_T_1236, 21, 0) @[el2_lib.scala 543:27]
    node _T_1365 = orr(_T_1364) @[el2_lib.scala 543:35]
    node _T_1366 = bits(_T_1236, 22, 22) @[el2_lib.scala 543:44]
    node _T_1367 = not(_T_1366) @[el2_lib.scala 543:40]
    node _T_1368 = bits(_T_1236, 22, 22) @[el2_lib.scala 543:51]
    node _T_1369 = mux(_T_1365, _T_1367, _T_1368) @[el2_lib.scala 543:23]
    _T_1237[21] <= _T_1369 @[el2_lib.scala 543:17]
    node _T_1370 = bits(_T_1236, 22, 0) @[el2_lib.scala 543:27]
    node _T_1371 = orr(_T_1370) @[el2_lib.scala 543:35]
    node _T_1372 = bits(_T_1236, 23, 23) @[el2_lib.scala 543:44]
    node _T_1373 = not(_T_1372) @[el2_lib.scala 543:40]
    node _T_1374 = bits(_T_1236, 23, 23) @[el2_lib.scala 543:51]
    node _T_1375 = mux(_T_1371, _T_1373, _T_1374) @[el2_lib.scala 543:23]
    _T_1237[22] <= _T_1375 @[el2_lib.scala 543:17]
    node _T_1376 = bits(_T_1236, 23, 0) @[el2_lib.scala 543:27]
    node _T_1377 = orr(_T_1376) @[el2_lib.scala 543:35]
    node _T_1378 = bits(_T_1236, 24, 24) @[el2_lib.scala 543:44]
    node _T_1379 = not(_T_1378) @[el2_lib.scala 543:40]
    node _T_1380 = bits(_T_1236, 24, 24) @[el2_lib.scala 543:51]
    node _T_1381 = mux(_T_1377, _T_1379, _T_1380) @[el2_lib.scala 543:23]
    _T_1237[23] <= _T_1381 @[el2_lib.scala 543:17]
    node _T_1382 = bits(_T_1236, 24, 0) @[el2_lib.scala 543:27]
    node _T_1383 = orr(_T_1382) @[el2_lib.scala 543:35]
    node _T_1384 = bits(_T_1236, 25, 25) @[el2_lib.scala 543:44]
    node _T_1385 = not(_T_1384) @[el2_lib.scala 543:40]
    node _T_1386 = bits(_T_1236, 25, 25) @[el2_lib.scala 543:51]
    node _T_1387 = mux(_T_1383, _T_1385, _T_1386) @[el2_lib.scala 543:23]
    _T_1237[24] <= _T_1387 @[el2_lib.scala 543:17]
    node _T_1388 = bits(_T_1236, 25, 0) @[el2_lib.scala 543:27]
    node _T_1389 = orr(_T_1388) @[el2_lib.scala 543:35]
    node _T_1390 = bits(_T_1236, 26, 26) @[el2_lib.scala 543:44]
    node _T_1391 = not(_T_1390) @[el2_lib.scala 543:40]
    node _T_1392 = bits(_T_1236, 26, 26) @[el2_lib.scala 543:51]
    node _T_1393 = mux(_T_1389, _T_1391, _T_1392) @[el2_lib.scala 543:23]
    _T_1237[25] <= _T_1393 @[el2_lib.scala 543:17]
    node _T_1394 = bits(_T_1236, 26, 0) @[el2_lib.scala 543:27]
    node _T_1395 = orr(_T_1394) @[el2_lib.scala 543:35]
    node _T_1396 = bits(_T_1236, 27, 27) @[el2_lib.scala 543:44]
    node _T_1397 = not(_T_1396) @[el2_lib.scala 543:40]
    node _T_1398 = bits(_T_1236, 27, 27) @[el2_lib.scala 543:51]
    node _T_1399 = mux(_T_1395, _T_1397, _T_1398) @[el2_lib.scala 543:23]
    _T_1237[26] <= _T_1399 @[el2_lib.scala 543:17]
    node _T_1400 = bits(_T_1236, 27, 0) @[el2_lib.scala 543:27]
    node _T_1401 = orr(_T_1400) @[el2_lib.scala 543:35]
    node _T_1402 = bits(_T_1236, 28, 28) @[el2_lib.scala 543:44]
    node _T_1403 = not(_T_1402) @[el2_lib.scala 543:40]
    node _T_1404 = bits(_T_1236, 28, 28) @[el2_lib.scala 543:51]
    node _T_1405 = mux(_T_1401, _T_1403, _T_1404) @[el2_lib.scala 543:23]
    _T_1237[27] <= _T_1405 @[el2_lib.scala 543:17]
    node _T_1406 = bits(_T_1236, 28, 0) @[el2_lib.scala 543:27]
    node _T_1407 = orr(_T_1406) @[el2_lib.scala 543:35]
    node _T_1408 = bits(_T_1236, 29, 29) @[el2_lib.scala 543:44]
    node _T_1409 = not(_T_1408) @[el2_lib.scala 543:40]
    node _T_1410 = bits(_T_1236, 29, 29) @[el2_lib.scala 543:51]
    node _T_1411 = mux(_T_1407, _T_1409, _T_1410) @[el2_lib.scala 543:23]
    _T_1237[28] <= _T_1411 @[el2_lib.scala 543:17]
    node _T_1412 = bits(_T_1236, 29, 0) @[el2_lib.scala 543:27]
    node _T_1413 = orr(_T_1412) @[el2_lib.scala 543:35]
    node _T_1414 = bits(_T_1236, 30, 30) @[el2_lib.scala 543:44]
    node _T_1415 = not(_T_1414) @[el2_lib.scala 543:40]
    node _T_1416 = bits(_T_1236, 30, 30) @[el2_lib.scala 543:51]
    node _T_1417 = mux(_T_1413, _T_1415, _T_1416) @[el2_lib.scala 543:23]
    _T_1237[29] <= _T_1417 @[el2_lib.scala 543:17]
    node _T_1418 = bits(_T_1236, 30, 0) @[el2_lib.scala 543:27]
    node _T_1419 = orr(_T_1418) @[el2_lib.scala 543:35]
    node _T_1420 = bits(_T_1236, 31, 31) @[el2_lib.scala 543:44]
    node _T_1421 = not(_T_1420) @[el2_lib.scala 543:40]
    node _T_1422 = bits(_T_1236, 31, 31) @[el2_lib.scala 543:51]
    node _T_1423 = mux(_T_1419, _T_1421, _T_1422) @[el2_lib.scala 543:23]
    _T_1237[30] <= _T_1423 @[el2_lib.scala 543:17]
    node _T_1424 = cat(_T_1237[2], _T_1237[1]) @[el2_lib.scala 545:14]
    node _T_1425 = cat(_T_1424, _T_1237[0]) @[el2_lib.scala 545:14]
    node _T_1426 = cat(_T_1237[4], _T_1237[3]) @[el2_lib.scala 545:14]
    node _T_1427 = cat(_T_1237[6], _T_1237[5]) @[el2_lib.scala 545:14]
    node _T_1428 = cat(_T_1427, _T_1426) @[el2_lib.scala 545:14]
    node _T_1429 = cat(_T_1428, _T_1425) @[el2_lib.scala 545:14]
    node _T_1430 = cat(_T_1237[8], _T_1237[7]) @[el2_lib.scala 545:14]
    node _T_1431 = cat(_T_1237[10], _T_1237[9]) @[el2_lib.scala 545:14]
    node _T_1432 = cat(_T_1431, _T_1430) @[el2_lib.scala 545:14]
    node _T_1433 = cat(_T_1237[12], _T_1237[11]) @[el2_lib.scala 545:14]
    node _T_1434 = cat(_T_1237[14], _T_1237[13]) @[el2_lib.scala 545:14]
    node _T_1435 = cat(_T_1434, _T_1433) @[el2_lib.scala 545:14]
    node _T_1436 = cat(_T_1435, _T_1432) @[el2_lib.scala 545:14]
    node _T_1437 = cat(_T_1436, _T_1429) @[el2_lib.scala 545:14]
    node _T_1438 = cat(_T_1237[16], _T_1237[15]) @[el2_lib.scala 545:14]
    node _T_1439 = cat(_T_1237[18], _T_1237[17]) @[el2_lib.scala 545:14]
    node _T_1440 = cat(_T_1439, _T_1438) @[el2_lib.scala 545:14]
    node _T_1441 = cat(_T_1237[20], _T_1237[19]) @[el2_lib.scala 545:14]
    node _T_1442 = cat(_T_1237[22], _T_1237[21]) @[el2_lib.scala 545:14]
    node _T_1443 = cat(_T_1442, _T_1441) @[el2_lib.scala 545:14]
    node _T_1444 = cat(_T_1443, _T_1440) @[el2_lib.scala 545:14]
    node _T_1445 = cat(_T_1237[24], _T_1237[23]) @[el2_lib.scala 545:14]
    node _T_1446 = cat(_T_1237[26], _T_1237[25]) @[el2_lib.scala 545:14]
    node _T_1447 = cat(_T_1446, _T_1445) @[el2_lib.scala 545:14]
    node _T_1448 = cat(_T_1237[28], _T_1237[27]) @[el2_lib.scala 545:14]
    node _T_1449 = cat(_T_1237[30], _T_1237[29]) @[el2_lib.scala 545:14]
    node _T_1450 = cat(_T_1449, _T_1448) @[el2_lib.scala 545:14]
    node _T_1451 = cat(_T_1450, _T_1447) @[el2_lib.scala 545:14]
    node _T_1452 = cat(_T_1451, _T_1444) @[el2_lib.scala 545:14]
    node _T_1453 = cat(_T_1452, _T_1437) @[el2_lib.scala 545:14]
    node _T_1454 = bits(_T_1236, 0, 0) @[el2_lib.scala 545:24]
    node _T_1455 = cat(_T_1453, _T_1454) @[Cat.scala 29:58]
    node _T_1456 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 193:87]
    node a_ff_eff = mux(_T_1235, _T_1455, _T_1456) @[el2_exu_div_ctl.scala 193:21]
    node _T_1457 = bits(smallnum_case_ff, 0, 0) @[el2_exu_div_ctl.scala 196:22]
    node _T_1458 = cat(UInt<28>("h00"), smallnum_ff) @[Cat.scala 29:58]
    node _T_1459 = bits(rem_ff, 0, 0) @[el2_exu_div_ctl.scala 197:12]
    node _T_1460 = eq(smallnum_case_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 198:6]
    node _T_1461 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 198:26]
    node _T_1462 = and(_T_1460, _T_1461) @[el2_exu_div_ctl.scala 198:24]
    node _T_1463 = bits(_T_1462, 0, 0) @[el2_exu_div_ctl.scala 198:35]
    node _T_1464 = mux(_T_1457, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1465 = mux(_T_1459, a_ff_eff, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1466 = mux(_T_1463, q_ff_eff, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_1467 = or(_T_1464, _T_1465) @[Mux.scala 27:72]
    node _T_1468 = or(_T_1467, _T_1466) @[Mux.scala 27:72]
    wire _T_1469 : UInt<32> @[Mux.scala 27:72]
    _T_1469 <= _T_1468 @[Mux.scala 27:72]
    io.out <= _T_1469 @[el2_exu_div_ctl.scala 195:10]
    node _T_1470 = bits(div_clken, 0, 0) @[el2_exu_div_ctl.scala 201:46]
    inst rvclkhdr of rvclkhdr_23 @[el2_lib.scala 483:22]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
    rvclkhdr.io.en <= _T_1470 @[el2_lib.scala 485:16]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
    node _T_1471 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 204:41]
    node _T_1472 = and(io.dp.valid, _T_1471) @[el2_exu_div_ctl.scala 204:39]
    reg _T_1473 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 204:26]
    _T_1473 <= _T_1472 @[el2_exu_div_ctl.scala 204:26]
    valid_ff_x <= _T_1473 @[el2_exu_div_ctl.scala 204:16]
    node _T_1474 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 205:35]
    node _T_1475 = and(finish, _T_1474) @[el2_exu_div_ctl.scala 205:33]
    reg _T_1476 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 205:25]
    _T_1476 <= _T_1475 @[el2_exu_div_ctl.scala 205:25]
    finish_ff <= _T_1476 @[el2_exu_div_ctl.scala 205:15]
    reg _T_1477 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 206:25]
    _T_1477 <= run_in @[el2_exu_div_ctl.scala 206:25]
    run_state <= _T_1477 @[el2_exu_div_ctl.scala 206:15]
    reg _T_1478 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 207:21]
    _T_1478 <= count_in @[el2_exu_div_ctl.scala 207:21]
    count <= _T_1478 @[el2_exu_div_ctl.scala 207:11]
    node _T_1479 = bits(io.dividend, 31, 31) @[el2_exu_div_ctl.scala 208:45]
    node _T_1480 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 208:68]
    reg _T_1481 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_1480 : @[Reg.scala 28:19]
      _T_1481 <= _T_1479 @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    dividend_neg_ff <= _T_1481 @[el2_exu_div_ctl.scala 208:21]
    node _T_1482 = bits(io.divisor, 31, 31) @[el2_exu_div_ctl.scala 209:43]
    node _T_1483 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 209:66]
    reg _T_1484 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_1483 : @[Reg.scala 28:19]
      _T_1484 <= _T_1482 @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    divisor_neg_ff <= _T_1484 @[el2_exu_div_ctl.scala 209:20]
    node _T_1485 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 210:53]
    reg _T_1486 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_1485 : @[Reg.scala 28:19]
      _T_1486 <= sign_eff @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    sign_ff <= _T_1486 @[el2_exu_div_ctl.scala 210:13]
    node _T_1487 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 211:58]
    reg _T_1488 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
    when _T_1487 : @[Reg.scala 28:19]
      _T_1488 <= io.dp.bits.rem @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    rem_ff <= _T_1488 @[el2_exu_div_ctl.scala 211:12]
    reg _T_1489 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 212:32]
    _T_1489 <= smallnum_case @[el2_exu_div_ctl.scala 212:32]
    smallnum_case_ff <= _T_1489 @[el2_exu_div_ctl.scala 212:22]
    reg _T_1490 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 213:27]
    _T_1490 <= smallnum @[el2_exu_div_ctl.scala 213:27]
    smallnum_ff <= _T_1490 @[el2_exu_div_ctl.scala 213:17]
    reg _T_1491 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 214:32]
    _T_1491 <= shortq_enable @[el2_exu_div_ctl.scala 214:32]
    shortq_enable_ff <= _T_1491 @[el2_exu_div_ctl.scala 214:22]
    reg _T_1492 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 215:31]
    _T_1492 <= shortq_shift @[el2_exu_div_ctl.scala 215:31]
    shortq_shift_xx <= _T_1492 @[el2_exu_div_ctl.scala 215:21]
    node _T_1493 = bits(qff_enable, 0, 0) @[el2_exu_div_ctl.scala 217:35]
    inst rvclkhdr_1 of rvclkhdr_24 @[el2_lib.scala 508:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_1.io.en <= _T_1493 @[el2_lib.scala 511:17]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1494 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1494 <= q_in @[el2_lib.scala 514:16]
    q_ff <= _T_1494 @[el2_exu_div_ctl.scala 217:8]
    node _T_1495 = bits(aff_enable, 0, 0) @[el2_exu_div_ctl.scala 218:35]
    inst rvclkhdr_2 of rvclkhdr_25 @[el2_lib.scala 508:23]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_2.io.en <= _T_1495 @[el2_lib.scala 511:17]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1496 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1496 <= a_in @[el2_lib.scala 514:16]
    a_ff <= _T_1496 @[el2_exu_div_ctl.scala 218:8]
    node _T_1497 = eq(io.dp.bits.unsign, UInt<1>("h00")) @[el2_exu_div_ctl.scala 219:22]
    node _T_1498 = bits(io.divisor, 31, 31) @[el2_exu_div_ctl.scala 219:53]
    node _T_1499 = and(_T_1497, _T_1498) @[el2_exu_div_ctl.scala 219:41]
    node _T_1500 = cat(_T_1499, io.divisor) @[Cat.scala 29:58]
    node _T_1501 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 219:84]
    inst rvclkhdr_3 of rvclkhdr_26 @[el2_lib.scala 508:23]
    rvclkhdr_3.clock <= clock
    rvclkhdr_3.reset <= reset
    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_3.io.en <= _T_1501 @[el2_lib.scala 511:17]
    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_1502 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_1502 <= _T_1500 @[el2_lib.scala 514:16]
    m_ff <= _T_1502 @[el2_exu_div_ctl.scala 219:8]
    
  module el2_exu : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip scan_mode : UInt<1>, flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip dbg_cmd_wrdata : UInt<32>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_debug_wdata_rs1_d : UInt<1>, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, flip dec_i0_alu_decode_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_pc_d : UInt<31>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip dec_csr_ren_d : UInt<1>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>, flip pred_correct_npc_x : UInt<31>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, flip dec_extint_stall : UInt<1>, flip dec_tlu_meihap : UInt<30>, exu_lsu_rs1_d : UInt<32>, exu_lsu_rs2_d : UInt<32>, exu_flush_final : UInt<1>, exu_flush_path_final : UInt<31>, exu_i0_result_x : UInt<32>, exu_i0_pc_x : UInt<31>, exu_csr_rs1_x : UInt<32>, exu_npc_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>}
    
    wire ghr_x_ns : UInt<8> @[el2_exu.scala 75:57]
    wire ghr_d_ns : UInt<8> @[el2_exu.scala 76:57]
    wire ghr_d : UInt<8> @[el2_exu.scala 77:67]
    wire i0_taken_d : UInt<1> @[el2_exu.scala 78:62]
    wire mul_valid_x : UInt<1> @[el2_exu.scala 79:62]
    wire i0_valid_d : UInt<1> @[el2_exu.scala 80:62]
    wire flush_lower_ff : UInt<1> @[el2_exu.scala 81:52]
    wire data_gate_en : UInt<1> @[el2_exu.scala 82:54]
    wire csr_rs1_in_d : UInt<32> @[el2_exu.scala 83:54]
    wire i0_predict_newp_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_exu.scala 84:50]
    wire i0_flush_path_d : UInt<31> @[el2_exu.scala 85:52]
    wire i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_exu.scala 86:52]
    wire i0_pp_r : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_exu.scala 87:64]
    wire i0_predict_p_x : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_exu.scala 88:52]
    wire final_predict_mp : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_exu.scala 89:44]
    wire pred_correct_npc_r : UInt<32> @[el2_exu.scala 90:50]
    wire i0_pred_correct_upper_d : UInt<1> @[el2_exu.scala 91:40]
    wire i0_flush_upper_d : UInt<1> @[el2_exu.scala 92:44]
    io.exu_mp_pkt.bits.prett <= UInt<1>("h00") @[el2_exu.scala 93:49]
    io.exu_mp_pkt.bits.br_start_error <= UInt<1>("h00") @[el2_exu.scala 94:36]
    io.exu_mp_pkt.bits.br_error <= UInt<1>("h00") @[el2_exu.scala 95:41]
    io.exu_mp_pkt.valid <= UInt<1>("h00") @[el2_exu.scala 96:47]
    i0_pp_r.bits.toffset <= UInt<1>("h00") @[el2_exu.scala 97:33]
    node x_data_en = bits(io.dec_data_en, 1, 1) @[el2_exu.scala 99:50]
    node r_data_en = bits(io.dec_data_en, 0, 0) @[el2_exu.scala 100:50]
    node x_ctl_en = bits(io.dec_ctl_en, 1, 1) @[el2_exu.scala 101:49]
    node r_ctl_en = bits(io.dec_ctl_en, 0, 0) @[el2_exu.scala 102:49]
    node _T = cat(io.i0_predict_fghr_d, io.i0_predict_index_d) @[Cat.scala 29:58]
    node predpipe_d = cat(_T, io.i0_predict_btag_d) @[Cat.scala 29:58]
    node _T_1 = bits(x_data_en, 0, 0) @[el2_exu.scala 106:59]
    inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
    rvclkhdr.clock <= clock
    rvclkhdr.reset <= reset
    rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr.io.en <= _T_1 @[el2_lib.scala 511:17]
    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_flush_path_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_flush_path_x <= i0_flush_path_d @[el2_lib.scala 514:16]
    node _T_2 = bits(x_data_en, 0, 0) @[el2_exu.scala 107:73]
    inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
    rvclkhdr_1.clock <= clock
    rvclkhdr_1.reset <= reset
    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_1.io.en <= _T_2 @[el2_lib.scala 511:17]
    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    _T_3 <= csr_rs1_in_d @[el2_lib.scala 514:16]
    io.exu_csr_rs1_x <= _T_3 @[el2_exu.scala 107:41]
    node _T_4 = bits(x_data_en, 0, 0) @[el2_exu.scala 108:83]
    inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 518:23]
    rvclkhdr_2.clock <= clock
    rvclkhdr_2.reset <= reset
    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_2.io.en <= _T_4 @[el2_lib.scala 521:17]
    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_5 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_lib.scala 524:33]
    _T_5.bits.way <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.pja <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.pret <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.prett <= UInt<31>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.hist <= UInt<2>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.bits.misp <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_5.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_6 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, rvclkhdr_2.io.l1clk with : (reset => (reset, _T_5)) @[el2_lib.scala 524:16]
    _T_6.bits.way <= i0_predict_p_d.bits.way @[el2_lib.scala 524:16]
    _T_6.bits.pja <= i0_predict_p_d.bits.pja @[el2_lib.scala 524:16]
    _T_6.bits.pret <= i0_predict_p_d.bits.pret @[el2_lib.scala 524:16]
    _T_6.bits.pcall <= i0_predict_p_d.bits.pcall @[el2_lib.scala 524:16]
    _T_6.bits.prett <= i0_predict_p_d.bits.prett @[el2_lib.scala 524:16]
    _T_6.bits.br_start_error <= i0_predict_p_d.bits.br_start_error @[el2_lib.scala 524:16]
    _T_6.bits.br_error <= i0_predict_p_d.bits.br_error @[el2_lib.scala 524:16]
    _T_6.bits.toffset <= i0_predict_p_d.bits.toffset @[el2_lib.scala 524:16]
    _T_6.bits.hist <= i0_predict_p_d.bits.hist @[el2_lib.scala 524:16]
    _T_6.bits.pc4 <= i0_predict_p_d.bits.pc4 @[el2_lib.scala 524:16]
    _T_6.bits.boffset <= i0_predict_p_d.bits.boffset @[el2_lib.scala 524:16]
    _T_6.bits.ataken <= i0_predict_p_d.bits.ataken @[el2_lib.scala 524:16]
    _T_6.bits.misp <= i0_predict_p_d.bits.misp @[el2_lib.scala 524:16]
    _T_6.valid <= i0_predict_p_d.valid @[el2_lib.scala 524:16]
    i0_predict_p_x.bits.way <= _T_6.bits.way @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.pja <= _T_6.bits.pja @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.pret <= _T_6.bits.pret @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.pcall <= _T_6.bits.pcall @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.prett <= _T_6.bits.prett @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.br_start_error <= _T_6.bits.br_start_error @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.br_error <= _T_6.bits.br_error @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.toffset <= _T_6.bits.toffset @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.hist <= _T_6.bits.hist @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.pc4 <= _T_6.bits.pc4 @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.boffset <= _T_6.bits.boffset @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.ataken <= _T_6.bits.ataken @[el2_exu.scala 108:49]
    i0_predict_p_x.bits.misp <= _T_6.bits.misp @[el2_exu.scala 108:49]
    i0_predict_p_x.valid <= _T_6.valid @[el2_exu.scala 108:49]
    node _T_7 = bits(x_data_en, 0, 0) @[el2_exu.scala 109:70]
    inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
    rvclkhdr_3.clock <= clock
    rvclkhdr_3.reset <= reset
    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_3.io.en <= _T_7 @[el2_lib.scala 511:17]
    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg predpipe_x : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    predpipe_x <= predpipe_d @[el2_lib.scala 514:16]
    node _T_8 = bits(r_data_en, 0, 0) @[el2_exu.scala 110:79]
    inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
    rvclkhdr_4.clock <= clock
    rvclkhdr_4.reset <= reset
    rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_4.io.en <= _T_8 @[el2_lib.scala 511:17]
    rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg predpipe_r : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    predpipe_r <= predpipe_x @[el2_lib.scala 514:16]
    node _T_9 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 111:80]
    inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
    rvclkhdr_5.clock <= clock
    rvclkhdr_5.reset <= reset
    rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_5.io.en <= _T_9 @[el2_lib.scala 511:17]
    rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg ghr_x : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    ghr_x <= ghr_x_ns @[el2_lib.scala 514:16]
    node _T_10 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 112:75]
    inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23]
    rvclkhdr_6.clock <= clock
    rvclkhdr_6.reset <= reset
    rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_6.io.en <= _T_10 @[el2_lib.scala 511:17]
    rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_pred_correct_upper_x : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[el2_lib.scala 514:16]
    node _T_11 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 113:60]
    inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23]
    rvclkhdr_7.clock <= clock
    rvclkhdr_7.reset <= reset
    rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_7.io.en <= _T_11 @[el2_lib.scala 511:17]
    rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_flush_upper_x : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_flush_upper_x <= i0_flush_upper_d @[el2_lib.scala 514:16]
    node _T_12 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 114:78]
    inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23]
    rvclkhdr_8.clock <= clock
    rvclkhdr_8.reset <= reset
    rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_8.io.en <= _T_12 @[el2_lib.scala 511:17]
    rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_taken_x : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_taken_x <= i0_taken_d @[el2_lib.scala 514:16]
    node _T_13 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 115:78]
    inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23]
    rvclkhdr_9.clock <= clock
    rvclkhdr_9.reset <= reset
    rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_9.io.en <= _T_13 @[el2_lib.scala 511:17]
    rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_valid_x : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_valid_x <= i0_valid_d @[el2_lib.scala 514:16]
    node _T_14 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 116:58]
    inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 518:23]
    rvclkhdr_10.clock <= clock
    rvclkhdr_10.reset <= reset
    rvclkhdr_10.io.clk <= clock @[el2_lib.scala 520:18]
    rvclkhdr_10.io.en <= _T_14 @[el2_lib.scala 521:17]
    rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
    wire _T_15 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_lib.scala 524:33]
    _T_15.bits.way <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.pja <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.pret <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.prett <= UInt<31>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.hist <= UInt<2>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.bits.misp <= UInt<1>("h00") @[el2_lib.scala 524:33]
    _T_15.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
    reg _T_16 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, rvclkhdr_10.io.l1clk with : (reset => (reset, _T_15)) @[el2_lib.scala 524:16]
    _T_16.bits.way <= i0_predict_p_x.bits.way @[el2_lib.scala 524:16]
    _T_16.bits.pja <= i0_predict_p_x.bits.pja @[el2_lib.scala 524:16]
    _T_16.bits.pret <= i0_predict_p_x.bits.pret @[el2_lib.scala 524:16]
    _T_16.bits.pcall <= i0_predict_p_x.bits.pcall @[el2_lib.scala 524:16]
    _T_16.bits.prett <= i0_predict_p_x.bits.prett @[el2_lib.scala 524:16]
    _T_16.bits.br_start_error <= i0_predict_p_x.bits.br_start_error @[el2_lib.scala 524:16]
    _T_16.bits.br_error <= i0_predict_p_x.bits.br_error @[el2_lib.scala 524:16]
    _T_16.bits.toffset <= i0_predict_p_x.bits.toffset @[el2_lib.scala 524:16]
    _T_16.bits.hist <= i0_predict_p_x.bits.hist @[el2_lib.scala 524:16]
    _T_16.bits.pc4 <= i0_predict_p_x.bits.pc4 @[el2_lib.scala 524:16]
    _T_16.bits.boffset <= i0_predict_p_x.bits.boffset @[el2_lib.scala 524:16]
    _T_16.bits.ataken <= i0_predict_p_x.bits.ataken @[el2_lib.scala 524:16]
    _T_16.bits.misp <= i0_predict_p_x.bits.misp @[el2_lib.scala 524:16]
    _T_16.valid <= i0_predict_p_x.valid @[el2_lib.scala 524:16]
    i0_pp_r.bits.way <= _T_16.bits.way @[el2_exu.scala 116:25]
    i0_pp_r.bits.pja <= _T_16.bits.pja @[el2_exu.scala 116:25]
    i0_pp_r.bits.pret <= _T_16.bits.pret @[el2_exu.scala 116:25]
    i0_pp_r.bits.pcall <= _T_16.bits.pcall @[el2_exu.scala 116:25]
    i0_pp_r.bits.prett <= _T_16.bits.prett @[el2_exu.scala 116:25]
    i0_pp_r.bits.br_start_error <= _T_16.bits.br_start_error @[el2_exu.scala 116:25]
    i0_pp_r.bits.br_error <= _T_16.bits.br_error @[el2_exu.scala 116:25]
    i0_pp_r.bits.toffset <= _T_16.bits.toffset @[el2_exu.scala 116:25]
    i0_pp_r.bits.hist <= _T_16.bits.hist @[el2_exu.scala 116:25]
    i0_pp_r.bits.pc4 <= _T_16.bits.pc4 @[el2_exu.scala 116:25]
    i0_pp_r.bits.boffset <= _T_16.bits.boffset @[el2_exu.scala 116:25]
    i0_pp_r.bits.ataken <= _T_16.bits.ataken @[el2_exu.scala 116:25]
    i0_pp_r.bits.misp <= _T_16.bits.misp @[el2_exu.scala 116:25]
    i0_pp_r.valid <= _T_16.valid @[el2_exu.scala 116:25]
    node _T_17 = bits(io.pred_correct_npc_x, 5, 0) @[el2_exu.scala 117:66]
    node _T_18 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 117:82]
    inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23]
    rvclkhdr_11.clock <= clock
    rvclkhdr_11.reset <= reset
    rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_11.io.en <= _T_18 @[el2_lib.scala 511:17]
    rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg pred_temp1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    pred_temp1 <= _T_17 @[el2_lib.scala 514:16]
    node _T_19 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 118:75]
    inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 508:23]
    rvclkhdr_12.clock <= clock
    rvclkhdr_12.reset <= reset
    rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_12.io.en <= _T_19 @[el2_lib.scala 511:17]
    rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_pred_correct_upper_r : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[el2_lib.scala 514:16]
    node _T_20 = bits(r_data_en, 0, 0) @[el2_exu.scala 119:68]
    inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 508:23]
    rvclkhdr_13.clock <= clock
    rvclkhdr_13.reset <= reset
    rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_13.io.en <= _T_20 @[el2_lib.scala 511:17]
    rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg i0_flush_path_upper_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    i0_flush_path_upper_r <= i0_flush_path_x @[el2_lib.scala 514:16]
    node _T_21 = bits(io.pred_correct_npc_x, 30, 6) @[el2_exu.scala 120:78]
    node _T_22 = bits(r_data_en, 0, 0) @[el2_exu.scala 120:96]
    inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 508:23]
    rvclkhdr_14.clock <= clock
    rvclkhdr_14.reset <= reset
    rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18]
    rvclkhdr_14.io.en <= _T_22 @[el2_lib.scala 511:17]
    rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
    reg pred_temp2 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
    pred_temp2 <= _T_21 @[el2_lib.scala 514:16]
    node _T_23 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58]
    pred_correct_npc_r <= _T_23 @[el2_exu.scala 121:41]
    node _T_24 = eq(UInt<10>("h0200"), UInt<6>("h020")) @[el2_exu.scala 123:24]
    node _T_25 = eq(UInt<10>("h0200"), UInt<7>("h040")) @[el2_exu.scala 123:50]
    node _T_26 = or(_T_24, _T_25) @[el2_exu.scala 123:32]
    when _T_26 : @[el2_exu.scala 123:58]
      node _T_27 = bits(data_gate_en, 0, 0) @[el2_exu.scala 124:71]
      reg _T_28 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
      when _T_27 : @[Reg.scala 28:19]
        _T_28 <= ghr_d_ns @[Reg.scala 28:23]
        skip @[Reg.scala 28:19]
      ghr_d <= _T_28 @[el2_exu.scala 124:33]
      node _T_29 = bits(data_gate_en, 0, 0) @[el2_exu.scala 125:69]
      reg _T_30 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
      when _T_29 : @[Reg.scala 28:19]
        _T_30 <= io.mul_p.valid @[Reg.scala 28:23]
        skip @[Reg.scala 28:19]
      mul_valid_x <= _T_30 @[el2_exu.scala 125:25]
      node _T_31 = bits(data_gate_en, 0, 0) @[el2_exu.scala 126:79]
      reg _T_32 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
      when _T_31 : @[Reg.scala 28:19]
        _T_32 <= io.dec_tlu_flush_lower_r @[Reg.scala 28:23]
        skip @[Reg.scala 28:19]
      flush_lower_ff <= _T_32 @[el2_exu.scala 126:25]
      skip @[el2_exu.scala 123:58]
    else : @[el2_exu.scala 127:14]
      node _T_33 = bits(data_gate_en, 0, 0) @[el2_exu.scala 128:65]
      inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 508:23]
      rvclkhdr_15.clock <= clock
      rvclkhdr_15.reset <= reset
      rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18]
      rvclkhdr_15.io.en <= _T_33 @[el2_lib.scala 511:17]
      rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
      reg _T_34 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
      _T_34 <= ghr_d_ns @[el2_lib.scala 514:16]
      ghr_d <= _T_34 @[el2_exu.scala 128:33]
      node _T_35 = bits(data_gate_en, 0, 0) @[el2_exu.scala 129:63]
      inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 508:23]
      rvclkhdr_16.clock <= clock
      rvclkhdr_16.reset <= reset
      rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18]
      rvclkhdr_16.io.en <= _T_35 @[el2_lib.scala 511:17]
      rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
      reg _T_36 : UInt<1>, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
      _T_36 <= io.mul_p.valid @[el2_lib.scala 514:16]
      mul_valid_x <= _T_36 @[el2_exu.scala 129:25]
      node _T_37 = bits(data_gate_en, 0, 0) @[el2_exu.scala 130:73]
      inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 508:23]
      rvclkhdr_17.clock <= clock
      rvclkhdr_17.reset <= reset
      rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18]
      rvclkhdr_17.io.en <= _T_37 @[el2_lib.scala 511:17]
      rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
      reg _T_38 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
      _T_38 <= io.dec_tlu_flush_lower_r @[el2_lib.scala 514:16]
      flush_lower_ff <= _T_38 @[el2_exu.scala 130:25]
      skip @[el2_exu.scala 127:14]
    node _T_39 = neq(ghr_d_ns, ghr_d) @[el2_exu.scala 134:39]
    node _T_40 = neq(io.mul_p.valid, mul_valid_x) @[el2_exu.scala 134:70]
    node _T_41 = or(_T_39, _T_40) @[el2_exu.scala 134:50]
    node _T_42 = neq(io.dec_tlu_flush_lower_r, flush_lower_ff) @[el2_exu.scala 134:116]
    node _T_43 = or(_T_41, _T_42) @[el2_exu.scala 134:87]
    data_gate_en <= _T_43 @[el2_exu.scala 134:25]
    node _T_44 = bits(io.dec_i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 135:61]
    node _T_45 = bits(io.dec_i0_rs1_bypass_en_d, 1, 1) @[el2_exu.scala 135:92]
    node i0_rs1_bypass_en_d = or(_T_44, _T_45) @[el2_exu.scala 135:65]
    node _T_46 = bits(io.dec_i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 136:61]
    node _T_47 = bits(io.dec_i0_rs2_bypass_en_d, 1, 1) @[el2_exu.scala 136:92]
    node i0_rs2_bypass_en_d = or(_T_46, _T_47) @[el2_exu.scala 136:65]
    node _T_48 = bits(io.dec_i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 139:30]
    node _T_49 = bits(_T_48, 0, 0) @[el2_exu.scala 139:34]
    node _T_50 = bits(io.dec_i0_rs1_bypass_en_d, 1, 1) @[el2_exu.scala 140:30]
    node _T_51 = bits(_T_50, 0, 0) @[el2_exu.scala 140:34]
    node _T_52 = mux(_T_49, io.dec_i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_53 = mux(_T_51, io.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_54 = or(_T_52, _T_53) @[Mux.scala 27:72]
    wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72]
    i0_rs1_bypass_data_d <= _T_54 @[Mux.scala 27:72]
    node _T_55 = bits(io.dec_i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 144:30]
    node _T_56 = bits(_T_55, 0, 0) @[el2_exu.scala 144:34]
    node _T_57 = bits(io.dec_i0_rs2_bypass_en_d, 1, 1) @[el2_exu.scala 145:30]
    node _T_58 = bits(_T_57, 0, 0) @[el2_exu.scala 145:34]
    node _T_59 = mux(_T_56, io.dec_i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_60 = mux(_T_58, io.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_61 = or(_T_59, _T_60) @[Mux.scala 27:72]
    wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72]
    i0_rs2_bypass_data_d <= _T_61 @[Mux.scala 27:72]
    node _T_62 = bits(i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 149:24]
    node _T_63 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 150:6]
    node _T_64 = and(_T_63, io.dec_i0_select_pc_d) @[el2_exu.scala 150:26]
    node _T_65 = bits(_T_64, 0, 0) @[el2_exu.scala 150:52]
    node _T_66 = cat(io.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_67 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 151:6]
    node _T_68 = and(_T_67, io.dec_debug_wdata_rs1_d) @[el2_exu.scala 151:26]
    node _T_69 = bits(_T_68, 0, 0) @[el2_exu.scala 151:55]
    node _T_70 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 152:6]
    node _T_71 = eq(io.dec_debug_wdata_rs1_d, UInt<1>("h00")) @[el2_exu.scala 152:28]
    node _T_72 = and(_T_70, _T_71) @[el2_exu.scala 152:26]
    node _T_73 = and(_T_72, io.dec_i0_rs1_en_d) @[el2_exu.scala 152:54]
    node _T_74 = bits(_T_73, 0, 0) @[el2_exu.scala 152:76]
    node _T_75 = mux(_T_62, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_76 = mux(_T_65, _T_66, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_77 = mux(_T_69, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_78 = mux(_T_74, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_79 = or(_T_75, _T_76) @[Mux.scala 27:72]
    node _T_80 = or(_T_79, _T_77) @[Mux.scala 27:72]
    node _T_81 = or(_T_80, _T_78) @[Mux.scala 27:72]
    wire i0_rs1_d : UInt<32> @[Mux.scala 27:72]
    i0_rs1_d <= _T_81 @[Mux.scala 27:72]
    node _T_82 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 156:6]
    node _T_83 = and(_T_82, io.dec_i0_rs2_en_d) @[el2_exu.scala 156:26]
    node _T_84 = bits(_T_83, 0, 0) @[el2_exu.scala 156:48]
    node _T_85 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 157:6]
    node _T_86 = bits(_T_85, 0, 0) @[el2_exu.scala 157:27]
    node _T_87 = bits(i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 158:26]
    node _T_88 = mux(_T_84, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_89 = mux(_T_86, io.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_90 = mux(_T_87, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_91 = or(_T_88, _T_89) @[Mux.scala 27:72]
    node _T_92 = or(_T_91, _T_90) @[Mux.scala 27:72]
    wire i0_rs2_d : UInt<32> @[Mux.scala 27:72]
    i0_rs2_d <= _T_92 @[Mux.scala 27:72]
    node _T_93 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 163:6]
    node _T_94 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_exu.scala 163:28]
    node _T_95 = and(_T_93, _T_94) @[el2_exu.scala 163:26]
    node _T_96 = and(_T_95, io.dec_i0_rs1_en_d) @[el2_exu.scala 163:49]
    node _T_97 = bits(_T_96, 0, 0) @[el2_exu.scala 163:71]
    node _T_98 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_exu.scala 164:27]
    node _T_99 = and(i0_rs1_bypass_en_d, _T_98) @[el2_exu.scala 164:25]
    node _T_100 = bits(_T_99, 0, 0) @[el2_exu.scala 164:49]
    node _T_101 = bits(io.dec_extint_stall, 0, 0) @[el2_exu.scala 165:27]
    node _T_102 = cat(io.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58]
    node _T_103 = mux(_T_97, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_104 = mux(_T_100, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_105 = mux(_T_101, _T_102, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_106 = or(_T_103, _T_104) @[Mux.scala 27:72]
    node _T_107 = or(_T_106, _T_105) @[Mux.scala 27:72]
    wire _T_108 : UInt<32> @[Mux.scala 27:72]
    _T_108 <= _T_107 @[Mux.scala 27:72]
    io.exu_lsu_rs1_d <= _T_108 @[el2_exu.scala 162:19]
    node _T_109 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 169:6]
    node _T_110 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_exu.scala 169:28]
    node _T_111 = and(_T_109, _T_110) @[el2_exu.scala 169:26]
    node _T_112 = and(_T_111, io.dec_i0_rs2_en_d) @[el2_exu.scala 169:49]
    node _T_113 = bits(_T_112, 0, 0) @[el2_exu.scala 169:71]
    node _T_114 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_exu.scala 170:27]
    node _T_115 = and(i0_rs2_bypass_en_d, _T_114) @[el2_exu.scala 170:25]
    node _T_116 = bits(_T_115, 0, 0) @[el2_exu.scala 170:49]
    node _T_117 = mux(_T_113, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_118 = mux(_T_116, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_119 = or(_T_117, _T_118) @[Mux.scala 27:72]
    wire _T_120 : UInt<32> @[Mux.scala 27:72]
    _T_120 <= _T_119 @[Mux.scala 27:72]
    io.exu_lsu_rs2_d <= _T_120 @[el2_exu.scala 168:19]
    node _T_121 = eq(i0_rs1_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 174:6]
    node _T_122 = and(_T_121, io.dec_i0_rs1_en_d) @[el2_exu.scala 174:26]
    node _T_123 = bits(_T_122, 0, 0) @[el2_exu.scala 174:48]
    node _T_124 = bits(i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 175:26]
    node _T_125 = mux(_T_123, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_126 = mux(_T_124, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72]
    wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72]
    muldiv_rs1_d <= _T_127 @[Mux.scala 27:72]
    node _T_128 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 179:6]
    node _T_129 = and(_T_128, io.dec_i0_rs2_en_d) @[el2_exu.scala 179:26]
    node _T_130 = bits(_T_129, 0, 0) @[el2_exu.scala 179:48]
    node _T_131 = eq(i0_rs2_bypass_en_d, UInt<1>("h00")) @[el2_exu.scala 180:6]
    node _T_132 = bits(_T_131, 0, 0) @[el2_exu.scala 180:27]
    node _T_133 = bits(i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 181:26]
    node _T_134 = mux(_T_130, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_135 = mux(_T_132, io.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_136 = mux(_T_133, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_137 = or(_T_134, _T_135) @[Mux.scala 27:72]
    node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72]
    wire muldiv_rs2_d : UInt<32> @[Mux.scala 27:72]
    muldiv_rs2_d <= _T_138 @[Mux.scala 27:72]
    node _T_139 = bits(io.dec_csr_ren_d, 0, 0) @[el2_exu.scala 184:47]
    node _T_140 = mux(_T_139, i0_rs1_d, io.exu_csr_rs1_x) @[el2_exu.scala 184:28]
    csr_rs1_in_d <= _T_140 @[el2_exu.scala 184:22]
    inst i_alu of el2_exu_alu_ctl @[el2_exu.scala 187:19]
    i_alu.clock <= clock
    i_alu.reset <= reset
    i_alu.io.scan_mode <= io.scan_mode @[el2_exu.scala 188:33]
    i_alu.io.enable <= x_ctl_en @[el2_exu.scala 189:41]
    i_alu.io.pp_in.bits.way <= i0_predict_newp_d.bits.way @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.pja <= i0_predict_newp_d.bits.pja @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.pret <= i0_predict_newp_d.bits.pret @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.pcall <= i0_predict_newp_d.bits.pcall @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.prett <= i0_predict_newp_d.bits.prett @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.br_start_error <= i0_predict_newp_d.bits.br_start_error @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.br_error <= i0_predict_newp_d.bits.br_error @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.toffset <= i0_predict_newp_d.bits.toffset @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.hist <= i0_predict_newp_d.bits.hist @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.pc4 <= i0_predict_newp_d.bits.pc4 @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.boffset <= i0_predict_newp_d.bits.boffset @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.ataken <= i0_predict_newp_d.bits.ataken @[el2_exu.scala 190:41]
    i_alu.io.pp_in.bits.misp <= i0_predict_newp_d.bits.misp @[el2_exu.scala 190:41]
    i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[el2_exu.scala 190:41]
    i_alu.io.valid_in <= io.dec_i0_alu_decode_d @[el2_exu.scala 191:33]
    i_alu.io.flush_upper_x <= i0_flush_upper_x @[el2_exu.scala 192:33]
    i_alu.io.flush_lower_r <= io.dec_tlu_flush_lower_r @[el2_exu.scala 193:33]
    node _T_141 = asSInt(i0_rs1_d) @[el2_exu.scala 194:44]
    i_alu.io.a_in <= _T_141 @[el2_exu.scala 194:33]
    i_alu.io.b_in <= i0_rs2_d @[el2_exu.scala 195:33]
    i_alu.io.pc_in <= io.dec_i0_pc_d @[el2_exu.scala 196:41]
    i_alu.io.brimm_in <= io.dec_i0_br_immed_d @[el2_exu.scala 197:33]
    i_alu.io.ap.csr_imm <= io.i0_ap.csr_imm @[el2_exu.scala 198:41]
    i_alu.io.ap.csr_write <= io.i0_ap.csr_write @[el2_exu.scala 198:41]
    i_alu.io.ap.predict_nt <= io.i0_ap.predict_nt @[el2_exu.scala 198:41]
    i_alu.io.ap.predict_t <= io.i0_ap.predict_t @[el2_exu.scala 198:41]
    i_alu.io.ap.jal <= io.i0_ap.jal @[el2_exu.scala 198:41]
    i_alu.io.ap.unsign <= io.i0_ap.unsign @[el2_exu.scala 198:41]
    i_alu.io.ap.slt <= io.i0_ap.slt @[el2_exu.scala 198:41]
    i_alu.io.ap.sub <= io.i0_ap.sub @[el2_exu.scala 198:41]
    i_alu.io.ap.add <= io.i0_ap.add @[el2_exu.scala 198:41]
    i_alu.io.ap.bge <= io.i0_ap.bge @[el2_exu.scala 198:41]
    i_alu.io.ap.blt <= io.i0_ap.blt @[el2_exu.scala 198:41]
    i_alu.io.ap.bne <= io.i0_ap.bne @[el2_exu.scala 198:41]
    i_alu.io.ap.beq <= io.i0_ap.beq @[el2_exu.scala 198:41]
    i_alu.io.ap.sra <= io.i0_ap.sra @[el2_exu.scala 198:41]
    i_alu.io.ap.srl <= io.i0_ap.srl @[el2_exu.scala 198:41]
    i_alu.io.ap.sll <= io.i0_ap.sll @[el2_exu.scala 198:41]
    i_alu.io.ap.lxor <= io.i0_ap.lxor @[el2_exu.scala 198:41]
    i_alu.io.ap.lor <= io.i0_ap.lor @[el2_exu.scala 198:41]
    i_alu.io.ap.land <= io.i0_ap.land @[el2_exu.scala 198:41]
    i_alu.io.csr_ren_in <= io.dec_csr_ren_d @[el2_exu.scala 199:33]
    i0_flush_upper_d <= i_alu.io.flush_upper_out @[el2_exu.scala 201:33]
    io.exu_flush_final <= i_alu.io.flush_final_out @[el2_exu.scala 202:33]
    i0_flush_path_d <= i_alu.io.flush_path_out @[el2_exu.scala 203:41]
    i0_predict_p_d.bits.way <= i_alu.io.predict_p_out.bits.way @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.pja <= i_alu.io.predict_p_out.bits.pja @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.pret <= i_alu.io.predict_p_out.bits.pret @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.pcall <= i_alu.io.predict_p_out.bits.pcall @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.prett <= i_alu.io.predict_p_out.bits.prett @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.br_start_error <= i_alu.io.predict_p_out.bits.br_start_error @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.br_error <= i_alu.io.predict_p_out.bits.br_error @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.toffset <= i_alu.io.predict_p_out.bits.toffset @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.hist <= i_alu.io.predict_p_out.bits.hist @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.pc4 <= i_alu.io.predict_p_out.bits.pc4 @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.boffset <= i_alu.io.predict_p_out.bits.boffset @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.ataken <= i_alu.io.predict_p_out.bits.ataken @[el2_exu.scala 204:41]
    i0_predict_p_d.bits.misp <= i_alu.io.predict_p_out.bits.misp @[el2_exu.scala 204:41]
    i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[el2_exu.scala 204:41]
    i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[el2_exu.scala 205:27]
    io.exu_i0_pc_x <= i_alu.io.pc_ff @[el2_exu.scala 206:41]
    inst i_mul of el2_exu_mul_ctl @[el2_exu.scala 208:19]
    i_mul.clock <= clock
    i_mul.reset <= reset
    i_mul.io.scan_mode <= io.scan_mode @[el2_exu.scala 209:33]
    i_mul.io.mul_p.bits.bfp <= io.mul_p.bits.bfp @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.crc32c_w <= io.mul_p.bits.crc32c_w @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.crc32c_h <= io.mul_p.bits.crc32c_h @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.crc32c_b <= io.mul_p.bits.crc32c_b @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.crc32_w <= io.mul_p.bits.crc32_w @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.crc32_h <= io.mul_p.bits.crc32_h @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.crc32_b <= io.mul_p.bits.crc32_b @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.unshfl <= io.mul_p.bits.unshfl @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.shfl <= io.mul_p.bits.shfl @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.grev <= io.mul_p.bits.grev @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.clmulr <= io.mul_p.bits.clmulr @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.clmulh <= io.mul_p.bits.clmulh @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.clmul <= io.mul_p.bits.clmul @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.bdep <= io.mul_p.bits.bdep @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.bext <= io.mul_p.bits.bext @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.low <= io.mul_p.bits.low @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.rs2_sign <= io.mul_p.bits.rs2_sign @[el2_exu.scala 210:41]
    i_mul.io.mul_p.bits.rs1_sign <= io.mul_p.bits.rs1_sign @[el2_exu.scala 210:41]
    i_mul.io.mul_p.valid <= io.mul_p.valid @[el2_exu.scala 210:41]
    i_mul.io.rs1_in <= muldiv_rs1_d @[el2_exu.scala 211:41]
    i_mul.io.rs2_in <= muldiv_rs2_d @[el2_exu.scala 212:41]
    inst i_div of el2_exu_div_ctl @[el2_exu.scala 215:19]
    i_div.clock <= clock
    i_div.reset <= reset
    i_div.io.scan_mode <= io.scan_mode @[el2_exu.scala 216:33]
    i_div.io.cancel <= io.dec_div_cancel @[el2_exu.scala 217:41]
    i_div.io.dp.bits.rem <= io.div_p.bits.rem @[el2_exu.scala 218:41]
    i_div.io.dp.bits.unsign <= io.div_p.bits.unsign @[el2_exu.scala 218:41]
    i_div.io.dp.valid <= io.div_p.valid @[el2_exu.scala 218:41]
    i_div.io.dividend <= muldiv_rs1_d @[el2_exu.scala 219:33]
    i_div.io.divisor <= muldiv_rs2_d @[el2_exu.scala 220:33]
    io.exu_div_wren <= i_div.io.finish_dly @[el2_exu.scala 221:41]
    io.exu_div_result <= i_div.io.out @[el2_exu.scala 222:33]
    node _T_142 = bits(mul_valid_x, 0, 0) @[el2_exu.scala 224:61]
    node _T_143 = mux(_T_142, i_mul.io.result_x, i_alu.io.result_ff) @[el2_exu.scala 224:48]
    io.exu_i0_result_x <= _T_143 @[el2_exu.scala 224:42]
    i0_predict_newp_d.bits.way <= io.dec_i0_predict_p_d.bits.way @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.pja <= io.dec_i0_predict_p_d.bits.pja @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.pret <= io.dec_i0_predict_p_d.bits.pret @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.pcall <= io.dec_i0_predict_p_d.bits.pcall @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.prett <= io.dec_i0_predict_p_d.bits.prett @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.br_start_error <= io.dec_i0_predict_p_d.bits.br_start_error @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.br_error <= io.dec_i0_predict_p_d.bits.br_error @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.toffset <= io.dec_i0_predict_p_d.bits.toffset @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.hist <= io.dec_i0_predict_p_d.bits.hist @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.pc4 <= io.dec_i0_predict_p_d.bits.pc4 @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.boffset <= io.dec_i0_predict_p_d.bits.boffset @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.ataken <= io.dec_i0_predict_p_d.bits.ataken @[el2_exu.scala 225:32]
    i0_predict_newp_d.bits.misp <= io.dec_i0_predict_p_d.bits.misp @[el2_exu.scala 225:32]
    i0_predict_newp_d.valid <= io.dec_i0_predict_p_d.valid @[el2_exu.scala 225:32]
    node _T_144 = bits(io.dec_i0_pc_d, 0, 0) @[el2_exu.scala 226:55]
    i0_predict_newp_d.bits.boffset <= _T_144 @[el2_exu.scala 226:37]
    io.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[el2_exu.scala 228:31]
    io.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[el2_exu.scala 229:31]
    io.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[el2_exu.scala 230:31]
    node _T_145 = and(i0_predict_p_d.valid, io.dec_i0_alu_decode_d) @[el2_exu.scala 233:54]
    node _T_146 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_exu.scala 233:81]
    node _T_147 = and(_T_145, _T_146) @[el2_exu.scala 233:79]
    i0_valid_d <= _T_147 @[el2_exu.scala 233:28]
    node _T_148 = and(i0_predict_p_d.bits.ataken, io.dec_i0_alu_decode_d) @[el2_exu.scala 234:59]
    i0_taken_d <= _T_148 @[el2_exu.scala 234:28]
    node _T_149 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_exu.scala 240:6]
    node _T_150 = and(_T_149, i0_valid_d) @[el2_exu.scala 240:32]
    node _T_151 = bits(_T_150, 0, 0) @[el2_exu.scala 240:47]
    node _T_152 = bits(ghr_d, 6, 0) @[el2_exu.scala 240:78]
    node _T_153 = cat(_T_152, i0_taken_d) @[Cat.scala 29:58]
    node _T_154 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_exu.scala 241:6]
    node _T_155 = eq(i0_valid_d, UInt<1>("h00")) @[el2_exu.scala 241:34]
    node _T_156 = and(_T_154, _T_155) @[el2_exu.scala 241:32]
    node _T_157 = bits(_T_156, 0, 0) @[el2_exu.scala 241:47]
    node _T_158 = bits(io.dec_tlu_flush_lower_r, 0, 0) @[el2_exu.scala 242:32]
    node _T_159 = mux(_T_151, _T_153, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_160 = mux(_T_157, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_161 = mux(_T_158, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72]
    node _T_162 = or(_T_159, _T_160) @[Mux.scala 27:72]
    node _T_163 = or(_T_162, _T_161) @[Mux.scala 27:72]
    wire _T_164 : UInt @[Mux.scala 27:72]
    _T_164 <= _T_163 @[Mux.scala 27:72]
    ghr_d_ns <= _T_164 @[el2_exu.scala 239:11]
    node _T_165 = eq(i0_valid_x, UInt<1>("h01")) @[el2_exu.scala 246:27]
    node _T_166 = bits(ghr_x, 6, 0) @[el2_exu.scala 246:44]
    node _T_167 = cat(_T_166, i0_taken_x) @[Cat.scala 29:58]
    node _T_168 = mux(_T_165, _T_167, ghr_x) @[el2_exu.scala 246:16]
    ghr_x_ns <= _T_168 @[el2_exu.scala 246:11]
    io.exu_i0_br_valid_r <= i0_pp_r.valid @[el2_exu.scala 248:36]
    io.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[el2_exu.scala 249:36]
    io.exu_i0_br_way_r <= i0_pp_r.bits.way @[el2_exu.scala 250:36]
    io.exu_i0_br_hist_r <= i0_pp_r.bits.hist @[el2_exu.scala 251:50]
    io.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[el2_exu.scala 252:42]
    node _T_169 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[el2_exu.scala 253:57]
    io.exu_i0_br_middle_r <= _T_169 @[el2_exu.scala 253:36]
    io.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[el2_exu.scala 254:36]
    node _T_170 = bits(predpipe_r, 20, 13) @[el2_exu.scala 255:64]
    io.exu_i0_br_fghr_r <= _T_170 @[el2_exu.scala 255:50]
    node _T_171 = bits(predpipe_r, 12, 5) @[el2_exu.scala 256:56]
    io.exu_i0_br_index_r <= _T_171 @[el2_exu.scala 256:42]
    node _T_172 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 257:74]
    wire _T_173 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_exu.scala 257:108]
    _T_173.bits.way <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.pja <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.pret <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.pcall <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.prett <= UInt<31>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.br_start_error <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.br_error <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.toffset <= UInt<12>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.hist <= UInt<2>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.pc4 <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.boffset <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.ataken <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.bits.misp <= UInt<1>("h00") @[el2_exu.scala 257:108]
    _T_173.valid <= UInt<1>("h00") @[el2_exu.scala 257:108]
    node _T_174 = mux(_T_172, i0_predict_p_x, _T_173) @[el2_exu.scala 257:57]
    final_predict_mp.bits.way <= _T_174.bits.way @[el2_exu.scala 257:50]
    final_predict_mp.bits.pja <= _T_174.bits.pja @[el2_exu.scala 257:50]
    final_predict_mp.bits.pret <= _T_174.bits.pret @[el2_exu.scala 257:50]
    final_predict_mp.bits.pcall <= _T_174.bits.pcall @[el2_exu.scala 257:50]
    final_predict_mp.bits.prett <= _T_174.bits.prett @[el2_exu.scala 257:50]
    final_predict_mp.bits.br_start_error <= _T_174.bits.br_start_error @[el2_exu.scala 257:50]
    final_predict_mp.bits.br_error <= _T_174.bits.br_error @[el2_exu.scala 257:50]
    final_predict_mp.bits.toffset <= _T_174.bits.toffset @[el2_exu.scala 257:50]
    final_predict_mp.bits.hist <= _T_174.bits.hist @[el2_exu.scala 257:50]
    final_predict_mp.bits.pc4 <= _T_174.bits.pc4 @[el2_exu.scala 257:50]
    final_predict_mp.bits.boffset <= _T_174.bits.boffset @[el2_exu.scala 257:50]
    final_predict_mp.bits.ataken <= _T_174.bits.ataken @[el2_exu.scala 257:50]
    final_predict_mp.bits.misp <= _T_174.bits.misp @[el2_exu.scala 257:50]
    final_predict_mp.valid <= _T_174.valid @[el2_exu.scala 257:50]
    node _T_175 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 258:66]
    node final_predpipe_mp = mux(_T_175, predpipe_x, UInt<1>("h00")) @[el2_exu.scala 258:49]
    node _T_176 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 260:60]
    node _T_177 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h01")) @[el2_exu.scala 260:95]
    node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_exu.scala 260:69]
    node _T_179 = and(_T_176, _T_178) @[el2_exu.scala 260:67]
    node after_flush_eghr = mux(_T_179, ghr_d, ghr_x) @[el2_exu.scala 260:42]
    io.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[el2_exu.scala 263:41]
    io.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[el2_exu.scala 264:41]
    io.exu_mp_pkt.bits.pcall <= final_predict_mp.bits.pcall @[el2_exu.scala 265:41]
    io.exu_mp_pkt.bits.pja <= final_predict_mp.bits.pja @[el2_exu.scala 266:41]
    io.exu_mp_pkt.bits.pret <= final_predict_mp.bits.pret @[el2_exu.scala 267:41]
    io.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[el2_exu.scala 268:41]
    io.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[el2_exu.scala 269:41]
    io.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[el2_exu.scala 270:41]
    node _T_180 = bits(final_predict_mp.bits.hist, 1, 0) @[el2_exu.scala 271:88]
    io.exu_mp_pkt.bits.hist <= _T_180 @[el2_exu.scala 271:58]
    node _T_181 = bits(final_predict_mp.bits.toffset, 11, 0) @[el2_exu.scala 272:83]
    io.exu_mp_pkt.bits.toffset <= _T_181 @[el2_exu.scala 272:50]
    io.exu_mp_fghr <= after_flush_eghr @[el2_exu.scala 273:36]
    node _T_182 = bits(final_predpipe_mp, 12, 5) @[el2_exu.scala 274:79]
    io.exu_mp_index <= _T_182 @[el2_exu.scala 274:58]
    node _T_183 = bits(final_predpipe_mp, 4, 0) @[el2_exu.scala 275:79]
    io.exu_mp_btag <= _T_183 @[el2_exu.scala 275:58]
    node _T_184 = bits(final_predpipe_mp, 20, 13) @[el2_exu.scala 276:57]
    io.exu_mp_eghr <= _T_184 @[el2_exu.scala 276:36]
    node _T_185 = bits(io.dec_tlu_flush_lower_r, 0, 0) @[el2_exu.scala 277:82]
    node _T_186 = mux(_T_185, io.dec_tlu_flush_path_r, i0_flush_path_d) @[el2_exu.scala 277:56]
    io.exu_flush_path_final <= _T_186 @[el2_exu.scala 277:50]
    node _T_187 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[el2_exu.scala 278:80]
    node _T_188 = mux(_T_187, pred_correct_npc_r, i0_flush_path_upper_r) @[el2_exu.scala 278:56]
    io.exu_npc_r <= _T_188 @[el2_exu.scala 278:50]
    
