[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_misaligned",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_load",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_bus_buffer_full_any",
    "sources":[
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_dec_lsu_valid_raw_d",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_d",
      "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_d"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"el2_lsu_bus_intf.gated_latch",
    "resourceId":"/vsrc/gated_latch.v"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"el2_lsu_bus_intf"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]