package snapshot
import chisel3._

object pt{
  val BHT_ADDR_HI            = "h9".U(4.W)
  val BHT_ADDR_LO            = "h2".U(2.W)
  val BHT_ARRAY_DEPTH        = "h100".U(11.W)
  val BHT_GHR_HASH_1         = "h0".U(1.W)
  val BHT_GHR_SIZE           = "8h".U(4.W)
  val BHT_SIZE               = "h200".U(12.W)
  val BTB_ADDR_HI            = "h09".U(5.W)
  val BTB_ADDR_LO            = "h2".U(2.W)
  val BTB_ARRAY_DEPTH        = "h100".U(9.W)
  val BTB_BTAG_FOLD          = "h0".U(1.W)
  val BTB_BTAG_SIZE          = "h5".U(4.W)
  val BTB_FOLD2_INDEX_HASH   = "h0".U(1.W)
  val BTB_INDEX1_HI          = "h09".U(5.W)
  val BTB_INDEX1_LO          = "h02".U(5.W)
  val BTB_INDEX2_HI          = "h11".U(5.W)
  val BTB_INDEX2_LO          = "h0A".U(5.W)
  val BTB_INDEX3_HI          = "h19".U(5.W)
  val BTB_INDEX3_LO          = "h12".U(5.W)
  val BTB_SIZE               = "h200".U(10.W)
  val BUILD_AHB_LITE         = "h0".U(1.W)
  val BUILD_AXI4             = "h1".U(1.W)
  val BUILD_AXI_NATIVE       = "h1".U(1.W)
  val BUS_PRTY_DEFAULT       = "h3".U(2.W)
  val DATA_ACCESS_ADDR0      = "h00000000".U(32.W)
  val DATA_ACCESS_ADDR1      = "hC0000000".U(32.W)
  val DATA_ACCESS_ADDR2      = "hA0000000".U(32.W)
  val DATA_ACCESS_ADDR3      = "h80000000".U(32.W)
  val DATA_ACCESS_ADDR4      = "h00000000".U(32.W)
  val DATA_ACCESS_ADDR5      = "h00000000".U(32.W)
  val DATA_ACCESS_ADDR6      = "h00000000".U(32.W)
  val DATA_ACCESS_ADDR7      = "h00000000".U(32.W)
  val DATA_ACCESS_ENABLE0    = "h1".U(1.W)
  val DATA_ACCESS_ENABLE1    = "h1".U(1.W)
  val DATA_ACCESS_ENABLE2    = "h1".U(1.W)
  val DATA_ACCESS_ENABLE3    = "h1".U(1.W)
  val DATA_ACCESS_ENABLE4    = "h0".U(1.W)
  val DATA_ACCESS_ENABLE5    = "h0".U(1.W)
  val DATA_ACCESS_ENABLE6    = "h0".U(1.W)
  val DATA_ACCESS_ENABLE7    = "h0".U(1.W)
  val DATA_ACCESS_MASK0      = "h7FFFFFFF".U(32.W)
  val DATA_ACCESS_MASK1      = "h3FFFFFFF".U(32.W)
  val DATA_ACCESS_MASK2      = "h1FFFFFFF".U(32.W)
  val DATA_ACCESS_MASK3      = "h0FFFFFFF".U(32.W)
  val DATA_ACCESS_MASK4      = "hFFFFFFFF".U(32.W)
  val DATA_ACCESS_MASK5      = "hFFFFFFFF".U(32.W)
  val DATA_ACCESS_MASK6      = "hFFFFFFFF".U(32.W)
  val DATA_ACCESS_MASK7      = "hFFFFFFFF".U(32.W)
  val DCCM_BANK_BITS         = "h2".U(3.W)
  val DCCM_BITS              = "h10".U(5.W)
  val DCCM_BYTE_WIDTH        = "h4".U(3.W)
  val DCCM_DATA_WIDTH        = "h20".U(6.W)
  val DCCM_ECC_WIDTH         = "h7".U(3.W)
  val DCCM_ENABLE            = "h1".U(1.W)
  val DCCM_FDATA_WIDTH       = "h27".U(6.W)
  val DCCM_INDEX_BITS        = "hC".U(4.W)
  val DCCM_NUM_BANKS         = "h04".U(5.W)
  val DCCM_REGION            = "hF".U(4.W)
  val DCCM_SADR              = "hF0040000".U(32.W)
  val DCCM_SIZE              = "h040".U(10.W)
  val DCCM_WIDTH_BITS        = "h2".U(2.W)
  val DMA_BUF_DEPTH          = "h5".U(3.W)
  val DMA_BUS_ID             = "h1".U(1.W)
  val DMA_BUS_PRTY           = "h2".U(2.W)
  val DMA_BUS_TAG            = "h1".U(4.W)
  val FAST_INTERRUPT_REDIRECT= "h1".U(1.W)
  val ICACHE_2BANKS          = "h1".U(1.W)
  val ICACHE_BANK_BITS       = "h1".U(3.W)
  val ICACHE_BANK_HI         = "h3".U(3.W)
  val ICACHE_BANK_LO         = "h3".U(2.W)
  val ICACHE_BANK_WIDTH      = "h8".U(4.W)
  val ICACHE_BANKS_WAY       = "h2".U(3.W)
  val ICACHE_BEAT_ADDR_HI    = "h5".U(4.W)
  val ICACHE_BEAT_BITS       = "h3".U(4.W)
  val ICACHE_DATA_DEPTH      = "h0200".U(14.W)
  val ICACHE_DATA_INDEX_LO   = "h4".U(3.W)
  val ICACHE_DATA_WIDTH      = "h40".U(7.W)
  val ICACHE_ECC             = "h1".U(1.W)
  val ICACHE_ENABLE          = "h1".U(1.W)
  val ICACHE_FDATA_WIDTH     = "h47".U(7.W)
  val ICACHE_INDEX_HI        = "h0C".U(5.W)
  val ICACHE_LN_SZ           = "h40".U(7.W)
  val ICACHE_NUM_BEATS       = "h8".U(4.W)
  val ICACHE_NUM_WAYS        = "h2".U(3.W)
  val ICACHE_ONLY            = "h0".U(1.W)
  val ICACHE_SCND_LAST       = "h6".U(4.W)
  val ICACHE_SIZE            = "h010".U(9.W)
  val ICACHE_STATUS_BITS     = "h1".U(3.W)
  val ICACHE_TAG_DEPTH       = "h0080".U(13.W)
  val ICACHE_TAG_INDEX_LO    = "h6".U(3.W)
  val ICACHE_TAG_LO          = "h0D".U(5.W)
  val ICACHE_WAYPACK         = "h0".U(1.W)
  val ICCM_BANK_BITS         = "h2".U(3.W)
  val ICCM_BANK_HI           = "h03".U(5.W)
  val ICCM_BANK_INDEX_LO     = "h04".U(5.W)
  val ICCM_BITS              = "h10".U(5.W)
  val ICCM_ENABLE            = "h1".U(1.W)
  val ICCM_ICACHE            = "h1".U(1.W)
  val ICCM_INDEX_BITS        = "hC".U(4.W)
  val ICCM_NUM_BANKS         = "h04".U(5.W)
  val ICCM_ONLY              = "h0".U(1.W)
  val ICCM_REGION            = "hE".U(4.W)
  val ICCM_SADR              = "hEE000000".U(32.W)
  val ICCM_SIZE              = "h040".U(10.W)
  val IFU_BUS_ID             = "h1".U(1.W)
  val IFU_BUS_PRTY           = "h2".U(2.W)
  val IFU_BUS_TAG            = "h3".U(4.W)
  val INST_ACCESS_ADDR0      = "h00000000".U(32.W)
  val INST_ACCESS_ADDR1      = "hC0000000".U(32.W)
  val INST_ACCESS_ADDR2      = "hA0000000".U(32.W)
  val INST_ACCESS_ADDR3      = "h80000000".U(32.W)
  val INST_ACCESS_ADDR4      = "h00000000".U(32.W)
  val INST_ACCESS_ADDR5      = "h00000000".U(32.W)
  val INST_ACCESS_ADDR6      = "h00000000".U(32.W)
  val INST_ACCESS_ADDR7      = "h00000000".U(32.W)
  val INST_ACCESS_ENABLE0    = "h1".U(1.W)
  val INST_ACCESS_ENABLE1    = "h1".U(1.W)
  val INST_ACCESS_ENABLE2    = "h1".U(1.W)
  val INST_ACCESS_ENABLE3    = "h1".U(1.W)
  val INST_ACCESS_ENABLE4    = "h0".U(1.W)
  val INST_ACCESS_ENABLE5    = "h0".U(1.W)
  val INST_ACCESS_ENABLE6    = "h0".U(1.W)
  val INST_ACCESS_ENABLE7    = "h0".U(1.W)
  val INST_ACCESS_MASK0      = "h7FFFFFFF".U(32.W)
  val INST_ACCESS_MASK1      = "h3FFFFFFF".U(32.W)
  val INST_ACCESS_MASK2      = "h1FFFFFFF".U(32.W)
  val INST_ACCESS_MASK3      = "h0FFFFFFF".U(32.W)
  val INST_ACCESS_MASK4      = "hFFFFFFFF".U(32.W)
  val INST_ACCESS_MASK5      = "hFFFFFFFF".U(32.W)
  val INST_ACCESS_MASK6      = "hFFFFFFFF".U(32.W)
  val INST_ACCESS_MASK7      = "hFFFFFFFF".U(32.W)
  val LOAD_TO_USE_PLUS1      = "h0".U(1.W)
  val LSU2DMA                = "h0".U(1.W)
  val LSU_BUS_ID             = "h1".U(1.W)
  val LSU_BUS_PRTY           = "h2".U(2.W)
  val LSU_BUS_TAG            = "h3".U(4.W)
  val LSU_NUM_NBLOAD         = "h04".U(5.W)
  val LSU_NUM_NBLOAD_WIDTH   = "h2".U(3.W)
  val LSU_SB_BITS            = "h10".U(5.W)
  val LSU_STBUF_DEPTH        = "h4".U(4.W)
  val NO_ICCM_NO_ICACHE      = "h0".U(1.W)
  val PIC_2CYCLE             = "h0".U(1.W)
  val PIC_BASE_ADDR          = "hF00C0000".U(32.W)
  val PIC_BITS               = "h0F".U(5.W)
  val PIC_INT_WORDS          = "h1".U(4.W)
  val PIC_REGION             = "hF".U(4.W)
  val PIC_SIZE               = "h020".U(9.W)
  val PIC_TOTAL_INT          = "h1F".U(8.W)
  val PIC_TOTAL_INT_PLUS1    = "h020".U(9.W)
  val RET_STACK_SIZE         = "h8".U(4.W)
  val SB_BUS_ID              = "h1".U(1.W)
  val SB_BUS_PRTY            = "h2".U(2.W)
  val SB_BUS_TAG             = "h1".U(4.W)
  val TIMER_LEGAL_EN         = "h1".U(1.W)
}
