;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_addrcheck : 
  module rvrangecheck : 
    input clock : Clock
    input reset : Reset
    output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
    
    wire start_addr : UInt<32> @[beh_lib.scala 139:25]
    start_addr <= UInt<6>("h020") @[beh_lib.scala 140:15]
    node region = bits(start_addr, 31, 28) @[beh_lib.scala 141:27]
    node _T = bits(io.addr, 31, 28) @[beh_lib.scala 143:28]
    node _T_1 = bits(region, 3, 0) @[beh_lib.scala 143:60]
    node _T_2 = eq(_T, _T_1) @[beh_lib.scala 143:50]
    io.in_region <= _T_2 @[beh_lib.scala 143:17]
    node _T_3 = bits(io.addr, 31, 15) @[beh_lib.scala 147:28]
    node _T_4 = bits(start_addr, 31, 15) @[beh_lib.scala 147:57]
    node _T_5 = eq(_T_3, _T_4) @[beh_lib.scala 147:43]
    io.in_range <= _T_5 @[beh_lib.scala 147:17]
    
  module rvrangecheck_1 : 
    input clock : Clock
    input reset : Reset
    output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
    
    wire start_addr : UInt<32> @[beh_lib.scala 139:25]
    start_addr <= UInt<6>("h020") @[beh_lib.scala 140:15]
    node region = bits(start_addr, 31, 28) @[beh_lib.scala 141:27]
    node _T = bits(io.addr, 31, 28) @[beh_lib.scala 143:28]
    node _T_1 = bits(region, 3, 0) @[beh_lib.scala 143:60]
    node _T_2 = eq(_T, _T_1) @[beh_lib.scala 143:50]
    io.in_region <= _T_2 @[beh_lib.scala 143:17]
    node _T_3 = bits(io.addr, 31, 15) @[beh_lib.scala 147:28]
    node _T_4 = bits(start_addr, 31, 15) @[beh_lib.scala 147:57]
    node _T_5 = eq(_T_3, _T_4) @[beh_lib.scala 147:43]
    io.in_range <= _T_5 @[beh_lib.scala 147:17]
    
  module el2_lsu_addrcheck : 
    input clock : Clock
    input reset : AsyncReset
    output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
    
    wire start_addr_in_dccm_d : UInt<1>
    start_addr_in_dccm_d <= UInt<1>("h00")
    wire start_addr_in_dccm_region_d : UInt<1>
    start_addr_in_dccm_region_d <= UInt<1>("h00")
    wire end_addr_in_dccm_d : UInt<1>
    end_addr_in_dccm_d <= UInt<1>("h00")
    wire end_addr_in_dccm_region_d : UInt<1>
    end_addr_in_dccm_region_d <= UInt<1>("h00")
    start_addr_in_dccm_d <= UInt<1>("h00") @[w.scala 61:36]
    start_addr_in_dccm_region_d <= UInt<1>("h00") @[w.scala 62:36]
    end_addr_in_dccm_d <= UInt<1>("h00") @[w.scala 63:36]
    end_addr_in_dccm_region_d <= UInt<1>("h00") @[w.scala 64:36]
    wire addr_in_iccm : UInt<1>
    addr_in_iccm <= UInt<1>("h00")
    addr_in_iccm <= UInt<1>("h01") @[w.scala 72:18]
    inst start_addr_pic_rangecheck of rvrangecheck @[w.scala 78:41]
    start_addr_pic_rangecheck.clock <= clock
    start_addr_pic_rangecheck.reset <= reset
    node _T = bits(io.start_addr_d, 31, 0) @[w.scala 79:55]
    start_addr_pic_rangecheck.io.addr <= _T @[w.scala 79:37]
    inst end_addr_pic_rangecheck of rvrangecheck_1 @[w.scala 84:39]
    end_addr_pic_rangecheck.clock <= clock
    end_addr_pic_rangecheck.reset <= reset
    node _T_1 = bits(io.end_addr_d, 31, 0) @[w.scala 85:51]
    end_addr_pic_rangecheck.io.addr <= _T_1 @[w.scala 85:35]
    node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 89:60]
    node _T_2 = bits(io.rs1_region_d, 3, 0) @[w.scala 90:48]
    node _T_3 = eq(_T_2, UInt<4>("h0f")) @[w.scala 90:54]
    node _T_4 = bits(io.rs1_region_d, 3, 0) @[w.scala 90:91]
    node _T_5 = eq(_T_4, UInt<4>("h0f")) @[w.scala 90:97]
    node base_reg_dccm_or_pic = or(_T_3, _T_5) @[w.scala 90:73]
    node _T_6 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[w.scala 91:57]
    io.addr_in_dccm_d <= _T_6 @[w.scala 91:32]
    node _T_7 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[w.scala 92:56]
    io.addr_in_pic_d <= _T_7 @[w.scala 92:32]
    node _T_8 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 94:63]
    node _T_9 = not(_T_8) @[w.scala 94:33]
    io.addr_external_d <= _T_9 @[w.scala 94:30]
    node _T_10 = bits(io.start_addr_d, 31, 28) @[w.scala 95:51]
    node csr_idx = cat(_T_10, UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_11 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[w.scala 96:50]
    node _T_12 = bits(_T_11, 0, 0) @[w.scala 96:50]
    node _T_13 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 96:92]
    node _T_14 = or(_T_13, addr_in_iccm) @[w.scala 96:121]
    node _T_15 = not(_T_14) @[w.scala 96:62]
    node _T_16 = and(_T_12, _T_15) @[w.scala 96:60]
    node _T_17 = and(_T_16, io.lsu_pkt_d.valid) @[w.scala 96:137]
    node _T_18 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[w.scala 96:180]
    node is_sideeffects_d = and(_T_17, _T_18) @[w.scala 96:158]
    node _T_19 = bits(io.start_addr_d, 1, 0) @[w.scala 97:69]
    node _T_20 = eq(_T_19, UInt<1>("h00")) @[w.scala 97:75]
    node _T_21 = and(io.lsu_pkt_d.word, _T_20) @[w.scala 97:51]
    node _T_22 = bits(io.start_addr_d, 0, 0) @[w.scala 97:124]
    node _T_23 = eq(_T_22, UInt<1>("h00")) @[w.scala 97:128]
    node _T_24 = and(io.lsu_pkt_d.half, _T_23) @[w.scala 97:106]
    node _T_25 = or(_T_21, _T_24) @[w.scala 97:85]
    node is_aligned_d = or(_T_25, io.lsu_pkt_d.by) @[w.scala 97:138]
    node _T_26 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_27 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
    node _T_28 = cat(_T_27, _T_26) @[Cat.scala 29:58]
    node _T_29 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_30 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
    node _T_31 = cat(_T_30, _T_29) @[Cat.scala 29:58]
    node _T_32 = cat(_T_31, _T_28) @[Cat.scala 29:58]
    node _T_33 = orr(_T_32) @[w.scala 101:98]
    node _T_34 = not(_T_33) @[w.scala 100:33]
    node _T_35 = bits(io.start_addr_d, 31, 0) @[w.scala 102:49]
    node _T_36 = or(_T_35, UInt<31>("h07fffffff")) @[w.scala 102:56]
    node _T_37 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[w.scala 102:105]
    node _T_38 = eq(_T_36, _T_37) @[w.scala 102:80]
    node _T_39 = and(UInt<1>("h01"), _T_38) @[w.scala 102:30]
    node _T_40 = bits(io.start_addr_d, 31, 0) @[w.scala 103:49]
    node _T_41 = or(_T_40, UInt<30>("h03fffffff")) @[w.scala 103:56]
    node _T_42 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[w.scala 103:105]
    node _T_43 = eq(_T_41, _T_42) @[w.scala 103:80]
    node _T_44 = and(UInt<1>("h01"), _T_43) @[w.scala 103:30]
    node _T_45 = or(_T_39, _T_44) @[w.scala 102:129]
    node _T_46 = bits(io.start_addr_d, 31, 0) @[w.scala 104:49]
    node _T_47 = or(_T_46, UInt<29>("h01fffffff")) @[w.scala 104:56]
    node _T_48 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[w.scala 104:105]
    node _T_49 = eq(_T_47, _T_48) @[w.scala 104:80]
    node _T_50 = and(UInt<1>("h01"), _T_49) @[w.scala 104:30]
    node _T_51 = or(_T_45, _T_50) @[w.scala 103:129]
    node _T_52 = bits(io.start_addr_d, 31, 0) @[w.scala 105:49]
    node _T_53 = or(_T_52, UInt<28>("h0fffffff")) @[w.scala 105:56]
    node _T_54 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[w.scala 105:105]
    node _T_55 = eq(_T_53, _T_54) @[w.scala 105:80]
    node _T_56 = and(UInt<1>("h01"), _T_55) @[w.scala 105:30]
    node _T_57 = or(_T_51, _T_56) @[w.scala 104:129]
    node _T_58 = bits(io.start_addr_d, 31, 0) @[w.scala 106:49]
    node _T_59 = or(_T_58, UInt<32>("h0ffffffff")) @[w.scala 106:56]
    node _T_60 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 106:105]
    node _T_61 = eq(_T_59, _T_60) @[w.scala 106:80]
    node _T_62 = and(UInt<1>("h00"), _T_61) @[w.scala 106:30]
    node _T_63 = or(_T_57, _T_62) @[w.scala 105:129]
    node _T_64 = bits(io.start_addr_d, 31, 0) @[w.scala 107:49]
    node _T_65 = or(_T_64, UInt<32>("h0ffffffff")) @[w.scala 107:56]
    node _T_66 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 107:105]
    node _T_67 = eq(_T_65, _T_66) @[w.scala 107:80]
    node _T_68 = and(UInt<1>("h00"), _T_67) @[w.scala 107:30]
    node _T_69 = or(_T_63, _T_68) @[w.scala 106:129]
    node _T_70 = bits(io.start_addr_d, 31, 0) @[w.scala 108:49]
    node _T_71 = or(_T_70, UInt<32>("h0ffffffff")) @[w.scala 108:56]
    node _T_72 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 108:105]
    node _T_73 = eq(_T_71, _T_72) @[w.scala 108:80]
    node _T_74 = and(UInt<1>("h00"), _T_73) @[w.scala 108:30]
    node _T_75 = or(_T_69, _T_74) @[w.scala 107:129]
    node _T_76 = bits(io.start_addr_d, 31, 0) @[w.scala 109:49]
    node _T_77 = or(_T_76, UInt<32>("h0ffffffff")) @[w.scala 109:56]
    node _T_78 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 109:105]
    node _T_79 = eq(_T_77, _T_78) @[w.scala 109:80]
    node _T_80 = and(UInt<1>("h00"), _T_79) @[w.scala 109:30]
    node _T_81 = or(_T_75, _T_80) @[w.scala 108:129]
    node _T_82 = bits(io.end_addr_d, 31, 0) @[w.scala 111:48]
    node _T_83 = or(_T_82, UInt<31>("h07fffffff")) @[w.scala 111:57]
    node _T_84 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[w.scala 111:106]
    node _T_85 = eq(_T_83, _T_84) @[w.scala 111:81]
    node _T_86 = and(UInt<1>("h01"), _T_85) @[w.scala 111:31]
    node _T_87 = bits(io.end_addr_d, 31, 0) @[w.scala 112:49]
    node _T_88 = or(_T_87, UInt<30>("h03fffffff")) @[w.scala 112:58]
    node _T_89 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[w.scala 112:107]
    node _T_90 = eq(_T_88, _T_89) @[w.scala 112:82]
    node _T_91 = and(UInt<1>("h01"), _T_90) @[w.scala 112:32]
    node _T_92 = or(_T_86, _T_91) @[w.scala 111:130]
    node _T_93 = bits(io.end_addr_d, 31, 0) @[w.scala 113:49]
    node _T_94 = or(_T_93, UInt<29>("h01fffffff")) @[w.scala 113:58]
    node _T_95 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[w.scala 113:107]
    node _T_96 = eq(_T_94, _T_95) @[w.scala 113:82]
    node _T_97 = and(UInt<1>("h01"), _T_96) @[w.scala 113:32]
    node _T_98 = or(_T_92, _T_97) @[w.scala 112:131]
    node _T_99 = bits(io.end_addr_d, 31, 0) @[w.scala 114:49]
    node _T_100 = or(_T_99, UInt<28>("h0fffffff")) @[w.scala 114:58]
    node _T_101 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[w.scala 114:107]
    node _T_102 = eq(_T_100, _T_101) @[w.scala 114:82]
    node _T_103 = and(UInt<1>("h01"), _T_102) @[w.scala 114:32]
    node _T_104 = or(_T_98, _T_103) @[w.scala 113:131]
    node _T_105 = bits(io.end_addr_d, 31, 0) @[w.scala 115:49]
    node _T_106 = or(_T_105, UInt<32>("h0ffffffff")) @[w.scala 115:58]
    node _T_107 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 115:107]
    node _T_108 = eq(_T_106, _T_107) @[w.scala 115:82]
    node _T_109 = and(UInt<1>("h00"), _T_108) @[w.scala 115:32]
    node _T_110 = or(_T_104, _T_109) @[w.scala 114:131]
    node _T_111 = bits(io.end_addr_d, 31, 0) @[w.scala 116:49]
    node _T_112 = or(_T_111, UInt<32>("h0ffffffff")) @[w.scala 116:58]
    node _T_113 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 116:107]
    node _T_114 = eq(_T_112, _T_113) @[w.scala 116:82]
    node _T_115 = and(UInt<1>("h00"), _T_114) @[w.scala 116:32]
    node _T_116 = or(_T_110, _T_115) @[w.scala 115:131]
    node _T_117 = bits(io.end_addr_d, 31, 0) @[w.scala 117:49]
    node _T_118 = or(_T_117, UInt<32>("h0ffffffff")) @[w.scala 117:58]
    node _T_119 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 117:107]
    node _T_120 = eq(_T_118, _T_119) @[w.scala 117:82]
    node _T_121 = and(UInt<1>("h00"), _T_120) @[w.scala 117:32]
    node _T_122 = or(_T_116, _T_121) @[w.scala 116:131]
    node _T_123 = bits(io.end_addr_d, 31, 0) @[w.scala 118:49]
    node _T_124 = or(_T_123, UInt<32>("h0ffffffff")) @[w.scala 118:58]
    node _T_125 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 118:107]
    node _T_126 = eq(_T_124, _T_125) @[w.scala 118:82]
    node _T_127 = and(UInt<1>("h00"), _T_126) @[w.scala 118:32]
    node _T_128 = or(_T_122, _T_127) @[w.scala 117:131]
    node _T_129 = and(_T_81, _T_128) @[w.scala 110:7]
    node non_dccm_access_ok = or(_T_34, _T_129) @[w.scala 101:103]
    node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[w.scala 120:57]
    node _T_130 = bits(io.start_addr_d, 1, 0) @[w.scala 121:70]
    node _T_131 = neq(_T_130, UInt<2>("h00")) @[w.scala 121:76]
    node _T_132 = not(io.lsu_pkt_d.word) @[w.scala 121:92]
    node _T_133 = or(_T_131, _T_132) @[w.scala 121:90]
    node picm_access_fault_d = and(io.addr_in_pic_d, _T_133) @[w.scala 121:51]
    wire unmapped_access_fault_d : UInt<1>
    unmapped_access_fault_d <= UInt<1>("h01")
    wire mpu_access_fault_d : UInt<1>
    mpu_access_fault_d <= UInt<1>("h01")
    node _T_134 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[w.scala 126:87]
    node _T_135 = not(_T_134) @[w.scala 126:64]
    node _T_136 = and(start_addr_in_dccm_region_d, _T_135) @[w.scala 126:62]
    node _T_137 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[w.scala 128:57]
    node _T_138 = not(_T_137) @[w.scala 128:36]
    node _T_139 = and(end_addr_in_dccm_region_d, _T_138) @[w.scala 128:34]
    node _T_140 = or(_T_136, _T_139) @[w.scala 126:112]
    node _T_141 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[w.scala 130:29]
    node _T_142 = or(_T_140, _T_141) @[w.scala 128:85]
    node _T_143 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[w.scala 132:29]
    node _T_144 = or(_T_142, _T_143) @[w.scala 130:85]
    unmapped_access_fault_d <= _T_144 @[w.scala 126:29]
    node _T_145 = not(start_addr_in_dccm_region_d) @[w.scala 134:33]
    node _T_146 = not(non_dccm_access_ok) @[w.scala 134:64]
    node _T_147 = and(_T_145, _T_146) @[w.scala 134:62]
    mpu_access_fault_d <= _T_147 @[w.scala 134:29]
    node _T_148 = or(unmapped_access_fault_d, mpu_access_fault_d) @[w.scala 146:49]
    node _T_149 = or(_T_148, picm_access_fault_d) @[w.scala 146:70]
    node _T_150 = or(_T_149, regpred_access_fault_d) @[w.scala 146:92]
    node _T_151 = and(_T_150, io.lsu_pkt_d.valid) @[w.scala 146:118]
    node _T_152 = not(io.lsu_pkt_d.dma) @[w.scala 146:141]
    node _T_153 = and(_T_151, _T_152) @[w.scala 146:139]
    io.access_fault_d <= _T_153 @[w.scala 146:21]
    node _T_154 = bits(unmapped_access_fault_d, 0, 0) @[w.scala 147:60]
    node _T_155 = bits(mpu_access_fault_d, 0, 0) @[w.scala 147:100]
    node _T_156 = bits(regpred_access_fault_d, 0, 0) @[w.scala 147:144]
    node _T_157 = bits(picm_access_fault_d, 0, 0) @[w.scala 147:185]
    node _T_158 = mux(_T_157, UInt<4>("h06"), UInt<4>("h00")) @[w.scala 147:164]
    node _T_159 = mux(_T_156, UInt<4>("h05"), _T_158) @[w.scala 147:120]
    node _T_160 = mux(_T_155, UInt<4>("h03"), _T_159) @[w.scala 147:80]
    node access_fault_mscause_d = mux(_T_154, UInt<4>("h02"), _T_160) @[w.scala 147:35]
    node _T_161 = bits(io.start_addr_d, 31, 28) @[w.scala 148:53]
    node _T_162 = bits(io.end_addr_d, 31, 28) @[w.scala 148:78]
    node regcross_misaligned_fault_d = neq(_T_161, _T_162) @[w.scala 148:61]
    node _T_163 = not(is_aligned_d) @[w.scala 149:59]
    node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_163) @[w.scala 149:57]
    node _T_164 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[w.scala 150:90]
    node _T_165 = or(regcross_misaligned_fault_d, _T_164) @[w.scala 150:57]
    node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[w.scala 150:113]
    node _T_167 = not(io.lsu_pkt_d.dma) @[w.scala 150:136]
    node _T_168 = and(_T_166, _T_167) @[w.scala 150:134]
    io.misaligned_fault_d <= _T_168 @[w.scala 150:25]
    node _T_169 = bits(sideeffect_misaligned_fault_d, 0, 0) @[w.scala 151:111]
    node _T_170 = mux(_T_169, UInt<4>("h01"), UInt<4>("h00")) @[w.scala 151:80]
    node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_170) @[w.scala 151:39]
    node _T_171 = bits(io.misaligned_fault_d, 0, 0) @[w.scala 152:50]
    node _T_172 = bits(misaligned_fault_mscause_d, 3, 0) @[w.scala 152:84]
    node _T_173 = bits(access_fault_mscause_d, 3, 0) @[w.scala 152:113]
    node _T_174 = mux(_T_171, _T_172, _T_173) @[w.scala 152:27]
    io.exc_mscause_d <= _T_174 @[w.scala 152:21]
    node _T_175 = not(start_addr_in_dccm_d) @[w.scala 153:66]
    node _T_176 = and(start_addr_in_dccm_region_d, _T_175) @[w.scala 153:64]
    node _T_177 = not(end_addr_in_dccm_d) @[w.scala 153:120]
    node _T_178 = and(end_addr_in_dccm_region_d, _T_177) @[w.scala 153:118]
    node _T_179 = or(_T_176, _T_178) @[w.scala 153:88]
    node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[w.scala 153:142]
    node _T_181 = and(_T_180, io.lsu_pkt_d.fast_int) @[w.scala 153:163]
    io.fir_dccm_access_error_d <= _T_181 @[w.scala 153:31]
    node _T_182 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[w.scala 154:66]
    node _T_183 = not(_T_182) @[w.scala 154:36]
    node _T_184 = and(_T_183, io.lsu_pkt_d.valid) @[w.scala 154:95]
    node _T_185 = and(_T_184, io.lsu_pkt_d.fast_int) @[w.scala 154:116]
    io.fir_nondccm_access_error_d <= _T_185 @[w.scala 154:33]
    reg _T_186 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[w.scala 156:60]
    _T_186 <= is_sideeffects_d @[w.scala 156:60]
    io.is_sideeffects_m <= _T_186 @[w.scala 156:50]
    
