[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
    "sources":[
      "~el2_dbg|el2_dbg>io_dma_dbg_ready"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_dbg|el2_dbg>io_dbg_resume_req",
    "sources":[
      "~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only",
      "~el2_dbg|el2_dbg>io_dec_tlu_debug_mode",
      "~el2_dbg|el2_dbg>io_dbg_cmd_valid",
      "~el2_dbg|el2_dbg>io_core_dbg_cmd_done",
      "~el2_dbg|el2_dbg>io_dmi_reg_wr_en",
      "~el2_dbg|el2_dbg>io_dmi_reg_en",
      "~el2_dbg|el2_dbg>io_dma_dbg_ready",
      "~el2_dbg|el2_dbg>io_dmi_reg_addr",
      "~el2_dbg|el2_dbg>reset"
    ]
  },
  {
    "class":"logger.LogLevelAnnotation",
    "globalLogLevel":{
      
    }
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"el2_dbg.TEC_RV_ICG",
    "resourceId":"/vsrc/TEC_RV_ICG.v"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"el2_dbg"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]