colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
quasar/el2_ifu_mem_ctl.fir

7738 lines
506 KiB
Plaintext
Raw Normal View History

Clk enable removed from predictor
2020-10-07 12:35:34 +08:00
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_mem_ctl :
ICCM Done
2020-10-12 19:46:52 +08:00
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
Branch Predictor started
2020-10-20 13:51:36 +08:00
extmodule TEC_RV_ICG_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_12 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_12 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_13 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_13 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_14 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_14 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_15 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_15 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_16 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_16 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
extmodule TEC_RV_ICG_17 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_17 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 403:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
clkhdr.EN <= io.en @[el2_lib.scala 406:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
Clk enable removed from predictor
2020-10-07 12:35:34 +08:00
module el2_ifu_mem_ctl :
input clock : Clock
input reset : UInt<1>
IMC 80%
2020-10-19 13:10:40 +08:00
output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, test : UInt, flip scan_mode : UInt<1>}
Clk enable removed from predictor
2020-10-07 12:35:34 +08:00
ICCM Done
2020-10-12 19:46:52 +08:00
io.ic_debug_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 128:20]
io.ic_debug_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:20]
io.ic_debug_tag_array <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:24]
io.ifu_miss_state_idle <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:25]
io.ifu_ic_mb_empty <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:21]
io.ic_dma_active <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:19]
io.ic_write_stall <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
io.ifu_pmu_ic_miss <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:21]
io.ifu_pmu_ic_hit <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:20]
io.ifu_pmu_bus_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:23]
io.ifu_pmu_bus_busy <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:22]
io.ifu_pmu_bus_trxn <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:22]
io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:21]
io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:18]
io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:20]
io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:19]
io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:20]
io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:21]
io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:19]
io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:20]
io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:19]
io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:19]
io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:19]
io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:20]
io.ifu_axi_arvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 155:21]
io.ic_debug_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 156:19]
io.ifu_axi_arid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 157:18]
io.ifu_axi_araddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 158:20]
io.ifu_axi_arregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 159:22]
io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 160:19]
io.ifu_axi_arsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 161:20]
io.ifu_axi_arburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 162:21]
io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 163:20]
io.ifu_axi_arcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 164:21]
io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 165:20]
io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 166:19]
io.ifu_axi_rready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 167:20]
io.iccm_dma_ecc_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 168:24]
io.iccm_dma_rvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 169:21]
io.iccm_dma_rdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 170:20]
io.iccm_dma_rtag <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 171:19]
io.iccm_ready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 172:16]
io.ic_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 173:16]
io.ic_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:14]
io.ic_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 175:14]
io.ic_wr_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:16]
io.ic_wr_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:16]
io.ic_debug_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 177:22]
io.ifu_ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 178:26]
io.ic_tag_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 179:18]
io.iccm_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 180:18]
io.iccm_wren <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 181:15]
io.iccm_rden <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 182:15]
io.iccm_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 183:18]
io.iccm_wr_size <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 184:18]
io.ic_hit_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 185:14]
io.ic_access_fault_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 186:23]
io.ic_access_fault_type_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 187:28]
io.iccm_rd_ecc_single_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 188:28]
io.iccm_rd_ecc_double_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 189:28]
io.ic_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 190:20]
io.ifu_async_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 191:27]
io.iccm_dma_sb_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 192:23]
io.ic_fetch_val_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 193:20]
io.ic_data_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 194:15]
io.ic_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 195:20]
io.ic_sel_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 196:24]
io.ifu_ic_debug_rd_data_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 197:32]
io.iccm_buf_correct_ecc <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 198:26]
io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 199:27]
io.ic_debug_way <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 200:18]
io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 201:22]
wire iccm_single_ecc_error : UInt<2>
iccm_single_ecc_error <= UInt<1>("h00")
wire ifc_fetch_req_f : UInt<1>
ifc_fetch_req_f <= UInt<1>("h00")
wire miss_pending : UInt<1>
miss_pending <= UInt<1>("h00")
wire scnd_miss_req : UInt<1>
scnd_miss_req <= UInt<1>("h00")
wire dma_iccm_req_f : UInt<1>
dma_iccm_req_f <= UInt<1>("h00")
wire iccm_correct_ecc : UInt<1>
iccm_correct_ecc <= UInt<1>("h00")
wire perr_state : UInt<3>
perr_state <= UInt<1>("h00")
wire err_stop_state : UInt<2>
err_stop_state <= UInt<1>("h00")
wire err_stop_fetch : UInt<1>
err_stop_fetch <= UInt<1>("h00")
wire miss_state : UInt<3>
miss_state <= UInt<1>("h00")
wire miss_nxtstate : UInt<3>
miss_nxtstate <= UInt<1>("h00")
wire miss_state_en : UInt<1>
miss_state_en <= UInt<1>("h00")
wire ifu_bus_rsp_valid : UInt<1>
ifu_bus_rsp_valid <= UInt<1>("h00")
wire bus_ifu_bus_clk_en : UInt<1>
bus_ifu_bus_clk_en <= UInt<1>("h00")
wire ifu_bus_rsp_ready : UInt<1>
ifu_bus_rsp_ready <= UInt<1>("h00")
wire uncacheable_miss_ff : UInt<1>
uncacheable_miss_ff <= UInt<1>("h00")
wire ic_act_miss_f : UInt<1>
ic_act_miss_f <= UInt<1>("h00")
wire ic_byp_hit_f : UInt<1>
ic_byp_hit_f <= UInt<1>("h00")
wire bus_new_data_beat_count : UInt<3>
bus_new_data_beat_count <= UInt<1>("h00")
wire bus_ifu_wr_en_ff : UInt<1>
bus_ifu_wr_en_ff <= UInt<1>("h00")
wire last_beat : UInt<1>
last_beat <= UInt<1>("h00")
wire last_data_recieved_ff : UInt<1>
last_data_recieved_ff <= UInt<1>("h00")
wire stream_eol_f : UInt<1>
stream_eol_f <= UInt<1>("h00")
wire ic_miss_under_miss_f : UInt<1>
ic_miss_under_miss_f <= UInt<1>("h00")
wire ic_ignore_2nd_miss_f : UInt<1>
ic_ignore_2nd_miss_f <= UInt<1>("h00")
reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 234:30]
flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 234:30]
node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 235:53]
node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 235:71]
node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 235:86]
node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 235:107]
node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 236:42]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 412:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr.io.en <= debug_c1_clken @[el2_lib.scala 414:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
node _T_3 = bits(fetch_bf_f_c1_clken, 0, 0) @[el2_ifu_mem_ctl.scala 238:63]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 412:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_1.io.en <= _T_3 @[el2_lib.scala 414:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
node _T_4 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 239:52]
node _T_5 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 239:78]
node _T_6 = and(_T_4, _T_5) @[el2_ifu_mem_ctl.scala 239:55]
io.iccm_dma_sb_error <= _T_6 @[el2_ifu_mem_ctl.scala 239:24]
node _T_7 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 240:57]
io.ifu_async_error_start <= _T_7 @[el2_ifu_mem_ctl.scala 240:28]
node _T_8 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 241:54]
node _T_9 = or(iccm_correct_ecc, _T_8) @[el2_ifu_mem_ctl.scala 241:40]
node _T_10 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 241:90]
node _T_11 = or(_T_9, _T_10) @[el2_ifu_mem_ctl.scala 241:72]
node _T_12 = or(_T_11, err_stop_fetch) @[el2_ifu_mem_ctl.scala 241:112]
node _T_13 = or(_T_12, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 241:129]
io.ic_dma_active <= _T_13 @[el2_ifu_mem_ctl.scala 241:20]
node _T_14 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 242:44]
node _T_15 = and(_T_14, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 242:65]
node _T_16 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 242:111]
node _T_17 = and(_T_15, _T_16) @[el2_ifu_mem_ctl.scala 242:85]
node _T_18 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 243:39]
node _T_19 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 243:71]
node _T_20 = or(_T_18, _T_19) @[el2_ifu_mem_ctl.scala 243:55]
node _T_21 = dshr(uncacheable_miss_ff, _T_20) @[el2_ifu_mem_ctl.scala 243:26]
node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_mem_ctl.scala 243:26]
node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 243:5]
node _T_24 = and(_T_17, _T_23) @[el2_ifu_mem_ctl.scala 242:116]
node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 243:91]
node scnd_miss_req_in = and(_T_24, _T_25) @[el2_ifu_mem_ctl.scala 243:89]
node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 245:52]
node _T_26 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30]
when _T_26 : @[Conditional.scala 40:58]
node _T_27 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 249:45]
node _T_28 = and(ic_act_miss_f, _T_27) @[el2_ifu_mem_ctl.scala 249:43]
node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_mem_ctl.scala 249:66]
node _T_30 = mux(_T_29, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 249:27]
miss_nxtstate <= _T_30 @[el2_ifu_mem_ctl.scala 249:21]
node _T_31 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:40]
node _T_32 = and(ic_act_miss_f, _T_31) @[el2_ifu_mem_ctl.scala 250:38]
miss_state_en <= _T_32 @[el2_ifu_mem_ctl.scala 250:21]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_33 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30]
when _T_33 : @[Conditional.scala 39:67]
node _T_34 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 252:112]
node _T_35 = or(last_data_recieved_ff, _T_34) @[el2_ifu_mem_ctl.scala 252:92]
node _T_36 = and(ic_byp_hit_f, _T_35) @[el2_ifu_mem_ctl.scala 252:66]
node _T_37 = and(_T_36, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 252:126]
node _T_38 = or(io.dec_tlu_force_halt, _T_37) @[el2_ifu_mem_ctl.scala 252:51]
node _T_39 = bits(_T_38, 0, 0) @[el2_ifu_mem_ctl.scala 252:150]
node _T_40 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 253:30]
node _T_41 = and(ic_byp_hit_f, _T_40) @[el2_ifu_mem_ctl.scala 253:27]
node _T_42 = and(_T_41, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 253:53]
node _T_43 = bits(_T_42, 0, 0) @[el2_ifu_mem_ctl.scala 253:77]
node _T_44 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:16]
node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:32]
node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 254:30]
node _T_47 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 254:72]
node _T_48 = and(_T_46, _T_47) @[el2_ifu_mem_ctl.scala 254:52]
node _T_49 = and(_T_48, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 254:85]
node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_mem_ctl.scala 254:109]
node _T_51 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 255:36]
node _T_52 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:51]
node _T_53 = and(_T_51, _T_52) @[el2_ifu_mem_ctl.scala 255:49]
node _T_54 = bits(_T_53, 0, 0) @[el2_ifu_mem_ctl.scala 255:73]
node _T_55 = or(ic_byp_hit_f, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 256:34]
node _T_56 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:56]
node _T_57 = and(_T_55, _T_56) @[el2_ifu_mem_ctl.scala 256:54]
node _T_58 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 256:97]
node _T_59 = eq(_T_58, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:78]
node _T_60 = and(_T_57, _T_59) @[el2_ifu_mem_ctl.scala 256:76]
node _T_61 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:112]
node _T_62 = and(_T_60, _T_61) @[el2_ifu_mem_ctl.scala 256:110]
node _T_63 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:136]
node _T_64 = and(_T_62, _T_63) @[el2_ifu_mem_ctl.scala 256:134]
node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_mem_ctl.scala 256:158]
node _T_66 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:22]
node _T_67 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:40]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_mem_ctl.scala 257:37]
node _T_69 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 257:81]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_mem_ctl.scala 257:60]
node _T_71 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:102]
node _T_72 = and(_T_70, _T_71) @[el2_ifu_mem_ctl.scala 257:100]
node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_mem_ctl.scala 257:124]
node _T_74 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 258:44]
node _T_75 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 258:89]
node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 258:70]
node _T_77 = and(_T_74, _T_76) @[el2_ifu_mem_ctl.scala 258:68]
node _T_78 = bits(_T_77, 0, 0) @[el2_ifu_mem_ctl.scala 258:103]
node _T_79 = mux(_T_78, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 258:22]
node _T_80 = mux(_T_73, UInt<3>("h00"), _T_79) @[el2_ifu_mem_ctl.scala 257:20]
node _T_81 = mux(_T_65, UInt<3>("h06"), _T_80) @[el2_ifu_mem_ctl.scala 256:18]
node _T_82 = mux(_T_54, UInt<3>("h00"), _T_81) @[el2_ifu_mem_ctl.scala 255:16]
node _T_83 = mux(_T_50, UInt<3>("h01"), _T_82) @[el2_ifu_mem_ctl.scala 254:14]
node _T_84 = mux(_T_43, UInt<3>("h03"), _T_83) @[el2_ifu_mem_ctl.scala 253:12]
node _T_85 = mux(_T_39, UInt<3>("h00"), _T_84) @[el2_ifu_mem_ctl.scala 252:27]
miss_nxtstate <= _T_85 @[el2_ifu_mem_ctl.scala 252:21]
node _T_86 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 259:46]
node _T_87 = or(_T_86, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 259:67]
node _T_88 = or(_T_87, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 259:82]
node _T_89 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 259:125]
node _T_90 = or(_T_88, _T_89) @[el2_ifu_mem_ctl.scala 259:105]
node _T_91 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 259:160]
node _T_92 = and(bus_ifu_wr_en_ff, _T_91) @[el2_ifu_mem_ctl.scala 259:158]
node _T_93 = or(_T_90, _T_92) @[el2_ifu_mem_ctl.scala 259:138]
miss_state_en <= _T_93 @[el2_ifu_mem_ctl.scala 259:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_94 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30]
when _T_94 : @[Conditional.scala 39:67]
miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 262:21]
node _T_95 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 263:43]
node _T_96 = or(_T_95, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 263:59]
node _T_97 = or(_T_96, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 263:74]
miss_state_en <= _T_97 @[el2_ifu_mem_ctl.scala 263:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_98 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30]
when _T_98 : @[Conditional.scala 39:67]
node _T_99 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 266:49]
node _T_100 = or(_T_99, stream_eol_f) @[el2_ifu_mem_ctl.scala 266:72]
node _T_101 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 266:108]
node _T_102 = eq(_T_101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 266:89]
node _T_103 = and(_T_100, _T_102) @[el2_ifu_mem_ctl.scala 266:87]
node _T_104 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 266:124]
node _T_105 = and(_T_103, _T_104) @[el2_ifu_mem_ctl.scala 266:122]
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_mem_ctl.scala 266:148]
node _T_107 = mux(_T_106, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 266:27]
miss_nxtstate <= _T_107 @[el2_ifu_mem_ctl.scala 266:21]
node _T_108 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 267:43]
node _T_109 = or(_T_108, stream_eol_f) @[el2_ifu_mem_ctl.scala 267:67]
node _T_110 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 267:105]
node _T_111 = or(_T_109, _T_110) @[el2_ifu_mem_ctl.scala 267:84]
node _T_112 = or(_T_111, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 267:118]
miss_state_en <= _T_112 @[el2_ifu_mem_ctl.scala 267:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_113 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30]
when _T_113 : @[Conditional.scala 39:67]
node _T_114 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 270:69]
node _T_115 = eq(_T_114, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:50]
node _T_116 = and(io.exu_flush_final, _T_115) @[el2_ifu_mem_ctl.scala 270:48]
node _T_117 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:84]
node _T_118 = and(_T_116, _T_117) @[el2_ifu_mem_ctl.scala 270:82]
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_mem_ctl.scala 270:108]
node _T_120 = mux(_T_119, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 270:27]
miss_nxtstate <= _T_120 @[el2_ifu_mem_ctl.scala 270:21]
node _T_121 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 271:63]
node _T_122 = or(io.exu_flush_final, _T_121) @[el2_ifu_mem_ctl.scala 271:43]
node _T_123 = or(_T_122, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 271:76]
miss_state_en <= _T_123 @[el2_ifu_mem_ctl.scala 271:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_124 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30]
when _T_124 : @[Conditional.scala 39:67]
node _T_125 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 274:71]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:52]
node _T_127 = and(ic_miss_under_miss_f, _T_126) @[el2_ifu_mem_ctl.scala 274:50]
node _T_128 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:86]
node _T_129 = and(_T_127, _T_128) @[el2_ifu_mem_ctl.scala 274:84]
node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_mem_ctl.scala 274:110]
node _T_131 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 275:56]
node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:37]
node _T_133 = and(ic_ignore_2nd_miss_f, _T_132) @[el2_ifu_mem_ctl.scala 275:35]
node _T_134 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:71]
node _T_135 = and(_T_133, _T_134) @[el2_ifu_mem_ctl.scala 275:69]
node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_mem_ctl.scala 275:95]
node _T_137 = mux(_T_136, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 275:12]
node _T_138 = mux(_T_130, UInt<3>("h05"), _T_137) @[el2_ifu_mem_ctl.scala 274:27]
miss_nxtstate <= _T_138 @[el2_ifu_mem_ctl.scala 274:21]
node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 276:42]
node _T_140 = or(_T_139, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 276:55]
node _T_141 = or(_T_140, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 276:78]
node _T_142 = or(_T_141, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 276:101]
miss_state_en <= _T_142 @[el2_ifu_mem_ctl.scala 276:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_143 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30]
when _T_143 : @[Conditional.scala 39:67]
node _T_144 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 280:31]
node _T_145 = bits(_T_144, 0, 0) @[el2_ifu_mem_ctl.scala 280:44]
node _T_146 = mux(_T_145, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 280:12]
node _T_147 = mux(io.exu_flush_final, _T_146, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 279:62]
node _T_148 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_147) @[el2_ifu_mem_ctl.scala 279:27]
miss_nxtstate <= _T_148 @[el2_ifu_mem_ctl.scala 279:21]
node _T_149 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 281:42]
node _T_150 = or(_T_149, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 281:55]
node _T_151 = or(_T_150, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 281:76]
miss_state_en <= _T_151 @[el2_ifu_mem_ctl.scala 281:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_152 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30]
when _T_152 : @[Conditional.scala 39:67]
node _T_153 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 285:31]
node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_mem_ctl.scala 285:44]
node _T_155 = mux(_T_154, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 285:12]
node _T_156 = mux(io.exu_flush_final, _T_155, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 284:62]
node _T_157 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_156) @[el2_ifu_mem_ctl.scala 284:27]
miss_nxtstate <= _T_157 @[el2_ifu_mem_ctl.scala 284:21]
node _T_158 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 286:42]
node _T_159 = or(_T_158, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 286:55]
node _T_160 = or(_T_159, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 286:76]
miss_state_en <= _T_160 @[el2_ifu_mem_ctl.scala 286:21]
skip @[Conditional.scala 39:67]
node _T_161 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 289:61]
reg _T_162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_161 : @[Reg.scala 28:19]
_T_162 <= miss_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
miss_state <= _T_162 @[el2_ifu_mem_ctl.scala 289:14]
wire crit_byp_hit_f : UInt<1>
crit_byp_hit_f <= UInt<1>("h00")
wire way_status_mb_scnd_ff : UInt<1>
way_status_mb_scnd_ff <= UInt<1>("h00")
wire way_status : UInt<1>
way_status <= UInt<1>("h00")
wire tagv_mb_scnd_ff : UInt<2>
tagv_mb_scnd_ff <= UInt<1>("h00")
wire ic_tag_valid : UInt<2>
ic_tag_valid <= UInt<1>("h00")
wire uncacheable_miss_scnd_ff : UInt<1>
uncacheable_miss_scnd_ff <= UInt<1>("h00")
wire imb_scnd_ff : UInt<31>
imb_scnd_ff <= UInt<1>("h00")
wire reset_all_tags : UInt<1>
reset_all_tags <= UInt<1>("h00")
wire bus_rd_addr_count : UInt<3>
bus_rd_addr_count <= UInt<1>("h00")
wire ifu_bus_rid_ff : UInt<3>
ifu_bus_rid_ff <= UInt<1>("h00")
node _T_163 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 300:30]
miss_pending <= _T_163 @[el2_ifu_mem_ctl.scala 300:16]
node _T_164 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 301:39]
node _T_165 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 301:73]
node _T_166 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 301:95]
node _T_167 = and(_T_165, _T_166) @[el2_ifu_mem_ctl.scala 301:93]
node crit_wd_byp_ok_ff = or(_T_164, _T_167) @[el2_ifu_mem_ctl.scala 301:58]
node _T_168 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 302:57]
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:38]
node _T_170 = and(miss_pending, _T_169) @[el2_ifu_mem_ctl.scala 302:36]
node _T_171 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 302:86]
node _T_172 = and(_T_171, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 302:106]
node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:72]
node _T_174 = and(_T_170, _T_173) @[el2_ifu_mem_ctl.scala 302:70]
node _T_175 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 303:37]
node _T_176 = and(_T_175, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 303:57]
node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 303:23]
node _T_178 = and(_T_174, _T_177) @[el2_ifu_mem_ctl.scala 302:128]
node _T_179 = or(_T_178, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 303:77]
node _T_180 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 304:36]
node _T_181 = and(miss_pending, _T_180) @[el2_ifu_mem_ctl.scala 304:19]
node sel_hold_imb = or(_T_179, _T_181) @[el2_ifu_mem_ctl.scala 303:93]
node _T_182 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 306:40]
node _T_183 = or(_T_182, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 306:57]
node _T_184 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 306:83]
node sel_hold_imb_scnd = and(_T_183, _T_184) @[el2_ifu_mem_ctl.scala 306:81]
node _T_185 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 307:46]
node way_status_mb_scnd_in = mux(_T_185, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 307:34]
node _T_186 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 309:40]
node _T_187 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 309:96]
node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15]
node _T_189 = mux(_T_188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_190 = and(_T_189, ic_tag_valid) @[el2_ifu_mem_ctl.scala 309:113]
node tagv_mb_scnd_in = mux(_T_186, tagv_mb_scnd_ff, _T_190) @[el2_ifu_mem_ctl.scala 309:28]
node _T_191 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 310:56]
node uncacheable_miss_scnd_in = mux(_T_191, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 310:37]
reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:38]
_T_192 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 311:38]
uncacheable_miss_scnd_ff <= _T_192 @[el2_ifu_mem_ctl.scala 311:28]
node _T_193 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 312:43]
node imb_scnd_in = mux(_T_193, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 312:24]
reg _T_194 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 313:25]
_T_194 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 313:25]
imb_scnd_ff <= _T_194 @[el2_ifu_mem_ctl.scala 313:15]
reg _T_195 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 314:35]
_T_195 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 314:35]
way_status_mb_scnd_ff <= _T_195 @[el2_ifu_mem_ctl.scala 314:25]
reg _T_196 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 315:29]
_T_196 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 315:29]
tagv_mb_scnd_ff <= _T_196 @[el2_ifu_mem_ctl.scala 315:19]
node _T_197 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15]
node _T_198 = mux(_T_197, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_198) @[el2_ifu_mem_ctl.scala 318:45]
wire ifc_iccm_access_f : UInt<1>
ifc_iccm_access_f <= UInt<1>("h00")
wire ifc_region_acc_fault_final_f : UInt<1>
ifc_region_acc_fault_final_f <= UInt<1>("h00")
node _T_199 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:48]
node _T_200 = and(ifc_fetch_req_f, _T_199) @[el2_ifu_mem_ctl.scala 321:46]
node _T_201 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:69]
node fetch_req_icache_f = and(_T_200, _T_201) @[el2_ifu_mem_ctl.scala 321:67]
node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 322:46]
node _T_202 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:45]
node _T_203 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 323:73]
node _T_204 = or(_T_202, _T_203) @[el2_ifu_mem_ctl.scala 323:59]
node _T_205 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 323:105]
node _T_206 = or(_T_204, _T_205) @[el2_ifu_mem_ctl.scala 323:91]
node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_206) @[el2_ifu_mem_ctl.scala 323:41]
wire stream_hit_f : UInt<1>
stream_hit_f <= UInt<1>("h00")
node _T_207 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 325:35]
node _T_208 = and(_T_207, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 325:52]
node _T_209 = and(_T_208, miss_pending) @[el2_ifu_mem_ctl.scala 325:73]
ic_byp_hit_f <= _T_209 @[el2_ifu_mem_ctl.scala 325:16]
wire sel_mb_addr_ff : UInt<1>
sel_mb_addr_ff <= UInt<1>("h00")
wire imb_ff : UInt<31>
imb_ff <= UInt<1>("h00")
wire ifu_fetch_addr_int_f : UInt<31>
ifu_fetch_addr_int_f <= UInt<1>("h00")
node _T_210 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 329:35]
node _T_211 = and(_T_210, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 329:39]
node _T_212 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:62]
node _T_213 = and(_T_211, _T_212) @[el2_ifu_mem_ctl.scala 329:60]
node _T_214 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:81]
node _T_215 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 329:108]
node _T_216 = or(_T_214, _T_215) @[el2_ifu_mem_ctl.scala 329:95]
node _T_217 = and(_T_213, _T_216) @[el2_ifu_mem_ctl.scala 329:78]
node _T_218 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:128]
node ic_act_hit_f = and(_T_217, _T_218) @[el2_ifu_mem_ctl.scala 329:126]
node _T_219 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 330:37]
node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:23]
node _T_221 = or(_T_220, reset_all_tags) @[el2_ifu_mem_ctl.scala 330:41]
node _T_222 = and(_T_221, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 330:59]
node _T_223 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:82]
node _T_224 = and(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 330:80]
node _T_225 = or(_T_224, scnd_miss_req) @[el2_ifu_mem_ctl.scala 330:97]
node _T_226 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:116]
node _T_227 = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 330:114]
ic_act_miss_f <= _T_227 @[el2_ifu_mem_ctl.scala 330:17]
node _T_228 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 331:28]
node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 331:42]
node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 331:60]
node _T_231 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 331:94]
node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 331:81]
node _T_233 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 332:12]
node _T_234 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 332:63]
node _T_235 = neq(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 332:39]
node _T_236 = and(_T_232, _T_235) @[el2_ifu_mem_ctl.scala 331:111]
node _T_237 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:93]
node _T_238 = and(_T_236, _T_237) @[el2_ifu_mem_ctl.scala 332:91]
node _T_239 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:116]
node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 332:114]
node _T_241 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:134]
node _T_242 = and(_T_240, _T_241) @[el2_ifu_mem_ctl.scala 332:132]
ic_miss_under_miss_f <= _T_242 @[el2_ifu_mem_ctl.scala 331:24]
node _T_243 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 333:42]
node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 333:28]
node _T_245 = or(_T_244, reset_all_tags) @[el2_ifu_mem_ctl.scala 333:46]
node _T_246 = and(_T_245, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 333:64]
node _T_247 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 333:99]
node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 333:85]
node _T_249 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 334:13]
node _T_250 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 334:62]
node _T_251 = eq(_T_249, _T_250) @[el2_ifu_mem_ctl.scala 334:39]
node _T_252 = or(_T_251, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 334:91]
node _T_253 = and(_T_248, _T_252) @[el2_ifu_mem_ctl.scala 333:117]
ic_ignore_2nd_miss_f <= _T_253 @[el2_ifu_mem_ctl.scala 333:24]
node _T_254 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 336:31]
node _T_255 = or(_T_254, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 336:46]
node _T_256 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 336:94]
node _T_257 = or(_T_255, _T_256) @[el2_ifu_mem_ctl.scala 336:62]
io.ic_hit_f <= _T_257 @[el2_ifu_mem_ctl.scala 336:15]
node _T_258 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 337:47]
node _T_259 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 337:98]
node _T_260 = mux(_T_259, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 337:84]
node uncacheable_miss_in = mux(_T_258, uncacheable_miss_scnd_ff, _T_260) @[el2_ifu_mem_ctl.scala 337:32]
node _T_261 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 338:34]
node _T_262 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 338:72]
node _T_263 = mux(_T_262, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 338:58]
node imb_in = mux(_T_261, imb_scnd_ff, _T_263) @[el2_ifu_mem_ctl.scala 338:19]
wire ifu_wr_cumulative_err_data : UInt<1>
ifu_wr_cumulative_err_data <= UInt<1>("h00")
node _T_264 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 340:38]
node _T_265 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 340:89]
node _T_266 = eq(_T_264, _T_265) @[el2_ifu_mem_ctl.scala 340:75]
node _T_267 = and(_T_266, scnd_miss_req) @[el2_ifu_mem_ctl.scala 340:127]
node _T_268 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 340:145]
node scnd_miss_index_match = and(_T_267, _T_268) @[el2_ifu_mem_ctl.scala 340:143]
wire way_status_mb_ff : UInt<1>
way_status_mb_ff <= UInt<1>("h00")
wire way_status_rep_new : UInt<1>
way_status_rep_new <= UInt<1>("h00")
node _T_269 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 343:47]
node _T_270 = and(scnd_miss_req, _T_269) @[el2_ifu_mem_ctl.scala 343:45]
node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_mem_ctl.scala 343:71]
node _T_272 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 344:26]
node _T_273 = bits(_T_272, 0, 0) @[el2_ifu_mem_ctl.scala 344:52]
node _T_274 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 345:26]
node _T_275 = mux(_T_274, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 345:12]
node _T_276 = mux(_T_273, way_status_rep_new, _T_275) @[el2_ifu_mem_ctl.scala 344:10]
node way_status_mb_in = mux(_T_271, way_status_mb_scnd_ff, _T_276) @[el2_ifu_mem_ctl.scala 343:29]
wire replace_way_mb_any : UInt<2>
replace_way_mb_any <= UInt<1>("h00")
wire tagv_mb_ff : UInt<2>
tagv_mb_ff <= UInt<1>("h00")
node _T_277 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 348:38]
node _T_278 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15]
node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_280 = and(_T_279, replace_way_mb_any) @[el2_ifu_mem_ctl.scala 348:110]
node _T_281 = or(tagv_mb_scnd_ff, _T_280) @[el2_ifu_mem_ctl.scala 348:62]
node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 349:20]
node _T_283 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 349:77]
node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15]
node _T_285 = mux(_T_284, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_286 = and(ic_tag_valid, _T_285) @[el2_ifu_mem_ctl.scala 349:53]
node _T_287 = mux(_T_282, tagv_mb_ff, _T_286) @[el2_ifu_mem_ctl.scala 349:6]
node tagv_mb_in = mux(_T_277, _T_281, _T_287) @[el2_ifu_mem_ctl.scala 348:23]
wire scnd_miss_req_q : UInt<1>
scnd_miss_req_q <= UInt<1>("h00")
wire reset_ic_ff : UInt<1>
reset_ic_ff <= UInt<1>("h00")
node _T_288 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 352:36]
node _T_289 = and(miss_pending, _T_288) @[el2_ifu_mem_ctl.scala 352:34]
node _T_290 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 352:72]
node reset_ic_in = and(_T_289, _T_290) @[el2_ifu_mem_ctl.scala 352:53]
reg _T_291 : UInt, clock @[el2_ifu_mem_ctl.scala 353:25]
_T_291 <= reset_ic_in @[el2_ifu_mem_ctl.scala 353:25]
reset_ic_ff <= _T_291 @[el2_ifu_mem_ctl.scala 353:15]
reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 354:37]
fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 354:37]
reg _T_292 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 355:34]
_T_292 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 355:34]
ifu_fetch_addr_int_f <= _T_292 @[el2_ifu_mem_ctl.scala 355:24]
reg _T_293 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 357:33]
_T_293 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 357:33]
uncacheable_miss_ff <= _T_293 @[el2_ifu_mem_ctl.scala 357:23]
reg _T_294 : UInt, clock @[el2_ifu_mem_ctl.scala 358:20]
_T_294 <= imb_in @[el2_ifu_mem_ctl.scala 358:20]
imb_ff <= _T_294 @[el2_ifu_mem_ctl.scala 358:10]
wire miss_addr : UInt<26>
miss_addr <= UInt<1>("h00")
node _T_295 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 360:26]
node _T_296 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 360:47]
node _T_297 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 361:25]
node _T_298 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 361:44]
node _T_299 = mux(_T_297, _T_298, miss_addr) @[el2_ifu_mem_ctl.scala 361:8]
node miss_addr_in = mux(_T_295, _T_296, _T_299) @[el2_ifu_mem_ctl.scala 360:25]
reg _T_300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 362:23]
_T_300 <= miss_addr_in @[el2_ifu_mem_ctl.scala 362:23]
miss_addr <= _T_300 @[el2_ifu_mem_ctl.scala 362:13]
reg _T_301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 363:30]
_T_301 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 363:30]
way_status_mb_ff <= _T_301 @[el2_ifu_mem_ctl.scala 363:20]
reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 364:24]
_T_302 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 364:24]
tagv_mb_ff <= _T_302 @[el2_ifu_mem_ctl.scala 364:14]
wire stream_miss_f : UInt<1>
stream_miss_f <= UInt<1>("h00")
node _T_303 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 366:68]
node _T_304 = and(_T_303, flush_final_f) @[el2_ifu_mem_ctl.scala 366:87]
node _T_305 = eq(_T_304, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:55]
node _T_306 = and(io.ifc_fetch_req_bf, _T_305) @[el2_ifu_mem_ctl.scala 366:53]
node _T_307 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:106]
node ifc_fetch_req_qual_bf = and(_T_306, _T_307) @[el2_ifu_mem_ctl.scala 366:104]
reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 367:36]
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 367:36]
node _T_308 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 368:44]
node _T_309 = and(ifc_fetch_req_f_raw, _T_308) @[el2_ifu_mem_ctl.scala 368:42]
ifc_fetch_req_f <= _T_309 @[el2_ifu_mem_ctl.scala 368:19]
reg _T_310 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 369:31]
_T_310 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 369:31]
ifc_iccm_access_f <= _T_310 @[el2_ifu_mem_ctl.scala 369:21]
wire ifc_region_acc_fault_final_bf : UInt<1>
ifc_region_acc_fault_final_bf <= UInt<1>("h00")
reg _T_311 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 371:42]
_T_311 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 371:42]
ifc_region_acc_fault_final_f <= _T_311 @[el2_ifu_mem_ctl.scala 371:32]
reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 372:39]
ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 372:39]
node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58]
node _T_312 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 374:38]
node _T_313 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 374:68]
node _T_314 = or(_T_312, _T_313) @[el2_ifu_mem_ctl.scala 374:55]
node _T_315 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 374:103]
node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 374:84]
node _T_317 = and(_T_314, _T_316) @[el2_ifu_mem_ctl.scala 374:82]
node _T_318 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 374:119]
node ifu_ic_mb_empty = or(_T_317, _T_318) @[el2_ifu_mem_ctl.scala 374:117]
node ifu_miss_state_idle = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 375:40]
wire write_ic_16_bytes : UInt<1>
write_ic_16_bytes <= UInt<1>("h00")
wire reset_tag_valid_for_miss : UInt<1>
reset_tag_valid_for_miss <= UInt<1>("h00")
node _T_319 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 378:35]
node _T_320 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 378:57]
node _T_321 = and(_T_319, _T_320) @[el2_ifu_mem_ctl.scala 378:55]
node sel_mb_addr = or(_T_321, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 378:79]
node _T_322 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 379:50]
node _T_323 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 379:68]
node _T_324 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 379:124]
node _T_325 = cat(_T_323, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
node _T_326 = cat(_T_325, _T_324) @[Cat.scala 29:58]
node _T_327 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 380:50]
node _T_328 = eq(_T_327, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 380:37]
node _T_329 = mux(_T_322, _T_326, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_330 = mux(_T_328, ifu_fetch_addr_int_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_331 = or(_T_329, _T_330) @[Mux.scala 27:72]
wire ic_rw_addr : UInt<31> @[Mux.scala 27:72]
ic_rw_addr <= _T_331 @[Mux.scala 27:72]
IMC 80%
2020-10-19 13:10:40 +08:00
wire bus_ifu_wr_en_ff_q : UInt<1>
bus_ifu_wr_en_ff_q <= UInt<1>("h00")
node _T_332 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 382:41]
node _T_333 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 382:63]
node _T_334 = and(_T_332, _T_333) @[el2_ifu_mem_ctl.scala 382:61]
node _T_335 = and(_T_334, last_beat) @[el2_ifu_mem_ctl.scala 382:84]
node sel_mb_status_addr = and(_T_335, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 382:96]
node _T_336 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 383:62]
node _T_337 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 383:116]
node _T_338 = cat(_T_336, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
node _T_339 = cat(_T_338, _T_337) @[Cat.scala 29:58]
node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_339, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 383:31]
reg _T_340 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 385:51]
_T_340 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 385:51]
sel_mb_addr_ff <= _T_340 @[el2_ifu_mem_ctl.scala 385:18]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ifu_bus_rdata_ff : UInt<64>
ifu_bus_rdata_ff <= UInt<1>("h00")
wire ic_miss_buff_half : UInt<64>
ic_miss_buff_half <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
wire _T_341 : UInt<1>[35] @[el2_lib.scala 322:18]
wire _T_342 : UInt<1>[35] @[el2_lib.scala 323:18]
wire _T_343 : UInt<1>[35] @[el2_lib.scala 324:18]
wire _T_344 : UInt<1>[31] @[el2_lib.scala 325:18]
wire _T_345 : UInt<1>[31] @[el2_lib.scala 326:18]
wire _T_346 : UInt<1>[31] @[el2_lib.scala 327:18]
wire _T_347 : UInt<1>[7] @[el2_lib.scala 328:18]
node _T_348 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 335:36]
_T_341[0] <= _T_348 @[el2_lib.scala 335:30]
node _T_349 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 336:36]
_T_342[0] <= _T_349 @[el2_lib.scala 336:30]
node _T_350 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 335:36]
_T_341[1] <= _T_350 @[el2_lib.scala 335:30]
node _T_351 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 337:36]
_T_343[0] <= _T_351 @[el2_lib.scala 337:30]
node _T_352 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 336:36]
_T_342[1] <= _T_352 @[el2_lib.scala 336:30]
node _T_353 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 337:36]
_T_343[1] <= _T_353 @[el2_lib.scala 337:30]
node _T_354 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 335:36]
_T_341[2] <= _T_354 @[el2_lib.scala 335:30]
node _T_355 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 336:36]
_T_342[2] <= _T_355 @[el2_lib.scala 336:30]
node _T_356 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 337:36]
_T_343[2] <= _T_356 @[el2_lib.scala 337:30]
node _T_357 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 335:36]
_T_341[3] <= _T_357 @[el2_lib.scala 335:30]
node _T_358 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 338:36]
_T_344[0] <= _T_358 @[el2_lib.scala 338:30]
node _T_359 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 336:36]
_T_342[3] <= _T_359 @[el2_lib.scala 336:30]
node _T_360 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 338:36]
_T_344[1] <= _T_360 @[el2_lib.scala 338:30]
node _T_361 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 335:36]
_T_341[4] <= _T_361 @[el2_lib.scala 335:30]
node _T_362 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 336:36]
_T_342[4] <= _T_362 @[el2_lib.scala 336:30]
node _T_363 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 338:36]
_T_344[2] <= _T_363 @[el2_lib.scala 338:30]
node _T_364 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 337:36]
_T_343[3] <= _T_364 @[el2_lib.scala 337:30]
node _T_365 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 338:36]
_T_344[3] <= _T_365 @[el2_lib.scala 338:30]
node _T_366 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 335:36]
_T_341[5] <= _T_366 @[el2_lib.scala 335:30]
node _T_367 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 337:36]
_T_343[4] <= _T_367 @[el2_lib.scala 337:30]
node _T_368 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 338:36]
_T_344[4] <= _T_368 @[el2_lib.scala 338:30]
node _T_369 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 336:36]
_T_342[5] <= _T_369 @[el2_lib.scala 336:30]
node _T_370 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 337:36]
_T_343[5] <= _T_370 @[el2_lib.scala 337:30]
node _T_371 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 338:36]
_T_344[5] <= _T_371 @[el2_lib.scala 338:30]
node _T_372 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 335:36]
_T_341[6] <= _T_372 @[el2_lib.scala 335:30]
node _T_373 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 336:36]
_T_342[6] <= _T_373 @[el2_lib.scala 336:30]
node _T_374 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 337:36]
_T_343[6] <= _T_374 @[el2_lib.scala 337:30]
node _T_375 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 338:36]
_T_344[6] <= _T_375 @[el2_lib.scala 338:30]
node _T_376 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 335:36]
_T_341[7] <= _T_376 @[el2_lib.scala 335:30]
node _T_377 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 339:36]
_T_345[0] <= _T_377 @[el2_lib.scala 339:30]
node _T_378 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 336:36]
_T_342[7] <= _T_378 @[el2_lib.scala 336:30]
node _T_379 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 339:36]
_T_345[1] <= _T_379 @[el2_lib.scala 339:30]
node _T_380 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 335:36]
_T_341[8] <= _T_380 @[el2_lib.scala 335:30]
node _T_381 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 336:36]
_T_342[8] <= _T_381 @[el2_lib.scala 336:30]
node _T_382 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 339:36]
_T_345[2] <= _T_382 @[el2_lib.scala 339:30]
node _T_383 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 337:36]
_T_343[7] <= _T_383 @[el2_lib.scala 337:30]
node _T_384 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 339:36]
_T_345[3] <= _T_384 @[el2_lib.scala 339:30]
node _T_385 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 335:36]
_T_341[9] <= _T_385 @[el2_lib.scala 335:30]
node _T_386 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 337:36]
_T_343[8] <= _T_386 @[el2_lib.scala 337:30]
node _T_387 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 339:36]
_T_345[4] <= _T_387 @[el2_lib.scala 339:30]
node _T_388 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 336:36]
_T_342[9] <= _T_388 @[el2_lib.scala 336:30]
node _T_389 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 337:36]
_T_343[9] <= _T_389 @[el2_lib.scala 337:30]
node _T_390 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 339:36]
_T_345[5] <= _T_390 @[el2_lib.scala 339:30]
node _T_391 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 335:36]
_T_341[10] <= _T_391 @[el2_lib.scala 335:30]
node _T_392 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 336:36]
_T_342[10] <= _T_392 @[el2_lib.scala 336:30]
node _T_393 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 337:36]
_T_343[10] <= _T_393 @[el2_lib.scala 337:30]
node _T_394 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 339:36]
_T_345[6] <= _T_394 @[el2_lib.scala 339:30]
node _T_395 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 338:36]
_T_344[7] <= _T_395 @[el2_lib.scala 338:30]
node _T_396 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 339:36]
_T_345[7] <= _T_396 @[el2_lib.scala 339:30]
node _T_397 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 335:36]
_T_341[11] <= _T_397 @[el2_lib.scala 335:30]
node _T_398 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 338:36]
_T_344[8] <= _T_398 @[el2_lib.scala 338:30]
node _T_399 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 339:36]
_T_345[8] <= _T_399 @[el2_lib.scala 339:30]
node _T_400 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 336:36]
_T_342[11] <= _T_400 @[el2_lib.scala 336:30]
node _T_401 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 338:36]
_T_344[9] <= _T_401 @[el2_lib.scala 338:30]
node _T_402 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 339:36]
_T_345[9] <= _T_402 @[el2_lib.scala 339:30]
node _T_403 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 335:36]
_T_341[12] <= _T_403 @[el2_lib.scala 335:30]
node _T_404 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 336:36]
_T_342[12] <= _T_404 @[el2_lib.scala 336:30]
node _T_405 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 338:36]
_T_344[10] <= _T_405 @[el2_lib.scala 338:30]
node _T_406 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 339:36]
_T_345[10] <= _T_406 @[el2_lib.scala 339:30]
node _T_407 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 337:36]
_T_343[11] <= _T_407 @[el2_lib.scala 337:30]
node _T_408 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 338:36]
_T_344[11] <= _T_408 @[el2_lib.scala 338:30]
node _T_409 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 339:36]
_T_345[11] <= _T_409 @[el2_lib.scala 339:30]
node _T_410 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 335:36]
_T_341[13] <= _T_410 @[el2_lib.scala 335:30]
node _T_411 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 337:36]
_T_343[12] <= _T_411 @[el2_lib.scala 337:30]
node _T_412 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 338:36]
_T_344[12] <= _T_412 @[el2_lib.scala 338:30]
node _T_413 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 339:36]
_T_345[12] <= _T_413 @[el2_lib.scala 339:30]
node _T_414 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 336:36]
_T_342[13] <= _T_414 @[el2_lib.scala 336:30]
node _T_415 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 337:36]
_T_343[13] <= _T_415 @[el2_lib.scala 337:30]
node _T_416 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 338:36]
_T_344[13] <= _T_416 @[el2_lib.scala 338:30]
node _T_417 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 339:36]
_T_345[13] <= _T_417 @[el2_lib.scala 339:30]
node _T_418 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 335:36]
_T_341[14] <= _T_418 @[el2_lib.scala 335:30]
node _T_419 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 336:36]
_T_342[14] <= _T_419 @[el2_lib.scala 336:30]
node _T_420 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 337:36]
_T_343[14] <= _T_420 @[el2_lib.scala 337:30]
node _T_421 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 338:36]
_T_344[14] <= _T_421 @[el2_lib.scala 338:30]
node _T_422 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 339:36]
_T_345[14] <= _T_422 @[el2_lib.scala 339:30]
node _T_423 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 335:36]
_T_341[15] <= _T_423 @[el2_lib.scala 335:30]
node _T_424 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 340:36]
_T_346[0] <= _T_424 @[el2_lib.scala 340:30]
node _T_425 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 336:36]
_T_342[15] <= _T_425 @[el2_lib.scala 336:30]
node _T_426 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 340:36]
_T_346[1] <= _T_426 @[el2_lib.scala 340:30]
node _T_427 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 335:36]
_T_341[16] <= _T_427 @[el2_lib.scala 335:30]
node _T_428 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 336:36]
_T_342[16] <= _T_428 @[el2_lib.scala 336:30]
node _T_429 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 340:36]
_T_346[2] <= _T_429 @[el2_lib.scala 340:30]
node _T_430 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 337:36]
_T_343[15] <= _T_430 @[el2_lib.scala 337:30]
node _T_431 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 340:36]
_T_346[3] <= _T_431 @[el2_lib.scala 340:30]
node _T_432 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 335:36]
_T_341[17] <= _T_432 @[el2_lib.scala 335:30]
node _T_433 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 337:36]
_T_343[16] <= _T_433 @[el2_lib.scala 337:30]
node _T_434 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 340:36]
_T_346[4] <= _T_434 @[el2_lib.scala 340:30]
node _T_435 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 336:36]
_T_342[17] <= _T_435 @[el2_lib.scala 336:30]
node _T_436 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 337:36]
_T_343[17] <= _T_436 @[el2_lib.scala 337:30]
node _T_437 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 340:36]
_T_346[5] <= _T_437 @[el2_lib.scala 340:30]
node _T_438 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 335:36]
_T_341[18] <= _T_438 @[el2_lib.scala 335:30]
node _T_439 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 336:36]
_T_342[18] <= _T_439 @[el2_lib.scala 336:30]
node _T_440 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 337:36]
_T_343[18] <= _T_440 @[el2_lib.scala 337:30]
node _T_441 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 340:36]
_T_346[6] <= _T_441 @[el2_lib.scala 340:30]
node _T_442 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 338:36]
_T_344[15] <= _T_442 @[el2_lib.scala 338:30]
node _T_443 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 340:36]
_T_346[7] <= _T_443 @[el2_lib.scala 340:30]
node _T_444 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 335:36]
_T_341[19] <= _T_444 @[el2_lib.scala 335:30]
node _T_445 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 338:36]
_T_344[16] <= _T_445 @[el2_lib.scala 338:30]
node _T_446 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 340:36]
_T_346[8] <= _T_446 @[el2_lib.scala 340:30]
node _T_447 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 336:36]
_T_342[19] <= _T_447 @[el2_lib.scala 336:30]
node _T_448 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 338:36]
_T_344[17] <= _T_448 @[el2_lib.scala 338:30]
node _T_449 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 340:36]
_T_346[9] <= _T_449 @[el2_lib.scala 340:30]
node _T_450 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 335:36]
_T_341[20] <= _T_450 @[el2_lib.scala 335:30]
node _T_451 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 336:36]
_T_342[20] <= _T_451 @[el2_lib.scala 336:30]
node _T_452 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 338:36]
_T_344[18] <= _T_452 @[el2_lib.scala 338:30]
node _T_453 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 340:36]
_T_346[10] <= _T_453 @[el2_lib.scala 340:30]
node _T_454 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 337:36]
_T_343[19] <= _T_454 @[el2_lib.scala 337:30]
node _T_455 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 338:36]
_T_344[19] <= _T_455 @[el2_lib.scala 338:30]
node _T_456 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 340:36]
_T_346[11] <= _T_456 @[el2_lib.scala 340:30]
node _T_457 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 335:36]
_T_341[21] <= _T_457 @[el2_lib.scala 335:30]
node _T_458 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 337:36]
_T_343[20] <= _T_458 @[el2_lib.scala 337:30]
node _T_459 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 338:36]
_T_344[20] <= _T_459 @[el2_lib.scala 338:30]
node _T_460 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 340:36]
_T_346[12] <= _T_460 @[el2_lib.scala 340:30]
node _T_461 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 336:36]
_T_342[21] <= _T_461 @[el2_lib.scala 336:30]
node _T_462 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 337:36]
_T_343[21] <= _T_462 @[el2_lib.scala 337:30]
node _T_463 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 338:36]
_T_344[21] <= _T_463 @[el2_lib.scala 338:30]
node _T_464 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 340:36]
_T_346[13] <= _T_464 @[el2_lib.scala 340:30]
node _T_465 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 335:36]
_T_341[22] <= _T_465 @[el2_lib.scala 335:30]
node _T_466 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 336:36]
_T_342[22] <= _T_466 @[el2_lib.scala 336:30]
node _T_467 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 337:36]
_T_343[22] <= _T_467 @[el2_lib.scala 337:30]
node _T_468 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 338:36]
_T_344[22] <= _T_468 @[el2_lib.scala 338:30]
node _T_469 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 340:36]
_T_346[14] <= _T_469 @[el2_lib.scala 340:30]
node _T_470 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 339:36]
_T_345[15] <= _T_470 @[el2_lib.scala 339:30]
node _T_471 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 340:36]
_T_346[15] <= _T_471 @[el2_lib.scala 340:30]
node _T_472 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 335:36]
_T_341[23] <= _T_472 @[el2_lib.scala 335:30]
node _T_473 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 339:36]
_T_345[16] <= _T_473 @[el2_lib.scala 339:30]
node _T_474 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 340:36]
_T_346[16] <= _T_474 @[el2_lib.scala 340:30]
node _T_475 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 336:36]
_T_342[23] <= _T_475 @[el2_lib.scala 336:30]
node _T_476 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 339:36]
_T_345[17] <= _T_476 @[el2_lib.scala 339:30]
node _T_477 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 340:36]
_T_346[17] <= _T_477 @[el2_lib.scala 340:30]
node _T_478 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 335:36]
_T_341[24] <= _T_478 @[el2_lib.scala 335:30]
node _T_479 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 336:36]
_T_342[24] <= _T_479 @[el2_lib.scala 336:30]
node _T_480 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 339:36]
_T_345[18] <= _T_480 @[el2_lib.scala 339:30]
node _T_481 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 340:36]
_T_346[18] <= _T_481 @[el2_lib.scala 340:30]
node _T_482 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 337:36]
_T_343[23] <= _T_482 @[el2_lib.scala 337:30]
node _T_483 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 339:36]
_T_345[19] <= _T_483 @[el2_lib.scala 339:30]
node _T_484 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 340:36]
_T_346[19] <= _T_484 @[el2_lib.scala 340:30]
node _T_485 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 335:36]
_T_341[25] <= _T_485 @[el2_lib.scala 335:30]
node _T_486 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 337:36]
_T_343[24] <= _T_486 @[el2_lib.scala 337:30]
node _T_487 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 339:36]
_T_345[20] <= _T_487 @[el2_lib.scala 339:30]
node _T_488 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 340:36]
_T_346[20] <= _T_488 @[el2_lib.scala 340:30]
node _T_489 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 336:36]
_T_342[25] <= _T_489 @[el2_lib.scala 336:30]
node _T_490 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 337:36]
_T_343[25] <= _T_490 @[el2_lib.scala 337:30]
node _T_491 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 339:36]
_T_345[21] <= _T_491 @[el2_lib.scala 339:30]
node _T_492 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 340:36]
_T_346[21] <= _T_492 @[el2_lib.scala 340:30]
node _T_493 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 335:36]
_T_341[26] <= _T_493 @[el2_lib.scala 335:30]
node _T_494 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 336:36]
_T_342[26] <= _T_494 @[el2_lib.scala 336:30]
node _T_495 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 337:36]
_T_343[26] <= _T_495 @[el2_lib.scala 337:30]
node _T_496 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 339:36]
_T_345[22] <= _T_496 @[el2_lib.scala 339:30]
node _T_497 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 340:36]
_T_346[22] <= _T_497 @[el2_lib.scala 340:30]
node _T_498 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 338:36]
_T_344[23] <= _T_498 @[el2_lib.scala 338:30]
node _T_499 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 339:36]
_T_345[23] <= _T_499 @[el2_lib.scala 339:30]
node _T_500 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 340:36]
_T_346[23] <= _T_500 @[el2_lib.scala 340:30]
node _T_501 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 335:36]
_T_341[27] <= _T_501 @[el2_lib.scala 335:30]
node _T_502 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 338:36]
_T_344[24] <= _T_502 @[el2_lib.scala 338:30]
node _T_503 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 339:36]
_T_345[24] <= _T_503 @[el2_lib.scala 339:30]
node _T_504 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 340:36]
_T_346[24] <= _T_504 @[el2_lib.scala 340:30]
node _T_505 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 336:36]
_T_342[27] <= _T_505 @[el2_lib.scala 336:30]
node _T_506 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 338:36]
_T_344[25] <= _T_506 @[el2_lib.scala 338:30]
node _T_507 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 339:36]
_T_345[25] <= _T_507 @[el2_lib.scala 339:30]
node _T_508 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 340:36]
_T_346[25] <= _T_508 @[el2_lib.scala 340:30]
node _T_509 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 335:36]
_T_341[28] <= _T_509 @[el2_lib.scala 335:30]
node _T_510 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 336:36]
_T_342[28] <= _T_510 @[el2_lib.scala 336:30]
node _T_511 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 338:36]
_T_344[26] <= _T_511 @[el2_lib.scala 338:30]
node _T_512 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 339:36]
_T_345[26] <= _T_512 @[el2_lib.scala 339:30]
node _T_513 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 340:36]
_T_346[26] <= _T_513 @[el2_lib.scala 340:30]
node _T_514 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 337:36]
_T_343[27] <= _T_514 @[el2_lib.scala 337:30]
node _T_515 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 338:36]
_T_344[27] <= _T_515 @[el2_lib.scala 338:30]
node _T_516 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 339:36]
_T_345[27] <= _T_516 @[el2_lib.scala 339:30]
node _T_517 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 340:36]
_T_346[27] <= _T_517 @[el2_lib.scala 340:30]
node _T_518 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 335:36]
_T_341[29] <= _T_518 @[el2_lib.scala 335:30]
node _T_519 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 337:36]
_T_343[28] <= _T_519 @[el2_lib.scala 337:30]
node _T_520 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 338:36]
_T_344[28] <= _T_520 @[el2_lib.scala 338:30]
node _T_521 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 339:36]
_T_345[28] <= _T_521 @[el2_lib.scala 339:30]
node _T_522 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 340:36]
_T_346[28] <= _T_522 @[el2_lib.scala 340:30]
node _T_523 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 336:36]
_T_342[29] <= _T_523 @[el2_lib.scala 336:30]
node _T_524 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 337:36]
_T_343[29] <= _T_524 @[el2_lib.scala 337:30]
node _T_525 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 338:36]
_T_344[29] <= _T_525 @[el2_lib.scala 338:30]
node _T_526 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 339:36]
_T_345[29] <= _T_526 @[el2_lib.scala 339:30]
node _T_527 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 340:36]
_T_346[29] <= _T_527 @[el2_lib.scala 340:30]
node _T_528 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 335:36]
_T_341[30] <= _T_528 @[el2_lib.scala 335:30]
node _T_529 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 336:36]
_T_342[30] <= _T_529 @[el2_lib.scala 336:30]
node _T_530 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 337:36]
_T_343[30] <= _T_530 @[el2_lib.scala 337:30]
node _T_531 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 338:36]
_T_344[30] <= _T_531 @[el2_lib.scala 338:30]
node _T_532 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 339:36]
_T_345[30] <= _T_532 @[el2_lib.scala 339:30]
node _T_533 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 340:36]
_T_346[30] <= _T_533 @[el2_lib.scala 340:30]
node _T_534 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 335:36]
_T_341[31] <= _T_534 @[el2_lib.scala 335:30]
node _T_535 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 341:36]
_T_347[0] <= _T_535 @[el2_lib.scala 341:30]
node _T_536 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 336:36]
_T_342[31] <= _T_536 @[el2_lib.scala 336:30]
node _T_537 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 341:36]
_T_347[1] <= _T_537 @[el2_lib.scala 341:30]
node _T_538 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 335:36]
_T_341[32] <= _T_538 @[el2_lib.scala 335:30]
node _T_539 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 336:36]
_T_342[32] <= _T_539 @[el2_lib.scala 336:30]
node _T_540 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 341:36]
_T_347[2] <= _T_540 @[el2_lib.scala 341:30]
node _T_541 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 337:36]
_T_343[31] <= _T_541 @[el2_lib.scala 337:30]
node _T_542 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 341:36]
_T_347[3] <= _T_542 @[el2_lib.scala 341:30]
node _T_543 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 335:36]
_T_341[33] <= _T_543 @[el2_lib.scala 335:30]
node _T_544 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 337:36]
_T_343[32] <= _T_544 @[el2_lib.scala 337:30]
node _T_545 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 341:36]
_T_347[4] <= _T_545 @[el2_lib.scala 341:30]
node _T_546 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 336:36]
_T_342[33] <= _T_546 @[el2_lib.scala 336:30]
node _T_547 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 337:36]
_T_343[33] <= _T_547 @[el2_lib.scala 337:30]
node _T_548 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 341:36]
_T_347[5] <= _T_548 @[el2_lib.scala 341:30]
node _T_549 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 335:36]
_T_341[34] <= _T_549 @[el2_lib.scala 335:30]
node _T_550 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 336:36]
_T_342[34] <= _T_550 @[el2_lib.scala 336:30]
node _T_551 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 337:36]
_T_343[34] <= _T_551 @[el2_lib.scala 337:30]
node _T_552 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 341:36]
_T_347[6] <= _T_552 @[el2_lib.scala 341:30]
node _T_553 = cat(_T_341[1], _T_341[0]) @[el2_lib.scala 343:27]
node _T_554 = cat(_T_341[3], _T_341[2]) @[el2_lib.scala 343:27]
node _T_555 = cat(_T_554, _T_553) @[el2_lib.scala 343:27]
node _T_556 = cat(_T_341[5], _T_341[4]) @[el2_lib.scala 343:27]
node _T_557 = cat(_T_341[7], _T_341[6]) @[el2_lib.scala 343:27]
node _T_558 = cat(_T_557, _T_556) @[el2_lib.scala 343:27]
node _T_559 = cat(_T_558, _T_555) @[el2_lib.scala 343:27]
node _T_560 = cat(_T_341[9], _T_341[8]) @[el2_lib.scala 343:27]
node _T_561 = cat(_T_341[11], _T_341[10]) @[el2_lib.scala 343:27]
node _T_562 = cat(_T_561, _T_560) @[el2_lib.scala 343:27]
node _T_563 = cat(_T_341[13], _T_341[12]) @[el2_lib.scala 343:27]
node _T_564 = cat(_T_341[16], _T_341[15]) @[el2_lib.scala 343:27]
node _T_565 = cat(_T_564, _T_341[14]) @[el2_lib.scala 343:27]
node _T_566 = cat(_T_565, _T_563) @[el2_lib.scala 343:27]
node _T_567 = cat(_T_566, _T_562) @[el2_lib.scala 343:27]
node _T_568 = cat(_T_567, _T_559) @[el2_lib.scala 343:27]
node _T_569 = cat(_T_341[18], _T_341[17]) @[el2_lib.scala 343:27]
node _T_570 = cat(_T_341[20], _T_341[19]) @[el2_lib.scala 343:27]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_571 = cat(_T_570, _T_569) @[el2_lib.scala 343:27]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_572 = cat(_T_341[22], _T_341[21]) @[el2_lib.scala 343:27]
node _T_573 = cat(_T_341[25], _T_341[24]) @[el2_lib.scala 343:27]
node _T_574 = cat(_T_573, _T_341[23]) @[el2_lib.scala 343:27]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_575 = cat(_T_574, _T_572) @[el2_lib.scala 343:27]
node _T_576 = cat(_T_575, _T_571) @[el2_lib.scala 343:27]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_577 = cat(_T_341[27], _T_341[26]) @[el2_lib.scala 343:27]
node _T_578 = cat(_T_341[29], _T_341[28]) @[el2_lib.scala 343:27]
node _T_579 = cat(_T_578, _T_577) @[el2_lib.scala 343:27]
node _T_580 = cat(_T_341[31], _T_341[30]) @[el2_lib.scala 343:27]
node _T_581 = cat(_T_341[34], _T_341[33]) @[el2_lib.scala 343:27]
node _T_582 = cat(_T_581, _T_341[32]) @[el2_lib.scala 343:27]
node _T_583 = cat(_T_582, _T_580) @[el2_lib.scala 343:27]
node _T_584 = cat(_T_583, _T_579) @[el2_lib.scala 343:27]
node _T_585 = cat(_T_584, _T_576) @[el2_lib.scala 343:27]
node _T_586 = cat(_T_585, _T_568) @[el2_lib.scala 343:27]
node _T_587 = xorr(_T_586) @[el2_lib.scala 343:34]
node _T_588 = cat(_T_342[1], _T_342[0]) @[el2_lib.scala 343:44]
node _T_589 = cat(_T_342[3], _T_342[2]) @[el2_lib.scala 343:44]
node _T_590 = cat(_T_589, _T_588) @[el2_lib.scala 343:44]
node _T_591 = cat(_T_342[5], _T_342[4]) @[el2_lib.scala 343:44]
node _T_592 = cat(_T_342[7], _T_342[6]) @[el2_lib.scala 343:44]
node _T_593 = cat(_T_592, _T_591) @[el2_lib.scala 343:44]
node _T_594 = cat(_T_593, _T_590) @[el2_lib.scala 343:44]
node _T_595 = cat(_T_342[9], _T_342[8]) @[el2_lib.scala 343:44]
node _T_596 = cat(_T_342[11], _T_342[10]) @[el2_lib.scala 343:44]
node _T_597 = cat(_T_596, _T_595) @[el2_lib.scala 343:44]
node _T_598 = cat(_T_342[13], _T_342[12]) @[el2_lib.scala 343:44]
node _T_599 = cat(_T_342[16], _T_342[15]) @[el2_lib.scala 343:44]
node _T_600 = cat(_T_599, _T_342[14]) @[el2_lib.scala 343:44]
node _T_601 = cat(_T_600, _T_598) @[el2_lib.scala 343:44]
node _T_602 = cat(_T_601, _T_597) @[el2_lib.scala 343:44]
node _T_603 = cat(_T_602, _T_594) @[el2_lib.scala 343:44]
node _T_604 = cat(_T_342[18], _T_342[17]) @[el2_lib.scala 343:44]
node _T_605 = cat(_T_342[20], _T_342[19]) @[el2_lib.scala 343:44]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_606 = cat(_T_605, _T_604) @[el2_lib.scala 343:44]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_607 = cat(_T_342[22], _T_342[21]) @[el2_lib.scala 343:44]
node _T_608 = cat(_T_342[25], _T_342[24]) @[el2_lib.scala 343:44]
node _T_609 = cat(_T_608, _T_342[23]) @[el2_lib.scala 343:44]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_610 = cat(_T_609, _T_607) @[el2_lib.scala 343:44]
node _T_611 = cat(_T_610, _T_606) @[el2_lib.scala 343:44]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_612 = cat(_T_342[27], _T_342[26]) @[el2_lib.scala 343:44]
node _T_613 = cat(_T_342[29], _T_342[28]) @[el2_lib.scala 343:44]
node _T_614 = cat(_T_613, _T_612) @[el2_lib.scala 343:44]
node _T_615 = cat(_T_342[31], _T_342[30]) @[el2_lib.scala 343:44]
node _T_616 = cat(_T_342[34], _T_342[33]) @[el2_lib.scala 343:44]
node _T_617 = cat(_T_616, _T_342[32]) @[el2_lib.scala 343:44]
node _T_618 = cat(_T_617, _T_615) @[el2_lib.scala 343:44]
node _T_619 = cat(_T_618, _T_614) @[el2_lib.scala 343:44]
node _T_620 = cat(_T_619, _T_611) @[el2_lib.scala 343:44]
node _T_621 = cat(_T_620, _T_603) @[el2_lib.scala 343:44]
node _T_622 = xorr(_T_621) @[el2_lib.scala 343:51]
node _T_623 = cat(_T_343[1], _T_343[0]) @[el2_lib.scala 343:61]
node _T_624 = cat(_T_343[3], _T_343[2]) @[el2_lib.scala 343:61]
node _T_625 = cat(_T_624, _T_623) @[el2_lib.scala 343:61]
node _T_626 = cat(_T_343[5], _T_343[4]) @[el2_lib.scala 343:61]
node _T_627 = cat(_T_343[7], _T_343[6]) @[el2_lib.scala 343:61]
node _T_628 = cat(_T_627, _T_626) @[el2_lib.scala 343:61]
node _T_629 = cat(_T_628, _T_625) @[el2_lib.scala 343:61]
node _T_630 = cat(_T_343[9], _T_343[8]) @[el2_lib.scala 343:61]
node _T_631 = cat(_T_343[11], _T_343[10]) @[el2_lib.scala 343:61]
node _T_632 = cat(_T_631, _T_630) @[el2_lib.scala 343:61]
node _T_633 = cat(_T_343[13], _T_343[12]) @[el2_lib.scala 343:61]
node _T_634 = cat(_T_343[16], _T_343[15]) @[el2_lib.scala 343:61]
node _T_635 = cat(_T_634, _T_343[14]) @[el2_lib.scala 343:61]
node _T_636 = cat(_T_635, _T_633) @[el2_lib.scala 343:61]
node _T_637 = cat(_T_636, _T_632) @[el2_lib.scala 343:61]
node _T_638 = cat(_T_637, _T_629) @[el2_lib.scala 343:61]
node _T_639 = cat(_T_343[18], _T_343[17]) @[el2_lib.scala 343:61]
node _T_640 = cat(_T_343[20], _T_343[19]) @[el2_lib.scala 343:61]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_641 = cat(_T_640, _T_639) @[el2_lib.scala 343:61]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_642 = cat(_T_343[22], _T_343[21]) @[el2_lib.scala 343:61]
node _T_643 = cat(_T_343[25], _T_343[24]) @[el2_lib.scala 343:61]
node _T_644 = cat(_T_643, _T_343[23]) @[el2_lib.scala 343:61]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_645 = cat(_T_644, _T_642) @[el2_lib.scala 343:61]
node _T_646 = cat(_T_645, _T_641) @[el2_lib.scala 343:61]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_647 = cat(_T_343[27], _T_343[26]) @[el2_lib.scala 343:61]
node _T_648 = cat(_T_343[29], _T_343[28]) @[el2_lib.scala 343:61]
node _T_649 = cat(_T_648, _T_647) @[el2_lib.scala 343:61]
node _T_650 = cat(_T_343[31], _T_343[30]) @[el2_lib.scala 343:61]
node _T_651 = cat(_T_343[34], _T_343[33]) @[el2_lib.scala 343:61]
node _T_652 = cat(_T_651, _T_343[32]) @[el2_lib.scala 343:61]
node _T_653 = cat(_T_652, _T_650) @[el2_lib.scala 343:61]
node _T_654 = cat(_T_653, _T_649) @[el2_lib.scala 343:61]
node _T_655 = cat(_T_654, _T_646) @[el2_lib.scala 343:61]
node _T_656 = cat(_T_655, _T_638) @[el2_lib.scala 343:61]
node _T_657 = xorr(_T_656) @[el2_lib.scala 343:68]
node _T_658 = cat(_T_344[2], _T_344[1]) @[el2_lib.scala 343:78]
node _T_659 = cat(_T_658, _T_344[0]) @[el2_lib.scala 343:78]
node _T_660 = cat(_T_344[4], _T_344[3]) @[el2_lib.scala 343:78]
node _T_661 = cat(_T_344[6], _T_344[5]) @[el2_lib.scala 343:78]
node _T_662 = cat(_T_661, _T_660) @[el2_lib.scala 343:78]
node _T_663 = cat(_T_662, _T_659) @[el2_lib.scala 343:78]
node _T_664 = cat(_T_344[8], _T_344[7]) @[el2_lib.scala 343:78]
node _T_665 = cat(_T_344[10], _T_344[9]) @[el2_lib.scala 343:78]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_666 = cat(_T_665, _T_664) @[el2_lib.scala 343:78]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_667 = cat(_T_344[12], _T_344[11]) @[el2_lib.scala 343:78]
node _T_668 = cat(_T_344[14], _T_344[13]) @[el2_lib.scala 343:78]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_669 = cat(_T_668, _T_667) @[el2_lib.scala 343:78]
node _T_670 = cat(_T_669, _T_666) @[el2_lib.scala 343:78]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_671 = cat(_T_670, _T_663) @[el2_lib.scala 343:78]
node _T_672 = cat(_T_344[16], _T_344[15]) @[el2_lib.scala 343:78]
node _T_673 = cat(_T_344[18], _T_344[17]) @[el2_lib.scala 343:78]
node _T_674 = cat(_T_673, _T_672) @[el2_lib.scala 343:78]
node _T_675 = cat(_T_344[20], _T_344[19]) @[el2_lib.scala 343:78]
node _T_676 = cat(_T_344[22], _T_344[21]) @[el2_lib.scala 343:78]
node _T_677 = cat(_T_676, _T_675) @[el2_lib.scala 343:78]
node _T_678 = cat(_T_677, _T_674) @[el2_lib.scala 343:78]
node _T_679 = cat(_T_344[24], _T_344[23]) @[el2_lib.scala 343:78]
node _T_680 = cat(_T_344[26], _T_344[25]) @[el2_lib.scala 343:78]
node _T_681 = cat(_T_680, _T_679) @[el2_lib.scala 343:78]
node _T_682 = cat(_T_344[28], _T_344[27]) @[el2_lib.scala 343:78]
node _T_683 = cat(_T_344[30], _T_344[29]) @[el2_lib.scala 343:78]
node _T_684 = cat(_T_683, _T_682) @[el2_lib.scala 343:78]
node _T_685 = cat(_T_684, _T_681) @[el2_lib.scala 343:78]
node _T_686 = cat(_T_685, _T_678) @[el2_lib.scala 343:78]
node _T_687 = cat(_T_686, _T_671) @[el2_lib.scala 343:78]
node _T_688 = xorr(_T_687) @[el2_lib.scala 343:85]
node _T_689 = cat(_T_345[2], _T_345[1]) @[el2_lib.scala 343:95]
node _T_690 = cat(_T_689, _T_345[0]) @[el2_lib.scala 343:95]
node _T_691 = cat(_T_345[4], _T_345[3]) @[el2_lib.scala 343:95]
node _T_692 = cat(_T_345[6], _T_345[5]) @[el2_lib.scala 343:95]
node _T_693 = cat(_T_692, _T_691) @[el2_lib.scala 343:95]
node _T_694 = cat(_T_693, _T_690) @[el2_lib.scala 343:95]
node _T_695 = cat(_T_345[8], _T_345[7]) @[el2_lib.scala 343:95]
node _T_696 = cat(_T_345[10], _T_345[9]) @[el2_lib.scala 343:95]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_697 = cat(_T_696, _T_695) @[el2_lib.scala 343:95]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_698 = cat(_T_345[12], _T_345[11]) @[el2_lib.scala 343:95]
node _T_699 = cat(_T_345[14], _T_345[13]) @[el2_lib.scala 343:95]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_700 = cat(_T_699, _T_698) @[el2_lib.scala 343:95]
node _T_701 = cat(_T_700, _T_697) @[el2_lib.scala 343:95]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_702 = cat(_T_701, _T_694) @[el2_lib.scala 343:95]
node _T_703 = cat(_T_345[16], _T_345[15]) @[el2_lib.scala 343:95]
node _T_704 = cat(_T_345[18], _T_345[17]) @[el2_lib.scala 343:95]
node _T_705 = cat(_T_704, _T_703) @[el2_lib.scala 343:95]
node _T_706 = cat(_T_345[20], _T_345[19]) @[el2_lib.scala 343:95]
node _T_707 = cat(_T_345[22], _T_345[21]) @[el2_lib.scala 343:95]
node _T_708 = cat(_T_707, _T_706) @[el2_lib.scala 343:95]
node _T_709 = cat(_T_708, _T_705) @[el2_lib.scala 343:95]
node _T_710 = cat(_T_345[24], _T_345[23]) @[el2_lib.scala 343:95]
node _T_711 = cat(_T_345[26], _T_345[25]) @[el2_lib.scala 343:95]
node _T_712 = cat(_T_711, _T_710) @[el2_lib.scala 343:95]
node _T_713 = cat(_T_345[28], _T_345[27]) @[el2_lib.scala 343:95]
node _T_714 = cat(_T_345[30], _T_345[29]) @[el2_lib.scala 343:95]
node _T_715 = cat(_T_714, _T_713) @[el2_lib.scala 343:95]
node _T_716 = cat(_T_715, _T_712) @[el2_lib.scala 343:95]
node _T_717 = cat(_T_716, _T_709) @[el2_lib.scala 343:95]
node _T_718 = cat(_T_717, _T_702) @[el2_lib.scala 343:95]
node _T_719 = xorr(_T_718) @[el2_lib.scala 343:102]
node _T_720 = cat(_T_346[2], _T_346[1]) @[el2_lib.scala 343:112]
node _T_721 = cat(_T_720, _T_346[0]) @[el2_lib.scala 343:112]
node _T_722 = cat(_T_346[4], _T_346[3]) @[el2_lib.scala 343:112]
node _T_723 = cat(_T_346[6], _T_346[5]) @[el2_lib.scala 343:112]
node _T_724 = cat(_T_723, _T_722) @[el2_lib.scala 343:112]
node _T_725 = cat(_T_724, _T_721) @[el2_lib.scala 343:112]
node _T_726 = cat(_T_346[8], _T_346[7]) @[el2_lib.scala 343:112]
node _T_727 = cat(_T_346[10], _T_346[9]) @[el2_lib.scala 343:112]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_728 = cat(_T_727, _T_726) @[el2_lib.scala 343:112]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_729 = cat(_T_346[12], _T_346[11]) @[el2_lib.scala 343:112]
node _T_730 = cat(_T_346[14], _T_346[13]) @[el2_lib.scala 343:112]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_731 = cat(_T_730, _T_729) @[el2_lib.scala 343:112]
node _T_732 = cat(_T_731, _T_728) @[el2_lib.scala 343:112]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_733 = cat(_T_732, _T_725) @[el2_lib.scala 343:112]
node _T_734 = cat(_T_346[16], _T_346[15]) @[el2_lib.scala 343:112]
node _T_735 = cat(_T_346[18], _T_346[17]) @[el2_lib.scala 343:112]
node _T_736 = cat(_T_735, _T_734) @[el2_lib.scala 343:112]
node _T_737 = cat(_T_346[20], _T_346[19]) @[el2_lib.scala 343:112]
node _T_738 = cat(_T_346[22], _T_346[21]) @[el2_lib.scala 343:112]
node _T_739 = cat(_T_738, _T_737) @[el2_lib.scala 343:112]
node _T_740 = cat(_T_739, _T_736) @[el2_lib.scala 343:112]
node _T_741 = cat(_T_346[24], _T_346[23]) @[el2_lib.scala 343:112]
node _T_742 = cat(_T_346[26], _T_346[25]) @[el2_lib.scala 343:112]
node _T_743 = cat(_T_742, _T_741) @[el2_lib.scala 343:112]
node _T_744 = cat(_T_346[28], _T_346[27]) @[el2_lib.scala 343:112]
node _T_745 = cat(_T_346[30], _T_346[29]) @[el2_lib.scala 343:112]
node _T_746 = cat(_T_745, _T_744) @[el2_lib.scala 343:112]
node _T_747 = cat(_T_746, _T_743) @[el2_lib.scala 343:112]
node _T_748 = cat(_T_747, _T_740) @[el2_lib.scala 343:112]
node _T_749 = cat(_T_748, _T_733) @[el2_lib.scala 343:112]
node _T_750 = xorr(_T_749) @[el2_lib.scala 343:119]
node _T_751 = cat(_T_347[2], _T_347[1]) @[el2_lib.scala 343:129]
node _T_752 = cat(_T_751, _T_347[0]) @[el2_lib.scala 343:129]
node _T_753 = cat(_T_347[4], _T_347[3]) @[el2_lib.scala 343:129]
node _T_754 = cat(_T_347[6], _T_347[5]) @[el2_lib.scala 343:129]
node _T_755 = cat(_T_754, _T_753) @[el2_lib.scala 343:129]
node _T_756 = cat(_T_755, _T_752) @[el2_lib.scala 343:129]
node _T_757 = xorr(_T_756) @[el2_lib.scala 343:136]
node _T_758 = cat(_T_719, _T_750) @[Cat.scala 29:58]
node _T_759 = cat(_T_758, _T_757) @[Cat.scala 29:58]
node _T_760 = cat(_T_657, _T_688) @[Cat.scala 29:58]
node _T_761 = cat(_T_587, _T_622) @[Cat.scala 29:58]
node _T_762 = cat(_T_761, _T_760) @[Cat.scala 29:58]
node ic_wr_ecc = cat(_T_762, _T_759) @[Cat.scala 29:58]
wire _T_763 : UInt<1>[35] @[el2_lib.scala 322:18]
wire _T_764 : UInt<1>[35] @[el2_lib.scala 323:18]
wire _T_765 : UInt<1>[35] @[el2_lib.scala 324:18]
wire _T_766 : UInt<1>[31] @[el2_lib.scala 325:18]
wire _T_767 : UInt<1>[31] @[el2_lib.scala 326:18]
wire _T_768 : UInt<1>[31] @[el2_lib.scala 327:18]
wire _T_769 : UInt<1>[7] @[el2_lib.scala 328:18]
node _T_770 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 335:36]
_T_763[0] <= _T_770 @[el2_lib.scala 335:30]
node _T_771 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 336:36]
_T_764[0] <= _T_771 @[el2_lib.scala 336:30]
node _T_772 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 335:36]
_T_763[1] <= _T_772 @[el2_lib.scala 335:30]
node _T_773 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 337:36]
_T_765[0] <= _T_773 @[el2_lib.scala 337:30]
node _T_774 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 336:36]
_T_764[1] <= _T_774 @[el2_lib.scala 336:30]
node _T_775 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 337:36]
_T_765[1] <= _T_775 @[el2_lib.scala 337:30]
node _T_776 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 335:36]
_T_763[2] <= _T_776 @[el2_lib.scala 335:30]
node _T_777 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 336:36]
_T_764[2] <= _T_777 @[el2_lib.scala 336:30]
node _T_778 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 337:36]
_T_765[2] <= _T_778 @[el2_lib.scala 337:30]
node _T_779 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 335:36]
_T_763[3] <= _T_779 @[el2_lib.scala 335:30]
node _T_780 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 338:36]
_T_766[0] <= _T_780 @[el2_lib.scala 338:30]
node _T_781 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 336:36]
_T_764[3] <= _T_781 @[el2_lib.scala 336:30]
node _T_782 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 338:36]
_T_766[1] <= _T_782 @[el2_lib.scala 338:30]
node _T_783 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 335:36]
_T_763[4] <= _T_783 @[el2_lib.scala 335:30]
node _T_784 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 336:36]
_T_764[4] <= _T_784 @[el2_lib.scala 336:30]
node _T_785 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 338:36]
_T_766[2] <= _T_785 @[el2_lib.scala 338:30]
node _T_786 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 337:36]
_T_765[3] <= _T_786 @[el2_lib.scala 337:30]
node _T_787 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 338:36]
_T_766[3] <= _T_787 @[el2_lib.scala 338:30]
node _T_788 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 335:36]
_T_763[5] <= _T_788 @[el2_lib.scala 335:30]
node _T_789 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 337:36]
_T_765[4] <= _T_789 @[el2_lib.scala 337:30]
node _T_790 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 338:36]
_T_766[4] <= _T_790 @[el2_lib.scala 338:30]
node _T_791 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 336:36]
_T_764[5] <= _T_791 @[el2_lib.scala 336:30]
node _T_792 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 337:36]
_T_765[5] <= _T_792 @[el2_lib.scala 337:30]
node _T_793 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 338:36]
_T_766[5] <= _T_793 @[el2_lib.scala 338:30]
node _T_794 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 335:36]
_T_763[6] <= _T_794 @[el2_lib.scala 335:30]
node _T_795 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 336:36]
_T_764[6] <= _T_795 @[el2_lib.scala 336:30]
node _T_796 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 337:36]
_T_765[6] <= _T_796 @[el2_lib.scala 337:30]
node _T_797 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 338:36]
_T_766[6] <= _T_797 @[el2_lib.scala 338:30]
node _T_798 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 335:36]
_T_763[7] <= _T_798 @[el2_lib.scala 335:30]
node _T_799 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 339:36]
_T_767[0] <= _T_799 @[el2_lib.scala 339:30]
node _T_800 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 336:36]
_T_764[7] <= _T_800 @[el2_lib.scala 336:30]
node _T_801 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 339:36]
_T_767[1] <= _T_801 @[el2_lib.scala 339:30]
node _T_802 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 335:36]
_T_763[8] <= _T_802 @[el2_lib.scala 335:30]
node _T_803 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 336:36]
_T_764[8] <= _T_803 @[el2_lib.scala 336:30]
node _T_804 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 339:36]
_T_767[2] <= _T_804 @[el2_lib.scala 339:30]
node _T_805 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 337:36]
_T_765[7] <= _T_805 @[el2_lib.scala 337:30]
node _T_806 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 339:36]
_T_767[3] <= _T_806 @[el2_lib.scala 339:30]
node _T_807 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 335:36]
_T_763[9] <= _T_807 @[el2_lib.scala 335:30]
node _T_808 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 337:36]
_T_765[8] <= _T_808 @[el2_lib.scala 337:30]
node _T_809 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 339:36]
_T_767[4] <= _T_809 @[el2_lib.scala 339:30]
node _T_810 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 336:36]
_T_764[9] <= _T_810 @[el2_lib.scala 336:30]
node _T_811 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 337:36]
_T_765[9] <= _T_811 @[el2_lib.scala 337:30]
node _T_812 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 339:36]
_T_767[5] <= _T_812 @[el2_lib.scala 339:30]
node _T_813 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 335:36]
_T_763[10] <= _T_813 @[el2_lib.scala 335:30]
node _T_814 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 336:36]
_T_764[10] <= _T_814 @[el2_lib.scala 336:30]
node _T_815 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 337:36]
_T_765[10] <= _T_815 @[el2_lib.scala 337:30]
node _T_816 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 339:36]
_T_767[6] <= _T_816 @[el2_lib.scala 339:30]
node _T_817 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 338:36]
_T_766[7] <= _T_817 @[el2_lib.scala 338:30]
node _T_818 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 339:36]
_T_767[7] <= _T_818 @[el2_lib.scala 339:30]
node _T_819 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 335:36]
_T_763[11] <= _T_819 @[el2_lib.scala 335:30]
node _T_820 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 338:36]
_T_766[8] <= _T_820 @[el2_lib.scala 338:30]
node _T_821 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 339:36]
_T_767[8] <= _T_821 @[el2_lib.scala 339:30]
node _T_822 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 336:36]
_T_764[11] <= _T_822 @[el2_lib.scala 336:30]
node _T_823 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 338:36]
_T_766[9] <= _T_823 @[el2_lib.scala 338:30]
node _T_824 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 339:36]
_T_767[9] <= _T_824 @[el2_lib.scala 339:30]
node _T_825 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 335:36]
_T_763[12] <= _T_825 @[el2_lib.scala 335:30]
node _T_826 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 336:36]
_T_764[12] <= _T_826 @[el2_lib.scala 336:30]
node _T_827 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 338:36]
_T_766[10] <= _T_827 @[el2_lib.scala 338:30]
node _T_828 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 339:36]
_T_767[10] <= _T_828 @[el2_lib.scala 339:30]
node _T_829 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 337:36]
_T_765[11] <= _T_829 @[el2_lib.scala 337:30]
node _T_830 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 338:36]
_T_766[11] <= _T_830 @[el2_lib.scala 338:30]
node _T_831 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 339:36]
_T_767[11] <= _T_831 @[el2_lib.scala 339:30]
node _T_832 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 335:36]
_T_763[13] <= _T_832 @[el2_lib.scala 335:30]
node _T_833 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 337:36]
_T_765[12] <= _T_833 @[el2_lib.scala 337:30]
node _T_834 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 338:36]
_T_766[12] <= _T_834 @[el2_lib.scala 338:30]
node _T_835 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 339:36]
_T_767[12] <= _T_835 @[el2_lib.scala 339:30]
node _T_836 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 336:36]
_T_764[13] <= _T_836 @[el2_lib.scala 336:30]
node _T_837 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 337:36]
_T_765[13] <= _T_837 @[el2_lib.scala 337:30]
node _T_838 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 338:36]
_T_766[13] <= _T_838 @[el2_lib.scala 338:30]
node _T_839 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 339:36]
_T_767[13] <= _T_839 @[el2_lib.scala 339:30]
node _T_840 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 335:36]
_T_763[14] <= _T_840 @[el2_lib.scala 335:30]
node _T_841 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 336:36]
_T_764[14] <= _T_841 @[el2_lib.scala 336:30]
node _T_842 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 337:36]
_T_765[14] <= _T_842 @[el2_lib.scala 337:30]
node _T_843 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 338:36]
_T_766[14] <= _T_843 @[el2_lib.scala 338:30]
node _T_844 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 339:36]
_T_767[14] <= _T_844 @[el2_lib.scala 339:30]
node _T_845 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 335:36]
_T_763[15] <= _T_845 @[el2_lib.scala 335:30]
node _T_846 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 340:36]
_T_768[0] <= _T_846 @[el2_lib.scala 340:30]
node _T_847 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 336:36]
_T_764[15] <= _T_847 @[el2_lib.scala 336:30]
node _T_848 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 340:36]
_T_768[1] <= _T_848 @[el2_lib.scala 340:30]
node _T_849 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 335:36]
_T_763[16] <= _T_849 @[el2_lib.scala 335:30]
node _T_850 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 336:36]
_T_764[16] <= _T_850 @[el2_lib.scala 336:30]
node _T_851 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 340:36]
_T_768[2] <= _T_851 @[el2_lib.scala 340:30]
node _T_852 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 337:36]
_T_765[15] <= _T_852 @[el2_lib.scala 337:30]
node _T_853 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 340:36]
_T_768[3] <= _T_853 @[el2_lib.scala 340:30]
node _T_854 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 335:36]
_T_763[17] <= _T_854 @[el2_lib.scala 335:30]
node _T_855 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 337:36]
_T_765[16] <= _T_855 @[el2_lib.scala 337:30]
node _T_856 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 340:36]
_T_768[4] <= _T_856 @[el2_lib.scala 340:30]
node _T_857 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 336:36]
_T_764[17] <= _T_857 @[el2_lib.scala 336:30]
node _T_858 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 337:36]
_T_765[17] <= _T_858 @[el2_lib.scala 337:30]
node _T_859 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 340:36]
_T_768[5] <= _T_859 @[el2_lib.scala 340:30]
node _T_860 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 335:36]
_T_763[18] <= _T_860 @[el2_lib.scala 335:30]
node _T_861 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 336:36]
_T_764[18] <= _T_861 @[el2_lib.scala 336:30]
node _T_862 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 337:36]
_T_765[18] <= _T_862 @[el2_lib.scala 337:30]
node _T_863 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 340:36]
_T_768[6] <= _T_863 @[el2_lib.scala 340:30]
node _T_864 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 338:36]
_T_766[15] <= _T_864 @[el2_lib.scala 338:30]
node _T_865 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 340:36]
_T_768[7] <= _T_865 @[el2_lib.scala 340:30]
node _T_866 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 335:36]
_T_763[19] <= _T_866 @[el2_lib.scala 335:30]
node _T_867 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 338:36]
_T_766[16] <= _T_867 @[el2_lib.scala 338:30]
node _T_868 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 340:36]
_T_768[8] <= _T_868 @[el2_lib.scala 340:30]
node _T_869 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 336:36]
_T_764[19] <= _T_869 @[el2_lib.scala 336:30]
node _T_870 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 338:36]
_T_766[17] <= _T_870 @[el2_lib.scala 338:30]
node _T_871 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 340:36]
_T_768[9] <= _T_871 @[el2_lib.scala 340:30]
node _T_872 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 335:36]
_T_763[20] <= _T_872 @[el2_lib.scala 335:30]
node _T_873 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 336:36]
_T_764[20] <= _T_873 @[el2_lib.scala 336:30]
node _T_874 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 338:36]
_T_766[18] <= _T_874 @[el2_lib.scala 338:30]
node _T_875 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 340:36]
_T_768[10] <= _T_875 @[el2_lib.scala 340:30]
node _T_876 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 337:36]
_T_765[19] <= _T_876 @[el2_lib.scala 337:30]
node _T_877 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 338:36]
_T_766[19] <= _T_877 @[el2_lib.scala 338:30]
node _T_878 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 340:36]
_T_768[11] <= _T_878 @[el2_lib.scala 340:30]
node _T_879 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 335:36]
_T_763[21] <= _T_879 @[el2_lib.scala 335:30]
node _T_880 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 337:36]
_T_765[20] <= _T_880 @[el2_lib.scala 337:30]
node _T_881 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 338:36]
_T_766[20] <= _T_881 @[el2_lib.scala 338:30]
node _T_882 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 340:36]
_T_768[12] <= _T_882 @[el2_lib.scala 340:30]
node _T_883 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 336:36]
_T_764[21] <= _T_883 @[el2_lib.scala 336:30]
node _T_884 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 337:36]
_T_765[21] <= _T_884 @[el2_lib.scala 337:30]
node _T_885 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 338:36]
_T_766[21] <= _T_885 @[el2_lib.scala 338:30]
node _T_886 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 340:36]
_T_768[13] <= _T_886 @[el2_lib.scala 340:30]
node _T_887 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 335:36]
_T_763[22] <= _T_887 @[el2_lib.scala 335:30]
node _T_888 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 336:36]
_T_764[22] <= _T_888 @[el2_lib.scala 336:30]
node _T_889 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 337:36]
_T_765[22] <= _T_889 @[el2_lib.scala 337:30]
node _T_890 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 338:36]
_T_766[22] <= _T_890 @[el2_lib.scala 338:30]
node _T_891 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 340:36]
_T_768[14] <= _T_891 @[el2_lib.scala 340:30]
node _T_892 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 339:36]
_T_767[15] <= _T_892 @[el2_lib.scala 339:30]
node _T_893 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 340:36]
_T_768[15] <= _T_893 @[el2_lib.scala 340:30]
node _T_894 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 335:36]
_T_763[23] <= _T_894 @[el2_lib.scala 335:30]
node _T_895 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 339:36]
_T_767[16] <= _T_895 @[el2_lib.scala 339:30]
node _T_896 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 340:36]
_T_768[16] <= _T_896 @[el2_lib.scala 340:30]
node _T_897 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 336:36]
_T_764[23] <= _T_897 @[el2_lib.scala 336:30]
node _T_898 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 339:36]
_T_767[17] <= _T_898 @[el2_lib.scala 339:30]
node _T_899 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 340:36]
_T_768[17] <= _T_899 @[el2_lib.scala 340:30]
node _T_900 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 335:36]
_T_763[24] <= _T_900 @[el2_lib.scala 335:30]
node _T_901 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 336:36]
_T_764[24] <= _T_901 @[el2_lib.scala 336:30]
node _T_902 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 339:36]
_T_767[18] <= _T_902 @[el2_lib.scala 339:30]
node _T_903 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 340:36]
_T_768[18] <= _T_903 @[el2_lib.scala 340:30]
node _T_904 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 337:36]
_T_765[23] <= _T_904 @[el2_lib.scala 337:30]
node _T_905 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 339:36]
_T_767[19] <= _T_905 @[el2_lib.scala 339:30]
node _T_906 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 340:36]
_T_768[19] <= _T_906 @[el2_lib.scala 340:30]
node _T_907 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 335:36]
_T_763[25] <= _T_907 @[el2_lib.scala 335:30]
node _T_908 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 337:36]
_T_765[24] <= _T_908 @[el2_lib.scala 337:30]
node _T_909 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 339:36]
_T_767[20] <= _T_909 @[el2_lib.scala 339:30]
node _T_910 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 340:36]
_T_768[20] <= _T_910 @[el2_lib.scala 340:30]
node _T_911 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 336:36]
_T_764[25] <= _T_911 @[el2_lib.scala 336:30]
node _T_912 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 337:36]
_T_765[25] <= _T_912 @[el2_lib.scala 337:30]
node _T_913 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 339:36]
_T_767[21] <= _T_913 @[el2_lib.scala 339:30]
node _T_914 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 340:36]
_T_768[21] <= _T_914 @[el2_lib.scala 340:30]
node _T_915 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 335:36]
_T_763[26] <= _T_915 @[el2_lib.scala 335:30]
node _T_916 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 336:36]
_T_764[26] <= _T_916 @[el2_lib.scala 336:30]
node _T_917 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 337:36]
_T_765[26] <= _T_917 @[el2_lib.scala 337:30]
node _T_918 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 339:36]
_T_767[22] <= _T_918 @[el2_lib.scala 339:30]
node _T_919 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 340:36]
_T_768[22] <= _T_919 @[el2_lib.scala 340:30]
node _T_920 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 338:36]
_T_766[23] <= _T_920 @[el2_lib.scala 338:30]
node _T_921 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 339:36]
_T_767[23] <= _T_921 @[el2_lib.scala 339:30]
node _T_922 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 340:36]
_T_768[23] <= _T_922 @[el2_lib.scala 340:30]
node _T_923 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 335:36]
_T_763[27] <= _T_923 @[el2_lib.scala 335:30]
node _T_924 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 338:36]
_T_766[24] <= _T_924 @[el2_lib.scala 338:30]
node _T_925 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 339:36]
_T_767[24] <= _T_925 @[el2_lib.scala 339:30]
node _T_926 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 340:36]
_T_768[24] <= _T_926 @[el2_lib.scala 340:30]
node _T_927 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 336:36]
_T_764[27] <= _T_927 @[el2_lib.scala 336:30]
node _T_928 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 338:36]
_T_766[25] <= _T_928 @[el2_lib.scala 338:30]
node _T_929 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 339:36]
_T_767[25] <= _T_929 @[el2_lib.scala 339:30]
node _T_930 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 340:36]
_T_768[25] <= _T_930 @[el2_lib.scala 340:30]
node _T_931 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 335:36]
_T_763[28] <= _T_931 @[el2_lib.scala 335:30]
node _T_932 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 336:36]
_T_764[28] <= _T_932 @[el2_lib.scala 336:30]
node _T_933 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 338:36]
_T_766[26] <= _T_933 @[el2_lib.scala 338:30]
node _T_934 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 339:36]
_T_767[26] <= _T_934 @[el2_lib.scala 339:30]
node _T_935 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 340:36]
_T_768[26] <= _T_935 @[el2_lib.scala 340:30]
node _T_936 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 337:36]
_T_765[27] <= _T_936 @[el2_lib.scala 337:30]
node _T_937 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 338:36]
_T_766[27] <= _T_937 @[el2_lib.scala 338:30]
node _T_938 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 339:36]
_T_767[27] <= _T_938 @[el2_lib.scala 339:30]
node _T_939 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 340:36]
_T_768[27] <= _T_939 @[el2_lib.scala 340:30]
node _T_940 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 335:36]
_T_763[29] <= _T_940 @[el2_lib.scala 335:30]
node _T_941 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 337:36]
_T_765[28] <= _T_941 @[el2_lib.scala 337:30]
node _T_942 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 338:36]
_T_766[28] <= _T_942 @[el2_lib.scala 338:30]
node _T_943 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 339:36]
_T_767[28] <= _T_943 @[el2_lib.scala 339:30]
node _T_944 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 340:36]
_T_768[28] <= _T_944 @[el2_lib.scala 340:30]
node _T_945 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 336:36]
_T_764[29] <= _T_945 @[el2_lib.scala 336:30]
node _T_946 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 337:36]
_T_765[29] <= _T_946 @[el2_lib.scala 337:30]
node _T_947 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 338:36]
_T_766[29] <= _T_947 @[el2_lib.scala 338:30]
node _T_948 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 339:36]
_T_767[29] <= _T_948 @[el2_lib.scala 339:30]
node _T_949 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 340:36]
_T_768[29] <= _T_949 @[el2_lib.scala 340:30]
node _T_950 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 335:36]
_T_763[30] <= _T_950 @[el2_lib.scala 335:30]
node _T_951 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 336:36]
_T_764[30] <= _T_951 @[el2_lib.scala 336:30]
node _T_952 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 337:36]
_T_765[30] <= _T_952 @[el2_lib.scala 337:30]
node _T_953 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 338:36]
_T_766[30] <= _T_953 @[el2_lib.scala 338:30]
node _T_954 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 339:36]
_T_767[30] <= _T_954 @[el2_lib.scala 339:30]
node _T_955 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 340:36]
_T_768[30] <= _T_955 @[el2_lib.scala 340:30]
node _T_956 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 335:36]
_T_763[31] <= _T_956 @[el2_lib.scala 335:30]
node _T_957 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 341:36]
_T_769[0] <= _T_957 @[el2_lib.scala 341:30]
node _T_958 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 336:36]
_T_764[31] <= _T_958 @[el2_lib.scala 336:30]
node _T_959 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 341:36]
_T_769[1] <= _T_959 @[el2_lib.scala 341:30]
node _T_960 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 335:36]
_T_763[32] <= _T_960 @[el2_lib.scala 335:30]
node _T_961 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 336:36]
_T_764[32] <= _T_961 @[el2_lib.scala 336:30]
node _T_962 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 341:36]
_T_769[2] <= _T_962 @[el2_lib.scala 341:30]
node _T_963 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 337:36]
_T_765[31] <= _T_963 @[el2_lib.scala 337:30]
node _T_964 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 341:36]
_T_769[3] <= _T_964 @[el2_lib.scala 341:30]
node _T_965 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 335:36]
_T_763[33] <= _T_965 @[el2_lib.scala 335:30]
node _T_966 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 337:36]
_T_765[32] <= _T_966 @[el2_lib.scala 337:30]
node _T_967 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 341:36]
_T_769[4] <= _T_967 @[el2_lib.scala 341:30]
node _T_968 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 336:36]
_T_764[33] <= _T_968 @[el2_lib.scala 336:30]
node _T_969 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 337:36]
_T_765[33] <= _T_969 @[el2_lib.scala 337:30]
node _T_970 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 341:36]
_T_769[5] <= _T_970 @[el2_lib.scala 341:30]
node _T_971 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 335:36]
_T_763[34] <= _T_971 @[el2_lib.scala 335:30]
node _T_972 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 336:36]
_T_764[34] <= _T_972 @[el2_lib.scala 336:30]
node _T_973 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 337:36]
_T_765[34] <= _T_973 @[el2_lib.scala 337:30]
node _T_974 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 341:36]
_T_769[6] <= _T_974 @[el2_lib.scala 341:30]
node _T_975 = cat(_T_763[1], _T_763[0]) @[el2_lib.scala 343:27]
node _T_976 = cat(_T_763[3], _T_763[2]) @[el2_lib.scala 343:27]
node _T_977 = cat(_T_976, _T_975) @[el2_lib.scala 343:27]
node _T_978 = cat(_T_763[5], _T_763[4]) @[el2_lib.scala 343:27]
node _T_979 = cat(_T_763[7], _T_763[6]) @[el2_lib.scala 343:27]
node _T_980 = cat(_T_979, _T_978) @[el2_lib.scala 343:27]
node _T_981 = cat(_T_980, _T_977) @[el2_lib.scala 343:27]
node _T_982 = cat(_T_763[9], _T_763[8]) @[el2_lib.scala 343:27]
node _T_983 = cat(_T_763[11], _T_763[10]) @[el2_lib.scala 343:27]
node _T_984 = cat(_T_983, _T_982) @[el2_lib.scala 343:27]
node _T_985 = cat(_T_763[13], _T_763[12]) @[el2_lib.scala 343:27]
node _T_986 = cat(_T_763[16], _T_763[15]) @[el2_lib.scala 343:27]
node _T_987 = cat(_T_986, _T_763[14]) @[el2_lib.scala 343:27]
node _T_988 = cat(_T_987, _T_985) @[el2_lib.scala 343:27]
node _T_989 = cat(_T_988, _T_984) @[el2_lib.scala 343:27]
node _T_990 = cat(_T_989, _T_981) @[el2_lib.scala 343:27]
node _T_991 = cat(_T_763[18], _T_763[17]) @[el2_lib.scala 343:27]
node _T_992 = cat(_T_763[20], _T_763[19]) @[el2_lib.scala 343:27]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_993 = cat(_T_992, _T_991) @[el2_lib.scala 343:27]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_994 = cat(_T_763[22], _T_763[21]) @[el2_lib.scala 343:27]
node _T_995 = cat(_T_763[25], _T_763[24]) @[el2_lib.scala 343:27]
node _T_996 = cat(_T_995, _T_763[23]) @[el2_lib.scala 343:27]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_997 = cat(_T_996, _T_994) @[el2_lib.scala 343:27]
node _T_998 = cat(_T_997, _T_993) @[el2_lib.scala 343:27]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_999 = cat(_T_763[27], _T_763[26]) @[el2_lib.scala 343:27]
node _T_1000 = cat(_T_763[29], _T_763[28]) @[el2_lib.scala 343:27]
node _T_1001 = cat(_T_1000, _T_999) @[el2_lib.scala 343:27]
node _T_1002 = cat(_T_763[31], _T_763[30]) @[el2_lib.scala 343:27]
node _T_1003 = cat(_T_763[34], _T_763[33]) @[el2_lib.scala 343:27]
node _T_1004 = cat(_T_1003, _T_763[32]) @[el2_lib.scala 343:27]
node _T_1005 = cat(_T_1004, _T_1002) @[el2_lib.scala 343:27]
node _T_1006 = cat(_T_1005, _T_1001) @[el2_lib.scala 343:27]
node _T_1007 = cat(_T_1006, _T_998) @[el2_lib.scala 343:27]
node _T_1008 = cat(_T_1007, _T_990) @[el2_lib.scala 343:27]
node _T_1009 = xorr(_T_1008) @[el2_lib.scala 343:34]
node _T_1010 = cat(_T_764[1], _T_764[0]) @[el2_lib.scala 343:44]
node _T_1011 = cat(_T_764[3], _T_764[2]) @[el2_lib.scala 343:44]
node _T_1012 = cat(_T_1011, _T_1010) @[el2_lib.scala 343:44]
node _T_1013 = cat(_T_764[5], _T_764[4]) @[el2_lib.scala 343:44]
node _T_1014 = cat(_T_764[7], _T_764[6]) @[el2_lib.scala 343:44]
node _T_1015 = cat(_T_1014, _T_1013) @[el2_lib.scala 343:44]
node _T_1016 = cat(_T_1015, _T_1012) @[el2_lib.scala 343:44]
node _T_1017 = cat(_T_764[9], _T_764[8]) @[el2_lib.scala 343:44]
node _T_1018 = cat(_T_764[11], _T_764[10]) @[el2_lib.scala 343:44]
node _T_1019 = cat(_T_1018, _T_1017) @[el2_lib.scala 343:44]
node _T_1020 = cat(_T_764[13], _T_764[12]) @[el2_lib.scala 343:44]
node _T_1021 = cat(_T_764[16], _T_764[15]) @[el2_lib.scala 343:44]
node _T_1022 = cat(_T_1021, _T_764[14]) @[el2_lib.scala 343:44]
node _T_1023 = cat(_T_1022, _T_1020) @[el2_lib.scala 343:44]
node _T_1024 = cat(_T_1023, _T_1019) @[el2_lib.scala 343:44]
node _T_1025 = cat(_T_1024, _T_1016) @[el2_lib.scala 343:44]
node _T_1026 = cat(_T_764[18], _T_764[17]) @[el2_lib.scala 343:44]
node _T_1027 = cat(_T_764[20], _T_764[19]) @[el2_lib.scala 343:44]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1028 = cat(_T_1027, _T_1026) @[el2_lib.scala 343:44]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1029 = cat(_T_764[22], _T_764[21]) @[el2_lib.scala 343:44]
node _T_1030 = cat(_T_764[25], _T_764[24]) @[el2_lib.scala 343:44]
node _T_1031 = cat(_T_1030, _T_764[23]) @[el2_lib.scala 343:44]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1032 = cat(_T_1031, _T_1029) @[el2_lib.scala 343:44]
node _T_1033 = cat(_T_1032, _T_1028) @[el2_lib.scala 343:44]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1034 = cat(_T_764[27], _T_764[26]) @[el2_lib.scala 343:44]
node _T_1035 = cat(_T_764[29], _T_764[28]) @[el2_lib.scala 343:44]
node _T_1036 = cat(_T_1035, _T_1034) @[el2_lib.scala 343:44]
node _T_1037 = cat(_T_764[31], _T_764[30]) @[el2_lib.scala 343:44]
node _T_1038 = cat(_T_764[34], _T_764[33]) @[el2_lib.scala 343:44]
node _T_1039 = cat(_T_1038, _T_764[32]) @[el2_lib.scala 343:44]
node _T_1040 = cat(_T_1039, _T_1037) @[el2_lib.scala 343:44]
node _T_1041 = cat(_T_1040, _T_1036) @[el2_lib.scala 343:44]
node _T_1042 = cat(_T_1041, _T_1033) @[el2_lib.scala 343:44]
node _T_1043 = cat(_T_1042, _T_1025) @[el2_lib.scala 343:44]
node _T_1044 = xorr(_T_1043) @[el2_lib.scala 343:51]
node _T_1045 = cat(_T_765[1], _T_765[0]) @[el2_lib.scala 343:61]
node _T_1046 = cat(_T_765[3], _T_765[2]) @[el2_lib.scala 343:61]
node _T_1047 = cat(_T_1046, _T_1045) @[el2_lib.scala 343:61]
node _T_1048 = cat(_T_765[5], _T_765[4]) @[el2_lib.scala 343:61]
node _T_1049 = cat(_T_765[7], _T_765[6]) @[el2_lib.scala 343:61]
node _T_1050 = cat(_T_1049, _T_1048) @[el2_lib.scala 343:61]
node _T_1051 = cat(_T_1050, _T_1047) @[el2_lib.scala 343:61]
node _T_1052 = cat(_T_765[9], _T_765[8]) @[el2_lib.scala 343:61]
node _T_1053 = cat(_T_765[11], _T_765[10]) @[el2_lib.scala 343:61]
node _T_1054 = cat(_T_1053, _T_1052) @[el2_lib.scala 343:61]
node _T_1055 = cat(_T_765[13], _T_765[12]) @[el2_lib.scala 343:61]
node _T_1056 = cat(_T_765[16], _T_765[15]) @[el2_lib.scala 343:61]
node _T_1057 = cat(_T_1056, _T_765[14]) @[el2_lib.scala 343:61]
node _T_1058 = cat(_T_1057, _T_1055) @[el2_lib.scala 343:61]
node _T_1059 = cat(_T_1058, _T_1054) @[el2_lib.scala 343:61]
node _T_1060 = cat(_T_1059, _T_1051) @[el2_lib.scala 343:61]
node _T_1061 = cat(_T_765[18], _T_765[17]) @[el2_lib.scala 343:61]
node _T_1062 = cat(_T_765[20], _T_765[19]) @[el2_lib.scala 343:61]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1063 = cat(_T_1062, _T_1061) @[el2_lib.scala 343:61]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1064 = cat(_T_765[22], _T_765[21]) @[el2_lib.scala 343:61]
node _T_1065 = cat(_T_765[25], _T_765[24]) @[el2_lib.scala 343:61]
node _T_1066 = cat(_T_1065, _T_765[23]) @[el2_lib.scala 343:61]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1067 = cat(_T_1066, _T_1064) @[el2_lib.scala 343:61]
node _T_1068 = cat(_T_1067, _T_1063) @[el2_lib.scala 343:61]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1069 = cat(_T_765[27], _T_765[26]) @[el2_lib.scala 343:61]
node _T_1070 = cat(_T_765[29], _T_765[28]) @[el2_lib.scala 343:61]
node _T_1071 = cat(_T_1070, _T_1069) @[el2_lib.scala 343:61]
node _T_1072 = cat(_T_765[31], _T_765[30]) @[el2_lib.scala 343:61]
node _T_1073 = cat(_T_765[34], _T_765[33]) @[el2_lib.scala 343:61]
node _T_1074 = cat(_T_1073, _T_765[32]) @[el2_lib.scala 343:61]
node _T_1075 = cat(_T_1074, _T_1072) @[el2_lib.scala 343:61]
node _T_1076 = cat(_T_1075, _T_1071) @[el2_lib.scala 343:61]
node _T_1077 = cat(_T_1076, _T_1068) @[el2_lib.scala 343:61]
node _T_1078 = cat(_T_1077, _T_1060) @[el2_lib.scala 343:61]
node _T_1079 = xorr(_T_1078) @[el2_lib.scala 343:68]
node _T_1080 = cat(_T_766[2], _T_766[1]) @[el2_lib.scala 343:78]
node _T_1081 = cat(_T_1080, _T_766[0]) @[el2_lib.scala 343:78]
node _T_1082 = cat(_T_766[4], _T_766[3]) @[el2_lib.scala 343:78]
node _T_1083 = cat(_T_766[6], _T_766[5]) @[el2_lib.scala 343:78]
node _T_1084 = cat(_T_1083, _T_1082) @[el2_lib.scala 343:78]
node _T_1085 = cat(_T_1084, _T_1081) @[el2_lib.scala 343:78]
node _T_1086 = cat(_T_766[8], _T_766[7]) @[el2_lib.scala 343:78]
node _T_1087 = cat(_T_766[10], _T_766[9]) @[el2_lib.scala 343:78]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 343:78]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1089 = cat(_T_766[12], _T_766[11]) @[el2_lib.scala 343:78]
node _T_1090 = cat(_T_766[14], _T_766[13]) @[el2_lib.scala 343:78]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 343:78]
node _T_1092 = cat(_T_1091, _T_1088) @[el2_lib.scala 343:78]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1093 = cat(_T_1092, _T_1085) @[el2_lib.scala 343:78]
node _T_1094 = cat(_T_766[16], _T_766[15]) @[el2_lib.scala 343:78]
node _T_1095 = cat(_T_766[18], _T_766[17]) @[el2_lib.scala 343:78]
node _T_1096 = cat(_T_1095, _T_1094) @[el2_lib.scala 343:78]
node _T_1097 = cat(_T_766[20], _T_766[19]) @[el2_lib.scala 343:78]
node _T_1098 = cat(_T_766[22], _T_766[21]) @[el2_lib.scala 343:78]
node _T_1099 = cat(_T_1098, _T_1097) @[el2_lib.scala 343:78]
node _T_1100 = cat(_T_1099, _T_1096) @[el2_lib.scala 343:78]
node _T_1101 = cat(_T_766[24], _T_766[23]) @[el2_lib.scala 343:78]
node _T_1102 = cat(_T_766[26], _T_766[25]) @[el2_lib.scala 343:78]
node _T_1103 = cat(_T_1102, _T_1101) @[el2_lib.scala 343:78]
node _T_1104 = cat(_T_766[28], _T_766[27]) @[el2_lib.scala 343:78]
node _T_1105 = cat(_T_766[30], _T_766[29]) @[el2_lib.scala 343:78]
node _T_1106 = cat(_T_1105, _T_1104) @[el2_lib.scala 343:78]
node _T_1107 = cat(_T_1106, _T_1103) @[el2_lib.scala 343:78]
node _T_1108 = cat(_T_1107, _T_1100) @[el2_lib.scala 343:78]
node _T_1109 = cat(_T_1108, _T_1093) @[el2_lib.scala 343:78]
node _T_1110 = xorr(_T_1109) @[el2_lib.scala 343:85]
node _T_1111 = cat(_T_767[2], _T_767[1]) @[el2_lib.scala 343:95]
node _T_1112 = cat(_T_1111, _T_767[0]) @[el2_lib.scala 343:95]
node _T_1113 = cat(_T_767[4], _T_767[3]) @[el2_lib.scala 343:95]
node _T_1114 = cat(_T_767[6], _T_767[5]) @[el2_lib.scala 343:95]
node _T_1115 = cat(_T_1114, _T_1113) @[el2_lib.scala 343:95]
node _T_1116 = cat(_T_1115, _T_1112) @[el2_lib.scala 343:95]
node _T_1117 = cat(_T_767[8], _T_767[7]) @[el2_lib.scala 343:95]
node _T_1118 = cat(_T_767[10], _T_767[9]) @[el2_lib.scala 343:95]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1119 = cat(_T_1118, _T_1117) @[el2_lib.scala 343:95]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1120 = cat(_T_767[12], _T_767[11]) @[el2_lib.scala 343:95]
node _T_1121 = cat(_T_767[14], _T_767[13]) @[el2_lib.scala 343:95]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1122 = cat(_T_1121, _T_1120) @[el2_lib.scala 343:95]
node _T_1123 = cat(_T_1122, _T_1119) @[el2_lib.scala 343:95]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1124 = cat(_T_1123, _T_1116) @[el2_lib.scala 343:95]
node _T_1125 = cat(_T_767[16], _T_767[15]) @[el2_lib.scala 343:95]
node _T_1126 = cat(_T_767[18], _T_767[17]) @[el2_lib.scala 343:95]
node _T_1127 = cat(_T_1126, _T_1125) @[el2_lib.scala 343:95]
node _T_1128 = cat(_T_767[20], _T_767[19]) @[el2_lib.scala 343:95]
node _T_1129 = cat(_T_767[22], _T_767[21]) @[el2_lib.scala 343:95]
node _T_1130 = cat(_T_1129, _T_1128) @[el2_lib.scala 343:95]
node _T_1131 = cat(_T_1130, _T_1127) @[el2_lib.scala 343:95]
node _T_1132 = cat(_T_767[24], _T_767[23]) @[el2_lib.scala 343:95]
node _T_1133 = cat(_T_767[26], _T_767[25]) @[el2_lib.scala 343:95]
node _T_1134 = cat(_T_1133, _T_1132) @[el2_lib.scala 343:95]
node _T_1135 = cat(_T_767[28], _T_767[27]) @[el2_lib.scala 343:95]
node _T_1136 = cat(_T_767[30], _T_767[29]) @[el2_lib.scala 343:95]
node _T_1137 = cat(_T_1136, _T_1135) @[el2_lib.scala 343:95]
node _T_1138 = cat(_T_1137, _T_1134) @[el2_lib.scala 343:95]
node _T_1139 = cat(_T_1138, _T_1131) @[el2_lib.scala 343:95]
node _T_1140 = cat(_T_1139, _T_1124) @[el2_lib.scala 343:95]
node _T_1141 = xorr(_T_1140) @[el2_lib.scala 343:102]
node _T_1142 = cat(_T_768[2], _T_768[1]) @[el2_lib.scala 343:112]
node _T_1143 = cat(_T_1142, _T_768[0]) @[el2_lib.scala 343:112]
node _T_1144 = cat(_T_768[4], _T_768[3]) @[el2_lib.scala 343:112]
node _T_1145 = cat(_T_768[6], _T_768[5]) @[el2_lib.scala 343:112]
node _T_1146 = cat(_T_1145, _T_1144) @[el2_lib.scala 343:112]
node _T_1147 = cat(_T_1146, _T_1143) @[el2_lib.scala 343:112]
node _T_1148 = cat(_T_768[8], _T_768[7]) @[el2_lib.scala 343:112]
node _T_1149 = cat(_T_768[10], _T_768[9]) @[el2_lib.scala 343:112]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1150 = cat(_T_1149, _T_1148) @[el2_lib.scala 343:112]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1151 = cat(_T_768[12], _T_768[11]) @[el2_lib.scala 343:112]
node _T_1152 = cat(_T_768[14], _T_768[13]) @[el2_lib.scala 343:112]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1153 = cat(_T_1152, _T_1151) @[el2_lib.scala 343:112]
node _T_1154 = cat(_T_1153, _T_1150) @[el2_lib.scala 343:112]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1155 = cat(_T_1154, _T_1147) @[el2_lib.scala 343:112]
node _T_1156 = cat(_T_768[16], _T_768[15]) @[el2_lib.scala 343:112]
node _T_1157 = cat(_T_768[18], _T_768[17]) @[el2_lib.scala 343:112]
node _T_1158 = cat(_T_1157, _T_1156) @[el2_lib.scala 343:112]
node _T_1159 = cat(_T_768[20], _T_768[19]) @[el2_lib.scala 343:112]
node _T_1160 = cat(_T_768[22], _T_768[21]) @[el2_lib.scala 343:112]
node _T_1161 = cat(_T_1160, _T_1159) @[el2_lib.scala 343:112]
node _T_1162 = cat(_T_1161, _T_1158) @[el2_lib.scala 343:112]
node _T_1163 = cat(_T_768[24], _T_768[23]) @[el2_lib.scala 343:112]
node _T_1164 = cat(_T_768[26], _T_768[25]) @[el2_lib.scala 343:112]
node _T_1165 = cat(_T_1164, _T_1163) @[el2_lib.scala 343:112]
node _T_1166 = cat(_T_768[28], _T_768[27]) @[el2_lib.scala 343:112]
node _T_1167 = cat(_T_768[30], _T_768[29]) @[el2_lib.scala 343:112]
node _T_1168 = cat(_T_1167, _T_1166) @[el2_lib.scala 343:112]
node _T_1169 = cat(_T_1168, _T_1165) @[el2_lib.scala 343:112]
node _T_1170 = cat(_T_1169, _T_1162) @[el2_lib.scala 343:112]
node _T_1171 = cat(_T_1170, _T_1155) @[el2_lib.scala 343:112]
node _T_1172 = xorr(_T_1171) @[el2_lib.scala 343:119]
node _T_1173 = cat(_T_769[2], _T_769[1]) @[el2_lib.scala 343:129]
node _T_1174 = cat(_T_1173, _T_769[0]) @[el2_lib.scala 343:129]
node _T_1175 = cat(_T_769[4], _T_769[3]) @[el2_lib.scala 343:129]
node _T_1176 = cat(_T_769[6], _T_769[5]) @[el2_lib.scala 343:129]
node _T_1177 = cat(_T_1176, _T_1175) @[el2_lib.scala 343:129]
node _T_1178 = cat(_T_1177, _T_1174) @[el2_lib.scala 343:129]
node _T_1179 = xorr(_T_1178) @[el2_lib.scala 343:136]
node _T_1180 = cat(_T_1141, _T_1172) @[Cat.scala 29:58]
node _T_1181 = cat(_T_1180, _T_1179) @[Cat.scala 29:58]
node _T_1182 = cat(_T_1079, _T_1110) @[Cat.scala 29:58]
node _T_1183 = cat(_T_1009, _T_1044) @[Cat.scala 29:58]
node _T_1184 = cat(_T_1183, _T_1182) @[Cat.scala 29:58]
node ic_miss_buff_ecc = cat(_T_1184, _T_1181) @[Cat.scala 29:58]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ic_wr_16bytes_data : UInt<142>
ic_wr_16bytes_data <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1185 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 391:72]
node _T_1186 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 391:72]
io.ic_wr_data[0] <= _T_1185 @[el2_ifu_mem_ctl.scala 391:17]
io.ic_wr_data[1] <= _T_1186 @[el2_ifu_mem_ctl.scala 391:17]
io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 392:23]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ic_rd_parity_final_err : UInt<1>
ic_rd_parity_final_err <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1187 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 394:56]
node _T_1188 = and(_T_1187, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 394:83]
node _T_1189 = or(_T_1188, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 394:99]
io.ic_error_start <= _T_1189 @[el2_ifu_mem_ctl.scala 394:21]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ic_debug_tag_val_rd_out : UInt<1>
ic_debug_tag_val_rd_out <= UInt<1>("h00")
wire ic_debug_ict_array_sel_ff : UInt<1>
ic_debug_ict_array_sel_ff <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1190 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 397:63]
node _T_1191 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 397:121]
node _T_1192 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 397:161]
node _T_1193 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58]
node _T_1194 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58]
node _T_1195 = cat(_T_1194, _T_1193) @[Cat.scala 29:58]
node _T_1196 = cat(UInt<32>("h00"), _T_1192) @[Cat.scala 29:58]
node _T_1197 = cat(UInt<2>("h00"), _T_1191) @[Cat.scala 29:58]
node _T_1198 = cat(_T_1197, _T_1196) @[Cat.scala 29:58]
node _T_1199 = cat(_T_1198, _T_1195) @[Cat.scala 29:58]
node ifu_ic_debug_rd_data_in = mux(_T_1190, _T_1199, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 397:36]
reg _T_1200 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 400:37]
_T_1200 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 400:37]
io.ifu_ic_debug_rd_data <= _T_1200 @[el2_ifu_mem_ctl.scala 400:27]
node _T_1201 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 401:74]
node _T_1202 = xorr(_T_1201) @[el2_lib.scala 203:13]
node _T_1203 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 401:74]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1204 = xorr(_T_1203) @[el2_lib.scala 203:13]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1205 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 401:74]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1206 = xorr(_T_1205) @[el2_lib.scala 203:13]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1207 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 401:74]
ICCM Done
2020-10-12 19:46:52 +08:00
node _T_1208 = xorr(_T_1207) @[el2_lib.scala 203:13]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1209 = cat(_T_1208, _T_1206) @[Cat.scala 29:58]
node _T_1210 = cat(_T_1209, _T_1204) @[Cat.scala 29:58]
node ic_wr_parity = cat(_T_1210, _T_1202) @[Cat.scala 29:58]
node _T_1211 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 402:82]
node _T_1212 = xorr(_T_1211) @[el2_lib.scala 203:13]
node _T_1213 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 402:82]
node _T_1214 = xorr(_T_1213) @[el2_lib.scala 203:13]
node _T_1215 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 402:82]
node _T_1216 = xorr(_T_1215) @[el2_lib.scala 203:13]
node _T_1217 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 402:82]
node _T_1218 = xorr(_T_1217) @[el2_lib.scala 203:13]
node _T_1219 = cat(_T_1218, _T_1216) @[Cat.scala 29:58]
node _T_1220 = cat(_T_1219, _T_1214) @[Cat.scala 29:58]
node ic_miss_buff_parity = cat(_T_1220, _T_1212) @[Cat.scala 29:58]
node _T_1221 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 404:43]
node _T_1222 = bits(_T_1221, 0, 0) @[el2_ifu_mem_ctl.scala 404:47]
node _T_1223 = bits(ifu_bus_rdata_ff, 63, 0) @[el2_ifu_mem_ctl.scala 404:117]
node _T_1224 = bits(ic_miss_buff_half, 63, 0) @[el2_ifu_mem_ctl.scala 404:201]
node _T_1225 = cat(ic_miss_buff_ecc, _T_1224) @[Cat.scala 29:58]
node _T_1226 = cat(ic_wr_ecc, _T_1223) @[Cat.scala 29:58]
node _T_1227 = cat(_T_1226, _T_1225) @[Cat.scala 29:58]
node _T_1228 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
node _T_1229 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
node _T_1230 = cat(_T_1229, _T_1228) @[Cat.scala 29:58]
node _T_1231 = mux(_T_1222, _T_1227, _T_1230) @[el2_ifu_mem_ctl.scala 404:28]
ic_wr_16bytes_data <= _T_1231 @[el2_ifu_mem_ctl.scala 404:22]
ICCM Done
2020-10-12 19:46:52 +08:00
wire bus_ifu_wr_data_error_ff : UInt<1>
bus_ifu_wr_data_error_ff <= UInt<1>("h00")
wire ifu_wr_data_comb_err_ff : UInt<1>
ifu_wr_data_comb_err_ff <= UInt<1>("h00")
wire reset_beat_cnt : UInt<1>
reset_beat_cnt <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1232 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 410:53]
node _T_1233 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:82]
node ifu_wr_cumulative_err = and(_T_1232, _T_1233) @[el2_ifu_mem_ctl.scala 410:80]
node _T_1234 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 411:55]
ifu_wr_cumulative_err_data <= _T_1234 @[el2_ifu_mem_ctl.scala 411:30]
reg _T_1235 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 412:61]
_T_1235 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 412:61]
ifu_wr_data_comb_err_ff <= _T_1235 @[el2_ifu_mem_ctl.scala 412:27]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ic_crit_wd_rdy : UInt<1>
ic_crit_wd_rdy <= UInt<1>("h00")
wire ifu_byp_data_err_new : UInt<1>
ifu_byp_data_err_new <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1236 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 415:51]
node _T_1237 = or(ic_crit_wd_rdy, _T_1236) @[el2_ifu_mem_ctl.scala 415:38]
node _T_1238 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 415:77]
node _T_1239 = or(_T_1237, _T_1238) @[el2_ifu_mem_ctl.scala 415:64]
node _T_1240 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 415:98]
node sel_byp_data = and(_T_1239, _T_1240) @[el2_ifu_mem_ctl.scala 415:96]
node _T_1241 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 416:51]
node _T_1242 = or(ic_crit_wd_rdy, _T_1241) @[el2_ifu_mem_ctl.scala 416:38]
node _T_1243 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 416:77]
node _T_1244 = or(_T_1242, _T_1243) @[el2_ifu_mem_ctl.scala 416:64]
node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:21]
node _T_1246 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:98]
node sel_ic_data = and(_T_1245, _T_1246) @[el2_ifu_mem_ctl.scala 416:96]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ic_byp_data_only_new : UInt<80>
ic_byp_data_only_new <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1247 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 420:81]
node _T_1248 = or(sel_byp_data, _T_1247) @[el2_ifu_mem_ctl.scala 420:47]
node _T_1249 = bits(_T_1248, 0, 0) @[el2_ifu_mem_ctl.scala 420:140]
node _T_1250 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15]
node _T_1251 = mux(_T_1250, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
node _T_1252 = and(_T_1251, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 422:64]
node _T_1253 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15]
node _T_1254 = mux(_T_1253, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
node _T_1255 = and(_T_1254, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 422:109]
node ic_premux_data = or(_T_1252, _T_1255) @[el2_ifu_mem_ctl.scala 422:83]
node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 424:58]
node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 426:42]
node _T_1256 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 428:40]
node fetch_req_f_qual = and(io.ic_hit_f, _T_1256) @[el2_ifu_mem_ctl.scala 428:38]
ICCM Done
2020-10-12 19:46:52 +08:00
wire ifc_region_acc_fault_memory_f : UInt<1>
ifc_region_acc_fault_memory_f <= UInt<1>("h00")
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_1257 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 430:57]
node _T_1258 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 430:82]
node _T_1259 = and(_T_1257, _T_1258) @[el2_ifu_mem_ctl.scala 430:80]
io.ic_access_fault_f <= _T_1259 @[el2_ifu_mem_ctl.scala 430:24]
node _T_1260 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 431:62]
node _T_1261 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 432:32]
node _T_1262 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 433:47]
node _T_1263 = mux(_T_1262, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 433:10]
node _T_1264 = mux(_T_1261, UInt<2>("h02"), _T_1263) @[el2_ifu_mem_ctl.scala 432:8]
node _T_1265 = mux(_T_1260, UInt<1>("h01"), _T_1264) @[el2_ifu_mem_ctl.scala 431:35]
io.ic_access_fault_type_f <= _T_1265 @[el2_ifu_mem_ctl.scala 431:29]
wire ifu_bp_inst_mask_f : UInt<1>
ifu_bp_inst_mask_f <= UInt<1>("h00")
node _T_1266 = and(fetch_req_f_qual, ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 435:45]
node _T_1267 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_1268 = eq(ifu_fetch_addr_int_f, _T_1267) @[el2_ifu_mem_ctl.scala 435:77]
node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 435:68]
node _T_1270 = and(_T_1266, _T_1269) @[el2_ifu_mem_ctl.scala 435:66]
node _T_1271 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 435:128]
node _T_1272 = and(_T_1270, _T_1271) @[el2_ifu_mem_ctl.scala 435:111]
node _T_1273 = cat(_T_1272, fetch_req_f_qual) @[Cat.scala 29:58]
io.ic_fetch_val_f <= _T_1273 @[el2_ifu_mem_ctl.scala 435:21]
node _T_1274 = bits(io.ic_rd_data, 1, 0) @[el2_ifu_mem_ctl.scala 436:33]
node two_byte_instr = neq(_T_1274, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:39]
wire ic_miss_buff_data_in : UInt<64>
ic_miss_buff_data_in <= UInt<1>("h00")
wire ifu_bus_rsp_tag : UInt<3>
ifu_bus_rsp_tag <= UInt<1>("h00")
wire bus_ifu_wr_en : UInt<1>
bus_ifu_wr_en <= UInt<1>("h00")
node _T_1275 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_0 = and(bus_ifu_wr_en, _T_1275) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1276 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_1 = and(bus_ifu_wr_en, _T_1276) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1277 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_2 = and(bus_ifu_wr_en, _T_1277) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1278 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_3 = and(bus_ifu_wr_en, _T_1278) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1279 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_4 = and(bus_ifu_wr_en, _T_1279) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1280 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_5 = and(bus_ifu_wr_en, _T_1280) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1281 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_6 = and(bus_ifu_wr_en, _T_1281) @[el2_ifu_mem_ctl.scala 442:73]
node _T_1282 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:91]
node write_fill_data_7 = and(bus_ifu_wr_en, _T_1282) @[el2_ifu_mem_ctl.scala 442:73]
wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 443:31]
node _T_1283 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1284 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1283 : @[Reg.scala 28:19]
_T_1284 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[0] <= _T_1284 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1285 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1286 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1285 : @[Reg.scala 28:19]
_T_1286 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[1] <= _T_1286 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1287 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1288 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1287 : @[Reg.scala 28:19]
_T_1288 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[2] <= _T_1288 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1289 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1290 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1289 : @[Reg.scala 28:19]
_T_1290 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[3] <= _T_1290 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1291 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1292 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1291 : @[Reg.scala 28:19]
_T_1292 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[4] <= _T_1292 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1293 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1294 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1293 : @[Reg.scala 28:19]
_T_1294 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[5] <= _T_1294 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1295 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1296 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1295 : @[Reg.scala 28:19]
_T_1296 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[6] <= _T_1296 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1297 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1297 : @[Reg.scala 28:19]
_T_1298 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[7] <= _T_1298 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1299 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1299 : @[Reg.scala 28:19]
_T_1300 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[8] <= _T_1300 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1301 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1301 : @[Reg.scala 28:19]
_T_1302 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[9] <= _T_1302 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1303 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1304 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1303 : @[Reg.scala 28:19]
_T_1304 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[10] <= _T_1304 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1305 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1305 : @[Reg.scala 28:19]
_T_1306 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[11] <= _T_1306 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1307 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1307 : @[Reg.scala 28:19]
_T_1308 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[12] <= _T_1308 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1309 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1309 : @[Reg.scala 28:19]
_T_1310 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[13] <= _T_1310 @[el2_ifu_mem_ctl.scala 446:28]
node _T_1311 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
reg _T_1312 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1311 : @[Reg.scala 28:19]
_T_1312 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[14] <= _T_1312 @[el2_ifu_mem_ctl.scala 445:26]
node _T_1313 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
reg _T_1314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_1313 : @[Reg.scala 28:19]
_T_1314 <= ic_miss_buff_data_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ic_miss_buff_data[15] <= _T_1314 @[el2_ifu_mem_ctl.scala 446:28]
wire ic_miss_buff_data_valid : UInt<8>
ic_miss_buff_data_valid <= UInt<1>("h00")
node _T_1315 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1316 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1317 = and(_T_1315, _T_1316) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1317) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1318 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1319 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1320 = and(_T_1318, _T_1319) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1320) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1321 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1322 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1323 = and(_T_1321, _T_1322) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1323) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1324 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1325 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1326 = and(_T_1324, _T_1325) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1326) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1327 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1328 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1329 = and(_T_1327, _T_1328) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1329) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1330 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1331 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1332 = and(_T_1330, _T_1331) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1332) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1333 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1334 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1335 = and(_T_1333, _T_1334) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1335) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1336 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 448:113]
node _T_1337 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
node _T_1338 = and(_T_1336, _T_1337) @[el2_ifu_mem_ctl.scala 448:116]
node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1338) @[el2_ifu_mem_ctl.scala 448:88]
node _T_1339 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58]
node _T_1340 = cat(_T_1339, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58]
node _T_1341 = cat(_T_1340, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58]
node _T_1342 = cat(_T_1341, ic_miss_buff_data_valid_in_3) @[Cat.scala 29:58]
node _T_1343 = cat(_T_1342, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58]
node _T_1344 = cat(_T_1343, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58]
node _T_1345 = cat(_T_1344, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58]
reg _T_1346 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 449:60]
_T_1346 <= _T_1345 @[el2_ifu_mem_ctl.scala 449:60]
ic_miss_buff_data_valid <= _T_1346 @[el2_ifu_mem_ctl.scala 449:27]
wire bus_ifu_wr_data_error : UInt<1>
bus_ifu_wr_data_error <= UInt<1>("h00")
wire ic_miss_buff_data_error : UInt<8>
ic_miss_buff_data_error <= UInt<1>("h00")
node _T_1347 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1348 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1349 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1350 = and(_T_1348, _T_1349) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_0 = mux(_T_1347, bus_ifu_wr_data_error, _T_1350) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1351 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1352 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1353 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1354 = and(_T_1352, _T_1353) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_1 = mux(_T_1351, bus_ifu_wr_data_error, _T_1354) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1355 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1356 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1357 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1358 = and(_T_1356, _T_1357) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_2 = mux(_T_1355, bus_ifu_wr_data_error, _T_1358) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1359 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1360 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1361 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1362 = and(_T_1360, _T_1361) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_3 = mux(_T_1359, bus_ifu_wr_data_error, _T_1362) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1363 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1364 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1365 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1366 = and(_T_1364, _T_1365) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_4 = mux(_T_1363, bus_ifu_wr_data_error, _T_1366) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1367 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1368 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1369 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1370 = and(_T_1368, _T_1369) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_5 = mux(_T_1367, bus_ifu_wr_data_error, _T_1370) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1371 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1372 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1373 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1374 = and(_T_1372, _T_1373) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_6 = mux(_T_1371, bus_ifu_wr_data_error, _T_1374) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1375 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
node _T_1376 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 453:28]
node _T_1377 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
node _T_1378 = and(_T_1376, _T_1377) @[el2_ifu_mem_ctl.scala 453:32]
node ic_miss_buff_data_error_in_7 = mux(_T_1375, bus_ifu_wr_data_error, _T_1378) @[el2_ifu_mem_ctl.scala 452:72]
node _T_1379 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58]
node _T_1380 = cat(_T_1379, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58]
node _T_1381 = cat(_T_1380, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58]
node _T_1382 = cat(_T_1381, ic_miss_buff_data_error_in_3) @[Cat.scala 29:58]
node _T_1383 = cat(_T_1382, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58]
node _T_1384 = cat(_T_1383, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58]
node _T_1385 = cat(_T_1384, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58]
reg _T_1386 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 454:60]
_T_1386 <= _T_1385 @[el2_ifu_mem_ctl.scala 454:60]
ic_miss_buff_data_error <= _T_1386 @[el2_ifu_mem_ctl.scala 454:27]
node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 457:28]
node _T_1387 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 458:42]
node _T_1388 = add(_T_1387, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 458:70]
node bypass_index_5_3_inc = tail(_T_1388, 1) @[el2_ifu_mem_ctl.scala 458:70]
node _T_1389 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1390 = eq(_T_1389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1391 = bits(_T_1390, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1392 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1393 = eq(_T_1392, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1394 = bits(_T_1393, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1395 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1396 = eq(_T_1395, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1397 = bits(_T_1396, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1398 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1399 = eq(_T_1398, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1400 = bits(_T_1399, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1401 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1402 = eq(_T_1401, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1403 = bits(_T_1402, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1404 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1405 = eq(_T_1404, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1406 = bits(_T_1405, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1407 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1408 = eq(_T_1407, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1409 = bits(_T_1408, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1410 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
node _T_1411 = eq(_T_1410, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 459:114]
node _T_1412 = bits(_T_1411, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
node _T_1413 = mux(_T_1391, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1414 = mux(_T_1394, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1415 = mux(_T_1397, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1416 = mux(_T_1400, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1417 = mux(_T_1403, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1418 = mux(_T_1406, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1419 = mux(_T_1409, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1420 = mux(_T_1412, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1421 = or(_T_1413, _T_1414) @[Mux.scala 27:72]
node _T_1422 = or(_T_1421, _T_1415) @[Mux.scala 27:72]
node _T_1423 = or(_T_1422, _T_1416) @[Mux.scala 27:72]
node _T_1424 = or(_T_1423, _T_1417) @[Mux.scala 27:72]
node _T_1425 = or(_T_1424, _T_1418) @[Mux.scala 27:72]
node _T_1426 = or(_T_1425, _T_1419) @[Mux.scala 27:72]
node _T_1427 = or(_T_1426, _T_1420) @[Mux.scala 27:72]
wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72]
bypass_valid_value_check <= _T_1427 @[Mux.scala 27:72]
node _T_1428 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 460:71]
node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:58]
node _T_1430 = and(bypass_valid_value_check, _T_1429) @[el2_ifu_mem_ctl.scala 460:56]
node _T_1431 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 460:90]
node _T_1432 = eq(_T_1431, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:77]
node _T_1433 = and(_T_1430, _T_1432) @[el2_ifu_mem_ctl.scala 460:75]
node _T_1434 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 461:71]
node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 461:58]
node _T_1436 = and(bypass_valid_value_check, _T_1435) @[el2_ifu_mem_ctl.scala 461:56]
node _T_1437 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 461:89]
node _T_1438 = and(_T_1436, _T_1437) @[el2_ifu_mem_ctl.scala 461:75]
node _T_1439 = or(_T_1433, _T_1438) @[el2_ifu_mem_ctl.scala 460:95]
node _T_1440 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 462:70]
node _T_1441 = and(bypass_valid_value_check, _T_1440) @[el2_ifu_mem_ctl.scala 462:56]
node _T_1442 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 462:89]
node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 462:76]
node _T_1444 = and(_T_1441, _T_1443) @[el2_ifu_mem_ctl.scala 462:74]
node _T_1445 = or(_T_1439, _T_1444) @[el2_ifu_mem_ctl.scala 461:94]
node _T_1446 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 463:47]
node _T_1447 = and(bypass_valid_value_check, _T_1446) @[el2_ifu_mem_ctl.scala 463:33]
node _T_1448 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 463:65]
node _T_1449 = and(_T_1447, _T_1448) @[el2_ifu_mem_ctl.scala 463:51]
node _T_1450 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1451 = bits(_T_1450, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1452 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1453 = bits(_T_1452, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1454 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1455 = bits(_T_1454, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1456 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1457 = bits(_T_1456, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1458 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1459 = bits(_T_1458, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1460 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1461 = bits(_T_1460, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1462 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1463 = bits(_T_1462, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1464 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 463:132]
node _T_1465 = bits(_T_1464, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
node _T_1466 = mux(_T_1451, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1467 = mux(_T_1453, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1468 = mux(_T_1455, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1469 = mux(_T_1457, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1470 = mux(_T_1459, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1471 = mux(_T_1461, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1472 = mux(_T_1463, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1473 = mux(_T_1465, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1474 = or(_T_1466, _T_1467) @[Mux.scala 27:72]
node _T_1475 = or(_T_1474, _T_1468) @[Mux.scala 27:72]
node _T_1476 = or(_T_1475, _T_1469) @[Mux.scala 27:72]
node _T_1477 = or(_T_1476, _T_1470) @[Mux.scala 27:72]
node _T_1478 = or(_T_1477, _T_1471) @[Mux.scala 27:72]
node _T_1479 = or(_T_1478, _T_1472) @[Mux.scala 27:72]
node _T_1480 = or(_T_1479, _T_1473) @[Mux.scala 27:72]
wire _T_1481 : UInt<1> @[Mux.scala 27:72]
_T_1481 <= _T_1480 @[Mux.scala 27:72]
node _T_1482 = and(_T_1449, _T_1481) @[el2_ifu_mem_ctl.scala 463:69]
node _T_1483 = or(_T_1445, _T_1482) @[el2_ifu_mem_ctl.scala 462:94]
node _T_1484 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 464:70]
node _T_1485 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_1486 = eq(_T_1484, _T_1485) @[el2_ifu_mem_ctl.scala 464:95]
node _T_1487 = and(bypass_valid_value_check, _T_1486) @[el2_ifu_mem_ctl.scala 464:56]
node bypass_data_ready_in = or(_T_1483, _T_1487) @[el2_ifu_mem_ctl.scala 463:181]
io.test <= bypass_data_ready_in @[el2_ifu_mem_ctl.scala 466:11]
wire ic_crit_wd_rdy_new_ff : UInt<1>
ic_crit_wd_rdy_new_ff <= UInt<1>("h00")
node _T_1488 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 468:53]
node _T_1489 = and(_T_1488, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 468:73]
node _T_1490 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 468:98]
node _T_1491 = and(_T_1489, _T_1490) @[el2_ifu_mem_ctl.scala 468:96]
node _T_1492 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 468:120]
node _T_1493 = and(_T_1491, _T_1492) @[el2_ifu_mem_ctl.scala 468:118]
node _T_1494 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 469:75]
node _T_1495 = and(crit_wd_byp_ok_ff, _T_1494) @[el2_ifu_mem_ctl.scala 469:73]
node _T_1496 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 469:98]
node _T_1497 = and(_T_1495, _T_1496) @[el2_ifu_mem_ctl.scala 469:96]
node _T_1498 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 469:120]
node _T_1499 = and(_T_1497, _T_1498) @[el2_ifu_mem_ctl.scala 469:118]
node _T_1500 = or(_T_1493, _T_1499) @[el2_ifu_mem_ctl.scala 468:143]
node _T_1501 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 470:54]
node _T_1502 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 470:76]
node _T_1503 = and(_T_1501, _T_1502) @[el2_ifu_mem_ctl.scala 470:74]
node _T_1504 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 470:98]
node _T_1505 = and(_T_1503, _T_1504) @[el2_ifu_mem_ctl.scala 470:96]
node ic_crit_wd_rdy_new_in = or(_T_1500, _T_1505) @[el2_ifu_mem_ctl.scala 469:143]
reg _T_1506 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 471:58]
_T_1506 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 471:58]
ic_crit_wd_rdy_new_ff <= _T_1506 @[el2_ifu_mem_ctl.scala 471:25]
node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 472:45]
node _T_1507 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 473:51]
node byp_fetch_index_0 = cat(_T_1507, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_1508 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 474:51]
node byp_fetch_index_1 = cat(_T_1508, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_1509 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 475:49]
node _T_1510 = add(_T_1509, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 475:75]
node byp_fetch_index_inc = tail(_T_1510, 1) @[el2_ifu_mem_ctl.scala 475:75]
node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58]
node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_1511 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1513 = bits(_T_1512, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1514 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1515 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1516 = eq(_T_1515, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1517 = bits(_T_1516, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1518 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1519 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1520 = eq(_T_1519, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1521 = bits(_T_1520, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1522 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1523 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1524 = eq(_T_1523, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1525 = bits(_T_1524, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1526 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1527 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1528 = eq(_T_1527, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1529 = bits(_T_1528, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1530 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1531 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1532 = eq(_T_1531, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1533 = bits(_T_1532, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1534 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1535 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1536 = eq(_T_1535, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1537 = bits(_T_1536, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1538 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1539 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
node _T_1540 = eq(_T_1539, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 478:118]
node _T_1541 = bits(_T_1540, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
node _T_1542 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 478:157]
node _T_1543 = mux(_T_1513, _T_1514, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1544 = mux(_T_1517, _T_1518, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1545 = mux(_T_1521, _T_1522, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1546 = mux(_T_1525, _T_1526, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1547 = mux(_T_1529, _T_1530, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1548 = mux(_T_1533, _T_1534, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1549 = mux(_T_1537, _T_1538, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1550 = mux(_T_1541, _T_1542, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1551 = or(_T_1543, _T_1544) @[Mux.scala 27:72]
node _T_1552 = or(_T_1551, _T_1545) @[Mux.scala 27:72]
node _T_1553 = or(_T_1552, _T_1546) @[Mux.scala 27:72]
node _T_1554 = or(_T_1553, _T_1547) @[Mux.scala 27:72]
node _T_1555 = or(_T_1554, _T_1548) @[Mux.scala 27:72]
node _T_1556 = or(_T_1555, _T_1549) @[Mux.scala 27:72]
node _T_1557 = or(_T_1556, _T_1550) @[Mux.scala 27:72]
wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72]
ic_miss_buff_data_error_bypass <= _T_1557 @[Mux.scala 27:72]
node _T_1558 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1559 = bits(_T_1558, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1560 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1561 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1562 = bits(_T_1561, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1563 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1564 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1565 = bits(_T_1564, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1566 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1567 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1568 = bits(_T_1567, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1569 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1570 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1571 = bits(_T_1570, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1572 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1573 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1574 = bits(_T_1573, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1575 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1576 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1577 = bits(_T_1576, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1578 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1579 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 479:104]
node _T_1580 = bits(_T_1579, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
node _T_1581 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 479:143]
node _T_1582 = mux(_T_1559, _T_1560, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1583 = mux(_T_1562, _T_1563, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1584 = mux(_T_1565, _T_1566, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1585 = mux(_T_1568, _T_1569, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1586 = mux(_T_1571, _T_1572, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1587 = mux(_T_1574, _T_1575, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1588 = mux(_T_1577, _T_1578, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1589 = mux(_T_1580, _T_1581, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1590 = or(_T_1582, _T_1583) @[Mux.scala 27:72]
node _T_1591 = or(_T_1590, _T_1584) @[Mux.scala 27:72]
node _T_1592 = or(_T_1591, _T_1585) @[Mux.scala 27:72]
node _T_1593 = or(_T_1592, _T_1586) @[Mux.scala 27:72]
node _T_1594 = or(_T_1593, _T_1587) @[Mux.scala 27:72]
node _T_1595 = or(_T_1594, _T_1588) @[Mux.scala 27:72]
node _T_1596 = or(_T_1595, _T_1589) @[Mux.scala 27:72]
wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72]
ic_miss_buff_data_error_bypass_inc <= _T_1596 @[Mux.scala 27:72]
node _T_1597 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 482:28]
node _T_1598 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 482:52]
node _T_1599 = and(_T_1597, _T_1598) @[el2_ifu_mem_ctl.scala 482:31]
when _T_1599 : @[el2_ifu_mem_ctl.scala 482:56]
ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 483:26]
skip @[el2_ifu_mem_ctl.scala 482:56]
else : @[el2_ifu_mem_ctl.scala 484:5]
node _T_1600 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 484:70]
ifu_byp_data_err_new <= _T_1600 @[el2_ifu_mem_ctl.scala 484:36]
skip @[el2_ifu_mem_ctl.scala 484:5]
node _T_1601 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 486:59]
node _T_1602 = bits(_T_1601, 0, 0) @[el2_ifu_mem_ctl.scala 486:63]
node _T_1603 = eq(_T_1602, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 486:38]
node _T_1604 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1605 = bits(_T_1604, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1606 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1607 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1608 = bits(_T_1607, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1609 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1610 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1611 = bits(_T_1610, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1612 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1613 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1614 = bits(_T_1613, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1615 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1616 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1617 = bits(_T_1616, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1618 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1619 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1620 = bits(_T_1619, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1621 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1622 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1623 = bits(_T_1622, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1624 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1625 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1626 = bits(_T_1625, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1627 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1628 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1629 = bits(_T_1628, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1630 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1631 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1632 = bits(_T_1631, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1633 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1634 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1635 = bits(_T_1634, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1636 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1637 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1638 = bits(_T_1637, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1639 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1640 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1641 = bits(_T_1640, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1642 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1643 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1644 = bits(_T_1643, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1645 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1646 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1647 = bits(_T_1646, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1648 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1649 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 487:73]
node _T_1650 = bits(_T_1649, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
node _T_1651 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
node _T_1652 = mux(_T_1605, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1653 = mux(_T_1608, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1654 = mux(_T_1611, _T_1612, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1655 = mux(_T_1614, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1656 = mux(_T_1617, _T_1618, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1657 = mux(_T_1620, _T_1621, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1658 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1659 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1660 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1661 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1662 = mux(_T_1635, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1663 = mux(_T_1638, _T_1639, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1664 = mux(_T_1641, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1665 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1666 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1667 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1668 = or(_T_1652, _T_1653) @[Mux.scala 27:72]
node _T_1669 = or(_T_1668, _T_1654) @[Mux.scala 27:72]
node _T_1670 = or(_T_1669, _T_1655) @[Mux.scala 27:72]
node _T_1671 = or(_T_1670, _T_1656) @[Mux.scala 27:72]
node _T_1672 = or(_T_1671, _T_1657) @[Mux.scala 27:72]
node _T_1673 = or(_T_1672, _T_1658) @[Mux.scala 27:72]
node _T_1674 = or(_T_1673, _T_1659) @[Mux.scala 27:72]
node _T_1675 = or(_T_1674, _T_1660) @[Mux.scala 27:72]
node _T_1676 = or(_T_1675, _T_1661) @[Mux.scala 27:72]
node _T_1677 = or(_T_1676, _T_1662) @[Mux.scala 27:72]
node _T_1678 = or(_T_1677, _T_1663) @[Mux.scala 27:72]
node _T_1679 = or(_T_1678, _T_1664) @[Mux.scala 27:72]
node _T_1680 = or(_T_1679, _T_1665) @[Mux.scala 27:72]
node _T_1681 = or(_T_1680, _T_1666) @[Mux.scala 27:72]
node _T_1682 = or(_T_1681, _T_1667) @[Mux.scala 27:72]
wire _T_1683 : UInt<16> @[Mux.scala 27:72]
_T_1683 <= _T_1682 @[Mux.scala 27:72]
node _T_1684 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1685 = bits(_T_1684, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1686 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1687 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1688 = bits(_T_1687, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1689 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1690 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1691 = bits(_T_1690, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1692 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1693 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1694 = bits(_T_1693, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1695 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1696 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1697 = bits(_T_1696, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1698 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1699 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1700 = bits(_T_1699, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1701 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1702 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1703 = bits(_T_1702, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1704 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1705 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1706 = bits(_T_1705, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1707 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1708 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1709 = bits(_T_1708, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1710 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1711 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1712 = bits(_T_1711, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1713 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1714 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1715 = bits(_T_1714, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1716 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1717 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1718 = bits(_T_1717, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1719 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1720 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1721 = bits(_T_1720, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1722 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1723 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1724 = bits(_T_1723, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1725 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1726 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1727 = bits(_T_1726, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1728 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1729 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 487:179]
node _T_1730 = bits(_T_1729, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
node _T_1731 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
node _T_1732 = mux(_T_1685, _T_1686, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1733 = mux(_T_1688, _T_1689, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1734 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1735 = mux(_T_1694, _T_1695, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1736 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1737 = mux(_T_1700, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1738 = mux(_T_1703, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1739 = mux(_T_1706, _T_1707, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1740 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1741 = mux(_T_1712, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1742 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1743 = mux(_T_1718, _T_1719, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1744 = mux(_T_1721, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1745 = mux(_T_1724, _T_1725, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1746 = mux(_T_1727, _T_1728, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1747 = mux(_T_1730, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1748 = or(_T_1732, _T_1733) @[Mux.scala 27:72]
node _T_1749 = or(_T_1748, _T_1734) @[Mux.scala 27:72]
node _T_1750 = or(_T_1749, _T_1735) @[Mux.scala 27:72]
node _T_1751 = or(_T_1750, _T_1736) @[Mux.scala 27:72]
node _T_1752 = or(_T_1751, _T_1737) @[Mux.scala 27:72]
node _T_1753 = or(_T_1752, _T_1738) @[Mux.scala 27:72]
node _T_1754 = or(_T_1753, _T_1739) @[Mux.scala 27:72]
node _T_1755 = or(_T_1754, _T_1740) @[Mux.scala 27:72]
node _T_1756 = or(_T_1755, _T_1741) @[Mux.scala 27:72]
node _T_1757 = or(_T_1756, _T_1742) @[Mux.scala 27:72]
node _T_1758 = or(_T_1757, _T_1743) @[Mux.scala 27:72]
node _T_1759 = or(_T_1758, _T_1744) @[Mux.scala 27:72]
node _T_1760 = or(_T_1759, _T_1745) @[Mux.scala 27:72]
node _T_1761 = or(_T_1760, _T_1746) @[Mux.scala 27:72]
node _T_1762 = or(_T_1761, _T_1747) @[Mux.scala 27:72]
wire _T_1763 : UInt<32> @[Mux.scala 27:72]
_T_1763 <= _T_1762 @[Mux.scala 27:72]
node _T_1764 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1765 = bits(_T_1764, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1766 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1767 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1768 = bits(_T_1767, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1769 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1770 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1771 = bits(_T_1770, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1772 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1773 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1774 = bits(_T_1773, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1775 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1776 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1777 = bits(_T_1776, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1778 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1779 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1780 = bits(_T_1779, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1781 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1782 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1783 = bits(_T_1782, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1784 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1785 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1786 = bits(_T_1785, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1787 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1788 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1789 = bits(_T_1788, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1790 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1791 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1792 = bits(_T_1791, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1793 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1794 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1795 = bits(_T_1794, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1796 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1797 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1798 = bits(_T_1797, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1799 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1800 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1801 = bits(_T_1800, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1802 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1803 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1804 = bits(_T_1803, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1805 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1806 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1807 = bits(_T_1806, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1808 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1809 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 487:285]
node _T_1810 = bits(_T_1809, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
node _T_1811 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
node _T_1812 = mux(_T_1765, _T_1766, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1813 = mux(_T_1768, _T_1769, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1814 = mux(_T_1771, _T_1772, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1815 = mux(_T_1774, _T_1775, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1816 = mux(_T_1777, _T_1778, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1817 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1818 = mux(_T_1783, _T_1784, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1819 = mux(_T_1786, _T_1787, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1820 = mux(_T_1789, _T_1790, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1821 = mux(_T_1792, _T_1793, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1822 = mux(_T_1795, _T_1796, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1823 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1824 = mux(_T_1801, _T_1802, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1825 = mux(_T_1804, _T_1805, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1826 = mux(_T_1807, _T_1808, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1827 = mux(_T_1810, _T_1811, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1828 = or(_T_1812, _T_1813) @[Mux.scala 27:72]
node _T_1829 = or(_T_1828, _T_1814) @[Mux.scala 27:72]
node _T_1830 = or(_T_1829, _T_1815) @[Mux.scala 27:72]
node _T_1831 = or(_T_1830, _T_1816) @[Mux.scala 27:72]
node _T_1832 = or(_T_1831, _T_1817) @[Mux.scala 27:72]
node _T_1833 = or(_T_1832, _T_1818) @[Mux.scala 27:72]
node _T_1834 = or(_T_1833, _T_1819) @[Mux.scala 27:72]
node _T_1835 = or(_T_1834, _T_1820) @[Mux.scala 27:72]
node _T_1836 = or(_T_1835, _T_1821) @[Mux.scala 27:72]
node _T_1837 = or(_T_1836, _T_1822) @[Mux.scala 27:72]
node _T_1838 = or(_T_1837, _T_1823) @[Mux.scala 27:72]
node _T_1839 = or(_T_1838, _T_1824) @[Mux.scala 27:72]
node _T_1840 = or(_T_1839, _T_1825) @[Mux.scala 27:72]
node _T_1841 = or(_T_1840, _T_1826) @[Mux.scala 27:72]
node _T_1842 = or(_T_1841, _T_1827) @[Mux.scala 27:72]
wire _T_1843 : UInt<32> @[Mux.scala 27:72]
_T_1843 <= _T_1842 @[Mux.scala 27:72]
node _T_1844 = cat(_T_1683, _T_1763) @[Cat.scala 29:58]
node _T_1845 = cat(_T_1844, _T_1843) @[Cat.scala 29:58]
node _T_1846 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1847 = bits(_T_1846, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1848 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1849 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1850 = bits(_T_1849, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1851 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1852 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1853 = bits(_T_1852, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1854 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1855 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1856 = bits(_T_1855, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1857 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1858 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1859 = bits(_T_1858, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1860 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1861 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1862 = bits(_T_1861, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1863 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1864 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1865 = bits(_T_1864, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1866 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1867 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1868 = bits(_T_1867, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1869 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1870 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1871 = bits(_T_1870, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1872 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1873 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1874 = bits(_T_1873, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1875 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1876 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1877 = bits(_T_1876, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1878 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1879 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1880 = bits(_T_1879, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1881 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1882 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1883 = bits(_T_1882, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1884 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1885 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1886 = bits(_T_1885, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1887 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1888 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1889 = bits(_T_1888, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1890 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1891 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 488:73]
node _T_1892 = bits(_T_1891, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
node _T_1893 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
node _T_1894 = mux(_T_1847, _T_1848, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1895 = mux(_T_1850, _T_1851, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1896 = mux(_T_1853, _T_1854, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1897 = mux(_T_1856, _T_1857, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1898 = mux(_T_1859, _T_1860, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1899 = mux(_T_1862, _T_1863, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1900 = mux(_T_1865, _T_1866, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1901 = mux(_T_1868, _T_1869, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1902 = mux(_T_1871, _T_1872, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1903 = mux(_T_1874, _T_1875, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1904 = mux(_T_1877, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1905 = mux(_T_1880, _T_1881, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1906 = mux(_T_1883, _T_1884, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1907 = mux(_T_1886, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1908 = mux(_T_1889, _T_1890, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1909 = mux(_T_1892, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1910 = or(_T_1894, _T_1895) @[Mux.scala 27:72]
node _T_1911 = or(_T_1910, _T_1896) @[Mux.scala 27:72]
node _T_1912 = or(_T_1911, _T_1897) @[Mux.scala 27:72]
node _T_1913 = or(_T_1912, _T_1898) @[Mux.scala 27:72]
node _T_1914 = or(_T_1913, _T_1899) @[Mux.scala 27:72]
node _T_1915 = or(_T_1914, _T_1900) @[Mux.scala 27:72]
node _T_1916 = or(_T_1915, _T_1901) @[Mux.scala 27:72]
node _T_1917 = or(_T_1916, _T_1902) @[Mux.scala 27:72]
node _T_1918 = or(_T_1917, _T_1903) @[Mux.scala 27:72]
node _T_1919 = or(_T_1918, _T_1904) @[Mux.scala 27:72]
node _T_1920 = or(_T_1919, _T_1905) @[Mux.scala 27:72]
node _T_1921 = or(_T_1920, _T_1906) @[Mux.scala 27:72]
node _T_1922 = or(_T_1921, _T_1907) @[Mux.scala 27:72]
node _T_1923 = or(_T_1922, _T_1908) @[Mux.scala 27:72]
node _T_1924 = or(_T_1923, _T_1909) @[Mux.scala 27:72]
wire _T_1925 : UInt<16> @[Mux.scala 27:72]
_T_1925 <= _T_1924 @[Mux.scala 27:72]
node _T_1926 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1927 = bits(_T_1926, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1928 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1929 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1930 = bits(_T_1929, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1931 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1932 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1933 = bits(_T_1932, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1934 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1935 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1936 = bits(_T_1935, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1937 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1938 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1939 = bits(_T_1938, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1940 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1941 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1942 = bits(_T_1941, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1943 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1944 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1945 = bits(_T_1944, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1946 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1947 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1948 = bits(_T_1947, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1949 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1950 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1951 = bits(_T_1950, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1952 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1953 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1954 = bits(_T_1953, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1955 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1956 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1957 = bits(_T_1956, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1958 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1959 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1960 = bits(_T_1959, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1961 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1962 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1963 = bits(_T_1962, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1964 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1965 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1966 = bits(_T_1965, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1967 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1968 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1969 = bits(_T_1968, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1970 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1971 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 488:183]
node _T_1972 = bits(_T_1971, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
node _T_1973 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
node _T_1974 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1975 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1976 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1977 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1978 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1979 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1980 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1981 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1982 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1983 = mux(_T_1954, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1984 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1985 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1986 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1987 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1988 = mux(_T_1969, _T_1970, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1989 = mux(_T_1972, _T_1973, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1990 = or(_T_1974, _T_1975) @[Mux.scala 27:72]
node _T_1991 = or(_T_1990, _T_1976) @[Mux.scala 27:72]
node _T_1992 = or(_T_1991, _T_1977) @[Mux.scala 27:72]
node _T_1993 = or(_T_1992, _T_1978) @[Mux.scala 27:72]
node _T_1994 = or(_T_1993, _T_1979) @[Mux.scala 27:72]
node _T_1995 = or(_T_1994, _T_1980) @[Mux.scala 27:72]
node _T_1996 = or(_T_1995, _T_1981) @[Mux.scala 27:72]
node _T_1997 = or(_T_1996, _T_1982) @[Mux.scala 27:72]
node _T_1998 = or(_T_1997, _T_1983) @[Mux.scala 27:72]
node _T_1999 = or(_T_1998, _T_1984) @[Mux.scala 27:72]
node _T_2000 = or(_T_1999, _T_1985) @[Mux.scala 27:72]
node _T_2001 = or(_T_2000, _T_1986) @[Mux.scala 27:72]
node _T_2002 = or(_T_2001, _T_1987) @[Mux.scala 27:72]
node _T_2003 = or(_T_2002, _T_1988) @[Mux.scala 27:72]
node _T_2004 = or(_T_2003, _T_1989) @[Mux.scala 27:72]
wire _T_2005 : UInt<32> @[Mux.scala 27:72]
_T_2005 <= _T_2004 @[Mux.scala 27:72]
node _T_2006 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2007 = bits(_T_2006, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2008 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2009 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2010 = bits(_T_2009, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2011 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2012 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2013 = bits(_T_2012, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2014 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2015 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2016 = bits(_T_2015, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2017 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2018 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2019 = bits(_T_2018, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2020 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2021 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2022 = bits(_T_2021, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2023 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2024 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2025 = bits(_T_2024, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2026 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2027 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2028 = bits(_T_2027, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2029 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2030 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2031 = bits(_T_2030, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2032 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2033 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2034 = bits(_T_2033, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2035 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2036 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2037 = bits(_T_2036, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2038 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2039 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2040 = bits(_T_2039, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2041 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2042 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2043 = bits(_T_2042, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2044 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2045 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2046 = bits(_T_2045, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2047 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2048 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2049 = bits(_T_2048, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2050 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2051 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 488:289]
node _T_2052 = bits(_T_2051, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
node _T_2053 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
node _T_2054 = mux(_T_2007, _T_2008, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2055 = mux(_T_2010, _T_2011, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2056 = mux(_T_2013, _T_2014, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2057 = mux(_T_2016, _T_2017, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2058 = mux(_T_2019, _T_2020, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2059 = mux(_T_2022, _T_2023, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2060 = mux(_T_2025, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2061 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2062 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2063 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2064 = mux(_T_2037, _T_2038, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2065 = mux(_T_2040, _T_2041, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2066 = mux(_T_2043, _T_2044, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2067 = mux(_T_2046, _T_2047, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2068 = mux(_T_2049, _T_2050, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2069 = mux(_T_2052, _T_2053, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2070 = or(_T_2054, _T_2055) @[Mux.scala 27:72]
node _T_2071 = or(_T_2070, _T_2056) @[Mux.scala 27:72]
node _T_2072 = or(_T_2071, _T_2057) @[Mux.scala 27:72]
node _T_2073 = or(_T_2072, _T_2058) @[Mux.scala 27:72]
node _T_2074 = or(_T_2073, _T_2059) @[Mux.scala 27:72]
node _T_2075 = or(_T_2074, _T_2060) @[Mux.scala 27:72]
node _T_2076 = or(_T_2075, _T_2061) @[Mux.scala 27:72]
node _T_2077 = or(_T_2076, _T_2062) @[Mux.scala 27:72]
node _T_2078 = or(_T_2077, _T_2063) @[Mux.scala 27:72]
node _T_2079 = or(_T_2078, _T_2064) @[Mux.scala 27:72]
node _T_2080 = or(_T_2079, _T_2065) @[Mux.scala 27:72]
node _T_2081 = or(_T_2080, _T_2066) @[Mux.scala 27:72]
node _T_2082 = or(_T_2081, _T_2067) @[Mux.scala 27:72]
node _T_2083 = or(_T_2082, _T_2068) @[Mux.scala 27:72]
node _T_2084 = or(_T_2083, _T_2069) @[Mux.scala 27:72]
wire _T_2085 : UInt<32> @[Mux.scala 27:72]
_T_2085 <= _T_2084 @[Mux.scala 27:72]
node _T_2086 = cat(_T_1925, _T_2005) @[Cat.scala 29:58]
node _T_2087 = cat(_T_2086, _T_2085) @[Cat.scala 29:58]
node ic_byp_data_only_pre_new = mux(_T_1603, _T_1845, _T_2087) @[el2_ifu_mem_ctl.scala 486:37]
node _T_2088 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 490:52]
node _T_2089 = bits(_T_2088, 0, 0) @[el2_ifu_mem_ctl.scala 490:62]
node _T_2090 = eq(_T_2089, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 490:31]
node _T_2091 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 490:128]
node _T_2092 = cat(UInt<16>("h00"), _T_2091) @[Cat.scala 29:58]
node _T_2093 = mux(_T_2090, ic_byp_data_only_pre_new, _T_2092) @[el2_ifu_mem_ctl.scala 490:30]
ic_byp_data_only_new <= _T_2093 @[el2_ifu_mem_ctl.scala 490:24]
node _T_2094 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 492:27]
node _T_2095 = bits(ifu_fetch_addr_int_f, 6, 6) @[el2_ifu_mem_ctl.scala 492:75]
node miss_wrap_f = neq(_T_2094, _T_2095) @[el2_ifu_mem_ctl.scala 492:51]
node _T_2096 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2097 = eq(_T_2096, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2098 = bits(_T_2097, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2099 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2100 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2101 = eq(_T_2100, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2102 = bits(_T_2101, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2103 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2104 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2105 = eq(_T_2104, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2106 = bits(_T_2105, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2107 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2108 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2109 = eq(_T_2108, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2110 = bits(_T_2109, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2111 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2112 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2113 = eq(_T_2112, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2114 = bits(_T_2113, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2115 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2116 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2117 = eq(_T_2116, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2118 = bits(_T_2117, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2119 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2120 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2121 = eq(_T_2120, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2122 = bits(_T_2121, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2123 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2124 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
node _T_2125 = eq(_T_2124, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 493:127]
node _T_2126 = bits(_T_2125, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
node _T_2127 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 493:166]
node _T_2128 = mux(_T_2098, _T_2099, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2129 = mux(_T_2102, _T_2103, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2130 = mux(_T_2106, _T_2107, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2131 = mux(_T_2110, _T_2111, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2132 = mux(_T_2114, _T_2115, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2133 = mux(_T_2118, _T_2119, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2134 = mux(_T_2122, _T_2123, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2135 = mux(_T_2126, _T_2127, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2136 = or(_T_2128, _T_2129) @[Mux.scala 27:72]
node _T_2137 = or(_T_2136, _T_2130) @[Mux.scala 27:72]
node _T_2138 = or(_T_2137, _T_2131) @[Mux.scala 27:72]
node _T_2139 = or(_T_2138, _T_2132) @[Mux.scala 27:72]
node _T_2140 = or(_T_2139, _T_2133) @[Mux.scala 27:72]
node _T_2141 = or(_T_2140, _T_2134) @[Mux.scala 27:72]
node _T_2142 = or(_T_2141, _T_2135) @[Mux.scala 27:72]
wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72]
ic_miss_buff_data_valid_bypass_index <= _T_2142 @[Mux.scala 27:72]
node _T_2143 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2144 = bits(_T_2143, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2145 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2146 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2147 = bits(_T_2146, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2148 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2149 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2150 = bits(_T_2149, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2151 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2152 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2153 = bits(_T_2152, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2154 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2155 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2156 = bits(_T_2155, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2157 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2158 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2159 = bits(_T_2158, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2160 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2161 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2162 = bits(_T_2161, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2163 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2164 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 494:110]
node _T_2165 = bits(_T_2164, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
node _T_2166 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 494:149]
node _T_2167 = mux(_T_2144, _T_2145, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2168 = mux(_T_2147, _T_2148, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2169 = mux(_T_2150, _T_2151, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2170 = mux(_T_2153, _T_2154, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2171 = mux(_T_2156, _T_2157, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2172 = mux(_T_2159, _T_2160, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2173 = mux(_T_2162, _T_2163, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2174 = mux(_T_2165, _T_2166, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2175 = or(_T_2167, _T_2168) @[Mux.scala 27:72]
node _T_2176 = or(_T_2175, _T_2169) @[Mux.scala 27:72]
node _T_2177 = or(_T_2176, _T_2170) @[Mux.scala 27:72]
node _T_2178 = or(_T_2177, _T_2171) @[Mux.scala 27:72]
node _T_2179 = or(_T_2178, _T_2172) @[Mux.scala 27:72]
node _T_2180 = or(_T_2179, _T_2173) @[Mux.scala 27:72]
node _T_2181 = or(_T_2180, _T_2174) @[Mux.scala 27:72]
wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72]
ic_miss_buff_data_valid_inc_bypass_index <= _T_2181 @[Mux.scala 27:72]
node _T_2182 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 495:85]
node _T_2183 = eq(_T_2182, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 495:69]
node _T_2184 = and(ic_miss_buff_data_valid_bypass_index, _T_2183) @[el2_ifu_mem_ctl.scala 495:67]
node _T_2185 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 495:107]
node _T_2186 = eq(_T_2185, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 495:91]
node _T_2187 = and(_T_2184, _T_2186) @[el2_ifu_mem_ctl.scala 495:89]
node _T_2188 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 496:61]
node _T_2189 = eq(_T_2188, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 496:45]
node _T_2190 = and(ic_miss_buff_data_valid_bypass_index, _T_2189) @[el2_ifu_mem_ctl.scala 496:43]
node _T_2191 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 496:83]
node _T_2192 = and(_T_2190, _T_2191) @[el2_ifu_mem_ctl.scala 496:65]
node _T_2193 = or(_T_2187, _T_2192) @[el2_ifu_mem_ctl.scala 495:112]
node _T_2194 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 497:61]
node _T_2195 = and(ic_miss_buff_data_valid_bypass_index, _T_2194) @[el2_ifu_mem_ctl.scala 497:43]
node _T_2196 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 497:83]
node _T_2197 = eq(_T_2196, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 497:67]
node _T_2198 = and(_T_2195, _T_2197) @[el2_ifu_mem_ctl.scala 497:65]
node _T_2199 = or(_T_2193, _T_2198) @[el2_ifu_mem_ctl.scala 496:88]
node _T_2200 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 498:61]
node _T_2201 = and(ic_miss_buff_data_valid_bypass_index, _T_2200) @[el2_ifu_mem_ctl.scala 498:43]
node _T_2202 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 498:83]
node _T_2203 = and(_T_2201, _T_2202) @[el2_ifu_mem_ctl.scala 498:65]
node _T_2204 = and(_T_2203, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 498:87]
node _T_2205 = or(_T_2199, _T_2204) @[el2_ifu_mem_ctl.scala 497:88]
node _T_2206 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 499:61]
node _T_2207 = eq(_T_2206, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 499:45]
node _T_2208 = and(ic_miss_buff_data_valid_bypass_index, _T_2207) @[el2_ifu_mem_ctl.scala 499:43]
node _T_2209 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 499:83]
node _T_2210 = eq(_T_2209, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 499:67]
node _T_2211 = and(_T_2208, _T_2210) @[el2_ifu_mem_ctl.scala 499:65]
node _T_2212 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 499:105]
node _T_2213 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_2214 = eq(_T_2212, _T_2213) @[el2_ifu_mem_ctl.scala 499:131]
node _T_2215 = and(_T_2211, _T_2214) @[el2_ifu_mem_ctl.scala 499:87]
node miss_buff_hit_unq_f = or(_T_2205, _T_2215) @[el2_ifu_mem_ctl.scala 498:131]
node _T_2216 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 501:30]
node _T_2217 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 501:68]
node _T_2218 = and(miss_buff_hit_unq_f, _T_2217) @[el2_ifu_mem_ctl.scala 501:66]
node _T_2219 = and(_T_2216, _T_2218) @[el2_ifu_mem_ctl.scala 501:43]
stream_hit_f <= _T_2219 @[el2_ifu_mem_ctl.scala 501:16]
node _T_2220 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 502:31]
node _T_2221 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 502:69]
node _T_2222 = and(miss_buff_hit_unq_f, _T_2221) @[el2_ifu_mem_ctl.scala 502:67]
node _T_2223 = and(_T_2220, _T_2222) @[el2_ifu_mem_ctl.scala 502:44]
node _T_2224 = and(_T_2223, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 502:83]
stream_miss_f <= _T_2224 @[el2_ifu_mem_ctl.scala 502:17]
node _T_2225 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 503:35]
node _T_2226 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_2227 = eq(_T_2225, _T_2226) @[el2_ifu_mem_ctl.scala 503:60]
node _T_2228 = and(_T_2227, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 503:92]
node _T_2229 = and(_T_2228, stream_hit_f) @[el2_ifu_mem_ctl.scala 503:110]
stream_eol_f <= _T_2229 @[el2_ifu_mem_ctl.scala 503:16]
node _T_2230 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 504:55]
node _T_2231 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 504:87]
node _T_2232 = or(_T_2230, _T_2231) @[el2_ifu_mem_ctl.scala 504:74]
node _T_2233 = and(miss_buff_hit_unq_f, _T_2232) @[el2_ifu_mem_ctl.scala 504:41]
crit_byp_hit_f <= _T_2233 @[el2_ifu_mem_ctl.scala 504:18]
node _T_2234 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 507:37]
node _T_2235 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 507:70]
node _T_2236 = eq(_T_2235, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 507:55]
node other_tag = cat(_T_2234, _T_2236) @[Cat.scala 29:58]
node _T_2237 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2238 = bits(_T_2237, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2239 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2240 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2241 = bits(_T_2240, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2242 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2243 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2244 = bits(_T_2243, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2245 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2246 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2247 = bits(_T_2246, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2248 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2249 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2250 = bits(_T_2249, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2251 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2252 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2253 = bits(_T_2252, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2254 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2255 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2256 = bits(_T_2255, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2257 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2258 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 508:81]
node _T_2259 = bits(_T_2258, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
node _T_2260 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 508:120]
node _T_2261 = mux(_T_2238, _T_2239, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2262 = mux(_T_2241, _T_2242, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2263 = mux(_T_2244, _T_2245, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2264 = mux(_T_2247, _T_2248, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2265 = mux(_T_2250, _T_2251, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2266 = mux(_T_2253, _T_2254, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2267 = mux(_T_2256, _T_2257, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2268 = mux(_T_2259, _T_2260, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2269 = or(_T_2261, _T_2262) @[Mux.scala 27:72]
node _T_2270 = or(_T_2269, _T_2263) @[Mux.scala 27:72]
node _T_2271 = or(_T_2270, _T_2264) @[Mux.scala 27:72]
node _T_2272 = or(_T_2271, _T_2265) @[Mux.scala 27:72]
node _T_2273 = or(_T_2272, _T_2266) @[Mux.scala 27:72]
node _T_2274 = or(_T_2273, _T_2267) @[Mux.scala 27:72]
node _T_2275 = or(_T_2274, _T_2268) @[Mux.scala 27:72]
wire second_half_available : UInt<1> @[Mux.scala 27:72]
second_half_available <= _T_2275 @[Mux.scala 27:72]
node _T_2276 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 509:46]
write_ic_16_bytes <= _T_2276 @[el2_ifu_mem_ctl.scala 509:21]
node _T_2277 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2278 = eq(_T_2277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2279 = bits(_T_2278, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2280 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2281 = eq(_T_2280, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2282 = bits(_T_2281, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2283 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2284 = eq(_T_2283, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2285 = bits(_T_2284, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2286 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2287 = eq(_T_2286, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2288 = bits(_T_2287, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2289 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2290 = eq(_T_2289, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2291 = bits(_T_2290, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2292 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2293 = eq(_T_2292, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2294 = bits(_T_2293, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2295 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2296 = eq(_T_2295, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2297 = bits(_T_2296, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2298 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2299 = eq(_T_2298, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2300 = bits(_T_2299, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2301 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2302 = eq(_T_2301, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2303 = bits(_T_2302, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2304 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2305 = eq(_T_2304, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2306 = bits(_T_2305, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2307 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2308 = eq(_T_2307, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2309 = bits(_T_2308, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2310 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2311 = eq(_T_2310, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2312 = bits(_T_2311, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2313 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2314 = eq(_T_2313, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2315 = bits(_T_2314, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2316 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2317 = eq(_T_2316, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2318 = bits(_T_2317, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2319 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2320 = eq(_T_2319, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2321 = bits(_T_2320, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2322 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_2323 = eq(_T_2322, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 510:89]
node _T_2324 = bits(_T_2323, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
node _T_2325 = mux(_T_2279, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2326 = mux(_T_2282, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2327 = mux(_T_2285, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2328 = mux(_T_2288, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2329 = mux(_T_2291, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2330 = mux(_T_2294, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2331 = mux(_T_2297, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2332 = mux(_T_2300, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2333 = mux(_T_2303, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2334 = mux(_T_2306, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2335 = mux(_T_2309, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2336 = mux(_T_2312, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2337 = mux(_T_2315, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2338 = mux(_T_2318, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2339 = mux(_T_2321, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2340 = mux(_T_2324, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2341 = or(_T_2325, _T_2326) @[Mux.scala 27:72]
node _T_2342 = or(_T_2341, _T_2327) @[Mux.scala 27:72]
node _T_2343 = or(_T_2342, _T_2328) @[Mux.scala 27:72]
node _T_2344 = or(_T_2343, _T_2329) @[Mux.scala 27:72]
node _T_2345 = or(_T_2344, _T_2330) @[Mux.scala 27:72]
node _T_2346 = or(_T_2345, _T_2331) @[Mux.scala 27:72]
node _T_2347 = or(_T_2346, _T_2332) @[Mux.scala 27:72]
node _T_2348 = or(_T_2347, _T_2333) @[Mux.scala 27:72]
node _T_2349 = or(_T_2348, _T_2334) @[Mux.scala 27:72]
node _T_2350 = or(_T_2349, _T_2335) @[Mux.scala 27:72]
node _T_2351 = or(_T_2350, _T_2336) @[Mux.scala 27:72]
node _T_2352 = or(_T_2351, _T_2337) @[Mux.scala 27:72]
node _T_2353 = or(_T_2352, _T_2338) @[Mux.scala 27:72]
node _T_2354 = or(_T_2353, _T_2339) @[Mux.scala 27:72]
node _T_2355 = or(_T_2354, _T_2340) @[Mux.scala 27:72]
wire _T_2356 : UInt<32> @[Mux.scala 27:72]
_T_2356 <= _T_2355 @[Mux.scala 27:72]
node _T_2357 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2358 = eq(_T_2357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2359 = bits(_T_2358, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2360 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2361 = eq(_T_2360, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2362 = bits(_T_2361, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2363 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2364 = eq(_T_2363, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2365 = bits(_T_2364, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2366 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2367 = eq(_T_2366, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2368 = bits(_T_2367, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2369 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2370 = eq(_T_2369, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2371 = bits(_T_2370, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2372 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2373 = eq(_T_2372, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2374 = bits(_T_2373, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2375 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2376 = eq(_T_2375, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2377 = bits(_T_2376, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2378 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2379 = eq(_T_2378, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 511:64]
node _T_2380 = bits(_T_2379, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
node _T_2381 = mux(_T_2359, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2382 = mux(_T_2362, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2383 = mux(_T_2365, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2384 = mux(_T_2368, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2385 = mux(_T_2371, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2386 = mux(_T_2374, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2387 = mux(_T_2377, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2388 = mux(_T_2380, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2389 = or(_T_2381, _T_2382) @[Mux.scala 27:72]
node _T_2390 = or(_T_2389, _T_2383) @[Mux.scala 27:72]
node _T_2391 = or(_T_2390, _T_2384) @[Mux.scala 27:72]
node _T_2392 = or(_T_2391, _T_2385) @[Mux.scala 27:72]
node _T_2393 = or(_T_2392, _T_2386) @[Mux.scala 27:72]
node _T_2394 = or(_T_2393, _T_2387) @[Mux.scala 27:72]
node _T_2395 = or(_T_2394, _T_2388) @[Mux.scala 27:72]
wire _T_2396 : UInt<32> @[Mux.scala 27:72]
_T_2396 <= _T_2395 @[Mux.scala 27:72]
node _T_2397 = cat(_T_2356, _T_2396) @[Cat.scala 29:58]
ic_miss_buff_half <= _T_2397 @[el2_ifu_mem_ctl.scala 510:21]
node _T_2398 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 513:44]
node _T_2399 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 513:91]
node _T_2400 = eq(_T_2399, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 513:60]
node _T_2401 = and(_T_2398, _T_2400) @[el2_ifu_mem_ctl.scala 513:58]
ic_rd_parity_final_err <= _T_2401 @[el2_ifu_mem_ctl.scala 513:26]
wire ifu_ic_rw_int_addr_ff : UInt<5>
ifu_ic_rw_int_addr_ff <= UInt<1>("h00")
wire perr_sb_write_status : UInt<1>
perr_sb_write_status <= UInt<1>("h00")
reg perr_ic_index_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when perr_sb_write_status : @[Reg.scala 28:19]
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wire perr_sel_invalidate : UInt<1>
perr_sel_invalidate <= UInt<1>("h00")
node _T_2402 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15]
node perr_err_inv_way = mux(_T_2402, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_2403 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 520:34]
iccm_correct_ecc <= _T_2403 @[el2_ifu_mem_ctl.scala 520:20]
node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 521:37]
reg dma_sb_err_state_ff : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 522:61]
dma_sb_err_state_ff <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 522:61]
wire perr_nxtstate : UInt<3>
perr_nxtstate <= UInt<1>("h00")
wire perr_state_en : UInt<1>
perr_state_en <= UInt<1>("h00")
wire iccm_error_start : UInt<1>
iccm_error_start <= UInt<1>("h00")
node _T_2404 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30]
when _T_2404 : @[Conditional.scala 40:58]
node _T_2405 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 530:89]
node _T_2406 = and(io.ic_error_start, _T_2405) @[el2_ifu_mem_ctl.scala 530:87]
node _T_2407 = bits(_T_2406, 0, 0) @[el2_ifu_mem_ctl.scala 530:110]
node _T_2408 = mux(_T_2407, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 530:67]
node _T_2409 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2408) @[el2_ifu_mem_ctl.scala 530:27]
perr_nxtstate <= _T_2409 @[el2_ifu_mem_ctl.scala 530:21]
node _T_2410 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 531:44]
node _T_2411 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 531:67]
node _T_2412 = and(_T_2410, _T_2411) @[el2_ifu_mem_ctl.scala 531:65]
node _T_2413 = or(_T_2412, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 531:88]
node _T_2414 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 531:114]
node _T_2415 = and(_T_2413, _T_2414) @[el2_ifu_mem_ctl.scala 531:112]
perr_state_en <= _T_2415 @[el2_ifu_mem_ctl.scala 531:21]
perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 532:28]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_2416 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30]
when _T_2416 : @[Conditional.scala 39:67]
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 535:21]
node _T_2417 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 536:50]
perr_state_en <= _T_2417 @[el2_ifu_mem_ctl.scala 536:21]
node _T_2418 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 537:56]
perr_sel_invalidate <= _T_2418 @[el2_ifu_mem_ctl.scala 537:27]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_2419 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30]
when _T_2419 : @[Conditional.scala 39:67]
node _T_2420 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 540:54]
node _T_2421 = or(_T_2420, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 540:84]
node _T_2422 = bits(_T_2421, 0, 0) @[el2_ifu_mem_ctl.scala 540:115]
node _T_2423 = mux(_T_2422, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 540:27]
perr_nxtstate <= _T_2423 @[el2_ifu_mem_ctl.scala 540:21]
node _T_2424 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 541:50]
perr_state_en <= _T_2424 @[el2_ifu_mem_ctl.scala 541:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_2425 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30]
when _T_2425 : @[Conditional.scala 39:67]
node _T_2426 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 544:27]
perr_nxtstate <= _T_2426 @[el2_ifu_mem_ctl.scala 544:21]
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 545:21]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_2427 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30]
when _T_2427 : @[Conditional.scala 39:67]
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 548:21]
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 549:21]
skip @[Conditional.scala 39:67]
reg _T_2428 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when perr_state_en : @[Reg.scala 28:19]
_T_2428 <= perr_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
perr_state <= _T_2428 @[el2_ifu_mem_ctl.scala 552:14]
wire err_stop_nxtstate : UInt<2>
err_stop_nxtstate <= UInt<1>("h00")
wire err_stop_state_en : UInt<1>
err_stop_state_en <= UInt<1>("h00")
wire iccm_correction_state : UInt<1>
iccm_correction_state <= UInt<1>("h00")
node _T_2429 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30]
when _T_2429 : @[Conditional.scala 40:58]
err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 560:25]
node _T_2430 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 561:66]
node _T_2431 = and(io.dec_tlu_flush_err_wb, _T_2430) @[el2_ifu_mem_ctl.scala 561:52]
node _T_2432 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 561:83]
node _T_2433 = and(_T_2431, _T_2432) @[el2_ifu_mem_ctl.scala 561:81]
err_stop_state_en <= _T_2433 @[el2_ifu_mem_ctl.scala 561:25]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_2434 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30]
when _T_2434 : @[Conditional.scala 39:67]
node _T_2435 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 564:59]
node _T_2436 = or(_T_2435, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 564:86]
node _T_2437 = bits(_T_2436, 0, 0) @[el2_ifu_mem_ctl.scala 564:117]
node _T_2438 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 565:31]
node _T_2439 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 565:56]
node _T_2440 = and(_T_2439, two_byte_instr) @[el2_ifu_mem_ctl.scala 565:59]
node _T_2441 = or(_T_2438, _T_2440) @[el2_ifu_mem_ctl.scala 565:38]
node _T_2442 = bits(_T_2441, 0, 0) @[el2_ifu_mem_ctl.scala 565:83]
node _T_2443 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 566:31]
node _T_2444 = bits(_T_2443, 0, 0) @[el2_ifu_mem_ctl.scala 566:41]
node _T_2445 = mux(_T_2444, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 566:14]
node _T_2446 = mux(_T_2442, UInt<2>("h03"), _T_2445) @[el2_ifu_mem_ctl.scala 565:12]
node _T_2447 = mux(_T_2437, UInt<2>("h00"), _T_2446) @[el2_ifu_mem_ctl.scala 564:31]
err_stop_nxtstate <= _T_2447 @[el2_ifu_mem_ctl.scala 564:25]
node _T_2448 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 567:54]
node _T_2449 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 567:99]
node _T_2450 = or(_T_2448, _T_2449) @[el2_ifu_mem_ctl.scala 567:81]
node _T_2451 = or(_T_2450, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 567:103]
node _T_2452 = or(_T_2451, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 567:126]
err_stop_state_en <= _T_2452 @[el2_ifu_mem_ctl.scala 567:25]
node _T_2453 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 568:43]
node _T_2454 = eq(_T_2453, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 568:48]
node _T_2455 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 568:75]
node _T_2456 = and(_T_2455, two_byte_instr) @[el2_ifu_mem_ctl.scala 568:79]
node _T_2457 = or(_T_2454, _T_2456) @[el2_ifu_mem_ctl.scala 568:56]
node _T_2458 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 568:122]
node _T_2459 = eq(_T_2458, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 568:101]
node _T_2460 = and(_T_2457, _T_2459) @[el2_ifu_mem_ctl.scala 568:99]
err_stop_fetch <= _T_2460 @[el2_ifu_mem_ctl.scala 568:22]
iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 569:29]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_2461 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30]
when _T_2461 : @[Conditional.scala 39:67]
node _T_2462 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 572:59]
node _T_2463 = or(_T_2462, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 572:86]
node _T_2464 = bits(_T_2463, 0, 0) @[el2_ifu_mem_ctl.scala 572:111]
node _T_2465 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 573:46]
node _T_2466 = bits(_T_2465, 0, 0) @[el2_ifu_mem_ctl.scala 573:50]
node _T_2467 = mux(_T_2466, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 573:29]
node _T_2468 = mux(_T_2464, UInt<2>("h00"), _T_2467) @[el2_ifu_mem_ctl.scala 572:31]
err_stop_nxtstate <= _T_2468 @[el2_ifu_mem_ctl.scala 572:25]
node _T_2469 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 574:54]
node _T_2470 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 574:99]
node _T_2471 = or(_T_2469, _T_2470) @[el2_ifu_mem_ctl.scala 574:81]
node _T_2472 = or(_T_2471, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 574:103]
err_stop_state_en <= _T_2472 @[el2_ifu_mem_ctl.scala 574:25]
node _T_2473 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 575:41]
node _T_2474 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 575:47]
node _T_2475 = and(_T_2473, _T_2474) @[el2_ifu_mem_ctl.scala 575:45]
node _T_2476 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 575:69]
node _T_2477 = and(_T_2475, _T_2476) @[el2_ifu_mem_ctl.scala 575:67]
err_stop_fetch <= _T_2477 @[el2_ifu_mem_ctl.scala 575:22]
iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 576:29]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_2478 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30]
when _T_2478 : @[Conditional.scala 39:67]
node _T_2479 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 579:62]
node _T_2480 = and(io.dec_tlu_flush_lower_wb, _T_2479) @[el2_ifu_mem_ctl.scala 579:60]
node _T_2481 = or(_T_2480, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 579:88]
node _T_2482 = or(_T_2481, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 579:115]
node _T_2483 = bits(_T_2482, 0, 0) @[el2_ifu_mem_ctl.scala 579:140]
node _T_2484 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 580:60]
node _T_2485 = mux(_T_2484, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 580:29]
node _T_2486 = mux(_T_2483, UInt<2>("h00"), _T_2485) @[el2_ifu_mem_ctl.scala 579:31]
err_stop_nxtstate <= _T_2486 @[el2_ifu_mem_ctl.scala 579:25]
node _T_2487 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 581:54]
node _T_2488 = or(_T_2487, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 581:81]
err_stop_state_en <= _T_2488 @[el2_ifu_mem_ctl.scala 581:25]
err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 582:22]
iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 583:29]
skip @[Conditional.scala 39:67]
reg _T_2489 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when err_stop_state_en : @[Reg.scala 28:19]
_T_2489 <= err_stop_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
err_stop_state <= _T_2489 @[el2_ifu_mem_ctl.scala 586:18]
bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 587:22]
reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 588:61]
bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 588:61]
reg _T_2490 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 589:52]
_T_2490 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 589:52]
scnd_miss_req_q <= _T_2490 @[el2_ifu_mem_ctl.scala 589:19]
reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 590:57]
scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 590:57]
wire bus_cmd_req_hold : UInt<1>
bus_cmd_req_hold <= UInt<1>("h00")
wire ifu_bus_cmd_valid : UInt<1>
ifu_bus_cmd_valid <= UInt<1>("h00")
wire bus_cmd_beat_count : UInt<3>
bus_cmd_beat_count <= UInt<1>("h00")
wire ifu_bus_cmd_ready : UInt<1>
ifu_bus_cmd_ready <= UInt<1>("h00")
node _T_2491 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 595:45]
node _T_2492 = or(_T_2491, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 595:64]
node _T_2493 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 595:87]
node _T_2494 = and(_T_2492, _T_2493) @[el2_ifu_mem_ctl.scala 595:85]
node _T_2495 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_2496 = eq(bus_cmd_beat_count, _T_2495) @[el2_ifu_mem_ctl.scala 595:133]
node _T_2497 = and(_T_2496, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 595:164]
node _T_2498 = and(_T_2497, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 595:184]
node _T_2499 = and(_T_2498, miss_pending) @[el2_ifu_mem_ctl.scala 595:204]
node _T_2500 = eq(_T_2499, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 595:112]
node ifc_bus_ic_req_ff_in = and(_T_2494, _T_2500) @[el2_ifu_mem_ctl.scala 595:110]
node _T_2501 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 596:80]
reg _T_2502 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2501 : @[Reg.scala 28:19]
_T_2502 <= ifc_bus_ic_req_ff_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ifu_bus_cmd_valid <= _T_2502 @[el2_ifu_mem_ctl.scala 596:21]
wire bus_cmd_sent : UInt<1>
bus_cmd_sent <= UInt<1>("h00")
node _T_2503 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 598:39]
node _T_2504 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:61]
node _T_2505 = and(_T_2503, _T_2504) @[el2_ifu_mem_ctl.scala 598:59]
node _T_2506 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:77]
node bus_cmd_req_in = and(_T_2505, _T_2506) @[el2_ifu_mem_ctl.scala 598:75]
reg _T_2507 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 599:49]
_T_2507 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 599:49]
bus_cmd_sent <= _T_2507 @[el2_ifu_mem_ctl.scala 599:16]
io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 601:22]
node _T_2508 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
node _T_2509 = mux(_T_2508, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_2510 = and(bus_rd_addr_count, _T_2509) @[el2_ifu_mem_ctl.scala 602:40]
io.ifu_axi_arid <= _T_2510 @[el2_ifu_mem_ctl.scala 602:19]
node _T_2511 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2512 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
node _T_2513 = mux(_T_2512, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_2514 = and(_T_2511, _T_2513) @[el2_ifu_mem_ctl.scala 603:57]
io.ifu_axi_araddr <= _T_2514 @[el2_ifu_mem_ctl.scala 603:21]
io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 604:21]
io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 605:22]
node _T_2515 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 606:43]
io.ifu_axi_arregion <= _T_2515 @[el2_ifu_mem_ctl.scala 606:23]
io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 607:22]
io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 608:21]
reg ifu_bus_arready_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ifu_bus_rvalid_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
ifu_bus_rvalid_unq_ff <= io.ifu_axi_rvalid @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ifu_bus_arvalid_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
ifu_bus_arvalid_ff <= io.ifu_axi_arvalid @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ifu_bus_rresp_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
ifu_bus_rresp_ff <= io.ifu_axi_rresp @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg _T_2516 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
_T_2516 <= io.ifu_axi_rdata @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ifu_bus_rdata_ff <= _T_2516 @[el2_ifu_mem_ctl.scala 618:20]
reg _T_2517 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
_T_2517 <= io.ifu_axi_rid @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ifu_bus_rid_ff <= _T_2517 @[el2_ifu_mem_ctl.scala 619:18]
ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 620:21]
ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 621:21]
ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 622:21]
ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 623:19]
ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 624:21]
node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 626:42]
node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 627:45]
node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 628:51]
node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 629:49]
node _T_2518 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 630:35]
node _T_2519 = and(_T_2518, miss_pending) @[el2_ifu_mem_ctl.scala 630:53]
node _T_2520 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 630:70]
node _T_2521 = and(_T_2519, _T_2520) @[el2_ifu_mem_ctl.scala 630:68]
bus_cmd_sent <= _T_2521 @[el2_ifu_mem_ctl.scala 630:16]
wire bus_last_data_beat : UInt<1>
bus_last_data_beat <= UInt<1>("h00")
node _T_2522 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 632:50]
node _T_2523 = and(bus_ifu_wr_en_ff, _T_2522) @[el2_ifu_mem_ctl.scala 632:48]
node _T_2524 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 632:72]
node bus_inc_data_beat_cnt = and(_T_2523, _T_2524) @[el2_ifu_mem_ctl.scala 632:70]
node _T_2525 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 633:68]
node _T_2526 = or(ic_act_miss_f, _T_2525) @[el2_ifu_mem_ctl.scala 633:48]
node bus_reset_data_beat_cnt = or(_T_2526, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 633:91]
node _T_2527 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:32]
node _T_2528 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:57]
node bus_hold_data_beat_cnt = and(_T_2527, _T_2528) @[el2_ifu_mem_ctl.scala 634:55]
wire bus_data_beat_count : UInt<3>
bus_data_beat_count <= UInt<1>("h00")
node _T_2529 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 636:115]
node _T_2530 = tail(_T_2529, 1) @[el2_ifu_mem_ctl.scala 636:115]
node _T_2531 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2532 = mux(bus_inc_data_beat_cnt, _T_2530, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2533 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2534 = or(_T_2531, _T_2532) @[Mux.scala 27:72]
node _T_2535 = or(_T_2534, _T_2533) @[Mux.scala 27:72]
wire _T_2536 : UInt<3> @[Mux.scala 27:72]
_T_2536 <= _T_2535 @[Mux.scala 27:72]
bus_new_data_beat_count <= _T_2536 @[el2_ifu_mem_ctl.scala 636:27]
reg _T_2537 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 637:56]
_T_2537 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 637:56]
bus_data_beat_count <= _T_2537 @[el2_ifu_mem_ctl.scala 637:23]
node _T_2538 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 638:49]
node _T_2539 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 638:73]
node _T_2540 = and(_T_2538, _T_2539) @[el2_ifu_mem_ctl.scala 638:71]
node _T_2541 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 638:116]
node _T_2542 = and(last_data_recieved_ff, _T_2541) @[el2_ifu_mem_ctl.scala 638:114]
node last_data_recieved_in = or(_T_2540, _T_2542) @[el2_ifu_mem_ctl.scala 638:89]
reg _T_2543 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 639:58]
_T_2543 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 639:58]
last_data_recieved_ff <= _T_2543 @[el2_ifu_mem_ctl.scala 639:25]
node _T_2544 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 641:35]
node _T_2545 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 641:56]
node _T_2546 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 642:39]
node _T_2547 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 643:45]
node _T_2548 = tail(_T_2547, 1) @[el2_ifu_mem_ctl.scala 643:45]
node _T_2549 = mux(bus_cmd_sent, _T_2548, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 643:12]
node _T_2550 = mux(scnd_miss_req_q, _T_2546, _T_2549) @[el2_ifu_mem_ctl.scala 642:10]
node bus_new_rd_addr_count = mux(_T_2544, _T_2545, _T_2550) @[el2_ifu_mem_ctl.scala 641:34]
node _T_2551 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 644:81]
node _T_2552 = or(_T_2551, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 644:97]
reg _T_2553 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2552 : @[Reg.scala 28:19]
_T_2553 <= bus_new_rd_addr_count @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
bus_rd_addr_count <= _T_2553 @[el2_ifu_mem_ctl.scala 644:21]
node _T_2554 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 646:48]
node _T_2555 = and(_T_2554, miss_pending) @[el2_ifu_mem_ctl.scala 646:68]
node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 646:85]
node bus_inc_cmd_beat_cnt = and(_T_2555, _T_2556) @[el2_ifu_mem_ctl.scala 646:83]
node _T_2557 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 647:51]
node _T_2558 = and(ic_act_miss_f, _T_2557) @[el2_ifu_mem_ctl.scala 647:49]
node bus_reset_cmd_beat_cnt_0 = or(_T_2558, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 647:73]
node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 648:57]
node _T_2559 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 649:31]
node _T_2560 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 649:71]
node _T_2561 = or(_T_2560, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 649:87]
node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 649:55]
node bus_hold_cmd_beat_cnt = and(_T_2559, _T_2562) @[el2_ifu_mem_ctl.scala 649:53]
node _T_2563 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 650:46]
node bus_cmd_beat_en = or(_T_2563, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 650:62]
node _T_2564 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 651:107]
node _T_2565 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 652:46]
node _T_2566 = tail(_T_2565, 1) @[el2_ifu_mem_ctl.scala 652:46]
node _T_2567 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2568 = mux(_T_2564, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2569 = mux(bus_inc_cmd_beat_cnt, _T_2566, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2570 = mux(bus_hold_cmd_beat_cnt, bus_cmd_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2571 = or(_T_2567, _T_2568) @[Mux.scala 27:72]
node _T_2572 = or(_T_2571, _T_2569) @[Mux.scala 27:72]
node _T_2573 = or(_T_2572, _T_2570) @[Mux.scala 27:72]
wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72]
bus_new_cmd_beat_count <= _T_2573 @[Mux.scala 27:72]
node _T_2574 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 653:84]
node _T_2575 = or(_T_2574, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 653:100]
node _T_2576 = and(_T_2575, bus_cmd_beat_en) @[el2_ifu_mem_ctl.scala 653:125]
reg _T_2577 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2576 : @[Reg.scala 28:19]
_T_2577 <= bus_new_cmd_beat_count @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
bus_cmd_beat_count <= _T_2577 @[el2_ifu_mem_ctl.scala 653:22]
node _T_2578 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 654:69]
node _T_2579 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 654:101]
node _T_2580 = mux(uncacheable_miss_ff, _T_2578, _T_2579) @[el2_ifu_mem_ctl.scala 654:28]
bus_last_data_beat <= _T_2580 @[el2_ifu_mem_ctl.scala 654:22]
node _T_2581 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 655:35]
bus_ifu_wr_en <= _T_2581 @[el2_ifu_mem_ctl.scala 655:17]
node _T_2582 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 656:41]
bus_ifu_wr_en_ff <= _T_2582 @[el2_ifu_mem_ctl.scala 656:20]
node _T_2583 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 657:44]
node _T_2584 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 657:61]
node _T_2585 = and(_T_2583, _T_2584) @[el2_ifu_mem_ctl.scala 657:59]
node _T_2586 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 657:103]
node _T_2587 = eq(_T_2586, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 657:84]
node _T_2588 = and(_T_2585, _T_2587) @[el2_ifu_mem_ctl.scala 657:82]
node _T_2589 = and(_T_2588, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 657:108]
bus_ifu_wr_en_ff_q <= _T_2589 @[el2_ifu_mem_ctl.scala 657:22]
node _T_2590 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 658:51]
node _T_2591 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 658:68]
node bus_ifu_wr_en_ff_wo_err = and(_T_2590, _T_2591) @[el2_ifu_mem_ctl.scala 658:66]
reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 659:61]
ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 659:61]
node _T_2592 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 660:66]
node _T_2593 = and(ic_act_miss_f_delayed, _T_2592) @[el2_ifu_mem_ctl.scala 660:53]
node _T_2594 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:86]
node _T_2595 = and(_T_2593, _T_2594) @[el2_ifu_mem_ctl.scala 660:84]
reset_tag_valid_for_miss <= _T_2595 @[el2_ifu_mem_ctl.scala 660:28]
node _T_2596 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 661:47]
node _T_2597 = and(_T_2596, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 661:50]
node _T_2598 = and(_T_2597, miss_pending) @[el2_ifu_mem_ctl.scala 661:68]
bus_ifu_wr_data_error <= _T_2598 @[el2_ifu_mem_ctl.scala 661:25]
node _T_2599 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 662:48]
node _T_2600 = and(_T_2599, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 662:52]
node _T_2601 = and(_T_2600, miss_pending) @[el2_ifu_mem_ctl.scala 662:73]
bus_ifu_wr_data_error_ff <= _T_2601 @[el2_ifu_mem_ctl.scala 662:28]
wire ifc_dma_access_ok_d : UInt<1>
ifc_dma_access_ok_d <= UInt<1>("h00")
reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 664:62]
ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 664:62]
node _T_2602 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 665:43]
ic_crit_wd_rdy <= _T_2602 @[el2_ifu_mem_ctl.scala 665:18]
node _T_2603 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 666:35]
last_beat <= _T_2603 @[el2_ifu_mem_ctl.scala 666:13]
reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 667:18]
node _T_2604 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:50]
node _T_2605 = and(io.ifc_dma_access_ok, _T_2604) @[el2_ifu_mem_ctl.scala 669:47]
node _T_2606 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:70]
node _T_2607 = and(_T_2605, _T_2606) @[el2_ifu_mem_ctl.scala 669:68]
ifc_dma_access_ok_d <= _T_2607 @[el2_ifu_mem_ctl.scala 669:23]
node _T_2608 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 670:54]
node _T_2609 = and(io.ifc_dma_access_ok, _T_2608) @[el2_ifu_mem_ctl.scala 670:51]
node _T_2610 = and(_T_2609, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 670:72]
node _T_2611 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 670:111]
node _T_2612 = and(_T_2610, _T_2611) @[el2_ifu_mem_ctl.scala 670:97]
node _T_2613 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 670:129]
node iccm_ready = and(_T_2612, _T_2613) @[el2_ifu_mem_ctl.scala 670:127]
reg _T_2614 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 672:51]
_T_2614 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 672:51]
dma_iccm_req_f <= _T_2614 @[el2_ifu_mem_ctl.scala 672:18]
node _T_2615 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 673:40]
node _T_2616 = and(_T_2615, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 673:58]
node _T_2617 = or(_T_2616, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 673:79]
io.iccm_wren <= _T_2617 @[el2_ifu_mem_ctl.scala 673:16]
node _T_2618 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 674:40]
node _T_2619 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 674:60]
node _T_2620 = and(_T_2618, _T_2619) @[el2_ifu_mem_ctl.scala 674:58]
node _T_2621 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 674:104]
node _T_2622 = or(_T_2620, _T_2621) @[el2_ifu_mem_ctl.scala 674:79]
io.iccm_rden <= _T_2622 @[el2_ifu_mem_ctl.scala 674:16]
node _T_2623 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 675:43]
node _T_2624 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 675:63]
node iccm_dma_rden = and(_T_2623, _T_2624) @[el2_ifu_mem_ctl.scala 675:61]
node _T_2625 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15]
node _T_2626 = mux(_T_2625, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_2627 = and(_T_2626, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 676:47]
io.iccm_wr_size <= _T_2627 @[el2_ifu_mem_ctl.scala 676:19]
node _T_2628 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 677:54]
wire _T_2629 : UInt<1>[18] @[el2_lib.scala 245:18]
wire _T_2630 : UInt<1>[18] @[el2_lib.scala 246:18]
wire _T_2631 : UInt<1>[18] @[el2_lib.scala 247:18]
wire _T_2632 : UInt<1>[15] @[el2_lib.scala 248:18]
wire _T_2633 : UInt<1>[15] @[el2_lib.scala 249:18]
wire _T_2634 : UInt<1>[6] @[el2_lib.scala 250:18]
node _T_2635 = bits(_T_2628, 0, 0) @[el2_lib.scala 257:36]
_T_2630[0] <= _T_2635 @[el2_lib.scala 257:30]
node _T_2636 = bits(_T_2628, 0, 0) @[el2_lib.scala 258:36]
_T_2631[0] <= _T_2636 @[el2_lib.scala 258:30]
node _T_2637 = bits(_T_2628, 0, 0) @[el2_lib.scala 261:36]
_T_2634[0] <= _T_2637 @[el2_lib.scala 261:30]
node _T_2638 = bits(_T_2628, 1, 1) @[el2_lib.scala 256:36]
_T_2629[0] <= _T_2638 @[el2_lib.scala 256:30]
node _T_2639 = bits(_T_2628, 1, 1) @[el2_lib.scala 258:36]
_T_2631[1] <= _T_2639 @[el2_lib.scala 258:30]
node _T_2640 = bits(_T_2628, 1, 1) @[el2_lib.scala 261:36]
_T_2634[1] <= _T_2640 @[el2_lib.scala 261:30]
node _T_2641 = bits(_T_2628, 2, 2) @[el2_lib.scala 258:36]
_T_2631[2] <= _T_2641 @[el2_lib.scala 258:30]
node _T_2642 = bits(_T_2628, 2, 2) @[el2_lib.scala 261:36]
_T_2634[2] <= _T_2642 @[el2_lib.scala 261:30]
node _T_2643 = bits(_T_2628, 3, 3) @[el2_lib.scala 256:36]
_T_2629[1] <= _T_2643 @[el2_lib.scala 256:30]
node _T_2644 = bits(_T_2628, 3, 3) @[el2_lib.scala 257:36]
_T_2630[1] <= _T_2644 @[el2_lib.scala 257:30]
node _T_2645 = bits(_T_2628, 3, 3) @[el2_lib.scala 261:36]
_T_2634[3] <= _T_2645 @[el2_lib.scala 261:30]
node _T_2646 = bits(_T_2628, 4, 4) @[el2_lib.scala 257:36]
_T_2630[2] <= _T_2646 @[el2_lib.scala 257:30]
node _T_2647 = bits(_T_2628, 4, 4) @[el2_lib.scala 261:36]
_T_2634[4] <= _T_2647 @[el2_lib.scala 261:30]
node _T_2648 = bits(_T_2628, 5, 5) @[el2_lib.scala 256:36]
_T_2629[2] <= _T_2648 @[el2_lib.scala 256:30]
node _T_2649 = bits(_T_2628, 5, 5) @[el2_lib.scala 261:36]
_T_2634[5] <= _T_2649 @[el2_lib.scala 261:30]
node _T_2650 = bits(_T_2628, 6, 6) @[el2_lib.scala 256:36]
_T_2629[3] <= _T_2650 @[el2_lib.scala 256:30]
node _T_2651 = bits(_T_2628, 6, 6) @[el2_lib.scala 257:36]
_T_2630[3] <= _T_2651 @[el2_lib.scala 257:30]
node _T_2652 = bits(_T_2628, 6, 6) @[el2_lib.scala 258:36]
_T_2631[3] <= _T_2652 @[el2_lib.scala 258:30]
node _T_2653 = bits(_T_2628, 6, 6) @[el2_lib.scala 259:36]
_T_2632[0] <= _T_2653 @[el2_lib.scala 259:30]
node _T_2654 = bits(_T_2628, 6, 6) @[el2_lib.scala 260:36]
_T_2633[0] <= _T_2654 @[el2_lib.scala 260:30]
node _T_2655 = bits(_T_2628, 7, 7) @[el2_lib.scala 257:36]
_T_2630[4] <= _T_2655 @[el2_lib.scala 257:30]
node _T_2656 = bits(_T_2628, 7, 7) @[el2_lib.scala 258:36]
_T_2631[4] <= _T_2656 @[el2_lib.scala 258:30]
node _T_2657 = bits(_T_2628, 7, 7) @[el2_lib.scala 259:36]
_T_2632[1] <= _T_2657 @[el2_lib.scala 259:30]
node _T_2658 = bits(_T_2628, 7, 7) @[el2_lib.scala 260:36]
_T_2633[1] <= _T_2658 @[el2_lib.scala 260:30]
node _T_2659 = bits(_T_2628, 8, 8) @[el2_lib.scala 256:36]
_T_2629[4] <= _T_2659 @[el2_lib.scala 256:30]
node _T_2660 = bits(_T_2628, 8, 8) @[el2_lib.scala 258:36]
_T_2631[5] <= _T_2660 @[el2_lib.scala 258:30]
node _T_2661 = bits(_T_2628, 8, 8) @[el2_lib.scala 259:36]
_T_2632[2] <= _T_2661 @[el2_lib.scala 259:30]
node _T_2662 = bits(_T_2628, 8, 8) @[el2_lib.scala 260:36]
_T_2633[2] <= _T_2662 @[el2_lib.scala 260:30]
node _T_2663 = bits(_T_2628, 9, 9) @[el2_lib.scala 258:36]
_T_2631[6] <= _T_2663 @[el2_lib.scala 258:30]
node _T_2664 = bits(_T_2628, 9, 9) @[el2_lib.scala 259:36]
_T_2632[3] <= _T_2664 @[el2_lib.scala 259:30]
node _T_2665 = bits(_T_2628, 9, 9) @[el2_lib.scala 260:36]
_T_2633[3] <= _T_2665 @[el2_lib.scala 260:30]
node _T_2666 = bits(_T_2628, 10, 10) @[el2_lib.scala 256:36]
_T_2629[5] <= _T_2666 @[el2_lib.scala 256:30]
node _T_2667 = bits(_T_2628, 10, 10) @[el2_lib.scala 257:36]
_T_2630[5] <= _T_2667 @[el2_lib.scala 257:30]
node _T_2668 = bits(_T_2628, 10, 10) @[el2_lib.scala 259:36]
_T_2632[4] <= _T_2668 @[el2_lib.scala 259:30]
node _T_2669 = bits(_T_2628, 10, 10) @[el2_lib.scala 260:36]
_T_2633[4] <= _T_2669 @[el2_lib.scala 260:30]
node _T_2670 = bits(_T_2628, 11, 11) @[el2_lib.scala 257:36]
_T_2630[6] <= _T_2670 @[el2_lib.scala 257:30]
node _T_2671 = bits(_T_2628, 11, 11) @[el2_lib.scala 259:36]
_T_2632[5] <= _T_2671 @[el2_lib.scala 259:30]
node _T_2672 = bits(_T_2628, 11, 11) @[el2_lib.scala 260:36]
_T_2633[5] <= _T_2672 @[el2_lib.scala 260:30]
node _T_2673 = bits(_T_2628, 12, 12) @[el2_lib.scala 256:36]
_T_2629[6] <= _T_2673 @[el2_lib.scala 256:30]
node _T_2674 = bits(_T_2628, 12, 12) @[el2_lib.scala 259:36]
_T_2632[6] <= _T_2674 @[el2_lib.scala 259:30]
node _T_2675 = bits(_T_2628, 12, 12) @[el2_lib.scala 260:36]
_T_2633[6] <= _T_2675 @[el2_lib.scala 260:30]
node _T_2676 = bits(_T_2628, 13, 13) @[el2_lib.scala 259:36]
_T_2632[7] <= _T_2676 @[el2_lib.scala 259:30]
node _T_2677 = bits(_T_2628, 13, 13) @[el2_lib.scala 260:36]
_T_2633[7] <= _T_2677 @[el2_lib.scala 260:30]
node _T_2678 = bits(_T_2628, 14, 14) @[el2_lib.scala 256:36]
_T_2629[7] <= _T_2678 @[el2_lib.scala 256:30]
node _T_2679 = bits(_T_2628, 14, 14) @[el2_lib.scala 257:36]
_T_2630[7] <= _T_2679 @[el2_lib.scala 257:30]
node _T_2680 = bits(_T_2628, 14, 14) @[el2_lib.scala 258:36]
_T_2631[7] <= _T_2680 @[el2_lib.scala 258:30]
node _T_2681 = bits(_T_2628, 14, 14) @[el2_lib.scala 260:36]
_T_2633[8] <= _T_2681 @[el2_lib.scala 260:30]
node _T_2682 = bits(_T_2628, 15, 15) @[el2_lib.scala 257:36]
_T_2630[8] <= _T_2682 @[el2_lib.scala 257:30]
node _T_2683 = bits(_T_2628, 15, 15) @[el2_lib.scala 258:36]
_T_2631[8] <= _T_2683 @[el2_lib.scala 258:30]
node _T_2684 = bits(_T_2628, 15, 15) @[el2_lib.scala 260:36]
_T_2633[9] <= _T_2684 @[el2_lib.scala 260:30]
node _T_2685 = bits(_T_2628, 16, 16) @[el2_lib.scala 256:36]
_T_2629[8] <= _T_2685 @[el2_lib.scala 256:30]
node _T_2686 = bits(_T_2628, 16, 16) @[el2_lib.scala 258:36]
_T_2631[9] <= _T_2686 @[el2_lib.scala 258:30]
node _T_2687 = bits(_T_2628, 16, 16) @[el2_lib.scala 260:36]
_T_2633[10] <= _T_2687 @[el2_lib.scala 260:30]
node _T_2688 = bits(_T_2628, 17, 17) @[el2_lib.scala 258:36]
_T_2631[10] <= _T_2688 @[el2_lib.scala 258:30]
node _T_2689 = bits(_T_2628, 17, 17) @[el2_lib.scala 260:36]
_T_2633[11] <= _T_2689 @[el2_lib.scala 260:30]
node _T_2690 = bits(_T_2628, 18, 18) @[el2_lib.scala 256:36]
_T_2629[9] <= _T_2690 @[el2_lib.scala 256:30]
node _T_2691 = bits(_T_2628, 18, 18) @[el2_lib.scala 257:36]
_T_2630[9] <= _T_2691 @[el2_lib.scala 257:30]
node _T_2692 = bits(_T_2628, 18, 18) @[el2_lib.scala 260:36]
_T_2633[12] <= _T_2692 @[el2_lib.scala 260:30]
node _T_2693 = bits(_T_2628, 19, 19) @[el2_lib.scala 257:36]
_T_2630[10] <= _T_2693 @[el2_lib.scala 257:30]
node _T_2694 = bits(_T_2628, 19, 19) @[el2_lib.scala 260:36]
_T_2633[13] <= _T_2694 @[el2_lib.scala 260:30]
node _T_2695 = bits(_T_2628, 20, 20) @[el2_lib.scala 256:36]
_T_2629[10] <= _T_2695 @[el2_lib.scala 256:30]
node _T_2696 = bits(_T_2628, 20, 20) @[el2_lib.scala 260:36]
_T_2633[14] <= _T_2696 @[el2_lib.scala 260:30]
node _T_2697 = bits(_T_2628, 21, 21) @[el2_lib.scala 256:36]
_T_2629[11] <= _T_2697 @[el2_lib.scala 256:30]
node _T_2698 = bits(_T_2628, 21, 21) @[el2_lib.scala 257:36]
_T_2630[11] <= _T_2698 @[el2_lib.scala 257:30]
node _T_2699 = bits(_T_2628, 21, 21) @[el2_lib.scala 258:36]
_T_2631[11] <= _T_2699 @[el2_lib.scala 258:30]
node _T_2700 = bits(_T_2628, 21, 21) @[el2_lib.scala 259:36]
_T_2632[8] <= _T_2700 @[el2_lib.scala 259:30]
node _T_2701 = bits(_T_2628, 22, 22) @[el2_lib.scala 257:36]
_T_2630[12] <= _T_2701 @[el2_lib.scala 257:30]
node _T_2702 = bits(_T_2628, 22, 22) @[el2_lib.scala 258:36]
_T_2631[12] <= _T_2702 @[el2_lib.scala 258:30]
node _T_2703 = bits(_T_2628, 22, 22) @[el2_lib.scala 259:36]
_T_2632[9] <= _T_2703 @[el2_lib.scala 259:30]
node _T_2704 = bits(_T_2628, 23, 23) @[el2_lib.scala 256:36]
_T_2629[12] <= _T_2704 @[el2_lib.scala 256:30]
node _T_2705 = bits(_T_2628, 23, 23) @[el2_lib.scala 258:36]
_T_2631[13] <= _T_2705 @[el2_lib.scala 258:30]
node _T_2706 = bits(_T_2628, 23, 23) @[el2_lib.scala 259:36]
_T_2632[10] <= _T_2706 @[el2_lib.scala 259:30]
node _T_2707 = bits(_T_2628, 24, 24) @[el2_lib.scala 258:36]
_T_2631[14] <= _T_2707 @[el2_lib.scala 258:30]
node _T_2708 = bits(_T_2628, 24, 24) @[el2_lib.scala 259:36]
_T_2632[11] <= _T_2708 @[el2_lib.scala 259:30]
node _T_2709 = bits(_T_2628, 25, 25) @[el2_lib.scala 256:36]
_T_2629[13] <= _T_2709 @[el2_lib.scala 256:30]
node _T_2710 = bits(_T_2628, 25, 25) @[el2_lib.scala 257:36]
_T_2630[13] <= _T_2710 @[el2_lib.scala 257:30]
node _T_2711 = bits(_T_2628, 25, 25) @[el2_lib.scala 259:36]
_T_2632[12] <= _T_2711 @[el2_lib.scala 259:30]
node _T_2712 = bits(_T_2628, 26, 26) @[el2_lib.scala 257:36]
_T_2630[14] <= _T_2712 @[el2_lib.scala 257:30]
node _T_2713 = bits(_T_2628, 26, 26) @[el2_lib.scala 259:36]
_T_2632[13] <= _T_2713 @[el2_lib.scala 259:30]
node _T_2714 = bits(_T_2628, 27, 27) @[el2_lib.scala 256:36]
_T_2629[14] <= _T_2714 @[el2_lib.scala 256:30]
node _T_2715 = bits(_T_2628, 27, 27) @[el2_lib.scala 259:36]
_T_2632[14] <= _T_2715 @[el2_lib.scala 259:30]
node _T_2716 = bits(_T_2628, 28, 28) @[el2_lib.scala 256:36]
_T_2629[15] <= _T_2716 @[el2_lib.scala 256:30]
node _T_2717 = bits(_T_2628, 28, 28) @[el2_lib.scala 257:36]
_T_2630[15] <= _T_2717 @[el2_lib.scala 257:30]
node _T_2718 = bits(_T_2628, 28, 28) @[el2_lib.scala 258:36]
_T_2631[15] <= _T_2718 @[el2_lib.scala 258:30]
node _T_2719 = bits(_T_2628, 29, 29) @[el2_lib.scala 257:36]
_T_2630[16] <= _T_2719 @[el2_lib.scala 257:30]
node _T_2720 = bits(_T_2628, 29, 29) @[el2_lib.scala 258:36]
_T_2631[16] <= _T_2720 @[el2_lib.scala 258:30]
node _T_2721 = bits(_T_2628, 30, 30) @[el2_lib.scala 256:36]
_T_2629[16] <= _T_2721 @[el2_lib.scala 256:30]
node _T_2722 = bits(_T_2628, 30, 30) @[el2_lib.scala 258:36]
_T_2631[17] <= _T_2722 @[el2_lib.scala 258:30]
node _T_2723 = bits(_T_2628, 31, 31) @[el2_lib.scala 256:36]
_T_2629[17] <= _T_2723 @[el2_lib.scala 256:30]
node _T_2724 = bits(_T_2628, 31, 31) @[el2_lib.scala 257:36]
_T_2630[17] <= _T_2724 @[el2_lib.scala 257:30]
node _T_2725 = cat(_T_2629[1], _T_2629[0]) @[el2_lib.scala 263:22]
node _T_2726 = cat(_T_2629[3], _T_2629[2]) @[el2_lib.scala 263:22]
node _T_2727 = cat(_T_2726, _T_2725) @[el2_lib.scala 263:22]
node _T_2728 = cat(_T_2629[5], _T_2629[4]) @[el2_lib.scala 263:22]
node _T_2729 = cat(_T_2629[8], _T_2629[7]) @[el2_lib.scala 263:22]
node _T_2730 = cat(_T_2729, _T_2629[6]) @[el2_lib.scala 263:22]
node _T_2731 = cat(_T_2730, _T_2728) @[el2_lib.scala 263:22]
node _T_2732 = cat(_T_2731, _T_2727) @[el2_lib.scala 263:22]
node _T_2733 = cat(_T_2629[10], _T_2629[9]) @[el2_lib.scala 263:22]
node _T_2734 = cat(_T_2629[12], _T_2629[11]) @[el2_lib.scala 263:22]
node _T_2735 = cat(_T_2734, _T_2733) @[el2_lib.scala 263:22]
node _T_2736 = cat(_T_2629[14], _T_2629[13]) @[el2_lib.scala 263:22]
node _T_2737 = cat(_T_2629[17], _T_2629[16]) @[el2_lib.scala 263:22]
node _T_2738 = cat(_T_2737, _T_2629[15]) @[el2_lib.scala 263:22]
node _T_2739 = cat(_T_2738, _T_2736) @[el2_lib.scala 263:22]
node _T_2740 = cat(_T_2739, _T_2735) @[el2_lib.scala 263:22]
node _T_2741 = cat(_T_2740, _T_2732) @[el2_lib.scala 263:22]
node _T_2742 = xorr(_T_2741) @[el2_lib.scala 263:29]
node _T_2743 = cat(_T_2630[1], _T_2630[0]) @[el2_lib.scala 263:39]
node _T_2744 = cat(_T_2630[3], _T_2630[2]) @[el2_lib.scala 263:39]
node _T_2745 = cat(_T_2744, _T_2743) @[el2_lib.scala 263:39]
node _T_2746 = cat(_T_2630[5], _T_2630[4]) @[el2_lib.scala 263:39]
node _T_2747 = cat(_T_2630[8], _T_2630[7]) @[el2_lib.scala 263:39]
node _T_2748 = cat(_T_2747, _T_2630[6]) @[el2_lib.scala 263:39]
node _T_2749 = cat(_T_2748, _T_2746) @[el2_lib.scala 263:39]
node _T_2750 = cat(_T_2749, _T_2745) @[el2_lib.scala 263:39]
node _T_2751 = cat(_T_2630[10], _T_2630[9]) @[el2_lib.scala 263:39]
node _T_2752 = cat(_T_2630[12], _T_2630[11]) @[el2_lib.scala 263:39]
node _T_2753 = cat(_T_2752, _T_2751) @[el2_lib.scala 263:39]
node _T_2754 = cat(_T_2630[14], _T_2630[13]) @[el2_lib.scala 263:39]
node _T_2755 = cat(_T_2630[17], _T_2630[16]) @[el2_lib.scala 263:39]
node _T_2756 = cat(_T_2755, _T_2630[15]) @[el2_lib.scala 263:39]
node _T_2757 = cat(_T_2756, _T_2754) @[el2_lib.scala 263:39]
node _T_2758 = cat(_T_2757, _T_2753) @[el2_lib.scala 263:39]
node _T_2759 = cat(_T_2758, _T_2750) @[el2_lib.scala 263:39]
node _T_2760 = xorr(_T_2759) @[el2_lib.scala 263:46]
node _T_2761 = cat(_T_2631[1], _T_2631[0]) @[el2_lib.scala 263:56]
node _T_2762 = cat(_T_2631[3], _T_2631[2]) @[el2_lib.scala 263:56]
node _T_2763 = cat(_T_2762, _T_2761) @[el2_lib.scala 263:56]
node _T_2764 = cat(_T_2631[5], _T_2631[4]) @[el2_lib.scala 263:56]
node _T_2765 = cat(_T_2631[8], _T_2631[7]) @[el2_lib.scala 263:56]
node _T_2766 = cat(_T_2765, _T_2631[6]) @[el2_lib.scala 263:56]
node _T_2767 = cat(_T_2766, _T_2764) @[el2_lib.scala 263:56]
node _T_2768 = cat(_T_2767, _T_2763) @[el2_lib.scala 263:56]
node _T_2769 = cat(_T_2631[10], _T_2631[9]) @[el2_lib.scala 263:56]
node _T_2770 = cat(_T_2631[12], _T_2631[11]) @[el2_lib.scala 263:56]
node _T_2771 = cat(_T_2770, _T_2769) @[el2_lib.scala 263:56]
node _T_2772 = cat(_T_2631[14], _T_2631[13]) @[el2_lib.scala 263:56]
node _T_2773 = cat(_T_2631[17], _T_2631[16]) @[el2_lib.scala 263:56]
node _T_2774 = cat(_T_2773, _T_2631[15]) @[el2_lib.scala 263:56]
node _T_2775 = cat(_T_2774, _T_2772) @[el2_lib.scala 263:56]
node _T_2776 = cat(_T_2775, _T_2771) @[el2_lib.scala 263:56]
node _T_2777 = cat(_T_2776, _T_2768) @[el2_lib.scala 263:56]
node _T_2778 = xorr(_T_2777) @[el2_lib.scala 263:63]
node _T_2779 = cat(_T_2632[2], _T_2632[1]) @[el2_lib.scala 263:73]
node _T_2780 = cat(_T_2779, _T_2632[0]) @[el2_lib.scala 263:73]
node _T_2781 = cat(_T_2632[4], _T_2632[3]) @[el2_lib.scala 263:73]
node _T_2782 = cat(_T_2632[6], _T_2632[5]) @[el2_lib.scala 263:73]
node _T_2783 = cat(_T_2782, _T_2781) @[el2_lib.scala 263:73]
node _T_2784 = cat(_T_2783, _T_2780) @[el2_lib.scala 263:73]
node _T_2785 = cat(_T_2632[8], _T_2632[7]) @[el2_lib.scala 263:73]
node _T_2786 = cat(_T_2632[10], _T_2632[9]) @[el2_lib.scala 263:73]
node _T_2787 = cat(_T_2786, _T_2785) @[el2_lib.scala 263:73]
node _T_2788 = cat(_T_2632[12], _T_2632[11]) @[el2_lib.scala 263:73]
node _T_2789 = cat(_T_2632[14], _T_2632[13]) @[el2_lib.scala 263:73]
node _T_2790 = cat(_T_2789, _T_2788) @[el2_lib.scala 263:73]
node _T_2791 = cat(_T_2790, _T_2787) @[el2_lib.scala 263:73]
node _T_2792 = cat(_T_2791, _T_2784) @[el2_lib.scala 263:73]
node _T_2793 = xorr(_T_2792) @[el2_lib.scala 263:80]
node _T_2794 = cat(_T_2633[2], _T_2633[1]) @[el2_lib.scala 263:90]
node _T_2795 = cat(_T_2794, _T_2633[0]) @[el2_lib.scala 263:90]
node _T_2796 = cat(_T_2633[4], _T_2633[3]) @[el2_lib.scala 263:90]
node _T_2797 = cat(_T_2633[6], _T_2633[5]) @[el2_lib.scala 263:90]
node _T_2798 = cat(_T_2797, _T_2796) @[el2_lib.scala 263:90]
node _T_2799 = cat(_T_2798, _T_2795) @[el2_lib.scala 263:90]
node _T_2800 = cat(_T_2633[8], _T_2633[7]) @[el2_lib.scala 263:90]
node _T_2801 = cat(_T_2633[10], _T_2633[9]) @[el2_lib.scala 263:90]
node _T_2802 = cat(_T_2801, _T_2800) @[el2_lib.scala 263:90]
node _T_2803 = cat(_T_2633[12], _T_2633[11]) @[el2_lib.scala 263:90]
node _T_2804 = cat(_T_2633[14], _T_2633[13]) @[el2_lib.scala 263:90]
node _T_2805 = cat(_T_2804, _T_2803) @[el2_lib.scala 263:90]
node _T_2806 = cat(_T_2805, _T_2802) @[el2_lib.scala 263:90]
node _T_2807 = cat(_T_2806, _T_2799) @[el2_lib.scala 263:90]
node _T_2808 = xorr(_T_2807) @[el2_lib.scala 263:97]
node _T_2809 = cat(_T_2634[2], _T_2634[1]) @[el2_lib.scala 263:107]
node _T_2810 = cat(_T_2809, _T_2634[0]) @[el2_lib.scala 263:107]
node _T_2811 = cat(_T_2634[5], _T_2634[4]) @[el2_lib.scala 263:107]
node _T_2812 = cat(_T_2811, _T_2634[3]) @[el2_lib.scala 263:107]
node _T_2813 = cat(_T_2812, _T_2810) @[el2_lib.scala 263:107]
node _T_2814 = xorr(_T_2813) @[el2_lib.scala 263:114]
node _T_2815 = cat(_T_2793, _T_2808) @[Cat.scala 29:58]
node _T_2816 = cat(_T_2815, _T_2814) @[Cat.scala 29:58]
node _T_2817 = cat(_T_2742, _T_2760) @[Cat.scala 29:58]
node _T_2818 = cat(_T_2817, _T_2778) @[Cat.scala 29:58]
node _T_2819 = cat(_T_2818, _T_2816) @[Cat.scala 29:58]
node _T_2820 = xorr(_T_2628) @[el2_lib.scala 264:13]
node _T_2821 = xorr(_T_2819) @[el2_lib.scala 264:23]
node _T_2822 = xor(_T_2820, _T_2821) @[el2_lib.scala 264:18]
node _T_2823 = cat(_T_2822, _T_2819) @[Cat.scala 29:58]
node _T_2824 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 677:93]
wire _T_2825 : UInt<1>[18] @[el2_lib.scala 245:18]
wire _T_2826 : UInt<1>[18] @[el2_lib.scala 246:18]
wire _T_2827 : UInt<1>[18] @[el2_lib.scala 247:18]
wire _T_2828 : UInt<1>[15] @[el2_lib.scala 248:18]
wire _T_2829 : UInt<1>[15] @[el2_lib.scala 249:18]
wire _T_2830 : UInt<1>[6] @[el2_lib.scala 250:18]
node _T_2831 = bits(_T_2824, 0, 0) @[el2_lib.scala 257:36]
_T_2826[0] <= _T_2831 @[el2_lib.scala 257:30]
node _T_2832 = bits(_T_2824, 0, 0) @[el2_lib.scala 258:36]
_T_2827[0] <= _T_2832 @[el2_lib.scala 258:30]
node _T_2833 = bits(_T_2824, 0, 0) @[el2_lib.scala 261:36]
_T_2830[0] <= _T_2833 @[el2_lib.scala 261:30]
node _T_2834 = bits(_T_2824, 1, 1) @[el2_lib.scala 256:36]
_T_2825[0] <= _T_2834 @[el2_lib.scala 256:30]
node _T_2835 = bits(_T_2824, 1, 1) @[el2_lib.scala 258:36]
_T_2827[1] <= _T_2835 @[el2_lib.scala 258:30]
node _T_2836 = bits(_T_2824, 1, 1) @[el2_lib.scala 261:36]
_T_2830[1] <= _T_2836 @[el2_lib.scala 261:30]
node _T_2837 = bits(_T_2824, 2, 2) @[el2_lib.scala 258:36]
_T_2827[2] <= _T_2837 @[el2_lib.scala 258:30]
node _T_2838 = bits(_T_2824, 2, 2) @[el2_lib.scala 261:36]
_T_2830[2] <= _T_2838 @[el2_lib.scala 261:30]
node _T_2839 = bits(_T_2824, 3, 3) @[el2_lib.scala 256:36]
_T_2825[1] <= _T_2839 @[el2_lib.scala 256:30]
node _T_2840 = bits(_T_2824, 3, 3) @[el2_lib.scala 257:36]
_T_2826[1] <= _T_2840 @[el2_lib.scala 257:30]
node _T_2841 = bits(_T_2824, 3, 3) @[el2_lib.scala 261:36]
_T_2830[3] <= _T_2841 @[el2_lib.scala 261:30]
node _T_2842 = bits(_T_2824, 4, 4) @[el2_lib.scala 257:36]
_T_2826[2] <= _T_2842 @[el2_lib.scala 257:30]
node _T_2843 = bits(_T_2824, 4, 4) @[el2_lib.scala 261:36]
_T_2830[4] <= _T_2843 @[el2_lib.scala 261:30]
node _T_2844 = bits(_T_2824, 5, 5) @[el2_lib.scala 256:36]
_T_2825[2] <= _T_2844 @[el2_lib.scala 256:30]
node _T_2845 = bits(_T_2824, 5, 5) @[el2_lib.scala 261:36]
_T_2830[5] <= _T_2845 @[el2_lib.scala 261:30]
node _T_2846 = bits(_T_2824, 6, 6) @[el2_lib.scala 256:36]
_T_2825[3] <= _T_2846 @[el2_lib.scala 256:30]
node _T_2847 = bits(_T_2824, 6, 6) @[el2_lib.scala 257:36]
_T_2826[3] <= _T_2847 @[el2_lib.scala 257:30]
node _T_2848 = bits(_T_2824, 6, 6) @[el2_lib.scala 258:36]
_T_2827[3] <= _T_2848 @[el2_lib.scala 258:30]
node _T_2849 = bits(_T_2824, 6, 6) @[el2_lib.scala 259:36]
_T_2828[0] <= _T_2849 @[el2_lib.scala 259:30]
node _T_2850 = bits(_T_2824, 6, 6) @[el2_lib.scala 260:36]
_T_2829[0] <= _T_2850 @[el2_lib.scala 260:30]
node _T_2851 = bits(_T_2824, 7, 7) @[el2_lib.scala 257:36]
_T_2826[4] <= _T_2851 @[el2_lib.scala 257:30]
node _T_2852 = bits(_T_2824, 7, 7) @[el2_lib.scala 258:36]
_T_2827[4] <= _T_2852 @[el2_lib.scala 258:30]
node _T_2853 = bits(_T_2824, 7, 7) @[el2_lib.scala 259:36]
_T_2828[1] <= _T_2853 @[el2_lib.scala 259:30]
node _T_2854 = bits(_T_2824, 7, 7) @[el2_lib.scala 260:36]
_T_2829[1] <= _T_2854 @[el2_lib.scala 260:30]
node _T_2855 = bits(_T_2824, 8, 8) @[el2_lib.scala 256:36]
_T_2825[4] <= _T_2855 @[el2_lib.scala 256:30]
node _T_2856 = bits(_T_2824, 8, 8) @[el2_lib.scala 258:36]
_T_2827[5] <= _T_2856 @[el2_lib.scala 258:30]
node _T_2857 = bits(_T_2824, 8, 8) @[el2_lib.scala 259:36]
_T_2828[2] <= _T_2857 @[el2_lib.scala 259:30]
node _T_2858 = bits(_T_2824, 8, 8) @[el2_lib.scala 260:36]
_T_2829[2] <= _T_2858 @[el2_lib.scala 260:30]
node _T_2859 = bits(_T_2824, 9, 9) @[el2_lib.scala 258:36]
_T_2827[6] <= _T_2859 @[el2_lib.scala 258:30]
node _T_2860 = bits(_T_2824, 9, 9) @[el2_lib.scala 259:36]
_T_2828[3] <= _T_2860 @[el2_lib.scala 259:30]
node _T_2861 = bits(_T_2824, 9, 9) @[el2_lib.scala 260:36]
_T_2829[3] <= _T_2861 @[el2_lib.scala 260:30]
node _T_2862 = bits(_T_2824, 10, 10) @[el2_lib.scala 256:36]
_T_2825[5] <= _T_2862 @[el2_lib.scala 256:30]
node _T_2863 = bits(_T_2824, 10, 10) @[el2_lib.scala 257:36]
_T_2826[5] <= _T_2863 @[el2_lib.scala 257:30]
node _T_2864 = bits(_T_2824, 10, 10) @[el2_lib.scala 259:36]
_T_2828[4] <= _T_2864 @[el2_lib.scala 259:30]
node _T_2865 = bits(_T_2824, 10, 10) @[el2_lib.scala 260:36]
_T_2829[4] <= _T_2865 @[el2_lib.scala 260:30]
node _T_2866 = bits(_T_2824, 11, 11) @[el2_lib.scala 257:36]
_T_2826[6] <= _T_2866 @[el2_lib.scala 257:30]
node _T_2867 = bits(_T_2824, 11, 11) @[el2_lib.scala 259:36]
_T_2828[5] <= _T_2867 @[el2_lib.scala 259:30]
node _T_2868 = bits(_T_2824, 11, 11) @[el2_lib.scala 260:36]
_T_2829[5] <= _T_2868 @[el2_lib.scala 260:30]
node _T_2869 = bits(_T_2824, 12, 12) @[el2_lib.scala 256:36]
_T_2825[6] <= _T_2869 @[el2_lib.scala 256:30]
node _T_2870 = bits(_T_2824, 12, 12) @[el2_lib.scala 259:36]
_T_2828[6] <= _T_2870 @[el2_lib.scala 259:30]
node _T_2871 = bits(_T_2824, 12, 12) @[el2_lib.scala 260:36]
_T_2829[6] <= _T_2871 @[el2_lib.scala 260:30]
node _T_2872 = bits(_T_2824, 13, 13) @[el2_lib.scala 259:36]
_T_2828[7] <= _T_2872 @[el2_lib.scala 259:30]
node _T_2873 = bits(_T_2824, 13, 13) @[el2_lib.scala 260:36]
_T_2829[7] <= _T_2873 @[el2_lib.scala 260:30]
node _T_2874 = bits(_T_2824, 14, 14) @[el2_lib.scala 256:36]
_T_2825[7] <= _T_2874 @[el2_lib.scala 256:30]
node _T_2875 = bits(_T_2824, 14, 14) @[el2_lib.scala 257:36]
_T_2826[7] <= _T_2875 @[el2_lib.scala 257:30]
node _T_2876 = bits(_T_2824, 14, 14) @[el2_lib.scala 258:36]
_T_2827[7] <= _T_2876 @[el2_lib.scala 258:30]
node _T_2877 = bits(_T_2824, 14, 14) @[el2_lib.scala 260:36]
_T_2829[8] <= _T_2877 @[el2_lib.scala 260:30]
node _T_2878 = bits(_T_2824, 15, 15) @[el2_lib.scala 257:36]
_T_2826[8] <= _T_2878 @[el2_lib.scala 257:30]
node _T_2879 = bits(_T_2824, 15, 15) @[el2_lib.scala 258:36]
_T_2827[8] <= _T_2879 @[el2_lib.scala 258:30]
node _T_2880 = bits(_T_2824, 15, 15) @[el2_lib.scala 260:36]
_T_2829[9] <= _T_2880 @[el2_lib.scala 260:30]
node _T_2881 = bits(_T_2824, 16, 16) @[el2_lib.scala 256:36]
_T_2825[8] <= _T_2881 @[el2_lib.scala 256:30]
node _T_2882 = bits(_T_2824, 16, 16) @[el2_lib.scala 258:36]
_T_2827[9] <= _T_2882 @[el2_lib.scala 258:30]
node _T_2883 = bits(_T_2824, 16, 16) @[el2_lib.scala 260:36]
_T_2829[10] <= _T_2883 @[el2_lib.scala 260:30]
node _T_2884 = bits(_T_2824, 17, 17) @[el2_lib.scala 258:36]
_T_2827[10] <= _T_2884 @[el2_lib.scala 258:30]
node _T_2885 = bits(_T_2824, 17, 17) @[el2_lib.scala 260:36]
_T_2829[11] <= _T_2885 @[el2_lib.scala 260:30]
node _T_2886 = bits(_T_2824, 18, 18) @[el2_lib.scala 256:36]
_T_2825[9] <= _T_2886 @[el2_lib.scala 256:30]
node _T_2887 = bits(_T_2824, 18, 18) @[el2_lib.scala 257:36]
_T_2826[9] <= _T_2887 @[el2_lib.scala 257:30]
node _T_2888 = bits(_T_2824, 18, 18) @[el2_lib.scala 260:36]
_T_2829[12] <= _T_2888 @[el2_lib.scala 260:30]
node _T_2889 = bits(_T_2824, 19, 19) @[el2_lib.scala 257:36]
_T_2826[10] <= _T_2889 @[el2_lib.scala 257:30]
node _T_2890 = bits(_T_2824, 19, 19) @[el2_lib.scala 260:36]
_T_2829[13] <= _T_2890 @[el2_lib.scala 260:30]
node _T_2891 = bits(_T_2824, 20, 20) @[el2_lib.scala 256:36]
_T_2825[10] <= _T_2891 @[el2_lib.scala 256:30]
node _T_2892 = bits(_T_2824, 20, 20) @[el2_lib.scala 260:36]
_T_2829[14] <= _T_2892 @[el2_lib.scala 260:30]
node _T_2893 = bits(_T_2824, 21, 21) @[el2_lib.scala 256:36]
_T_2825[11] <= _T_2893 @[el2_lib.scala 256:30]
node _T_2894 = bits(_T_2824, 21, 21) @[el2_lib.scala 257:36]
_T_2826[11] <= _T_2894 @[el2_lib.scala 257:30]
node _T_2895 = bits(_T_2824, 21, 21) @[el2_lib.scala 258:36]
_T_2827[11] <= _T_2895 @[el2_lib.scala 258:30]
node _T_2896 = bits(_T_2824, 21, 21) @[el2_lib.scala 259:36]
_T_2828[8] <= _T_2896 @[el2_lib.scala 259:30]
node _T_2897 = bits(_T_2824, 22, 22) @[el2_lib.scala 257:36]
_T_2826[12] <= _T_2897 @[el2_lib.scala 257:30]
node _T_2898 = bits(_T_2824, 22, 22) @[el2_lib.scala 258:36]
_T_2827[12] <= _T_2898 @[el2_lib.scala 258:30]
node _T_2899 = bits(_T_2824, 22, 22) @[el2_lib.scala 259:36]
_T_2828[9] <= _T_2899 @[el2_lib.scala 259:30]
node _T_2900 = bits(_T_2824, 23, 23) @[el2_lib.scala 256:36]
_T_2825[12] <= _T_2900 @[el2_lib.scala 256:30]
node _T_2901 = bits(_T_2824, 23, 23) @[el2_lib.scala 258:36]
_T_2827[13] <= _T_2901 @[el2_lib.scala 258:30]
node _T_2902 = bits(_T_2824, 23, 23) @[el2_lib.scala 259:36]
_T_2828[10] <= _T_2902 @[el2_lib.scala 259:30]
node _T_2903 = bits(_T_2824, 24, 24) @[el2_lib.scala 258:36]
_T_2827[14] <= _T_2903 @[el2_lib.scala 258:30]
node _T_2904 = bits(_T_2824, 24, 24) @[el2_lib.scala 259:36]
_T_2828[11] <= _T_2904 @[el2_lib.scala 259:30]
node _T_2905 = bits(_T_2824, 25, 25) @[el2_lib.scala 256:36]
_T_2825[13] <= _T_2905 @[el2_lib.scala 256:30]
node _T_2906 = bits(_T_2824, 25, 25) @[el2_lib.scala 257:36]
_T_2826[13] <= _T_2906 @[el2_lib.scala 257:30]
node _T_2907 = bits(_T_2824, 25, 25) @[el2_lib.scala 259:36]
_T_2828[12] <= _T_2907 @[el2_lib.scala 259:30]
node _T_2908 = bits(_T_2824, 26, 26) @[el2_lib.scala 257:36]
_T_2826[14] <= _T_2908 @[el2_lib.scala 257:30]
node _T_2909 = bits(_T_2824, 26, 26) @[el2_lib.scala 259:36]
_T_2828[13] <= _T_2909 @[el2_lib.scala 259:30]
node _T_2910 = bits(_T_2824, 27, 27) @[el2_lib.scala 256:36]
_T_2825[14] <= _T_2910 @[el2_lib.scala 256:30]
node _T_2911 = bits(_T_2824, 27, 27) @[el2_lib.scala 259:36]
_T_2828[14] <= _T_2911 @[el2_lib.scala 259:30]
node _T_2912 = bits(_T_2824, 28, 28) @[el2_lib.scala 256:36]
_T_2825[15] <= _T_2912 @[el2_lib.scala 256:30]
node _T_2913 = bits(_T_2824, 28, 28) @[el2_lib.scala 257:36]
_T_2826[15] <= _T_2913 @[el2_lib.scala 257:30]
node _T_2914 = bits(_T_2824, 28, 28) @[el2_lib.scala 258:36]
_T_2827[15] <= _T_2914 @[el2_lib.scala 258:30]
node _T_2915 = bits(_T_2824, 29, 29) @[el2_lib.scala 257:36]
_T_2826[16] <= _T_2915 @[el2_lib.scala 257:30]
node _T_2916 = bits(_T_2824, 29, 29) @[el2_lib.scala 258:36]
_T_2827[16] <= _T_2916 @[el2_lib.scala 258:30]
node _T_2917 = bits(_T_2824, 30, 30) @[el2_lib.scala 256:36]
_T_2825[16] <= _T_2917 @[el2_lib.scala 256:30]
node _T_2918 = bits(_T_2824, 30, 30) @[el2_lib.scala 258:36]
_T_2827[17] <= _T_2918 @[el2_lib.scala 258:30]
node _T_2919 = bits(_T_2824, 31, 31) @[el2_lib.scala 256:36]
_T_2825[17] <= _T_2919 @[el2_lib.scala 256:30]
node _T_2920 = bits(_T_2824, 31, 31) @[el2_lib.scala 257:36]
_T_2826[17] <= _T_2920 @[el2_lib.scala 257:30]
node _T_2921 = cat(_T_2825[1], _T_2825[0]) @[el2_lib.scala 263:22]
node _T_2922 = cat(_T_2825[3], _T_2825[2]) @[el2_lib.scala 263:22]
node _T_2923 = cat(_T_2922, _T_2921) @[el2_lib.scala 263:22]
node _T_2924 = cat(_T_2825[5], _T_2825[4]) @[el2_lib.scala 263:22]
node _T_2925 = cat(_T_2825[8], _T_2825[7]) @[el2_lib.scala 263:22]
node _T_2926 = cat(_T_2925, _T_2825[6]) @[el2_lib.scala 263:22]
node _T_2927 = cat(_T_2926, _T_2924) @[el2_lib.scala 263:22]
node _T_2928 = cat(_T_2927, _T_2923) @[el2_lib.scala 263:22]
node _T_2929 = cat(_T_2825[10], _T_2825[9]) @[el2_lib.scala 263:22]
node _T_2930 = cat(_T_2825[12], _T_2825[11]) @[el2_lib.scala 263:22]
node _T_2931 = cat(_T_2930, _T_2929) @[el2_lib.scala 263:22]
node _T_2932 = cat(_T_2825[14], _T_2825[13]) @[el2_lib.scala 263:22]
node _T_2933 = cat(_T_2825[17], _T_2825[16]) @[el2_lib.scala 263:22]
node _T_2934 = cat(_T_2933, _T_2825[15]) @[el2_lib.scala 263:22]
node _T_2935 = cat(_T_2934, _T_2932) @[el2_lib.scala 263:22]
node _T_2936 = cat(_T_2935, _T_2931) @[el2_lib.scala 263:22]
node _T_2937 = cat(_T_2936, _T_2928) @[el2_lib.scala 263:22]
node _T_2938 = xorr(_T_2937) @[el2_lib.scala 263:29]
node _T_2939 = cat(_T_2826[1], _T_2826[0]) @[el2_lib.scala 263:39]
node _T_2940 = cat(_T_2826[3], _T_2826[2]) @[el2_lib.scala 263:39]
node _T_2941 = cat(_T_2940, _T_2939) @[el2_lib.scala 263:39]
node _T_2942 = cat(_T_2826[5], _T_2826[4]) @[el2_lib.scala 263:39]
node _T_2943 = cat(_T_2826[8], _T_2826[7]) @[el2_lib.scala 263:39]
node _T_2944 = cat(_T_2943, _T_2826[6]) @[el2_lib.scala 263:39]
node _T_2945 = cat(_T_2944, _T_2942) @[el2_lib.scala 263:39]
node _T_2946 = cat(_T_2945, _T_2941) @[el2_lib.scala 263:39]
node _T_2947 = cat(_T_2826[10], _T_2826[9]) @[el2_lib.scala 263:39]
node _T_2948 = cat(_T_2826[12], _T_2826[11]) @[el2_lib.scala 263:39]
node _T_2949 = cat(_T_2948, _T_2947) @[el2_lib.scala 263:39]
node _T_2950 = cat(_T_2826[14], _T_2826[13]) @[el2_lib.scala 263:39]
node _T_2951 = cat(_T_2826[17], _T_2826[16]) @[el2_lib.scala 263:39]
node _T_2952 = cat(_T_2951, _T_2826[15]) @[el2_lib.scala 263:39]
node _T_2953 = cat(_T_2952, _T_2950) @[el2_lib.scala 263:39]
node _T_2954 = cat(_T_2953, _T_2949) @[el2_lib.scala 263:39]
node _T_2955 = cat(_T_2954, _T_2946) @[el2_lib.scala 263:39]
node _T_2956 = xorr(_T_2955) @[el2_lib.scala 263:46]
node _T_2957 = cat(_T_2827[1], _T_2827[0]) @[el2_lib.scala 263:56]
node _T_2958 = cat(_T_2827[3], _T_2827[2]) @[el2_lib.scala 263:56]
node _T_2959 = cat(_T_2958, _T_2957) @[el2_lib.scala 263:56]
node _T_2960 = cat(_T_2827[5], _T_2827[4]) @[el2_lib.scala 263:56]
node _T_2961 = cat(_T_2827[8], _T_2827[7]) @[el2_lib.scala 263:56]
node _T_2962 = cat(_T_2961, _T_2827[6]) @[el2_lib.scala 263:56]
node _T_2963 = cat(_T_2962, _T_2960) @[el2_lib.scala 263:56]
node _T_2964 = cat(_T_2963, _T_2959) @[el2_lib.scala 263:56]
node _T_2965 = cat(_T_2827[10], _T_2827[9]) @[el2_lib.scala 263:56]
node _T_2966 = cat(_T_2827[12], _T_2827[11]) @[el2_lib.scala 263:56]
node _T_2967 = cat(_T_2966, _T_2965) @[el2_lib.scala 263:56]
node _T_2968 = cat(_T_2827[14], _T_2827[13]) @[el2_lib.scala 263:56]
node _T_2969 = cat(_T_2827[17], _T_2827[16]) @[el2_lib.scala 263:56]
node _T_2970 = cat(_T_2969, _T_2827[15]) @[el2_lib.scala 263:56]
node _T_2971 = cat(_T_2970, _T_2968) @[el2_lib.scala 263:56]
node _T_2972 = cat(_T_2971, _T_2967) @[el2_lib.scala 263:56]
node _T_2973 = cat(_T_2972, _T_2964) @[el2_lib.scala 263:56]
node _T_2974 = xorr(_T_2973) @[el2_lib.scala 263:63]
node _T_2975 = cat(_T_2828[2], _T_2828[1]) @[el2_lib.scala 263:73]
node _T_2976 = cat(_T_2975, _T_2828[0]) @[el2_lib.scala 263:73]
node _T_2977 = cat(_T_2828[4], _T_2828[3]) @[el2_lib.scala 263:73]
node _T_2978 = cat(_T_2828[6], _T_2828[5]) @[el2_lib.scala 263:73]
node _T_2979 = cat(_T_2978, _T_2977) @[el2_lib.scala 263:73]
node _T_2980 = cat(_T_2979, _T_2976) @[el2_lib.scala 263:73]
node _T_2981 = cat(_T_2828[8], _T_2828[7]) @[el2_lib.scala 263:73]
node _T_2982 = cat(_T_2828[10], _T_2828[9]) @[el2_lib.scala 263:73]
node _T_2983 = cat(_T_2982, _T_2981) @[el2_lib.scala 263:73]
node _T_2984 = cat(_T_2828[12], _T_2828[11]) @[el2_lib.scala 263:73]
node _T_2985 = cat(_T_2828[14], _T_2828[13]) @[el2_lib.scala 263:73]
node _T_2986 = cat(_T_2985, _T_2984) @[el2_lib.scala 263:73]
node _T_2987 = cat(_T_2986, _T_2983) @[el2_lib.scala 263:73]
node _T_2988 = cat(_T_2987, _T_2980) @[el2_lib.scala 263:73]
node _T_2989 = xorr(_T_2988) @[el2_lib.scala 263:80]
node _T_2990 = cat(_T_2829[2], _T_2829[1]) @[el2_lib.scala 263:90]
node _T_2991 = cat(_T_2990, _T_2829[0]) @[el2_lib.scala 263:90]
node _T_2992 = cat(_T_2829[4], _T_2829[3]) @[el2_lib.scala 263:90]
node _T_2993 = cat(_T_2829[6], _T_2829[5]) @[el2_lib.scala 263:90]
node _T_2994 = cat(_T_2993, _T_2992) @[el2_lib.scala 263:90]
node _T_2995 = cat(_T_2994, _T_2991) @[el2_lib.scala 263:90]
node _T_2996 = cat(_T_2829[8], _T_2829[7]) @[el2_lib.scala 263:90]
node _T_2997 = cat(_T_2829[10], _T_2829[9]) @[el2_lib.scala 263:90]
node _T_2998 = cat(_T_2997, _T_2996) @[el2_lib.scala 263:90]
node _T_2999 = cat(_T_2829[12], _T_2829[11]) @[el2_lib.scala 263:90]
node _T_3000 = cat(_T_2829[14], _T_2829[13]) @[el2_lib.scala 263:90]
node _T_3001 = cat(_T_3000, _T_2999) @[el2_lib.scala 263:90]
node _T_3002 = cat(_T_3001, _T_2998) @[el2_lib.scala 263:90]
node _T_3003 = cat(_T_3002, _T_2995) @[el2_lib.scala 263:90]
node _T_3004 = xorr(_T_3003) @[el2_lib.scala 263:97]
node _T_3005 = cat(_T_2830[2], _T_2830[1]) @[el2_lib.scala 263:107]
node _T_3006 = cat(_T_3005, _T_2830[0]) @[el2_lib.scala 263:107]
node _T_3007 = cat(_T_2830[5], _T_2830[4]) @[el2_lib.scala 263:107]
node _T_3008 = cat(_T_3007, _T_2830[3]) @[el2_lib.scala 263:107]
node _T_3009 = cat(_T_3008, _T_3006) @[el2_lib.scala 263:107]
node _T_3010 = xorr(_T_3009) @[el2_lib.scala 263:114]
node _T_3011 = cat(_T_2989, _T_3004) @[Cat.scala 29:58]
node _T_3012 = cat(_T_3011, _T_3010) @[Cat.scala 29:58]
node _T_3013 = cat(_T_2938, _T_2956) @[Cat.scala 29:58]
node _T_3014 = cat(_T_3013, _T_2974) @[Cat.scala 29:58]
node _T_3015 = cat(_T_3014, _T_3012) @[Cat.scala 29:58]
node _T_3016 = xorr(_T_2824) @[el2_lib.scala 264:13]
node _T_3017 = xorr(_T_3015) @[el2_lib.scala 264:23]
node _T_3018 = xor(_T_3016, _T_3017) @[el2_lib.scala 264:18]
node _T_3019 = cat(_T_3018, _T_3015) @[Cat.scala 29:58]
node dma_mem_ecc = cat(_T_2823, _T_3019) @[Cat.scala 29:58]
wire iccm_ecc_corr_data_ff : UInt<39>
iccm_ecc_corr_data_ff <= UInt<1>("h00")
node _T_3020 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 679:67]
node _T_3021 = eq(_T_3020, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 679:45]
node _T_3022 = and(iccm_correct_ecc, _T_3021) @[el2_ifu_mem_ctl.scala 679:43]
node _T_3023 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58]
node _T_3024 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 680:20]
node _T_3025 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 680:43]
node _T_3026 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 680:63]
node _T_3027 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 680:86]
node _T_3028 = cat(_T_3026, _T_3027) @[Cat.scala 29:58]
node _T_3029 = cat(_T_3024, _T_3025) @[Cat.scala 29:58]
node _T_3030 = cat(_T_3029, _T_3028) @[Cat.scala 29:58]
node _T_3031 = mux(_T_3022, _T_3023, _T_3030) @[el2_ifu_mem_ctl.scala 679:25]
io.iccm_wr_data <= _T_3031 @[el2_ifu_mem_ctl.scala 679:19]
wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 681:33]
iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 682:26]
iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 683:26]
wire dma_mem_addr_ff : UInt<2>
dma_mem_addr_ff <= UInt<1>("h00")
node _T_3032 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 685:51]
node _T_3033 = bits(_T_3032, 0, 0) @[el2_ifu_mem_ctl.scala 685:55]
node iccm_dma_rdata_1_muxed = mux(_T_3033, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 685:35]
wire iccm_double_ecc_error : UInt<2>
iccm_double_ecc_error <= UInt<1>("h00")
node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 687:53]
node _T_3034 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58]
node _T_3035 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58]
node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3034, _T_3035) @[el2_ifu_mem_ctl.scala 688:30]
reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 689:54]
dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 689:54]
reg iccm_dma_rtag : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 690:69]
iccm_dma_rtag <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 690:69]
io.iccm_dma_rtag <= iccm_dma_rtag @[el2_ifu_mem_ctl.scala 691:20]
node _T_3036 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 693:69]
reg _T_3037 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 693:53]
_T_3037 <= _T_3036 @[el2_ifu_mem_ctl.scala 693:53]
dma_mem_addr_ff <= _T_3037 @[el2_ifu_mem_ctl.scala 693:19]
reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 694:59]
iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 694:59]
reg iccm_dma_rvalid : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 695:71]
iccm_dma_rvalid <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 695:71]
io.iccm_dma_rvalid <= iccm_dma_rvalid @[el2_ifu_mem_ctl.scala 696:22]
reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 697:74]
iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 697:74]
io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 698:25]
reg iccm_dma_rdata : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 699:70]
iccm_dma_rdata <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 699:70]
io.iccm_dma_rdata <= iccm_dma_rdata @[el2_ifu_mem_ctl.scala 700:21]
wire iccm_ecc_corr_index_ff : UInt<14>
iccm_ecc_corr_index_ff <= UInt<1>("h00")
node _T_3038 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 702:46]
node _T_3039 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 702:67]
node _T_3040 = and(_T_3038, _T_3039) @[el2_ifu_mem_ctl.scala 702:65]
node _T_3041 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 703:31]
node _T_3042 = eq(_T_3041, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:9]
node _T_3043 = and(_T_3042, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 703:50]
node _T_3044 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_3045 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 703:124]
node _T_3046 = mux(_T_3043, _T_3044, _T_3045) @[el2_ifu_mem_ctl.scala 703:8]
node _T_3047 = mux(_T_3040, io.dma_mem_addr, _T_3046) @[el2_ifu_mem_ctl.scala 702:25]
io.iccm_rw_addr <= _T_3047 @[el2_ifu_mem_ctl.scala 702:19]
node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58]
node _T_3048 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 705:76]
node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3048) @[el2_ifu_mem_ctl.scala 705:53]
node _T_3049 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 708:75]
node _T_3050 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:93]
node _T_3051 = and(_T_3049, _T_3050) @[el2_ifu_mem_ctl.scala 708:91]
node _T_3052 = and(_T_3051, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 708:113]
node _T_3053 = or(_T_3052, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 708:130]
node _T_3054 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:154]
node _T_3055 = and(_T_3053, _T_3054) @[el2_ifu_mem_ctl.scala 708:152]
node _T_3056 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 708:75]
node _T_3057 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:93]
node _T_3058 = and(_T_3056, _T_3057) @[el2_ifu_mem_ctl.scala 708:91]
node _T_3059 = and(_T_3058, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 708:113]
node _T_3060 = or(_T_3059, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 708:130]
node _T_3061 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:154]
node _T_3062 = and(_T_3060, _T_3061) @[el2_ifu_mem_ctl.scala 708:152]
node iccm_ecc_word_enable = cat(_T_3062, _T_3055) @[Cat.scala 29:58]
node _T_3063 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 709:73]
node _T_3064 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 709:93]
node _T_3065 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 709:128]
wire _T_3066 : UInt<1>[18] @[el2_lib.scala 276:18]
wire _T_3067 : UInt<1>[18] @[el2_lib.scala 277:18]
wire _T_3068 : UInt<1>[18] @[el2_lib.scala 278:18]
wire _T_3069 : UInt<1>[15] @[el2_lib.scala 279:18]
wire _T_3070 : UInt<1>[15] @[el2_lib.scala 280:18]
wire _T_3071 : UInt<1>[6] @[el2_lib.scala 281:18]
node _T_3072 = bits(_T_3064, 0, 0) @[el2_lib.scala 288:36]
_T_3066[0] <= _T_3072 @[el2_lib.scala 288:30]
node _T_3073 = bits(_T_3064, 0, 0) @[el2_lib.scala 289:36]
_T_3067[0] <= _T_3073 @[el2_lib.scala 289:30]
node _T_3074 = bits(_T_3064, 1, 1) @[el2_lib.scala 288:36]
_T_3066[1] <= _T_3074 @[el2_lib.scala 288:30]
node _T_3075 = bits(_T_3064, 1, 1) @[el2_lib.scala 290:36]
_T_3068[0] <= _T_3075 @[el2_lib.scala 290:30]
node _T_3076 = bits(_T_3064, 2, 2) @[el2_lib.scala 289:36]
_T_3067[1] <= _T_3076 @[el2_lib.scala 289:30]
node _T_3077 = bits(_T_3064, 2, 2) @[el2_lib.scala 290:36]
_T_3068[1] <= _T_3077 @[el2_lib.scala 290:30]
node _T_3078 = bits(_T_3064, 3, 3) @[el2_lib.scala 288:36]
_T_3066[2] <= _T_3078 @[el2_lib.scala 288:30]
node _T_3079 = bits(_T_3064, 3, 3) @[el2_lib.scala 289:36]
_T_3067[2] <= _T_3079 @[el2_lib.scala 289:30]
node _T_3080 = bits(_T_3064, 3, 3) @[el2_lib.scala 290:36]
_T_3068[2] <= _T_3080 @[el2_lib.scala 290:30]
node _T_3081 = bits(_T_3064, 4, 4) @[el2_lib.scala 288:36]
_T_3066[3] <= _T_3081 @[el2_lib.scala 288:30]
node _T_3082 = bits(_T_3064, 4, 4) @[el2_lib.scala 291:36]
_T_3069[0] <= _T_3082 @[el2_lib.scala 291:30]
node _T_3083 = bits(_T_3064, 5, 5) @[el2_lib.scala 289:36]
_T_3067[3] <= _T_3083 @[el2_lib.scala 289:30]
node _T_3084 = bits(_T_3064, 5, 5) @[el2_lib.scala 291:36]
_T_3069[1] <= _T_3084 @[el2_lib.scala 291:30]
node _T_3085 = bits(_T_3064, 6, 6) @[el2_lib.scala 288:36]
_T_3066[4] <= _T_3085 @[el2_lib.scala 288:30]
node _T_3086 = bits(_T_3064, 6, 6) @[el2_lib.scala 289:36]
_T_3067[4] <= _T_3086 @[el2_lib.scala 289:30]
node _T_3087 = bits(_T_3064, 6, 6) @[el2_lib.scala 291:36]
_T_3069[2] <= _T_3087 @[el2_lib.scala 291:30]
node _T_3088 = bits(_T_3064, 7, 7) @[el2_lib.scala 290:36]
_T_3068[3] <= _T_3088 @[el2_lib.scala 290:30]
node _T_3089 = bits(_T_3064, 7, 7) @[el2_lib.scala 291:36]
_T_3069[3] <= _T_3089 @[el2_lib.scala 291:30]
node _T_3090 = bits(_T_3064, 8, 8) @[el2_lib.scala 288:36]
_T_3066[5] <= _T_3090 @[el2_lib.scala 288:30]
node _T_3091 = bits(_T_3064, 8, 8) @[el2_lib.scala 290:36]
_T_3068[4] <= _T_3091 @[el2_lib.scala 290:30]
node _T_3092 = bits(_T_3064, 8, 8) @[el2_lib.scala 291:36]
_T_3069[4] <= _T_3092 @[el2_lib.scala 291:30]
node _T_3093 = bits(_T_3064, 9, 9) @[el2_lib.scala 289:36]
_T_3067[5] <= _T_3093 @[el2_lib.scala 289:30]
node _T_3094 = bits(_T_3064, 9, 9) @[el2_lib.scala 290:36]
_T_3068[5] <= _T_3094 @[el2_lib.scala 290:30]
node _T_3095 = bits(_T_3064, 9, 9) @[el2_lib.scala 291:36]
_T_3069[5] <= _T_3095 @[el2_lib.scala 291:30]
node _T_3096 = bits(_T_3064, 10, 10) @[el2_lib.scala 288:36]
_T_3066[6] <= _T_3096 @[el2_lib.scala 288:30]
node _T_3097 = bits(_T_3064, 10, 10) @[el2_lib.scala 289:36]
_T_3067[6] <= _T_3097 @[el2_lib.scala 289:30]
node _T_3098 = bits(_T_3064, 10, 10) @[el2_lib.scala 290:36]
_T_3068[6] <= _T_3098 @[el2_lib.scala 290:30]
node _T_3099 = bits(_T_3064, 10, 10) @[el2_lib.scala 291:36]
_T_3069[6] <= _T_3099 @[el2_lib.scala 291:30]
node _T_3100 = bits(_T_3064, 11, 11) @[el2_lib.scala 288:36]
_T_3066[7] <= _T_3100 @[el2_lib.scala 288:30]
node _T_3101 = bits(_T_3064, 11, 11) @[el2_lib.scala 292:36]
_T_3070[0] <= _T_3101 @[el2_lib.scala 292:30]
node _T_3102 = bits(_T_3064, 12, 12) @[el2_lib.scala 289:36]
_T_3067[7] <= _T_3102 @[el2_lib.scala 289:30]
node _T_3103 = bits(_T_3064, 12, 12) @[el2_lib.scala 292:36]
_T_3070[1] <= _T_3103 @[el2_lib.scala 292:30]
node _T_3104 = bits(_T_3064, 13, 13) @[el2_lib.scala 288:36]
_T_3066[8] <= _T_3104 @[el2_lib.scala 288:30]
node _T_3105 = bits(_T_3064, 13, 13) @[el2_lib.scala 289:36]
_T_3067[8] <= _T_3105 @[el2_lib.scala 289:30]
node _T_3106 = bits(_T_3064, 13, 13) @[el2_lib.scala 292:36]
_T_3070[2] <= _T_3106 @[el2_lib.scala 292:30]
node _T_3107 = bits(_T_3064, 14, 14) @[el2_lib.scala 290:36]
_T_3068[7] <= _T_3107 @[el2_lib.scala 290:30]
node _T_3108 = bits(_T_3064, 14, 14) @[el2_lib.scala 292:36]
_T_3070[3] <= _T_3108 @[el2_lib.scala 292:30]
node _T_3109 = bits(_T_3064, 15, 15) @[el2_lib.scala 288:36]
_T_3066[9] <= _T_3109 @[el2_lib.scala 288:30]
node _T_3110 = bits(_T_3064, 15, 15) @[el2_lib.scala 290:36]
_T_3068[8] <= _T_3110 @[el2_lib.scala 290:30]
node _T_3111 = bits(_T_3064, 15, 15) @[el2_lib.scala 292:36]
_T_3070[4] <= _T_3111 @[el2_lib.scala 292:30]
node _T_3112 = bits(_T_3064, 16, 16) @[el2_lib.scala 289:36]
_T_3067[9] <= _T_3112 @[el2_lib.scala 289:30]
node _T_3113 = bits(_T_3064, 16, 16) @[el2_lib.scala 290:36]
_T_3068[9] <= _T_3113 @[el2_lib.scala 290:30]
node _T_3114 = bits(_T_3064, 16, 16) @[el2_lib.scala 292:36]
_T_3070[5] <= _T_3114 @[el2_lib.scala 292:30]
node _T_3115 = bits(_T_3064, 17, 17) @[el2_lib.scala 288:36]
_T_3066[10] <= _T_3115 @[el2_lib.scala 288:30]
node _T_3116 = bits(_T_3064, 17, 17) @[el2_lib.scala 289:36]
_T_3067[10] <= _T_3116 @[el2_lib.scala 289:30]
node _T_3117 = bits(_T_3064, 17, 17) @[el2_lib.scala 290:36]
_T_3068[10] <= _T_3117 @[el2_lib.scala 290:30]
node _T_3118 = bits(_T_3064, 17, 17) @[el2_lib.scala 292:36]
_T_3070[6] <= _T_3118 @[el2_lib.scala 292:30]
node _T_3119 = bits(_T_3064, 18, 18) @[el2_lib.scala 291:36]
_T_3069[7] <= _T_3119 @[el2_lib.scala 291:30]
node _T_3120 = bits(_T_3064, 18, 18) @[el2_lib.scala 292:36]
_T_3070[7] <= _T_3120 @[el2_lib.scala 292:30]
node _T_3121 = bits(_T_3064, 19, 19) @[el2_lib.scala 288:36]
_T_3066[11] <= _T_3121 @[el2_lib.scala 288:30]
node _T_3122 = bits(_T_3064, 19, 19) @[el2_lib.scala 291:36]
_T_3069[8] <= _T_3122 @[el2_lib.scala 291:30]
node _T_3123 = bits(_T_3064, 19, 19) @[el2_lib.scala 292:36]
_T_3070[8] <= _T_3123 @[el2_lib.scala 292:30]
node _T_3124 = bits(_T_3064, 20, 20) @[el2_lib.scala 289:36]
_T_3067[11] <= _T_3124 @[el2_lib.scala 289:30]
node _T_3125 = bits(_T_3064, 20, 20) @[el2_lib.scala 291:36]
_T_3069[9] <= _T_3125 @[el2_lib.scala 291:30]
node _T_3126 = bits(_T_3064, 20, 20) @[el2_lib.scala 292:36]
_T_3070[9] <= _T_3126 @[el2_lib.scala 292:30]
node _T_3127 = bits(_T_3064, 21, 21) @[el2_lib.scala 288:36]
_T_3066[12] <= _T_3127 @[el2_lib.scala 288:30]
node _T_3128 = bits(_T_3064, 21, 21) @[el2_lib.scala 289:36]
_T_3067[12] <= _T_3128 @[el2_lib.scala 289:30]
node _T_3129 = bits(_T_3064, 21, 21) @[el2_lib.scala 291:36]
_T_3069[10] <= _T_3129 @[el2_lib.scala 291:30]
node _T_3130 = bits(_T_3064, 21, 21) @[el2_lib.scala 292:36]
_T_3070[10] <= _T_3130 @[el2_lib.scala 292:30]
node _T_3131 = bits(_T_3064, 22, 22) @[el2_lib.scala 290:36]
_T_3068[11] <= _T_3131 @[el2_lib.scala 290:30]
node _T_3132 = bits(_T_3064, 22, 22) @[el2_lib.scala 291:36]
_T_3069[11] <= _T_3132 @[el2_lib.scala 291:30]
node _T_3133 = bits(_T_3064, 22, 22) @[el2_lib.scala 292:36]
_T_3070[11] <= _T_3133 @[el2_lib.scala 292:30]
node _T_3134 = bits(_T_3064, 23, 23) @[el2_lib.scala 288:36]
_T_3066[13] <= _T_3134 @[el2_lib.scala 288:30]
node _T_3135 = bits(_T_3064, 23, 23) @[el2_lib.scala 290:36]
_T_3068[12] <= _T_3135 @[el2_lib.scala 290:30]
node _T_3136 = bits(_T_3064, 23, 23) @[el2_lib.scala 291:36]
_T_3069[12] <= _T_3136 @[el2_lib.scala 291:30]
node _T_3137 = bits(_T_3064, 23, 23) @[el2_lib.scala 292:36]
_T_3070[12] <= _T_3137 @[el2_lib.scala 292:30]
node _T_3138 = bits(_T_3064, 24, 24) @[el2_lib.scala 289:36]
_T_3067[13] <= _T_3138 @[el2_lib.scala 289:30]
node _T_3139 = bits(_T_3064, 24, 24) @[el2_lib.scala 290:36]
_T_3068[13] <= _T_3139 @[el2_lib.scala 290:30]
node _T_3140 = bits(_T_3064, 24, 24) @[el2_lib.scala 291:36]
_T_3069[13] <= _T_3140 @[el2_lib.scala 291:30]
node _T_3141 = bits(_T_3064, 24, 24) @[el2_lib.scala 292:36]
_T_3070[13] <= _T_3141 @[el2_lib.scala 292:30]
node _T_3142 = bits(_T_3064, 25, 25) @[el2_lib.scala 288:36]
_T_3066[14] <= _T_3142 @[el2_lib.scala 288:30]
node _T_3143 = bits(_T_3064, 25, 25) @[el2_lib.scala 289:36]
_T_3067[14] <= _T_3143 @[el2_lib.scala 289:30]
node _T_3144 = bits(_T_3064, 25, 25) @[el2_lib.scala 290:36]
_T_3068[14] <= _T_3144 @[el2_lib.scala 290:30]
node _T_3145 = bits(_T_3064, 25, 25) @[el2_lib.scala 291:36]
_T_3069[14] <= _T_3145 @[el2_lib.scala 291:30]
node _T_3146 = bits(_T_3064, 25, 25) @[el2_lib.scala 292:36]
_T_3070[14] <= _T_3146 @[el2_lib.scala 292:30]
node _T_3147 = bits(_T_3064, 26, 26) @[el2_lib.scala 288:36]
_T_3066[15] <= _T_3147 @[el2_lib.scala 288:30]
node _T_3148 = bits(_T_3064, 26, 26) @[el2_lib.scala 293:36]
_T_3071[0] <= _T_3148 @[el2_lib.scala 293:30]
node _T_3149 = bits(_T_3064, 27, 27) @[el2_lib.scala 289:36]
_T_3067[15] <= _T_3149 @[el2_lib.scala 289:30]
node _T_3150 = bits(_T_3064, 27, 27) @[el2_lib.scala 293:36]
_T_3071[1] <= _T_3150 @[el2_lib.scala 293:30]
node _T_3151 = bits(_T_3064, 28, 28) @[el2_lib.scala 288:36]
_T_3066[16] <= _T_3151 @[el2_lib.scala 288:30]
node _T_3152 = bits(_T_3064, 28, 28) @[el2_lib.scala 289:36]
_T_3067[16] <= _T_3152 @[el2_lib.scala 289:30]
node _T_3153 = bits(_T_3064, 28, 28) @[el2_lib.scala 293:36]
_T_3071[2] <= _T_3153 @[el2_lib.scala 293:30]
node _T_3154 = bits(_T_3064, 29, 29) @[el2_lib.scala 290:36]
_T_3068[15] <= _T_3154 @[el2_lib.scala 290:30]
node _T_3155 = bits(_T_3064, 29, 29) @[el2_lib.scala 293:36]
_T_3071[3] <= _T_3155 @[el2_lib.scala 293:30]
node _T_3156 = bits(_T_3064, 30, 30) @[el2_lib.scala 288:36]
_T_3066[17] <= _T_3156 @[el2_lib.scala 288:30]
node _T_3157 = bits(_T_3064, 30, 30) @[el2_lib.scala 290:36]
_T_3068[16] <= _T_3157 @[el2_lib.scala 290:30]
node _T_3158 = bits(_T_3064, 30, 30) @[el2_lib.scala 293:36]
_T_3071[4] <= _T_3158 @[el2_lib.scala 293:30]
node _T_3159 = bits(_T_3064, 31, 31) @[el2_lib.scala 289:36]
_T_3067[17] <= _T_3159 @[el2_lib.scala 289:30]
node _T_3160 = bits(_T_3064, 31, 31) @[el2_lib.scala 290:36]
_T_3068[17] <= _T_3160 @[el2_lib.scala 290:30]
node _T_3161 = bits(_T_3064, 31, 31) @[el2_lib.scala 293:36]
_T_3071[5] <= _T_3161 @[el2_lib.scala 293:30]
node _T_3162 = xorr(_T_3064) @[el2_lib.scala 296:30]
node _T_3163 = xorr(_T_3065) @[el2_lib.scala 296:44]
node _T_3164 = xor(_T_3162, _T_3163) @[el2_lib.scala 296:35]
node _T_3165 = not(UInt<1>("h00")) @[el2_lib.scala 296:52]
node _T_3166 = and(_T_3164, _T_3165) @[el2_lib.scala 296:50]
node _T_3167 = bits(_T_3065, 5, 5) @[el2_lib.scala 296:68]
node _T_3168 = cat(_T_3071[2], _T_3071[1]) @[el2_lib.scala 296:76]
node _T_3169 = cat(_T_3168, _T_3071[0]) @[el2_lib.scala 296:76]
node _T_3170 = cat(_T_3071[5], _T_3071[4]) @[el2_lib.scala 296:76]
node _T_3171 = cat(_T_3170, _T_3071[3]) @[el2_lib.scala 296:76]
node _T_3172 = cat(_T_3171, _T_3169) @[el2_lib.scala 296:76]
node _T_3173 = xorr(_T_3172) @[el2_lib.scala 296:83]
node _T_3174 = xor(_T_3167, _T_3173) @[el2_lib.scala 296:71]
node _T_3175 = bits(_T_3065, 4, 4) @[el2_lib.scala 296:95]
node _T_3176 = cat(_T_3070[2], _T_3070[1]) @[el2_lib.scala 296:103]
node _T_3177 = cat(_T_3176, _T_3070[0]) @[el2_lib.scala 296:103]
node _T_3178 = cat(_T_3070[4], _T_3070[3]) @[el2_lib.scala 296:103]
node _T_3179 = cat(_T_3070[6], _T_3070[5]) @[el2_lib.scala 296:103]
node _T_3180 = cat(_T_3179, _T_3178) @[el2_lib.scala 296:103]
node _T_3181 = cat(_T_3180, _T_3177) @[el2_lib.scala 296:103]
node _T_3182 = cat(_T_3070[8], _T_3070[7]) @[el2_lib.scala 296:103]
node _T_3183 = cat(_T_3070[10], _T_3070[9]) @[el2_lib.scala 296:103]
node _T_3184 = cat(_T_3183, _T_3182) @[el2_lib.scala 296:103]
node _T_3185 = cat(_T_3070[12], _T_3070[11]) @[el2_lib.scala 296:103]
node _T_3186 = cat(_T_3070[14], _T_3070[13]) @[el2_lib.scala 296:103]
node _T_3187 = cat(_T_3186, _T_3185) @[el2_lib.scala 296:103]
node _T_3188 = cat(_T_3187, _T_3184) @[el2_lib.scala 296:103]
node _T_3189 = cat(_T_3188, _T_3181) @[el2_lib.scala 296:103]
node _T_3190 = xorr(_T_3189) @[el2_lib.scala 296:110]
node _T_3191 = xor(_T_3175, _T_3190) @[el2_lib.scala 296:98]
node _T_3192 = bits(_T_3065, 3, 3) @[el2_lib.scala 296:122]
node _T_3193 = cat(_T_3069[2], _T_3069[1]) @[el2_lib.scala 296:130]
node _T_3194 = cat(_T_3193, _T_3069[0]) @[el2_lib.scala 296:130]
node _T_3195 = cat(_T_3069[4], _T_3069[3]) @[el2_lib.scala 296:130]
node _T_3196 = cat(_T_3069[6], _T_3069[5]) @[el2_lib.scala 296:130]
node _T_3197 = cat(_T_3196, _T_3195) @[el2_lib.scala 296:130]
node _T_3198 = cat(_T_3197, _T_3194) @[el2_lib.scala 296:130]
node _T_3199 = cat(_T_3069[8], _T_3069[7]) @[el2_lib.scala 296:130]
node _T_3200 = cat(_T_3069[10], _T_3069[9]) @[el2_lib.scala 296:130]
node _T_3201 = cat(_T_3200, _T_3199) @[el2_lib.scala 296:130]
node _T_3202 = cat(_T_3069[12], _T_3069[11]) @[el2_lib.scala 296:130]
node _T_3203 = cat(_T_3069[14], _T_3069[13]) @[el2_lib.scala 296:130]
node _T_3204 = cat(_T_3203, _T_3202) @[el2_lib.scala 296:130]
node _T_3205 = cat(_T_3204, _T_3201) @[el2_lib.scala 296:130]
node _T_3206 = cat(_T_3205, _T_3198) @[el2_lib.scala 296:130]
node _T_3207 = xorr(_T_3206) @[el2_lib.scala 296:137]
node _T_3208 = xor(_T_3192, _T_3207) @[el2_lib.scala 296:125]
node _T_3209 = bits(_T_3065, 2, 2) @[el2_lib.scala 296:149]
node _T_3210 = cat(_T_3068[1], _T_3068[0]) @[el2_lib.scala 296:157]
node _T_3211 = cat(_T_3068[3], _T_3068[2]) @[el2_lib.scala 296:157]
node _T_3212 = cat(_T_3211, _T_3210) @[el2_lib.scala 296:157]
node _T_3213 = cat(_T_3068[5], _T_3068[4]) @[el2_lib.scala 296:157]
node _T_3214 = cat(_T_3068[8], _T_3068[7]) @[el2_lib.scala 296:157]
node _T_3215 = cat(_T_3214, _T_3068[6]) @[el2_lib.scala 296:157]
node _T_3216 = cat(_T_3215, _T_3213) @[el2_lib.scala 296:157]
node _T_3217 = cat(_T_3216, _T_3212) @[el2_lib.scala 296:157]
node _T_3218 = cat(_T_3068[10], _T_3068[9]) @[el2_lib.scala 296:157]
node _T_3219 = cat(_T_3068[12], _T_3068[11]) @[el2_lib.scala 296:157]
node _T_3220 = cat(_T_3219, _T_3218) @[el2_lib.scala 296:157]
node _T_3221 = cat(_T_3068[14], _T_3068[13]) @[el2_lib.scala 296:157]
node _T_3222 = cat(_T_3068[17], _T_3068[16]) @[el2_lib.scala 296:157]
node _T_3223 = cat(_T_3222, _T_3068[15]) @[el2_lib.scala 296:157]
node _T_3224 = cat(_T_3223, _T_3221) @[el2_lib.scala 296:157]
node _T_3225 = cat(_T_3224, _T_3220) @[el2_lib.scala 296:157]
node _T_3226 = cat(_T_3225, _T_3217) @[el2_lib.scala 296:157]
node _T_3227 = xorr(_T_3226) @[el2_lib.scala 296:164]
node _T_3228 = xor(_T_3209, _T_3227) @[el2_lib.scala 296:152]
node _T_3229 = bits(_T_3065, 1, 1) @[el2_lib.scala 296:176]
node _T_3230 = cat(_T_3067[1], _T_3067[0]) @[el2_lib.scala 296:184]
node _T_3231 = cat(_T_3067[3], _T_3067[2]) @[el2_lib.scala 296:184]
node _T_3232 = cat(_T_3231, _T_3230) @[el2_lib.scala 296:184]
node _T_3233 = cat(_T_3067[5], _T_3067[4]) @[el2_lib.scala 296:184]
node _T_3234 = cat(_T_3067[8], _T_3067[7]) @[el2_lib.scala 296:184]
node _T_3235 = cat(_T_3234, _T_3067[6]) @[el2_lib.scala 296:184]
node _T_3236 = cat(_T_3235, _T_3233) @[el2_lib.scala 296:184]
node _T_3237 = cat(_T_3236, _T_3232) @[el2_lib.scala 296:184]
node _T_3238 = cat(_T_3067[10], _T_3067[9]) @[el2_lib.scala 296:184]
node _T_3239 = cat(_T_3067[12], _T_3067[11]) @[el2_lib.scala 296:184]
node _T_3240 = cat(_T_3239, _T_3238) @[el2_lib.scala 296:184]
node _T_3241 = cat(_T_3067[14], _T_3067[13]) @[el2_lib.scala 296:184]
node _T_3242 = cat(_T_3067[17], _T_3067[16]) @[el2_lib.scala 296:184]
node _T_3243 = cat(_T_3242, _T_3067[15]) @[el2_lib.scala 296:184]
node _T_3244 = cat(_T_3243, _T_3241) @[el2_lib.scala 296:184]
node _T_3245 = cat(_T_3244, _T_3240) @[el2_lib.scala 296:184]
node _T_3246 = cat(_T_3245, _T_3237) @[el2_lib.scala 296:184]
node _T_3247 = xorr(_T_3246) @[el2_lib.scala 296:191]
node _T_3248 = xor(_T_3229, _T_3247) @[el2_lib.scala 296:179]
node _T_3249 = bits(_T_3065, 0, 0) @[el2_lib.scala 296:203]
node _T_3250 = cat(_T_3066[1], _T_3066[0]) @[el2_lib.scala 296:211]
node _T_3251 = cat(_T_3066[3], _T_3066[2]) @[el2_lib.scala 296:211]
node _T_3252 = cat(_T_3251, _T_3250) @[el2_lib.scala 296:211]
node _T_3253 = cat(_T_3066[5], _T_3066[4]) @[el2_lib.scala 296:211]
node _T_3254 = cat(_T_3066[8], _T_3066[7]) @[el2_lib.scala 296:211]
node _T_3255 = cat(_T_3254, _T_3066[6]) @[el2_lib.scala 296:211]
node _T_3256 = cat(_T_3255, _T_3253) @[el2_lib.scala 296:211]
node _T_3257 = cat(_T_3256, _T_3252) @[el2_lib.scala 296:211]
node _T_3258 = cat(_T_3066[10], _T_3066[9]) @[el2_lib.scala 296:211]
node _T_3259 = cat(_T_3066[12], _T_3066[11]) @[el2_lib.scala 296:211]
node _T_3260 = cat(_T_3259, _T_3258) @[el2_lib.scala 296:211]
node _T_3261 = cat(_T_3066[14], _T_3066[13]) @[el2_lib.scala 296:211]
node _T_3262 = cat(_T_3066[17], _T_3066[16]) @[el2_lib.scala 296:211]
node _T_3263 = cat(_T_3262, _T_3066[15]) @[el2_lib.scala 296:211]
node _T_3264 = cat(_T_3263, _T_3261) @[el2_lib.scala 296:211]
node _T_3265 = cat(_T_3264, _T_3260) @[el2_lib.scala 296:211]
node _T_3266 = cat(_T_3265, _T_3257) @[el2_lib.scala 296:211]
node _T_3267 = xorr(_T_3266) @[el2_lib.scala 296:218]
node _T_3268 = xor(_T_3249, _T_3267) @[el2_lib.scala 296:206]
node _T_3269 = cat(_T_3228, _T_3248) @[Cat.scala 29:58]
node _T_3270 = cat(_T_3269, _T_3268) @[Cat.scala 29:58]
node _T_3271 = cat(_T_3191, _T_3208) @[Cat.scala 29:58]
node _T_3272 = cat(_T_3166, _T_3174) @[Cat.scala 29:58]
node _T_3273 = cat(_T_3272, _T_3271) @[Cat.scala 29:58]
node _T_3274 = cat(_T_3273, _T_3270) @[Cat.scala 29:58]
node _T_3275 = neq(_T_3274, UInt<1>("h00")) @[el2_lib.scala 297:44]
node _T_3276 = and(_T_3063, _T_3275) @[el2_lib.scala 297:32]
node _T_3277 = bits(_T_3274, 6, 6) @[el2_lib.scala 297:64]
node _T_3278 = and(_T_3276, _T_3277) @[el2_lib.scala 297:53]
node _T_3279 = neq(_T_3274, UInt<1>("h00")) @[el2_lib.scala 298:44]
node _T_3280 = and(_T_3063, _T_3279) @[el2_lib.scala 298:32]
node _T_3281 = bits(_T_3274, 6, 6) @[el2_lib.scala 298:65]
node _T_3282 = not(_T_3281) @[el2_lib.scala 298:55]
node _T_3283 = and(_T_3280, _T_3282) @[el2_lib.scala 298:53]
wire _T_3284 : UInt<1>[39] @[el2_lib.scala 299:26]
node _T_3285 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3286 = eq(_T_3285, UInt<1>("h01")) @[el2_lib.scala 302:41]
_T_3284[0] <= _T_3286 @[el2_lib.scala 302:23]
node _T_3287 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3288 = eq(_T_3287, UInt<2>("h02")) @[el2_lib.scala 302:41]
_T_3284[1] <= _T_3288 @[el2_lib.scala 302:23]
node _T_3289 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3290 = eq(_T_3289, UInt<2>("h03")) @[el2_lib.scala 302:41]
_T_3284[2] <= _T_3290 @[el2_lib.scala 302:23]
node _T_3291 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3292 = eq(_T_3291, UInt<3>("h04")) @[el2_lib.scala 302:41]
_T_3284[3] <= _T_3292 @[el2_lib.scala 302:23]
node _T_3293 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3294 = eq(_T_3293, UInt<3>("h05")) @[el2_lib.scala 302:41]
_T_3284[4] <= _T_3294 @[el2_lib.scala 302:23]
node _T_3295 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3296 = eq(_T_3295, UInt<3>("h06")) @[el2_lib.scala 302:41]
_T_3284[5] <= _T_3296 @[el2_lib.scala 302:23]
node _T_3297 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3298 = eq(_T_3297, UInt<3>("h07")) @[el2_lib.scala 302:41]
_T_3284[6] <= _T_3298 @[el2_lib.scala 302:23]
node _T_3299 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3300 = eq(_T_3299, UInt<4>("h08")) @[el2_lib.scala 302:41]
_T_3284[7] <= _T_3300 @[el2_lib.scala 302:23]
node _T_3301 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3302 = eq(_T_3301, UInt<4>("h09")) @[el2_lib.scala 302:41]
_T_3284[8] <= _T_3302 @[el2_lib.scala 302:23]
node _T_3303 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3304 = eq(_T_3303, UInt<4>("h0a")) @[el2_lib.scala 302:41]
_T_3284[9] <= _T_3304 @[el2_lib.scala 302:23]
node _T_3305 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3306 = eq(_T_3305, UInt<4>("h0b")) @[el2_lib.scala 302:41]
_T_3284[10] <= _T_3306 @[el2_lib.scala 302:23]
node _T_3307 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3308 = eq(_T_3307, UInt<4>("h0c")) @[el2_lib.scala 302:41]
_T_3284[11] <= _T_3308 @[el2_lib.scala 302:23]
node _T_3309 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3310 = eq(_T_3309, UInt<4>("h0d")) @[el2_lib.scala 302:41]
_T_3284[12] <= _T_3310 @[el2_lib.scala 302:23]
node _T_3311 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3312 = eq(_T_3311, UInt<4>("h0e")) @[el2_lib.scala 302:41]
_T_3284[13] <= _T_3312 @[el2_lib.scala 302:23]
node _T_3313 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3314 = eq(_T_3313, UInt<4>("h0f")) @[el2_lib.scala 302:41]
_T_3284[14] <= _T_3314 @[el2_lib.scala 302:23]
node _T_3315 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3316 = eq(_T_3315, UInt<5>("h010")) @[el2_lib.scala 302:41]
_T_3284[15] <= _T_3316 @[el2_lib.scala 302:23]
node _T_3317 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3318 = eq(_T_3317, UInt<5>("h011")) @[el2_lib.scala 302:41]
_T_3284[16] <= _T_3318 @[el2_lib.scala 302:23]
node _T_3319 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3320 = eq(_T_3319, UInt<5>("h012")) @[el2_lib.scala 302:41]
_T_3284[17] <= _T_3320 @[el2_lib.scala 302:23]
node _T_3321 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3322 = eq(_T_3321, UInt<5>("h013")) @[el2_lib.scala 302:41]
_T_3284[18] <= _T_3322 @[el2_lib.scala 302:23]
node _T_3323 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3324 = eq(_T_3323, UInt<5>("h014")) @[el2_lib.scala 302:41]
_T_3284[19] <= _T_3324 @[el2_lib.scala 302:23]
node _T_3325 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3326 = eq(_T_3325, UInt<5>("h015")) @[el2_lib.scala 302:41]
_T_3284[20] <= _T_3326 @[el2_lib.scala 302:23]
node _T_3327 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3328 = eq(_T_3327, UInt<5>("h016")) @[el2_lib.scala 302:41]
_T_3284[21] <= _T_3328 @[el2_lib.scala 302:23]
node _T_3329 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3330 = eq(_T_3329, UInt<5>("h017")) @[el2_lib.scala 302:41]
_T_3284[22] <= _T_3330 @[el2_lib.scala 302:23]
node _T_3331 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3332 = eq(_T_3331, UInt<5>("h018")) @[el2_lib.scala 302:41]
_T_3284[23] <= _T_3332 @[el2_lib.scala 302:23]
node _T_3333 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3334 = eq(_T_3333, UInt<5>("h019")) @[el2_lib.scala 302:41]
_T_3284[24] <= _T_3334 @[el2_lib.scala 302:23]
node _T_3335 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3336 = eq(_T_3335, UInt<5>("h01a")) @[el2_lib.scala 302:41]
_T_3284[25] <= _T_3336 @[el2_lib.scala 302:23]
node _T_3337 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3338 = eq(_T_3337, UInt<5>("h01b")) @[el2_lib.scala 302:41]
_T_3284[26] <= _T_3338 @[el2_lib.scala 302:23]
node _T_3339 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3340 = eq(_T_3339, UInt<5>("h01c")) @[el2_lib.scala 302:41]
_T_3284[27] <= _T_3340 @[el2_lib.scala 302:23]
node _T_3341 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3342 = eq(_T_3341, UInt<5>("h01d")) @[el2_lib.scala 302:41]
_T_3284[28] <= _T_3342 @[el2_lib.scala 302:23]
node _T_3343 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3344 = eq(_T_3343, UInt<5>("h01e")) @[el2_lib.scala 302:41]
_T_3284[29] <= _T_3344 @[el2_lib.scala 302:23]
node _T_3345 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3346 = eq(_T_3345, UInt<5>("h01f")) @[el2_lib.scala 302:41]
_T_3284[30] <= _T_3346 @[el2_lib.scala 302:23]
node _T_3347 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3348 = eq(_T_3347, UInt<6>("h020")) @[el2_lib.scala 302:41]
_T_3284[31] <= _T_3348 @[el2_lib.scala 302:23]
node _T_3349 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3350 = eq(_T_3349, UInt<6>("h021")) @[el2_lib.scala 302:41]
_T_3284[32] <= _T_3350 @[el2_lib.scala 302:23]
node _T_3351 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3352 = eq(_T_3351, UInt<6>("h022")) @[el2_lib.scala 302:41]
_T_3284[33] <= _T_3352 @[el2_lib.scala 302:23]
node _T_3353 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3354 = eq(_T_3353, UInt<6>("h023")) @[el2_lib.scala 302:41]
_T_3284[34] <= _T_3354 @[el2_lib.scala 302:23]
node _T_3355 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3356 = eq(_T_3355, UInt<6>("h024")) @[el2_lib.scala 302:41]
_T_3284[35] <= _T_3356 @[el2_lib.scala 302:23]
node _T_3357 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3358 = eq(_T_3357, UInt<6>("h025")) @[el2_lib.scala 302:41]
_T_3284[36] <= _T_3358 @[el2_lib.scala 302:23]
node _T_3359 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3360 = eq(_T_3359, UInt<6>("h026")) @[el2_lib.scala 302:41]
_T_3284[37] <= _T_3360 @[el2_lib.scala 302:23]
node _T_3361 = bits(_T_3274, 5, 0) @[el2_lib.scala 302:35]
node _T_3362 = eq(_T_3361, UInt<6>("h027")) @[el2_lib.scala 302:41]
_T_3284[38] <= _T_3362 @[el2_lib.scala 302:23]
node _T_3363 = bits(_T_3065, 6, 6) @[el2_lib.scala 304:37]
node _T_3364 = bits(_T_3064, 31, 26) @[el2_lib.scala 304:45]
node _T_3365 = bits(_T_3065, 5, 5) @[el2_lib.scala 304:60]
node _T_3366 = bits(_T_3064, 25, 11) @[el2_lib.scala 304:68]
node _T_3367 = bits(_T_3065, 4, 4) @[el2_lib.scala 304:83]
node _T_3368 = bits(_T_3064, 10, 4) @[el2_lib.scala 304:91]
node _T_3369 = bits(_T_3065, 3, 3) @[el2_lib.scala 304:105]
node _T_3370 = bits(_T_3064, 3, 1) @[el2_lib.scala 304:113]
node _T_3371 = bits(_T_3065, 2, 2) @[el2_lib.scala 304:126]
node _T_3372 = bits(_T_3064, 0, 0) @[el2_lib.scala 304:134]
node _T_3373 = bits(_T_3065, 1, 0) @[el2_lib.scala 304:145]
node _T_3374 = cat(_T_3372, _T_3373) @[Cat.scala 29:58]
node _T_3375 = cat(_T_3369, _T_3370) @[Cat.scala 29:58]
node _T_3376 = cat(_T_3375, _T_3371) @[Cat.scala 29:58]
node _T_3377 = cat(_T_3376, _T_3374) @[Cat.scala 29:58]
node _T_3378 = cat(_T_3366, _T_3367) @[Cat.scala 29:58]
node _T_3379 = cat(_T_3378, _T_3368) @[Cat.scala 29:58]
node _T_3380 = cat(_T_3363, _T_3364) @[Cat.scala 29:58]
node _T_3381 = cat(_T_3380, _T_3365) @[Cat.scala 29:58]
node _T_3382 = cat(_T_3381, _T_3379) @[Cat.scala 29:58]
node _T_3383 = cat(_T_3382, _T_3377) @[Cat.scala 29:58]
node _T_3384 = bits(_T_3278, 0, 0) @[el2_lib.scala 305:49]
node _T_3385 = cat(_T_3284[1], _T_3284[0]) @[el2_lib.scala 305:69]
node _T_3386 = cat(_T_3284[3], _T_3284[2]) @[el2_lib.scala 305:69]
node _T_3387 = cat(_T_3386, _T_3385) @[el2_lib.scala 305:69]
node _T_3388 = cat(_T_3284[5], _T_3284[4]) @[el2_lib.scala 305:69]
node _T_3389 = cat(_T_3284[8], _T_3284[7]) @[el2_lib.scala 305:69]
node _T_3390 = cat(_T_3389, _T_3284[6]) @[el2_lib.scala 305:69]
node _T_3391 = cat(_T_3390, _T_3388) @[el2_lib.scala 305:69]
node _T_3392 = cat(_T_3391, _T_3387) @[el2_lib.scala 305:69]
node _T_3393 = cat(_T_3284[10], _T_3284[9]) @[el2_lib.scala 305:69]
node _T_3394 = cat(_T_3284[13], _T_3284[12]) @[el2_lib.scala 305:69]
node _T_3395 = cat(_T_3394, _T_3284[11]) @[el2_lib.scala 305:69]
node _T_3396 = cat(_T_3395, _T_3393) @[el2_lib.scala 305:69]
node _T_3397 = cat(_T_3284[15], _T_3284[14]) @[el2_lib.scala 305:69]
node _T_3398 = cat(_T_3284[18], _T_3284[17]) @[el2_lib.scala 305:69]
node _T_3399 = cat(_T_3398, _T_3284[16]) @[el2_lib.scala 305:69]
node _T_3400 = cat(_T_3399, _T_3397) @[el2_lib.scala 305:69]
node _T_3401 = cat(_T_3400, _T_3396) @[el2_lib.scala 305:69]
node _T_3402 = cat(_T_3401, _T_3392) @[el2_lib.scala 305:69]
node _T_3403 = cat(_T_3284[20], _T_3284[19]) @[el2_lib.scala 305:69]
node _T_3404 = cat(_T_3284[23], _T_3284[22]) @[el2_lib.scala 305:69]
node _T_3405 = cat(_T_3404, _T_3284[21]) @[el2_lib.scala 305:69]
node _T_3406 = cat(_T_3405, _T_3403) @[el2_lib.scala 305:69]
node _T_3407 = cat(_T_3284[25], _T_3284[24]) @[el2_lib.scala 305:69]
node _T_3408 = cat(_T_3284[28], _T_3284[27]) @[el2_lib.scala 305:69]
node _T_3409 = cat(_T_3408, _T_3284[26]) @[el2_lib.scala 305:69]
node _T_3410 = cat(_T_3409, _T_3407) @[el2_lib.scala 305:69]
node _T_3411 = cat(_T_3410, _T_3406) @[el2_lib.scala 305:69]
node _T_3412 = cat(_T_3284[30], _T_3284[29]) @[el2_lib.scala 305:69]
node _T_3413 = cat(_T_3284[33], _T_3284[32]) @[el2_lib.scala 305:69]
node _T_3414 = cat(_T_3413, _T_3284[31]) @[el2_lib.scala 305:69]
node _T_3415 = cat(_T_3414, _T_3412) @[el2_lib.scala 305:69]
node _T_3416 = cat(_T_3284[35], _T_3284[34]) @[el2_lib.scala 305:69]
node _T_3417 = cat(_T_3284[38], _T_3284[37]) @[el2_lib.scala 305:69]
node _T_3418 = cat(_T_3417, _T_3284[36]) @[el2_lib.scala 305:69]
node _T_3419 = cat(_T_3418, _T_3416) @[el2_lib.scala 305:69]
node _T_3420 = cat(_T_3419, _T_3415) @[el2_lib.scala 305:69]
node _T_3421 = cat(_T_3420, _T_3411) @[el2_lib.scala 305:69]
node _T_3422 = cat(_T_3421, _T_3402) @[el2_lib.scala 305:69]
node _T_3423 = xor(_T_3422, _T_3383) @[el2_lib.scala 305:76]
node _T_3424 = mux(_T_3384, _T_3423, _T_3383) @[el2_lib.scala 305:31]
node _T_3425 = bits(_T_3424, 37, 32) @[el2_lib.scala 307:37]
node _T_3426 = bits(_T_3424, 30, 16) @[el2_lib.scala 307:61]
node _T_3427 = bits(_T_3424, 14, 8) @[el2_lib.scala 307:86]
node _T_3428 = bits(_T_3424, 6, 4) @[el2_lib.scala 307:110]
node _T_3429 = bits(_T_3424, 2, 2) @[el2_lib.scala 307:133]
node _T_3430 = cat(_T_3428, _T_3429) @[Cat.scala 29:58]
node _T_3431 = cat(_T_3425, _T_3426) @[Cat.scala 29:58]
node _T_3432 = cat(_T_3431, _T_3427) @[Cat.scala 29:58]
node _T_3433 = cat(_T_3432, _T_3430) @[Cat.scala 29:58]
node _T_3434 = bits(_T_3424, 38, 38) @[el2_lib.scala 308:39]
node _T_3435 = bits(_T_3274, 6, 0) @[el2_lib.scala 308:56]
node _T_3436 = eq(_T_3435, UInt<7>("h040")) @[el2_lib.scala 308:62]
node _T_3437 = xor(_T_3434, _T_3436) @[el2_lib.scala 308:44]
node _T_3438 = bits(_T_3424, 31, 31) @[el2_lib.scala 308:102]
node _T_3439 = bits(_T_3424, 15, 15) @[el2_lib.scala 308:124]
node _T_3440 = bits(_T_3424, 7, 7) @[el2_lib.scala 308:146]
node _T_3441 = bits(_T_3424, 3, 3) @[el2_lib.scala 308:167]
node _T_3442 = bits(_T_3424, 1, 0) @[el2_lib.scala 308:188]
node _T_3443 = cat(_T_3440, _T_3441) @[Cat.scala 29:58]
node _T_3444 = cat(_T_3443, _T_3442) @[Cat.scala 29:58]
node _T_3445 = cat(_T_3437, _T_3438) @[Cat.scala 29:58]
node _T_3446 = cat(_T_3445, _T_3439) @[Cat.scala 29:58]
node _T_3447 = cat(_T_3446, _T_3444) @[Cat.scala 29:58]
node _T_3448 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 709:73]
node _T_3449 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 709:93]
node _T_3450 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 709:128]
wire _T_3451 : UInt<1>[18] @[el2_lib.scala 276:18]
wire _T_3452 : UInt<1>[18] @[el2_lib.scala 277:18]
wire _T_3453 : UInt<1>[18] @[el2_lib.scala 278:18]
wire _T_3454 : UInt<1>[15] @[el2_lib.scala 279:18]
wire _T_3455 : UInt<1>[15] @[el2_lib.scala 280:18]
wire _T_3456 : UInt<1>[6] @[el2_lib.scala 281:18]
node _T_3457 = bits(_T_3449, 0, 0) @[el2_lib.scala 288:36]
_T_3451[0] <= _T_3457 @[el2_lib.scala 288:30]
node _T_3458 = bits(_T_3449, 0, 0) @[el2_lib.scala 289:36]
_T_3452[0] <= _T_3458 @[el2_lib.scala 289:30]
node _T_3459 = bits(_T_3449, 1, 1) @[el2_lib.scala 288:36]
_T_3451[1] <= _T_3459 @[el2_lib.scala 288:30]
node _T_3460 = bits(_T_3449, 1, 1) @[el2_lib.scala 290:36]
_T_3453[0] <= _T_3460 @[el2_lib.scala 290:30]
node _T_3461 = bits(_T_3449, 2, 2) @[el2_lib.scala 289:36]
_T_3452[1] <= _T_3461 @[el2_lib.scala 289:30]
node _T_3462 = bits(_T_3449, 2, 2) @[el2_lib.scala 290:36]
_T_3453[1] <= _T_3462 @[el2_lib.scala 290:30]
node _T_3463 = bits(_T_3449, 3, 3) @[el2_lib.scala 288:36]
_T_3451[2] <= _T_3463 @[el2_lib.scala 288:30]
node _T_3464 = bits(_T_3449, 3, 3) @[el2_lib.scala 289:36]
_T_3452[2] <= _T_3464 @[el2_lib.scala 289:30]
node _T_3465 = bits(_T_3449, 3, 3) @[el2_lib.scala 290:36]
_T_3453[2] <= _T_3465 @[el2_lib.scala 290:30]
node _T_3466 = bits(_T_3449, 4, 4) @[el2_lib.scala 288:36]
_T_3451[3] <= _T_3466 @[el2_lib.scala 288:30]
node _T_3467 = bits(_T_3449, 4, 4) @[el2_lib.scala 291:36]
_T_3454[0] <= _T_3467 @[el2_lib.scala 291:30]
node _T_3468 = bits(_T_3449, 5, 5) @[el2_lib.scala 289:36]
_T_3452[3] <= _T_3468 @[el2_lib.scala 289:30]
node _T_3469 = bits(_T_3449, 5, 5) @[el2_lib.scala 291:36]
_T_3454[1] <= _T_3469 @[el2_lib.scala 291:30]
node _T_3470 = bits(_T_3449, 6, 6) @[el2_lib.scala 288:36]
_T_3451[4] <= _T_3470 @[el2_lib.scala 288:30]
node _T_3471 = bits(_T_3449, 6, 6) @[el2_lib.scala 289:36]
_T_3452[4] <= _T_3471 @[el2_lib.scala 289:30]
node _T_3472 = bits(_T_3449, 6, 6) @[el2_lib.scala 291:36]
_T_3454[2] <= _T_3472 @[el2_lib.scala 291:30]
node _T_3473 = bits(_T_3449, 7, 7) @[el2_lib.scala 290:36]
_T_3453[3] <= _T_3473 @[el2_lib.scala 290:30]
node _T_3474 = bits(_T_3449, 7, 7) @[el2_lib.scala 291:36]
_T_3454[3] <= _T_3474 @[el2_lib.scala 291:30]
node _T_3475 = bits(_T_3449, 8, 8) @[el2_lib.scala 288:36]
_T_3451[5] <= _T_3475 @[el2_lib.scala 288:30]
node _T_3476 = bits(_T_3449, 8, 8) @[el2_lib.scala 290:36]
_T_3453[4] <= _T_3476 @[el2_lib.scala 290:30]
node _T_3477 = bits(_T_3449, 8, 8) @[el2_lib.scala 291:36]
_T_3454[4] <= _T_3477 @[el2_lib.scala 291:30]
node _T_3478 = bits(_T_3449, 9, 9) @[el2_lib.scala 289:36]
_T_3452[5] <= _T_3478 @[el2_lib.scala 289:30]
node _T_3479 = bits(_T_3449, 9, 9) @[el2_lib.scala 290:36]
_T_3453[5] <= _T_3479 @[el2_lib.scala 290:30]
node _T_3480 = bits(_T_3449, 9, 9) @[el2_lib.scala 291:36]
_T_3454[5] <= _T_3480 @[el2_lib.scala 291:30]
node _T_3481 = bits(_T_3449, 10, 10) @[el2_lib.scala 288:36]
_T_3451[6] <= _T_3481 @[el2_lib.scala 288:30]
node _T_3482 = bits(_T_3449, 10, 10) @[el2_lib.scala 289:36]
_T_3452[6] <= _T_3482 @[el2_lib.scala 289:30]
node _T_3483 = bits(_T_3449, 10, 10) @[el2_lib.scala 290:36]
_T_3453[6] <= _T_3483 @[el2_lib.scala 290:30]
node _T_3484 = bits(_T_3449, 10, 10) @[el2_lib.scala 291:36]
_T_3454[6] <= _T_3484 @[el2_lib.scala 291:30]
node _T_3485 = bits(_T_3449, 11, 11) @[el2_lib.scala 288:36]
_T_3451[7] <= _T_3485 @[el2_lib.scala 288:30]
node _T_3486 = bits(_T_3449, 11, 11) @[el2_lib.scala 292:36]
_T_3455[0] <= _T_3486 @[el2_lib.scala 292:30]
node _T_3487 = bits(_T_3449, 12, 12) @[el2_lib.scala 289:36]
_T_3452[7] <= _T_3487 @[el2_lib.scala 289:30]
node _T_3488 = bits(_T_3449, 12, 12) @[el2_lib.scala 292:36]
_T_3455[1] <= _T_3488 @[el2_lib.scala 292:30]
node _T_3489 = bits(_T_3449, 13, 13) @[el2_lib.scala 288:36]
_T_3451[8] <= _T_3489 @[el2_lib.scala 288:30]
node _T_3490 = bits(_T_3449, 13, 13) @[el2_lib.scala 289:36]
_T_3452[8] <= _T_3490 @[el2_lib.scala 289:30]
node _T_3491 = bits(_T_3449, 13, 13) @[el2_lib.scala 292:36]
_T_3455[2] <= _T_3491 @[el2_lib.scala 292:30]
node _T_3492 = bits(_T_3449, 14, 14) @[el2_lib.scala 290:36]
_T_3453[7] <= _T_3492 @[el2_lib.scala 290:30]
node _T_3493 = bits(_T_3449, 14, 14) @[el2_lib.scala 292:36]
_T_3455[3] <= _T_3493 @[el2_lib.scala 292:30]
node _T_3494 = bits(_T_3449, 15, 15) @[el2_lib.scala 288:36]
_T_3451[9] <= _T_3494 @[el2_lib.scala 288:30]
node _T_3495 = bits(_T_3449, 15, 15) @[el2_lib.scala 290:36]
_T_3453[8] <= _T_3495 @[el2_lib.scala 290:30]
node _T_3496 = bits(_T_3449, 15, 15) @[el2_lib.scala 292:36]
_T_3455[4] <= _T_3496 @[el2_lib.scala 292:30]
node _T_3497 = bits(_T_3449, 16, 16) @[el2_lib.scala 289:36]
_T_3452[9] <= _T_3497 @[el2_lib.scala 289:30]
node _T_3498 = bits(_T_3449, 16, 16) @[el2_lib.scala 290:36]
_T_3453[9] <= _T_3498 @[el2_lib.scala 290:30]
node _T_3499 = bits(_T_3449, 16, 16) @[el2_lib.scala 292:36]
_T_3455[5] <= _T_3499 @[el2_lib.scala 292:30]
node _T_3500 = bits(_T_3449, 17, 17) @[el2_lib.scala 288:36]
_T_3451[10] <= _T_3500 @[el2_lib.scala 288:30]
node _T_3501 = bits(_T_3449, 17, 17) @[el2_lib.scala 289:36]
_T_3452[10] <= _T_3501 @[el2_lib.scala 289:30]
node _T_3502 = bits(_T_3449, 17, 17) @[el2_lib.scala 290:36]
_T_3453[10] <= _T_3502 @[el2_lib.scala 290:30]
node _T_3503 = bits(_T_3449, 17, 17) @[el2_lib.scala 292:36]
_T_3455[6] <= _T_3503 @[el2_lib.scala 292:30]
node _T_3504 = bits(_T_3449, 18, 18) @[el2_lib.scala 291:36]
_T_3454[7] <= _T_3504 @[el2_lib.scala 291:30]
node _T_3505 = bits(_T_3449, 18, 18) @[el2_lib.scala 292:36]
_T_3455[7] <= _T_3505 @[el2_lib.scala 292:30]
node _T_3506 = bits(_T_3449, 19, 19) @[el2_lib.scala 288:36]
_T_3451[11] <= _T_3506 @[el2_lib.scala 288:30]
node _T_3507 = bits(_T_3449, 19, 19) @[el2_lib.scala 291:36]
_T_3454[8] <= _T_3507 @[el2_lib.scala 291:30]
node _T_3508 = bits(_T_3449, 19, 19) @[el2_lib.scala 292:36]
_T_3455[8] <= _T_3508 @[el2_lib.scala 292:30]
node _T_3509 = bits(_T_3449, 20, 20) @[el2_lib.scala 289:36]
_T_3452[11] <= _T_3509 @[el2_lib.scala 289:30]
node _T_3510 = bits(_T_3449, 20, 20) @[el2_lib.scala 291:36]
_T_3454[9] <= _T_3510 @[el2_lib.scala 291:30]
node _T_3511 = bits(_T_3449, 20, 20) @[el2_lib.scala 292:36]
_T_3455[9] <= _T_3511 @[el2_lib.scala 292:30]
node _T_3512 = bits(_T_3449, 21, 21) @[el2_lib.scala 288:36]
_T_3451[12] <= _T_3512 @[el2_lib.scala 288:30]
node _T_3513 = bits(_T_3449, 21, 21) @[el2_lib.scala 289:36]
_T_3452[12] <= _T_3513 @[el2_lib.scala 289:30]
node _T_3514 = bits(_T_3449, 21, 21) @[el2_lib.scala 291:36]
_T_3454[10] <= _T_3514 @[el2_lib.scala 291:30]
node _T_3515 = bits(_T_3449, 21, 21) @[el2_lib.scala 292:36]
_T_3455[10] <= _T_3515 @[el2_lib.scala 292:30]
node _T_3516 = bits(_T_3449, 22, 22) @[el2_lib.scala 290:36]
_T_3453[11] <= _T_3516 @[el2_lib.scala 290:30]
node _T_3517 = bits(_T_3449, 22, 22) @[el2_lib.scala 291:36]
_T_3454[11] <= _T_3517 @[el2_lib.scala 291:30]
node _T_3518 = bits(_T_3449, 22, 22) @[el2_lib.scala 292:36]
_T_3455[11] <= _T_3518 @[el2_lib.scala 292:30]
node _T_3519 = bits(_T_3449, 23, 23) @[el2_lib.scala 288:36]
_T_3451[13] <= _T_3519 @[el2_lib.scala 288:30]
node _T_3520 = bits(_T_3449, 23, 23) @[el2_lib.scala 290:36]
_T_3453[12] <= _T_3520 @[el2_lib.scala 290:30]
node _T_3521 = bits(_T_3449, 23, 23) @[el2_lib.scala 291:36]
_T_3454[12] <= _T_3521 @[el2_lib.scala 291:30]
node _T_3522 = bits(_T_3449, 23, 23) @[el2_lib.scala 292:36]
_T_3455[12] <= _T_3522 @[el2_lib.scala 292:30]
node _T_3523 = bits(_T_3449, 24, 24) @[el2_lib.scala 289:36]
_T_3452[13] <= _T_3523 @[el2_lib.scala 289:30]
node _T_3524 = bits(_T_3449, 24, 24) @[el2_lib.scala 290:36]
_T_3453[13] <= _T_3524 @[el2_lib.scala 290:30]
node _T_3525 = bits(_T_3449, 24, 24) @[el2_lib.scala 291:36]
_T_3454[13] <= _T_3525 @[el2_lib.scala 291:30]
node _T_3526 = bits(_T_3449, 24, 24) @[el2_lib.scala 292:36]
_T_3455[13] <= _T_3526 @[el2_lib.scala 292:30]
node _T_3527 = bits(_T_3449, 25, 25) @[el2_lib.scala 288:36]
_T_3451[14] <= _T_3527 @[el2_lib.scala 288:30]
node _T_3528 = bits(_T_3449, 25, 25) @[el2_lib.scala 289:36]
_T_3452[14] <= _T_3528 @[el2_lib.scala 289:30]
node _T_3529 = bits(_T_3449, 25, 25) @[el2_lib.scala 290:36]
_T_3453[14] <= _T_3529 @[el2_lib.scala 290:30]
node _T_3530 = bits(_T_3449, 25, 25) @[el2_lib.scala 291:36]
_T_3454[14] <= _T_3530 @[el2_lib.scala 291:30]
node _T_3531 = bits(_T_3449, 25, 25) @[el2_lib.scala 292:36]
_T_3455[14] <= _T_3531 @[el2_lib.scala 292:30]
node _T_3532 = bits(_T_3449, 26, 26) @[el2_lib.scala 288:36]
_T_3451[15] <= _T_3532 @[el2_lib.scala 288:30]
node _T_3533 = bits(_T_3449, 26, 26) @[el2_lib.scala 293:36]
_T_3456[0] <= _T_3533 @[el2_lib.scala 293:30]
node _T_3534 = bits(_T_3449, 27, 27) @[el2_lib.scala 289:36]
_T_3452[15] <= _T_3534 @[el2_lib.scala 289:30]
node _T_3535 = bits(_T_3449, 27, 27) @[el2_lib.scala 293:36]
_T_3456[1] <= _T_3535 @[el2_lib.scala 293:30]
node _T_3536 = bits(_T_3449, 28, 28) @[el2_lib.scala 288:36]
_T_3451[16] <= _T_3536 @[el2_lib.scala 288:30]
node _T_3537 = bits(_T_3449, 28, 28) @[el2_lib.scala 289:36]
_T_3452[16] <= _T_3537 @[el2_lib.scala 289:30]
node _T_3538 = bits(_T_3449, 28, 28) @[el2_lib.scala 293:36]
_T_3456[2] <= _T_3538 @[el2_lib.scala 293:30]
node _T_3539 = bits(_T_3449, 29, 29) @[el2_lib.scala 290:36]
_T_3453[15] <= _T_3539 @[el2_lib.scala 290:30]
node _T_3540 = bits(_T_3449, 29, 29) @[el2_lib.scala 293:36]
_T_3456[3] <= _T_3540 @[el2_lib.scala 293:30]
node _T_3541 = bits(_T_3449, 30, 30) @[el2_lib.scala 288:36]
_T_3451[17] <= _T_3541 @[el2_lib.scala 288:30]
node _T_3542 = bits(_T_3449, 30, 30) @[el2_lib.scala 290:36]
_T_3453[16] <= _T_3542 @[el2_lib.scala 290:30]
node _T_3543 = bits(_T_3449, 30, 30) @[el2_lib.scala 293:36]
_T_3456[4] <= _T_3543 @[el2_lib.scala 293:30]
node _T_3544 = bits(_T_3449, 31, 31) @[el2_lib.scala 289:36]
_T_3452[17] <= _T_3544 @[el2_lib.scala 289:30]
node _T_3545 = bits(_T_3449, 31, 31) @[el2_lib.scala 290:36]
_T_3453[17] <= _T_3545 @[el2_lib.scala 290:30]
node _T_3546 = bits(_T_3449, 31, 31) @[el2_lib.scala 293:36]
_T_3456[5] <= _T_3546 @[el2_lib.scala 293:30]
node _T_3547 = xorr(_T_3449) @[el2_lib.scala 296:30]
node _T_3548 = xorr(_T_3450) @[el2_lib.scala 296:44]
node _T_3549 = xor(_T_3547, _T_3548) @[el2_lib.scala 296:35]
node _T_3550 = not(UInt<1>("h00")) @[el2_lib.scala 296:52]
node _T_3551 = and(_T_3549, _T_3550) @[el2_lib.scala 296:50]
node _T_3552 = bits(_T_3450, 5, 5) @[el2_lib.scala 296:68]
node _T_3553 = cat(_T_3456[2], _T_3456[1]) @[el2_lib.scala 296:76]
node _T_3554 = cat(_T_3553, _T_3456[0]) @[el2_lib.scala 296:76]
node _T_3555 = cat(_T_3456[5], _T_3456[4]) @[el2_lib.scala 296:76]
node _T_3556 = cat(_T_3555, _T_3456[3]) @[el2_lib.scala 296:76]
node _T_3557 = cat(_T_3556, _T_3554) @[el2_lib.scala 296:76]
node _T_3558 = xorr(_T_3557) @[el2_lib.scala 296:83]
node _T_3559 = xor(_T_3552, _T_3558) @[el2_lib.scala 296:71]
node _T_3560 = bits(_T_3450, 4, 4) @[el2_lib.scala 296:95]
node _T_3561 = cat(_T_3455[2], _T_3455[1]) @[el2_lib.scala 296:103]
node _T_3562 = cat(_T_3561, _T_3455[0]) @[el2_lib.scala 296:103]
node _T_3563 = cat(_T_3455[4], _T_3455[3]) @[el2_lib.scala 296:103]
node _T_3564 = cat(_T_3455[6], _T_3455[5]) @[el2_lib.scala 296:103]
node _T_3565 = cat(_T_3564, _T_3563) @[el2_lib.scala 296:103]
node _T_3566 = cat(_T_3565, _T_3562) @[el2_lib.scala 296:103]
node _T_3567 = cat(_T_3455[8], _T_3455[7]) @[el2_lib.scala 296:103]
node _T_3568 = cat(_T_3455[10], _T_3455[9]) @[el2_lib.scala 296:103]
node _T_3569 = cat(_T_3568, _T_3567) @[el2_lib.scala 296:103]
node _T_3570 = cat(_T_3455[12], _T_3455[11]) @[el2_lib.scala 296:103]
node _T_3571 = cat(_T_3455[14], _T_3455[13]) @[el2_lib.scala 296:103]
node _T_3572 = cat(_T_3571, _T_3570) @[el2_lib.scala 296:103]
node _T_3573 = cat(_T_3572, _T_3569) @[el2_lib.scala 296:103]
node _T_3574 = cat(_T_3573, _T_3566) @[el2_lib.scala 296:103]
node _T_3575 = xorr(_T_3574) @[el2_lib.scala 296:110]
node _T_3576 = xor(_T_3560, _T_3575) @[el2_lib.scala 296:98]
node _T_3577 = bits(_T_3450, 3, 3) @[el2_lib.scala 296:122]
node _T_3578 = cat(_T_3454[2], _T_3454[1]) @[el2_lib.scala 296:130]
node _T_3579 = cat(_T_3578, _T_3454[0]) @[el2_lib.scala 296:130]
node _T_3580 = cat(_T_3454[4], _T_3454[3]) @[el2_lib.scala 296:130]
node _T_3581 = cat(_T_3454[6], _T_3454[5]) @[el2_lib.scala 296:130]
node _T_3582 = cat(_T_3581, _T_3580) @[el2_lib.scala 296:130]
node _T_3583 = cat(_T_3582, _T_3579) @[el2_lib.scala 296:130]
node _T_3584 = cat(_T_3454[8], _T_3454[7]) @[el2_lib.scala 296:130]
node _T_3585 = cat(_T_3454[10], _T_3454[9]) @[el2_lib.scala 296:130]
node _T_3586 = cat(_T_3585, _T_3584) @[el2_lib.scala 296:130]
node _T_3587 = cat(_T_3454[12], _T_3454[11]) @[el2_lib.scala 296:130]
node _T_3588 = cat(_T_3454[14], _T_3454[13]) @[el2_lib.scala 296:130]
node _T_3589 = cat(_T_3588, _T_3587) @[el2_lib.scala 296:130]
node _T_3590 = cat(_T_3589, _T_3586) @[el2_lib.scala 296:130]
node _T_3591 = cat(_T_3590, _T_3583) @[el2_lib.scala 296:130]
node _T_3592 = xorr(_T_3591) @[el2_lib.scala 296:137]
node _T_3593 = xor(_T_3577, _T_3592) @[el2_lib.scala 296:125]
node _T_3594 = bits(_T_3450, 2, 2) @[el2_lib.scala 296:149]
node _T_3595 = cat(_T_3453[1], _T_3453[0]) @[el2_lib.scala 296:157]
node _T_3596 = cat(_T_3453[3], _T_3453[2]) @[el2_lib.scala 296:157]
node _T_3597 = cat(_T_3596, _T_3595) @[el2_lib.scala 296:157]
node _T_3598 = cat(_T_3453[5], _T_3453[4]) @[el2_lib.scala 296:157]
node _T_3599 = cat(_T_3453[8], _T_3453[7]) @[el2_lib.scala 296:157]
node _T_3600 = cat(_T_3599, _T_3453[6]) @[el2_lib.scala 296:157]
node _T_3601 = cat(_T_3600, _T_3598) @[el2_lib.scala 296:157]
node _T_3602 = cat(_T_3601, _T_3597) @[el2_lib.scala 296:157]
node _T_3603 = cat(_T_3453[10], _T_3453[9]) @[el2_lib.scala 296:157]
node _T_3604 = cat(_T_3453[12], _T_3453[11]) @[el2_lib.scala 296:157]
node _T_3605 = cat(_T_3604, _T_3603) @[el2_lib.scala 296:157]
node _T_3606 = cat(_T_3453[14], _T_3453[13]) @[el2_lib.scala 296:157]
node _T_3607 = cat(_T_3453[17], _T_3453[16]) @[el2_lib.scala 296:157]
node _T_3608 = cat(_T_3607, _T_3453[15]) @[el2_lib.scala 296:157]
node _T_3609 = cat(_T_3608, _T_3606) @[el2_lib.scala 296:157]
node _T_3610 = cat(_T_3609, _T_3605) @[el2_lib.scala 296:157]
node _T_3611 = cat(_T_3610, _T_3602) @[el2_lib.scala 296:157]
node _T_3612 = xorr(_T_3611) @[el2_lib.scala 296:164]
node _T_3613 = xor(_T_3594, _T_3612) @[el2_lib.scala 296:152]
node _T_3614 = bits(_T_3450, 1, 1) @[el2_lib.scala 296:176]
node _T_3615 = cat(_T_3452[1], _T_3452[0]) @[el2_lib.scala 296:184]
node _T_3616 = cat(_T_3452[3], _T_3452[2]) @[el2_lib.scala 296:184]
node _T_3617 = cat(_T_3616, _T_3615) @[el2_lib.scala 296:184]
node _T_3618 = cat(_T_3452[5], _T_3452[4]) @[el2_lib.scala 296:184]
node _T_3619 = cat(_T_3452[8], _T_3452[7]) @[el2_lib.scala 296:184]
node _T_3620 = cat(_T_3619, _T_3452[6]) @[el2_lib.scala 296:184]
node _T_3621 = cat(_T_3620, _T_3618) @[el2_lib.scala 296:184]
node _T_3622 = cat(_T_3621, _T_3617) @[el2_lib.scala 296:184]
node _T_3623 = cat(_T_3452[10], _T_3452[9]) @[el2_lib.scala 296:184]
node _T_3624 = cat(_T_3452[12], _T_3452[11]) @[el2_lib.scala 296:184]
node _T_3625 = cat(_T_3624, _T_3623) @[el2_lib.scala 296:184]
node _T_3626 = cat(_T_3452[14], _T_3452[13]) @[el2_lib.scala 296:184]
node _T_3627 = cat(_T_3452[17], _T_3452[16]) @[el2_lib.scala 296:184]
node _T_3628 = cat(_T_3627, _T_3452[15]) @[el2_lib.scala 296:184]
node _T_3629 = cat(_T_3628, _T_3626) @[el2_lib.scala 296:184]
node _T_3630 = cat(_T_3629, _T_3625) @[el2_lib.scala 296:184]
node _T_3631 = cat(_T_3630, _T_3622) @[el2_lib.scala 296:184]
node _T_3632 = xorr(_T_3631) @[el2_lib.scala 296:191]
node _T_3633 = xor(_T_3614, _T_3632) @[el2_lib.scala 296:179]
node _T_3634 = bits(_T_3450, 0, 0) @[el2_lib.scala 296:203]
node _T_3635 = cat(_T_3451[1], _T_3451[0]) @[el2_lib.scala 296:211]
node _T_3636 = cat(_T_3451[3], _T_3451[2]) @[el2_lib.scala 296:211]
node _T_3637 = cat(_T_3636, _T_3635) @[el2_lib.scala 296:211]
node _T_3638 = cat(_T_3451[5], _T_3451[4]) @[el2_lib.scala 296:211]
node _T_3639 = cat(_T_3451[8], _T_3451[7]) @[el2_lib.scala 296:211]
node _T_3640 = cat(_T_3639, _T_3451[6]) @[el2_lib.scala 296:211]
node _T_3641 = cat(_T_3640, _T_3638) @[el2_lib.scala 296:211]
node _T_3642 = cat(_T_3641, _T_3637) @[el2_lib.scala 296:211]
node _T_3643 = cat(_T_3451[10], _T_3451[9]) @[el2_lib.scala 296:211]
node _T_3644 = cat(_T_3451[12], _T_3451[11]) @[el2_lib.scala 296:211]
node _T_3645 = cat(_T_3644, _T_3643) @[el2_lib.scala 296:211]
node _T_3646 = cat(_T_3451[14], _T_3451[13]) @[el2_lib.scala 296:211]
node _T_3647 = cat(_T_3451[17], _T_3451[16]) @[el2_lib.scala 296:211]
node _T_3648 = cat(_T_3647, _T_3451[15]) @[el2_lib.scala 296:211]
node _T_3649 = cat(_T_3648, _T_3646) @[el2_lib.scala 296:211]
node _T_3650 = cat(_T_3649, _T_3645) @[el2_lib.scala 296:211]
node _T_3651 = cat(_T_3650, _T_3642) @[el2_lib.scala 296:211]
node _T_3652 = xorr(_T_3651) @[el2_lib.scala 296:218]
node _T_3653 = xor(_T_3634, _T_3652) @[el2_lib.scala 296:206]
node _T_3654 = cat(_T_3613, _T_3633) @[Cat.scala 29:58]
node _T_3655 = cat(_T_3654, _T_3653) @[Cat.scala 29:58]
node _T_3656 = cat(_T_3576, _T_3593) @[Cat.scala 29:58]
node _T_3657 = cat(_T_3551, _T_3559) @[Cat.scala 29:58]
node _T_3658 = cat(_T_3657, _T_3656) @[Cat.scala 29:58]
node _T_3659 = cat(_T_3658, _T_3655) @[Cat.scala 29:58]
node _T_3660 = neq(_T_3659, UInt<1>("h00")) @[el2_lib.scala 297:44]
node _T_3661 = and(_T_3448, _T_3660) @[el2_lib.scala 297:32]
node _T_3662 = bits(_T_3659, 6, 6) @[el2_lib.scala 297:64]
node _T_3663 = and(_T_3661, _T_3662) @[el2_lib.scala 297:53]
node _T_3664 = neq(_T_3659, UInt<1>("h00")) @[el2_lib.scala 298:44]
node _T_3665 = and(_T_3448, _T_3664) @[el2_lib.scala 298:32]
node _T_3666 = bits(_T_3659, 6, 6) @[el2_lib.scala 298:65]
node _T_3667 = not(_T_3666) @[el2_lib.scala 298:55]
node _T_3668 = and(_T_3665, _T_3667) @[el2_lib.scala 298:53]
wire _T_3669 : UInt<1>[39] @[el2_lib.scala 299:26]
node _T_3670 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3671 = eq(_T_3670, UInt<1>("h01")) @[el2_lib.scala 302:41]
_T_3669[0] <= _T_3671 @[el2_lib.scala 302:23]
node _T_3672 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3673 = eq(_T_3672, UInt<2>("h02")) @[el2_lib.scala 302:41]
_T_3669[1] <= _T_3673 @[el2_lib.scala 302:23]
node _T_3674 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3675 = eq(_T_3674, UInt<2>("h03")) @[el2_lib.scala 302:41]
_T_3669[2] <= _T_3675 @[el2_lib.scala 302:23]
node _T_3676 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3677 = eq(_T_3676, UInt<3>("h04")) @[el2_lib.scala 302:41]
_T_3669[3] <= _T_3677 @[el2_lib.scala 302:23]
node _T_3678 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3679 = eq(_T_3678, UInt<3>("h05")) @[el2_lib.scala 302:41]
_T_3669[4] <= _T_3679 @[el2_lib.scala 302:23]
node _T_3680 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3681 = eq(_T_3680, UInt<3>("h06")) @[el2_lib.scala 302:41]
_T_3669[5] <= _T_3681 @[el2_lib.scala 302:23]
node _T_3682 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3683 = eq(_T_3682, UInt<3>("h07")) @[el2_lib.scala 302:41]
_T_3669[6] <= _T_3683 @[el2_lib.scala 302:23]
node _T_3684 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3685 = eq(_T_3684, UInt<4>("h08")) @[el2_lib.scala 302:41]
_T_3669[7] <= _T_3685 @[el2_lib.scala 302:23]
node _T_3686 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3687 = eq(_T_3686, UInt<4>("h09")) @[el2_lib.scala 302:41]
_T_3669[8] <= _T_3687 @[el2_lib.scala 302:23]
node _T_3688 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3689 = eq(_T_3688, UInt<4>("h0a")) @[el2_lib.scala 302:41]
_T_3669[9] <= _T_3689 @[el2_lib.scala 302:23]
node _T_3690 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3691 = eq(_T_3690, UInt<4>("h0b")) @[el2_lib.scala 302:41]
_T_3669[10] <= _T_3691 @[el2_lib.scala 302:23]
node _T_3692 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3693 = eq(_T_3692, UInt<4>("h0c")) @[el2_lib.scala 302:41]
_T_3669[11] <= _T_3693 @[el2_lib.scala 302:23]
node _T_3694 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3695 = eq(_T_3694, UInt<4>("h0d")) @[el2_lib.scala 302:41]
_T_3669[12] <= _T_3695 @[el2_lib.scala 302:23]
node _T_3696 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3697 = eq(_T_3696, UInt<4>("h0e")) @[el2_lib.scala 302:41]
_T_3669[13] <= _T_3697 @[el2_lib.scala 302:23]
node _T_3698 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3699 = eq(_T_3698, UInt<4>("h0f")) @[el2_lib.scala 302:41]
_T_3669[14] <= _T_3699 @[el2_lib.scala 302:23]
node _T_3700 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3701 = eq(_T_3700, UInt<5>("h010")) @[el2_lib.scala 302:41]
_T_3669[15] <= _T_3701 @[el2_lib.scala 302:23]
node _T_3702 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3703 = eq(_T_3702, UInt<5>("h011")) @[el2_lib.scala 302:41]
_T_3669[16] <= _T_3703 @[el2_lib.scala 302:23]
node _T_3704 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3705 = eq(_T_3704, UInt<5>("h012")) @[el2_lib.scala 302:41]
_T_3669[17] <= _T_3705 @[el2_lib.scala 302:23]
node _T_3706 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3707 = eq(_T_3706, UInt<5>("h013")) @[el2_lib.scala 302:41]
_T_3669[18] <= _T_3707 @[el2_lib.scala 302:23]
node _T_3708 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3709 = eq(_T_3708, UInt<5>("h014")) @[el2_lib.scala 302:41]
_T_3669[19] <= _T_3709 @[el2_lib.scala 302:23]
node _T_3710 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3711 = eq(_T_3710, UInt<5>("h015")) @[el2_lib.scala 302:41]
_T_3669[20] <= _T_3711 @[el2_lib.scala 302:23]
node _T_3712 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3713 = eq(_T_3712, UInt<5>("h016")) @[el2_lib.scala 302:41]
_T_3669[21] <= _T_3713 @[el2_lib.scala 302:23]
node _T_3714 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3715 = eq(_T_3714, UInt<5>("h017")) @[el2_lib.scala 302:41]
_T_3669[22] <= _T_3715 @[el2_lib.scala 302:23]
node _T_3716 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3717 = eq(_T_3716, UInt<5>("h018")) @[el2_lib.scala 302:41]
_T_3669[23] <= _T_3717 @[el2_lib.scala 302:23]
node _T_3718 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3719 = eq(_T_3718, UInt<5>("h019")) @[el2_lib.scala 302:41]
_T_3669[24] <= _T_3719 @[el2_lib.scala 302:23]
node _T_3720 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3721 = eq(_T_3720, UInt<5>("h01a")) @[el2_lib.scala 302:41]
_T_3669[25] <= _T_3721 @[el2_lib.scala 302:23]
node _T_3722 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3723 = eq(_T_3722, UInt<5>("h01b")) @[el2_lib.scala 302:41]
_T_3669[26] <= _T_3723 @[el2_lib.scala 302:23]
node _T_3724 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3725 = eq(_T_3724, UInt<5>("h01c")) @[el2_lib.scala 302:41]
_T_3669[27] <= _T_3725 @[el2_lib.scala 302:23]
node _T_3726 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3727 = eq(_T_3726, UInt<5>("h01d")) @[el2_lib.scala 302:41]
_T_3669[28] <= _T_3727 @[el2_lib.scala 302:23]
node _T_3728 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3729 = eq(_T_3728, UInt<5>("h01e")) @[el2_lib.scala 302:41]
_T_3669[29] <= _T_3729 @[el2_lib.scala 302:23]
node _T_3730 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3731 = eq(_T_3730, UInt<5>("h01f")) @[el2_lib.scala 302:41]
_T_3669[30] <= _T_3731 @[el2_lib.scala 302:23]
node _T_3732 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3733 = eq(_T_3732, UInt<6>("h020")) @[el2_lib.scala 302:41]
_T_3669[31] <= _T_3733 @[el2_lib.scala 302:23]
node _T_3734 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3735 = eq(_T_3734, UInt<6>("h021")) @[el2_lib.scala 302:41]
_T_3669[32] <= _T_3735 @[el2_lib.scala 302:23]
node _T_3736 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3737 = eq(_T_3736, UInt<6>("h022")) @[el2_lib.scala 302:41]
_T_3669[33] <= _T_3737 @[el2_lib.scala 302:23]
node _T_3738 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3739 = eq(_T_3738, UInt<6>("h023")) @[el2_lib.scala 302:41]
_T_3669[34] <= _T_3739 @[el2_lib.scala 302:23]
node _T_3740 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3741 = eq(_T_3740, UInt<6>("h024")) @[el2_lib.scala 302:41]
_T_3669[35] <= _T_3741 @[el2_lib.scala 302:23]
node _T_3742 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3743 = eq(_T_3742, UInt<6>("h025")) @[el2_lib.scala 302:41]
_T_3669[36] <= _T_3743 @[el2_lib.scala 302:23]
node _T_3744 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3745 = eq(_T_3744, UInt<6>("h026")) @[el2_lib.scala 302:41]
_T_3669[37] <= _T_3745 @[el2_lib.scala 302:23]
node _T_3746 = bits(_T_3659, 5, 0) @[el2_lib.scala 302:35]
node _T_3747 = eq(_T_3746, UInt<6>("h027")) @[el2_lib.scala 302:41]
_T_3669[38] <= _T_3747 @[el2_lib.scala 302:23]
node _T_3748 = bits(_T_3450, 6, 6) @[el2_lib.scala 304:37]
node _T_3749 = bits(_T_3449, 31, 26) @[el2_lib.scala 304:45]
node _T_3750 = bits(_T_3450, 5, 5) @[el2_lib.scala 304:60]
node _T_3751 = bits(_T_3449, 25, 11) @[el2_lib.scala 304:68]
node _T_3752 = bits(_T_3450, 4, 4) @[el2_lib.scala 304:83]
node _T_3753 = bits(_T_3449, 10, 4) @[el2_lib.scala 304:91]
node _T_3754 = bits(_T_3450, 3, 3) @[el2_lib.scala 304:105]
node _T_3755 = bits(_T_3449, 3, 1) @[el2_lib.scala 304:113]
node _T_3756 = bits(_T_3450, 2, 2) @[el2_lib.scala 304:126]
node _T_3757 = bits(_T_3449, 0, 0) @[el2_lib.scala 304:134]
node _T_3758 = bits(_T_3450, 1, 0) @[el2_lib.scala 304:145]
node _T_3759 = cat(_T_3757, _T_3758) @[Cat.scala 29:58]
node _T_3760 = cat(_T_3754, _T_3755) @[Cat.scala 29:58]
node _T_3761 = cat(_T_3760, _T_3756) @[Cat.scala 29:58]
node _T_3762 = cat(_T_3761, _T_3759) @[Cat.scala 29:58]
node _T_3763 = cat(_T_3751, _T_3752) @[Cat.scala 29:58]
node _T_3764 = cat(_T_3763, _T_3753) @[Cat.scala 29:58]
node _T_3765 = cat(_T_3748, _T_3749) @[Cat.scala 29:58]
node _T_3766 = cat(_T_3765, _T_3750) @[Cat.scala 29:58]
node _T_3767 = cat(_T_3766, _T_3764) @[Cat.scala 29:58]
node _T_3768 = cat(_T_3767, _T_3762) @[Cat.scala 29:58]
node _T_3769 = bits(_T_3663, 0, 0) @[el2_lib.scala 305:49]
node _T_3770 = cat(_T_3669[1], _T_3669[0]) @[el2_lib.scala 305:69]
node _T_3771 = cat(_T_3669[3], _T_3669[2]) @[el2_lib.scala 305:69]
node _T_3772 = cat(_T_3771, _T_3770) @[el2_lib.scala 305:69]
node _T_3773 = cat(_T_3669[5], _T_3669[4]) @[el2_lib.scala 305:69]
node _T_3774 = cat(_T_3669[8], _T_3669[7]) @[el2_lib.scala 305:69]
node _T_3775 = cat(_T_3774, _T_3669[6]) @[el2_lib.scala 305:69]
node _T_3776 = cat(_T_3775, _T_3773) @[el2_lib.scala 305:69]
node _T_3777 = cat(_T_3776, _T_3772) @[el2_lib.scala 305:69]
node _T_3778 = cat(_T_3669[10], _T_3669[9]) @[el2_lib.scala 305:69]
node _T_3779 = cat(_T_3669[13], _T_3669[12]) @[el2_lib.scala 305:69]
node _T_3780 = cat(_T_3779, _T_3669[11]) @[el2_lib.scala 305:69]
node _T_3781 = cat(_T_3780, _T_3778) @[el2_lib.scala 305:69]
node _T_3782 = cat(_T_3669[15], _T_3669[14]) @[el2_lib.scala 305:69]
node _T_3783 = cat(_T_3669[18], _T_3669[17]) @[el2_lib.scala 305:69]
node _T_3784 = cat(_T_3783, _T_3669[16]) @[el2_lib.scala 305:69]
node _T_3785 = cat(_T_3784, _T_3782) @[el2_lib.scala 305:69]
node _T_3786 = cat(_T_3785, _T_3781) @[el2_lib.scala 305:69]
node _T_3787 = cat(_T_3786, _T_3777) @[el2_lib.scala 305:69]
node _T_3788 = cat(_T_3669[20], _T_3669[19]) @[el2_lib.scala 305:69]
node _T_3789 = cat(_T_3669[23], _T_3669[22]) @[el2_lib.scala 305:69]
node _T_3790 = cat(_T_3789, _T_3669[21]) @[el2_lib.scala 305:69]
node _T_3791 = cat(_T_3790, _T_3788) @[el2_lib.scala 305:69]
node _T_3792 = cat(_T_3669[25], _T_3669[24]) @[el2_lib.scala 305:69]
node _T_3793 = cat(_T_3669[28], _T_3669[27]) @[el2_lib.scala 305:69]
node _T_3794 = cat(_T_3793, _T_3669[26]) @[el2_lib.scala 305:69]
node _T_3795 = cat(_T_3794, _T_3792) @[el2_lib.scala 305:69]
node _T_3796 = cat(_T_3795, _T_3791) @[el2_lib.scala 305:69]
node _T_3797 = cat(_T_3669[30], _T_3669[29]) @[el2_lib.scala 305:69]
node _T_3798 = cat(_T_3669[33], _T_3669[32]) @[el2_lib.scala 305:69]
node _T_3799 = cat(_T_3798, _T_3669[31]) @[el2_lib.scala 305:69]
node _T_3800 = cat(_T_3799, _T_3797) @[el2_lib.scala 305:69]
node _T_3801 = cat(_T_3669[35], _T_3669[34]) @[el2_lib.scala 305:69]
node _T_3802 = cat(_T_3669[38], _T_3669[37]) @[el2_lib.scala 305:69]
node _T_3803 = cat(_T_3802, _T_3669[36]) @[el2_lib.scala 305:69]
node _T_3804 = cat(_T_3803, _T_3801) @[el2_lib.scala 305:69]
node _T_3805 = cat(_T_3804, _T_3800) @[el2_lib.scala 305:69]
node _T_3806 = cat(_T_3805, _T_3796) @[el2_lib.scala 305:69]
node _T_3807 = cat(_T_3806, _T_3787) @[el2_lib.scala 305:69]
node _T_3808 = xor(_T_3807, _T_3768) @[el2_lib.scala 305:76]
node _T_3809 = mux(_T_3769, _T_3808, _T_3768) @[el2_lib.scala 305:31]
node _T_3810 = bits(_T_3809, 37, 32) @[el2_lib.scala 307:37]
node _T_3811 = bits(_T_3809, 30, 16) @[el2_lib.scala 307:61]
node _T_3812 = bits(_T_3809, 14, 8) @[el2_lib.scala 307:86]
node _T_3813 = bits(_T_3809, 6, 4) @[el2_lib.scala 307:110]
node _T_3814 = bits(_T_3809, 2, 2) @[el2_lib.scala 307:133]
node _T_3815 = cat(_T_3813, _T_3814) @[Cat.scala 29:58]
node _T_3816 = cat(_T_3810, _T_3811) @[Cat.scala 29:58]
node _T_3817 = cat(_T_3816, _T_3812) @[Cat.scala 29:58]
node _T_3818 = cat(_T_3817, _T_3815) @[Cat.scala 29:58]
node _T_3819 = bits(_T_3809, 38, 38) @[el2_lib.scala 308:39]
node _T_3820 = bits(_T_3659, 6, 0) @[el2_lib.scala 308:56]
node _T_3821 = eq(_T_3820, UInt<7>("h040")) @[el2_lib.scala 308:62]
node _T_3822 = xor(_T_3819, _T_3821) @[el2_lib.scala 308:44]
node _T_3823 = bits(_T_3809, 31, 31) @[el2_lib.scala 308:102]
node _T_3824 = bits(_T_3809, 15, 15) @[el2_lib.scala 308:124]
node _T_3825 = bits(_T_3809, 7, 7) @[el2_lib.scala 308:146]
node _T_3826 = bits(_T_3809, 3, 3) @[el2_lib.scala 308:167]
node _T_3827 = bits(_T_3809, 1, 0) @[el2_lib.scala 308:188]
node _T_3828 = cat(_T_3825, _T_3826) @[Cat.scala 29:58]
node _T_3829 = cat(_T_3828, _T_3827) @[Cat.scala 29:58]
node _T_3830 = cat(_T_3822, _T_3823) @[Cat.scala 29:58]
node _T_3831 = cat(_T_3830, _T_3824) @[Cat.scala 29:58]
node _T_3832 = cat(_T_3831, _T_3829) @[Cat.scala 29:58]
wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 710:32]
wire _T_3833 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 711:32]
_T_3833[0] <= _T_3447 @[el2_ifu_mem_ctl.scala 711:32]
_T_3833[1] <= _T_3832 @[el2_ifu_mem_ctl.scala 711:32]
iccm_corrected_ecc[0] <= _T_3833[0] @[el2_ifu_mem_ctl.scala 711:22]
iccm_corrected_ecc[1] <= _T_3833[1] @[el2_ifu_mem_ctl.scala 711:22]
wire _T_3834 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 712:33]
_T_3834[0] <= _T_3433 @[el2_ifu_mem_ctl.scala 712:33]
_T_3834[1] <= _T_3818 @[el2_ifu_mem_ctl.scala 712:33]
iccm_corrected_data[0] <= _T_3834[0] @[el2_ifu_mem_ctl.scala 712:23]
iccm_corrected_data[1] <= _T_3834[1] @[el2_ifu_mem_ctl.scala 712:23]
node _T_3835 = cat(_T_3278, _T_3663) @[Cat.scala 29:58]
iccm_single_ecc_error <= _T_3835 @[el2_ifu_mem_ctl.scala 713:25]
node _T_3836 = cat(_T_3283, _T_3668) @[Cat.scala 29:58]
iccm_double_ecc_error <= _T_3836 @[el2_ifu_mem_ctl.scala 714:25]
node _T_3837 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 715:54]
node _T_3838 = and(_T_3837, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 715:58]
node _T_3839 = and(_T_3838, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 715:78]
io.iccm_rd_ecc_single_err <= _T_3839 @[el2_ifu_mem_ctl.scala 715:29]
node _T_3840 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 716:54]
node _T_3841 = and(_T_3840, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 716:58]
io.iccm_rd_ecc_double_err <= _T_3841 @[el2_ifu_mem_ctl.scala 716:29]
node _T_3842 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 717:60]
node _T_3843 = bits(_T_3842, 0, 0) @[el2_ifu_mem_ctl.scala 717:64]
node iccm_corrected_data_f_mux = mux(_T_3843, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 717:38]
node _T_3844 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 718:59]
node _T_3845 = bits(_T_3844, 0, 0) @[el2_ifu_mem_ctl.scala 718:63]
node iccm_corrected_ecc_f_mux = mux(_T_3845, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 718:37]
wire iccm_rd_ecc_single_err_ff : UInt<1>
iccm_rd_ecc_single_err_ff <= UInt<1>("h00")
Branch Predictor started
2020-10-20 13:51:36 +08:00
node _T_3846 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:76]
node _T_3847 = and(io.iccm_rd_ecc_single_err, _T_3846) @[el2_ifu_mem_ctl.scala 720:74]
node _T_3848 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:106]
node _T_3849 = and(_T_3847, _T_3848) @[el2_ifu_mem_ctl.scala 720:104]
node iccm_ecc_write_status = or(_T_3849, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 720:127]
IMC 80%
2020-10-19 13:10:40 +08:00
node _T_3850 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 721:67]
node _T_3851 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 721:98]
node iccm_rd_ecc_single_err_hold_in = and(_T_3850, _T_3851) @[el2_ifu_mem_ctl.scala 721:96]
iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 722:20]
wire iccm_rw_addr_f : UInt<14>
iccm_rw_addr_f <= UInt<1>("h00")
node _T_3852 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 724:57]
node _T_3853 = bits(_T_3852, 0, 0) @[el2_ifu_mem_ctl.scala 724:67]
node _T_3854 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:102]
node _T_3855 = tail(_T_3854, 1) @[el2_ifu_mem_ctl.scala 724:102]
node iccm_ecc_corr_index_in = mux(_T_3853, iccm_rw_addr_f, _T_3855) @[el2_ifu_mem_ctl.scala 724:35]
Branch Predictor started
2020-10-20 13:51:36 +08:00
node _T_3856 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 725:67]
reg _T_3857 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 725:51]
_T_3857 <= _T_3856 @[el2_ifu_mem_ctl.scala 725:51]
iccm_rw_addr_f <= _T_3857 @[el2_ifu_mem_ctl.scala 725:18]
reg _T_3858 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 726:62]
_T_3858 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 726:62]
iccm_rd_ecc_single_err_ff <= _T_3858 @[el2_ifu_mem_ctl.scala 726:29]
node _T_3859 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58]
node _T_3860 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 727:152]
reg _T_3861 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3860 : @[Reg.scala 28:19]
_T_3861 <= _T_3859 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
iccm_ecc_corr_data_ff <= _T_3861 @[el2_ifu_mem_ctl.scala 727:25]
node _T_3862 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 728:119]
reg _T_3863 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3862 : @[Reg.scala 28:19]
_T_3863 <= iccm_ecc_corr_index_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
iccm_ecc_corr_index_ff <= _T_3863 @[el2_ifu_mem_ctl.scala 728:26]
node _T_3864 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:41]
node _T_3865 = and(io.ifc_fetch_req_bf, _T_3864) @[el2_ifu_mem_ctl.scala 729:39]
node _T_3866 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:72]
node _T_3867 = and(_T_3865, _T_3866) @[el2_ifu_mem_ctl.scala 729:70]
node _T_3868 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 730:19]
node _T_3869 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 730:34]
node _T_3870 = and(_T_3868, _T_3869) @[el2_ifu_mem_ctl.scala 730:32]
node _T_3871 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 731:19]
node _T_3872 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 731:39]
node _T_3873 = and(_T_3871, _T_3872) @[el2_ifu_mem_ctl.scala 731:37]
node _T_3874 = or(_T_3870, _T_3873) @[el2_ifu_mem_ctl.scala 730:88]
node _T_3875 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 732:19]
node _T_3876 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 732:43]
node _T_3877 = and(_T_3875, _T_3876) @[el2_ifu_mem_ctl.scala 732:41]
node _T_3878 = or(_T_3874, _T_3877) @[el2_ifu_mem_ctl.scala 731:88]
node _T_3879 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 733:19]
node _T_3880 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 733:37]
node _T_3881 = and(_T_3879, _T_3880) @[el2_ifu_mem_ctl.scala 733:35]
node _T_3882 = or(_T_3878, _T_3881) @[el2_ifu_mem_ctl.scala 732:88]
node _T_3883 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 734:19]
node _T_3884 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:40]
node _T_3885 = and(_T_3883, _T_3884) @[el2_ifu_mem_ctl.scala 734:38]
node _T_3886 = or(_T_3882, _T_3885) @[el2_ifu_mem_ctl.scala 733:88]
node _T_3887 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 735:19]
node _T_3888 = and(_T_3887, miss_state_en) @[el2_ifu_mem_ctl.scala 735:37]
node _T_3889 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 735:71]
node _T_3890 = and(_T_3888, _T_3889) @[el2_ifu_mem_ctl.scala 735:54]
node _T_3891 = or(_T_3886, _T_3890) @[el2_ifu_mem_ctl.scala 734:57]
node _T_3892 = eq(_T_3891, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 730:5]
node _T_3893 = and(_T_3867, _T_3892) @[el2_ifu_mem_ctl.scala 729:96]
node _T_3894 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 736:28]
node _T_3895 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:52]
node _T_3896 = and(_T_3894, _T_3895) @[el2_ifu_mem_ctl.scala 736:50]
node _T_3897 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:83]
node _T_3898 = and(_T_3896, _T_3897) @[el2_ifu_mem_ctl.scala 736:81]
node _T_3899 = or(_T_3893, _T_3898) @[el2_ifu_mem_ctl.scala 735:93]
io.ic_rd_en <= _T_3899 @[el2_ifu_mem_ctl.scala 729:15]
wire bus_ic_wr_en : UInt<1>
bus_ic_wr_en <= UInt<1>("h00")
node _T_3900 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15]
node _T_3901 = mux(_T_3900, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_3902 = and(bus_ic_wr_en, _T_3901) @[el2_ifu_mem_ctl.scala 738:31]
io.ic_wr_en <= _T_3902 @[el2_ifu_mem_ctl.scala 738:15]
node _T_3903 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 739:59]
node _T_3904 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 739:91]
node _T_3905 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 739:127]
node _T_3906 = or(_T_3905, stream_eol_f) @[el2_ifu_mem_ctl.scala 739:151]
node _T_3907 = eq(_T_3906, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:106]
node _T_3908 = and(_T_3904, _T_3907) @[el2_ifu_mem_ctl.scala 739:104]
node _T_3909 = or(_T_3903, _T_3908) @[el2_ifu_mem_ctl.scala 739:77]
node _T_3910 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 739:191]
node _T_3911 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:205]
node _T_3912 = and(_T_3910, _T_3911) @[el2_ifu_mem_ctl.scala 739:203]
node _T_3913 = eq(_T_3912, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:172]
node _T_3914 = and(_T_3909, _T_3913) @[el2_ifu_mem_ctl.scala 739:170]
node _T_3915 = eq(_T_3914, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:44]
node _T_3916 = and(write_ic_16_bytes, _T_3915) @[el2_ifu_mem_ctl.scala 739:42]
io.ic_write_stall <= _T_3916 @[el2_ifu_mem_ctl.scala 739:21]
reg _T_3917 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 740:53]
_T_3917 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 740:53]
reset_all_tags <= _T_3917 @[el2_ifu_mem_ctl.scala 740:18]
node _T_3918 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:18]
node _T_3919 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 741:62]
node _T_3920 = eq(_T_3919, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:48]
node _T_3921 = and(_T_3918, _T_3920) @[el2_ifu_mem_ctl.scala 741:46]
node _T_3922 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:79]
node ic_valid = and(_T_3921, _T_3922) @[el2_ifu_mem_ctl.scala 741:77]
node _T_3923 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 742:59]
node _T_3924 = and(_T_3923, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 742:81]
node _T_3925 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 742:122]
node _T_3926 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 743:23]
node ifu_status_wr_addr_w_debug = mux(_T_3924, _T_3925, _T_3926) @[el2_ifu_mem_ctl.scala 742:39]
reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 744:61]
ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 744:61]
wire way_status_wr_en : UInt<1>
way_status_wr_en <= UInt<1>("h00")
node _T_3927 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 746:73]
node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3927) @[el2_ifu_mem_ctl.scala 746:51]
reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 747:59]
way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 747:59]
wire way_status_new : UInt<1>
way_status_new <= UInt<1>("h00")
node _T_3928 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 749:54]
node _T_3929 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 750:55]
node _T_3930 = bits(io.ic_debug_wr_data, 6, 4) @[el2_ifu_mem_ctl.scala 750:79]
node _T_3931 = mux(UInt<1>("h01"), _T_3929, _T_3930) @[el2_ifu_mem_ctl.scala 750:8]
node way_status_new_w_debug = mux(_T_3928, _T_3931, way_status_new) @[el2_ifu_mem_ctl.scala 749:35]
reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 751:57]
way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 751:57]
node _T_3932 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_0 = eq(_T_3932, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3933 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_1 = eq(_T_3933, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3934 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_2 = eq(_T_3934, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3935 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_3 = eq(_T_3935, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3936 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_4 = eq(_T_3936, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3937 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_5 = eq(_T_3937, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3938 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_6 = eq(_T_3938, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3939 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_7 = eq(_T_3939, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3940 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_8 = eq(_T_3940, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3941 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_9 = eq(_T_3941, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3942 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_10 = eq(_T_3942, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3943 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_11 = eq(_T_3943, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3944 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_12 = eq(_T_3944, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3945 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_13 = eq(_T_3945, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3946 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_14 = eq(_T_3946, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 752:122]
node _T_3947 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
node way_status_clken_15 = eq(_T_3947, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 752:122]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 412:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_2.io.en <= way_status_clken_0 @[el2_lib.scala 414:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 412:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_3.io.en <= way_status_clken_1 @[el2_lib.scala 414:16]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 412:22]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_4.io.en <= way_status_clken_2 @[el2_lib.scala 414:16]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 412:22]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_5.io.en <= way_status_clken_3 @[el2_lib.scala 414:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 412:22]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_6.io.en <= way_status_clken_4 @[el2_lib.scala 414:16]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 412:22]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_7.io.en <= way_status_clken_5 @[el2_lib.scala 414:16]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 412:22]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_8.io.en <= way_status_clken_6 @[el2_lib.scala 414:16]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 412:22]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_9.io.en <= way_status_clken_7 @[el2_lib.scala 414:16]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 412:22]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_10.io.en <= way_status_clken_8 @[el2_lib.scala 414:16]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 412:22]
rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_11.io.en <= way_status_clken_9 @[el2_lib.scala 414:16]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 412:22]
rvclkhdr_12.clock <= clock
rvclkhdr_12.reset <= reset
rvclkhdr_12.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_12.io.en <= way_status_clken_10 @[el2_lib.scala 414:16]
rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 412:22]
rvclkhdr_13.clock <= clock
rvclkhdr_13.reset <= reset
rvclkhdr_13.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_13.io.en <= way_status_clken_11 @[el2_lib.scala 414:16]
rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 412:22]
rvclkhdr_14.clock <= clock
rvclkhdr_14.reset <= reset
rvclkhdr_14.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_14.io.en <= way_status_clken_12 @[el2_lib.scala 414:16]
rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 412:22]
rvclkhdr_15.clock <= clock
rvclkhdr_15.reset <= reset
rvclkhdr_15.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_15.io.en <= way_status_clken_13 @[el2_lib.scala 414:16]
rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 412:22]
rvclkhdr_16.clock <= clock
rvclkhdr_16.reset <= reset
rvclkhdr_16.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_16.io.en <= way_status_clken_14 @[el2_lib.scala 414:16]
rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 412:22]
rvclkhdr_17.clock <= clock
rvclkhdr_17.reset <= reset
rvclkhdr_17.io.clk <= clock @[el2_lib.scala 413:17]
rvclkhdr_17.io.en <= way_status_clken_15 @[el2_lib.scala 414:16]
rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 754:28]
node _T_3948 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3949 = and(_T_3948, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3950 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3949 : @[Reg.scala 28:19]
_T_3950 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[0] <= _T_3950 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3951 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3952 = and(_T_3951, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3953 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3952 : @[Reg.scala 28:19]
_T_3953 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[1] <= _T_3953 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3954 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3955 = and(_T_3954, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3956 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3955 : @[Reg.scala 28:19]
_T_3956 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[2] <= _T_3956 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3957 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3958 = and(_T_3957, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3959 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3958 : @[Reg.scala 28:19]
_T_3959 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[3] <= _T_3959 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3960 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3961 = and(_T_3960, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3962 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3961 : @[Reg.scala 28:19]
_T_3962 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[4] <= _T_3962 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3963 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3964 = and(_T_3963, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3965 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3964 : @[Reg.scala 28:19]
_T_3965 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[5] <= _T_3965 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3966 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3967 = and(_T_3966, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3968 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3967 : @[Reg.scala 28:19]
_T_3968 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[6] <= _T_3968 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3969 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3970 = and(_T_3969, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3971 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3970 : @[Reg.scala 28:19]
_T_3971 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[7] <= _T_3971 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3972 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3973 = and(_T_3972, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3974 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3973 : @[Reg.scala 28:19]
_T_3974 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[8] <= _T_3974 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3975 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3976 = and(_T_3975, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3977 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3976 : @[Reg.scala 28:19]
_T_3977 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[9] <= _T_3977 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3978 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3979 = and(_T_3978, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3980 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3979 : @[Reg.scala 28:19]
_T_3980 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[10] <= _T_3980 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3981 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3982 = and(_T_3981, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3983 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3982 : @[Reg.scala 28:19]
_T_3983 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[11] <= _T_3983 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3984 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3985 = and(_T_3984, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3986 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3985 : @[Reg.scala 28:19]
_T_3986 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[12] <= _T_3986 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3987 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3988 = and(_T_3987, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3989 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3988 : @[Reg.scala 28:19]
_T_3989 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[13] <= _T_3989 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3990 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3991 = and(_T_3990, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3992 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3991 : @[Reg.scala 28:19]
_T_3992 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[14] <= _T_3992 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3993 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3994 = and(_T_3993, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3995 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3994 : @[Reg.scala 28:19]
_T_3995 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[15] <= _T_3995 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3996 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_3997 = and(_T_3996, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_3998 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_3997 : @[Reg.scala 28:19]
_T_3998 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[16] <= _T_3998 @[el2_ifu_mem_ctl.scala 756:25]
node _T_3999 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4000 = and(_T_3999, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4001 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4000 : @[Reg.scala 28:19]
_T_4001 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[17] <= _T_4001 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4002 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4003 = and(_T_4002, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4004 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4003 : @[Reg.scala 28:19]
_T_4004 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[18] <= _T_4004 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4005 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4006 = and(_T_4005, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4007 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4006 : @[Reg.scala 28:19]
_T_4007 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[19] <= _T_4007 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4008 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4009 = and(_T_4008, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4010 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4009 : @[Reg.scala 28:19]
_T_4010 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[20] <= _T_4010 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4011 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4012 = and(_T_4011, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4013 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4012 : @[Reg.scala 28:19]
_T_4013 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[21] <= _T_4013 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4014 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4015 = and(_T_4014, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4016 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4015 : @[Reg.scala 28:19]
_T_4016 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[22] <= _T_4016 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4017 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4018 = and(_T_4017, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4019 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4018 : @[Reg.scala 28:19]
_T_4019 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[23] <= _T_4019 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4020 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4022 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4021 : @[Reg.scala 28:19]
_T_4022 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[24] <= _T_4022 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4023 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4024 = and(_T_4023, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4025 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4024 : @[Reg.scala 28:19]
_T_4025 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[25] <= _T_4025 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4026 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4027 = and(_T_4026, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4028 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4027 : @[Reg.scala 28:19]
_T_4028 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[26] <= _T_4028 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4029 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4030 = and(_T_4029, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4031 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4030 : @[Reg.scala 28:19]
_T_4031 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[27] <= _T_4031 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4032 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4033 = and(_T_4032, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4034 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4033 : @[Reg.scala 28:19]
_T_4034 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[28] <= _T_4034 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4035 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4036 = and(_T_4035, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4037 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4036 : @[Reg.scala 28:19]
_T_4037 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[29] <= _T_4037 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4038 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4039 = and(_T_4038, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4040 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4039 : @[Reg.scala 28:19]
_T_4040 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[30] <= _T_4040 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4041 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4042 = and(_T_4041, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4043 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4042 : @[Reg.scala 28:19]
_T_4043 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[31] <= _T_4043 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4044 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4046 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4045 : @[Reg.scala 28:19]
_T_4046 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[32] <= _T_4046 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4047 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4048 = and(_T_4047, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4049 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4048 : @[Reg.scala 28:19]
_T_4049 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[33] <= _T_4049 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4050 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4051 = and(_T_4050, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4052 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4051 : @[Reg.scala 28:19]
_T_4052 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[34] <= _T_4052 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4053 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4054 = and(_T_4053, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4055 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4054 : @[Reg.scala 28:19]
_T_4055 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[35] <= _T_4055 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4056 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4057 = and(_T_4056, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4058 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4057 : @[Reg.scala 28:19]
_T_4058 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[36] <= _T_4058 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4059 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4060 = and(_T_4059, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4061 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4060 : @[Reg.scala 28:19]
_T_4061 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[37] <= _T_4061 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4062 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4063 = and(_T_4062, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4064 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4063 : @[Reg.scala 28:19]
_T_4064 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[38] <= _T_4064 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4065 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4066 = and(_T_4065, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4067 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4066 : @[Reg.scala 28:19]
_T_4067 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[39] <= _T_4067 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4068 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4069 = and(_T_4068, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4070 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4069 : @[Reg.scala 28:19]
_T_4070 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[40] <= _T_4070 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4071 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4072 = and(_T_4071, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4073 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4072 : @[Reg.scala 28:19]
_T_4073 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[41] <= _T_4073 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4074 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4075 = and(_T_4074, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4076 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4075 : @[Reg.scala 28:19]
_T_4076 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[42] <= _T_4076 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4077 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4078 = and(_T_4077, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4079 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4078 : @[Reg.scala 28:19]
_T_4079 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[43] <= _T_4079 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4080 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4082 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4081 : @[Reg.scala 28:19]
_T_4082 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[44] <= _T_4082 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4083 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4084 = and(_T_4083, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4085 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4084 : @[Reg.scala 28:19]
_T_4085 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[45] <= _T_4085 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4086 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4087 = and(_T_4086, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4088 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4087 : @[Reg.scala 28:19]
_T_4088 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[46] <= _T_4088 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4089 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4090 = and(_T_4089, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4091 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4090 : @[Reg.scala 28:19]
_T_4091 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[47] <= _T_4091 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4092 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4093 = and(_T_4092, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4094 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4093 : @[Reg.scala 28:19]
_T_4094 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[48] <= _T_4094 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4095 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4096 = and(_T_4095, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4097 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4096 : @[Reg.scala 28:19]
_T_4097 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[49] <= _T_4097 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4098 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4099 = and(_T_4098, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4100 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4099 : @[Reg.scala 28:19]
_T_4100 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[50] <= _T_4100 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4101 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4102 = and(_T_4101, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4103 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4102 : @[Reg.scala 28:19]
_T_4103 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[51] <= _T_4103 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4104 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4106 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4105 : @[Reg.scala 28:19]
_T_4106 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[52] <= _T_4106 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4107 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4108 = and(_T_4107, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4109 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4108 : @[Reg.scala 28:19]
_T_4109 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[53] <= _T_4109 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4110 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4111 = and(_T_4110, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4112 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4111 : @[Reg.scala 28:19]
_T_4112 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[54] <= _T_4112 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4113 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4114 = and(_T_4113, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4115 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4114 : @[Reg.scala 28:19]
_T_4115 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[55] <= _T_4115 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4116 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4117 = and(_T_4116, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4118 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4117 : @[Reg.scala 28:19]
_T_4118 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[56] <= _T_4118 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4119 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4120 = and(_T_4119, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4121 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4120 : @[Reg.scala 28:19]
_T_4121 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[57] <= _T_4121 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4122 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4123 = and(_T_4122, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4124 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4123 : @[Reg.scala 28:19]
_T_4124 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[58] <= _T_4124 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4125 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4126 = and(_T_4125, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4127 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4126 : @[Reg.scala 28:19]
_T_4127 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[59] <= _T_4127 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4128 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4129 = and(_T_4128, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4130 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4129 : @[Reg.scala 28:19]
_T_4130 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[60] <= _T_4130 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4131 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4132 = and(_T_4131, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4133 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4132 : @[Reg.scala 28:19]
_T_4133 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[61] <= _T_4133 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4134 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4135 = and(_T_4134, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4136 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4135 : @[Reg.scala 28:19]
_T_4136 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[62] <= _T_4136 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4137 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4138 = and(_T_4137, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4139 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4138 : @[Reg.scala 28:19]
_T_4139 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[63] <= _T_4139 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4140 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4142 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4141 : @[Reg.scala 28:19]
_T_4142 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[64] <= _T_4142 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4143 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4144 = and(_T_4143, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4145 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4144 : @[Reg.scala 28:19]
_T_4145 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[65] <= _T_4145 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4146 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4147 = and(_T_4146, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4148 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4147 : @[Reg.scala 28:19]
_T_4148 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[66] <= _T_4148 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4149 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4150 = and(_T_4149, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4151 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4150 : @[Reg.scala 28:19]
_T_4151 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[67] <= _T_4151 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4152 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4153 = and(_T_4152, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4154 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4153 : @[Reg.scala 28:19]
_T_4154 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[68] <= _T_4154 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4155 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4156 = and(_T_4155, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4157 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4156 : @[Reg.scala 28:19]
_T_4157 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[69] <= _T_4157 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4158 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4159 = and(_T_4158, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4160 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4159 : @[Reg.scala 28:19]
_T_4160 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[70] <= _T_4160 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4161 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4162 = and(_T_4161, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4163 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4162 : @[Reg.scala 28:19]
_T_4163 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[71] <= _T_4163 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4164 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4166 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4165 : @[Reg.scala 28:19]
_T_4166 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[72] <= _T_4166 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4167 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4168 = and(_T_4167, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4169 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4168 : @[Reg.scala 28:19]
_T_4169 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[73] <= _T_4169 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4170 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4171 = and(_T_4170, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4172 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4171 : @[Reg.scala 28:19]
_T_4172 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[74] <= _T_4172 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4173 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4174 = and(_T_4173, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4175 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4174 : @[Reg.scala 28:19]
_T_4175 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[75] <= _T_4175 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4176 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4177 = and(_T_4176, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4178 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4177 : @[Reg.scala 28:19]
_T_4178 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[76] <= _T_4178 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4179 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4180 = and(_T_4179, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4181 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4180 : @[Reg.scala 28:19]
_T_4181 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[77] <= _T_4181 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4182 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4183 = and(_T_4182, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4184 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4183 : @[Reg.scala 28:19]
_T_4184 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[78] <= _T_4184 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4185 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4186 = and(_T_4185, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4187 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4186 : @[Reg.scala 28:19]
_T_4187 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[79] <= _T_4187 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4188 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4189 = and(_T_4188, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4190 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4189 : @[Reg.scala 28:19]
_T_4190 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[80] <= _T_4190 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4191 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4192 = and(_T_4191, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4193 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4192 : @[Reg.scala 28:19]
_T_4193 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[81] <= _T_4193 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4194 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4195 = and(_T_4194, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4196 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4195 : @[Reg.scala 28:19]
_T_4196 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[82] <= _T_4196 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4197 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4198 = and(_T_4197, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4199 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4198 : @[Reg.scala 28:19]
_T_4199 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[83] <= _T_4199 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4200 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4202 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4201 : @[Reg.scala 28:19]
_T_4202 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[84] <= _T_4202 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4203 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4204 = and(_T_4203, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4205 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4204 : @[Reg.scala 28:19]
_T_4205 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[85] <= _T_4205 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4206 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4207 = and(_T_4206, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4208 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4207 : @[Reg.scala 28:19]
_T_4208 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[86] <= _T_4208 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4209 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4210 = and(_T_4209, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4211 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4210 : @[Reg.scala 28:19]
_T_4211 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[87] <= _T_4211 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4212 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4213 = and(_T_4212, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4214 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4213 : @[Reg.scala 28:19]
_T_4214 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[88] <= _T_4214 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4215 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4216 = and(_T_4215, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4217 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4216 : @[Reg.scala 28:19]
_T_4217 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[89] <= _T_4217 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4218 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4219 = and(_T_4218, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4220 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4219 : @[Reg.scala 28:19]
_T_4220 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[90] <= _T_4220 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4221 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4222 = and(_T_4221, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4223 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4222 : @[Reg.scala 28:19]
_T_4223 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[91] <= _T_4223 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4224 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4226 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4225 : @[Reg.scala 28:19]
_T_4226 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[92] <= _T_4226 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4227 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4228 = and(_T_4227, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4229 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4228 : @[Reg.scala 28:19]
_T_4229 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[93] <= _T_4229 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4230 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4231 = and(_T_4230, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4232 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4231 : @[Reg.scala 28:19]
_T_4232 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[94] <= _T_4232 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4233 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4234 = and(_T_4233, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4235 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4234 : @[Reg.scala 28:19]
_T_4235 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[95] <= _T_4235 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4236 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4237 = and(_T_4236, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4238 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4237 : @[Reg.scala 28:19]
_T_4238 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[96] <= _T_4238 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4239 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4240 = and(_T_4239, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4241 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4240 : @[Reg.scala 28:19]
_T_4241 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[97] <= _T_4241 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4242 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4243 = and(_T_4242, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4244 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4243 : @[Reg.scala 28:19]
_T_4244 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[98] <= _T_4244 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4245 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4246 = and(_T_4245, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4247 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4246 : @[Reg.scala 28:19]
_T_4247 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[99] <= _T_4247 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4248 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4249 = and(_T_4248, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4250 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4249 : @[Reg.scala 28:19]
_T_4250 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[100] <= _T_4250 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4251 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4252 = and(_T_4251, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4253 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4252 : @[Reg.scala 28:19]
_T_4253 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[101] <= _T_4253 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4254 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4255 = and(_T_4254, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4256 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4255 : @[Reg.scala 28:19]
_T_4256 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[102] <= _T_4256 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4257 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4258 = and(_T_4257, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4259 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4258 : @[Reg.scala 28:19]
_T_4259 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[103] <= _T_4259 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4260 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4262 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4261 : @[Reg.scala 28:19]
_T_4262 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[104] <= _T_4262 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4263 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4264 = and(_T_4263, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4265 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4264 : @[Reg.scala 28:19]
_T_4265 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[105] <= _T_4265 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4266 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4267 = and(_T_4266, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4268 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4267 : @[Reg.scala 28:19]
_T_4268 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[106] <= _T_4268 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4269 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4270 = and(_T_4269, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4271 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4270 : @[Reg.scala 28:19]
_T_4271 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[107] <= _T_4271 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4272 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4273 = and(_T_4272, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4274 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4273 : @[Reg.scala 28:19]
_T_4274 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[108] <= _T_4274 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4275 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4276 = and(_T_4275, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4277 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4276 : @[Reg.scala 28:19]
_T_4277 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[109] <= _T_4277 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4278 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4279 = and(_T_4278, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4280 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4279 : @[Reg.scala 28:19]
_T_4280 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[110] <= _T_4280 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4281 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4282 = and(_T_4281, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4283 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4282 : @[Reg.scala 28:19]
_T_4283 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[111] <= _T_4283 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4284 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4286 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4285 : @[Reg.scala 28:19]
_T_4286 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[112] <= _T_4286 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4287 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4288 = and(_T_4287, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4289 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4288 : @[Reg.scala 28:19]
_T_4289 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[113] <= _T_4289 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4290 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4291 = and(_T_4290, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4292 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4291 : @[Reg.scala 28:19]
_T_4292 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[114] <= _T_4292 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4293 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4294 = and(_T_4293, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4295 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4294 : @[Reg.scala 28:19]
_T_4295 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[115] <= _T_4295 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4296 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4297 = and(_T_4296, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4298 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4297 : @[Reg.scala 28:19]
_T_4298 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[116] <= _T_4298 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4299 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4300 = and(_T_4299, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4301 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4300 : @[Reg.scala 28:19]
_T_4301 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[117] <= _T_4301 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4302 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4303 = and(_T_4302, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4304 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4303 : @[Reg.scala 28:19]
_T_4304 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[118] <= _T_4304 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4305 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4306 = and(_T_4305, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4307 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4306 : @[Reg.scala 28:19]
_T_4307 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[119] <= _T_4307 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4308 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4309 = and(_T_4308, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4310 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4309 : @[Reg.scala 28:19]
_T_4310 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[120] <= _T_4310 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4311 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4312 = and(_T_4311, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4313 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4312 : @[Reg.scala 28:19]
_T_4313 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[121] <= _T_4313 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4314 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4315 = and(_T_4314, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4316 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4315 : @[Reg.scala 28:19]
_T_4316 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[122] <= _T_4316 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4317 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4318 = and(_T_4317, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4319 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4318 : @[Reg.scala 28:19]
_T_4319 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[123] <= _T_4319 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4320 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4322 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4321 : @[Reg.scala 28:19]
_T_4322 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[124] <= _T_4322 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4323 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4324 = and(_T_4323, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4325 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4324 : @[Reg.scala 28:19]
_T_4325 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[125] <= _T_4325 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4326 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4327 = and(_T_4326, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4328 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4327 : @[Reg.scala 28:19]
_T_4328 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[126] <= _T_4328 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4329 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
node _T_4330 = and(_T_4329, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
reg _T_4331 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_4330 : @[Reg.scala 28:19]
_T_4331 <= way_status_new_ff @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
way_status_out[127] <= _T_4331 @[el2_ifu_mem_ctl.scala 756:25]
node _T_4332 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4333 = bits(_T_4332, 0, 0) @[Bitwise.scala 72:15]
node _T_4334 = mux(_T_4333, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4335 = and(_T_4334, way_status_out[0]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4336 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4337 = bits(_T_4336, 0, 0) @[Bitwise.scala 72:15]
node _T_4338 = mux(_T_4337, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4339 = and(_T_4338, way_status_out[1]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4340 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4341 = bits(_T_4340, 0, 0) @[Bitwise.scala 72:15]
node _T_4342 = mux(_T_4341, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4343 = and(_T_4342, way_status_out[2]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4344 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4345 = bits(_T_4344, 0, 0) @[Bitwise.scala 72:15]
node _T_4346 = mux(_T_4345, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4347 = and(_T_4346, way_status_out[3]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4348 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4349 = bits(_T_4348, 0, 0) @[Bitwise.scala 72:15]
node _T_4350 = mux(_T_4349, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4351 = and(_T_4350, way_status_out[4]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4352 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4353 = bits(_T_4352, 0, 0) @[Bitwise.scala 72:15]
node _T_4354 = mux(_T_4353, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4355 = and(_T_4354, way_status_out[5]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4356 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4357 = bits(_T_4356, 0, 0) @[Bitwise.scala 72:15]
node _T_4358 = mux(_T_4357, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4359 = and(_T_4358, way_status_out[6]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4360 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4361 = bits(_T_4360, 0, 0) @[Bitwise.scala 72:15]
node _T_4362 = mux(_T_4361, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4363 = and(_T_4362, way_status_out[7]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4364 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4365 = bits(_T_4364, 0, 0) @[Bitwise.scala 72:15]
node _T_4366 = mux(_T_4365, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4367 = and(_T_4366, way_status_out[8]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4368 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4369 = bits(_T_4368, 0, 0) @[Bitwise.scala 72:15]
node _T_4370 = mux(_T_4369, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4371 = and(_T_4370, way_status_out[9]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4372 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4373 = bits(_T_4372, 0, 0) @[Bitwise.scala 72:15]
node _T_4374 = mux(_T_4373, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4375 = and(_T_4374, way_status_out[10]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4376 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4377 = bits(_T_4376, 0, 0) @[Bitwise.scala 72:15]
node _T_4378 = mux(_T_4377, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4379 = and(_T_4378, way_status_out[11]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4380 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4381 = bits(_T_4380, 0, 0) @[Bitwise.scala 72:15]
node _T_4382 = mux(_T_4381, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4383 = and(_T_4382, way_status_out[12]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4384 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4385 = bits(_T_4384, 0, 0) @[Bitwise.scala 72:15]
node _T_4386 = mux(_T_4385, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4387 = and(_T_4386, way_status_out[13]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4388 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4389 = bits(_T_4388, 0, 0) @[Bitwise.scala 72:15]
node _T_4390 = mux(_T_4389, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4391 = and(_T_4390, way_status_out[14]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4392 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4393 = bits(_T_4392, 0, 0) @[Bitwise.scala 72:15]
node _T_4394 = mux(_T_4393, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4395 = and(_T_4394, way_status_out[15]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4396 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4397 = bits(_T_4396, 0, 0) @[Bitwise.scala 72:15]
node _T_4398 = mux(_T_4397, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4399 = and(_T_4398, way_status_out[16]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4400 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4401 = bits(_T_4400, 0, 0) @[Bitwise.scala 72:15]
node _T_4402 = mux(_T_4401, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4403 = and(_T_4402, way_status_out[17]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4404 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4405 = bits(_T_4404, 0, 0) @[Bitwise.scala 72:15]
node _T_4406 = mux(_T_4405, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4407 = and(_T_4406, way_status_out[18]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4408 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4409 = bits(_T_4408, 0, 0) @[Bitwise.scala 72:15]
node _T_4410 = mux(_T_4409, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4411 = and(_T_4410, way_status_out[19]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4412 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4413 = bits(_T_4412, 0, 0) @[Bitwise.scala 72:15]
node _T_4414 = mux(_T_4413, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4415 = and(_T_4414, way_status_out[20]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4416 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4417 = bits(_T_4416, 0, 0) @[Bitwise.scala 72:15]
node _T_4418 = mux(_T_4417, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4419 = and(_T_4418, way_status_out[21]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4420 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4421 = bits(_T_4420, 0, 0) @[Bitwise.scala 72:15]
node _T_4422 = mux(_T_4421, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4423 = and(_T_4422, way_status_out[22]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4424 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4425 = bits(_T_4424, 0, 0) @[Bitwise.scala 72:15]
node _T_4426 = mux(_T_4425, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4427 = and(_T_4426, way_status_out[23]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4428 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4429 = bits(_T_4428, 0, 0) @[Bitwise.scala 72:15]
node _T_4430 = mux(_T_4429, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4431 = and(_T_4430, way_status_out[24]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4432 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4433 = bits(_T_4432, 0, 0) @[Bitwise.scala 72:15]
node _T_4434 = mux(_T_4433, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4435 = and(_T_4434, way_status_out[25]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4436 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4437 = bits(_T_4436, 0, 0) @[Bitwise.scala 72:15]
node _T_4438 = mux(_T_4437, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4439 = and(_T_4438, way_status_out[26]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4440 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4441 = bits(_T_4440, 0, 0) @[Bitwise.scala 72:15]
node _T_4442 = mux(_T_4441, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4443 = and(_T_4442, way_status_out[27]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4444 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4445 = bits(_T_4444, 0, 0) @[Bitwise.scala 72:15]
node _T_4446 = mux(_T_4445, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4447 = and(_T_4446, way_status_out[28]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4448 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4449 = bits(_T_4448, 0, 0) @[Bitwise.scala 72:15]
node _T_4450 = mux(_T_4449, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4451 = and(_T_4450, way_status_out[29]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4452 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4453 = bits(_T_4452, 0, 0) @[Bitwise.scala 72:15]
node _T_4454 = mux(_T_4453, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4455 = and(_T_4454, way_status_out[30]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4456 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4457 = bits(_T_4456, 0, 0) @[Bitwise.scala 72:15]
node _T_4458 = mux(_T_4457, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4459 = and(_T_4458, way_status_out[31]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4460 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4461 = bits(_T_4460, 0, 0) @[Bitwise.scala 72:15]
node _T_4462 = mux(_T_4461, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4463 = and(_T_4462, way_status_out[32]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4464 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4465 = bits(_T_4464, 0, 0) @[Bitwise.scala 72:15]
node _T_4466 = mux(_T_4465, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4467 = and(_T_4466, way_status_out[33]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4468 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4469 = bits(_T_4468, 0, 0) @[Bitwise.scala 72:15]
node _T_4470 = mux(_T_4469, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4471 = and(_T_4470, way_status_out[34]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4472 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4473 = bits(_T_4472, 0, 0) @[Bitwise.scala 72:15]
node _T_4474 = mux(_T_4473, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4475 = and(_T_4474, way_status_out[35]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4476 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4477 = bits(_T_4476, 0, 0) @[Bitwise.scala 72:15]
node _T_4478 = mux(_T_4477, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4479 = and(_T_4478, way_status_out[36]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4480 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4481 = bits(_T_4480, 0, 0) @[Bitwise.scala 72:15]
node _T_4482 = mux(_T_4481, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4483 = and(_T_4482, way_status_out[37]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4484 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4485 = bits(_T_4484, 0, 0) @[Bitwise.scala 72:15]
node _T_4486 = mux(_T_4485, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4487 = and(_T_4486, way_status_out[38]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4488 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4489 = bits(_T_4488, 0, 0) @[Bitwise.scala 72:15]
node _T_4490 = mux(_T_4489, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4491 = and(_T_4490, way_status_out[39]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4492 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4493 = bits(_T_4492, 0, 0) @[Bitwise.scala 72:15]
node _T_4494 = mux(_T_4493, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4495 = and(_T_4494, way_status_out[40]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4496 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4497 = bits(_T_4496, 0, 0) @[Bitwise.scala 72:15]
node _T_4498 = mux(_T_4497, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4499 = and(_T_4498, way_status_out[41]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4500 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4501 = bits(_T_4500, 0, 0) @[Bitwise.scala 72:15]
node _T_4502 = mux(_T_4501, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4503 = and(_T_4502, way_status_out[42]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4504 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4505 = bits(_T_4504, 0, 0) @[Bitwise.scala 72:15]
node _T_4506 = mux(_T_4505, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4507 = and(_T_4506, way_status_out[43]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4508 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4509 = bits(_T_4508, 0, 0) @[Bitwise.scala 72:15]
node _T_4510 = mux(_T_4509, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4511 = and(_T_4510, way_status_out[44]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4512 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4513 = bits(_T_4512, 0, 0) @[Bitwise.scala 72:15]
node _T_4514 = mux(_T_4513, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4515 = and(_T_4514, way_status_out[45]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4516 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4517 = bits(_T_4516, 0, 0) @[Bitwise.scala 72:15]
node _T_4518 = mux(_T_4517, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4519 = and(_T_4518, way_status_out[46]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4521 = bits(_T_4520, 0, 0) @[Bitwise.scala 72:15]
node _T_4522 = mux(_T_4521, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4523 = and(_T_4522, way_status_out[47]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4524 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4525 = bits(_T_4524, 0, 0) @[Bitwise.scala 72:15]
node _T_4526 = mux(_T_4525, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4527 = and(_T_4526, way_status_out[48]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4528 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4529 = bits(_T_4528, 0, 0) @[Bitwise.scala 72:15]
node _T_4530 = mux(_T_4529, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4531 = and(_T_4530, way_status_out[49]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4532 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4533 = bits(_T_4532, 0, 0) @[Bitwise.scala 72:15]
node _T_4534 = mux(_T_4533, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4535 = and(_T_4534, way_status_out[50]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4536 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4537 = bits(_T_4536, 0, 0) @[Bitwise.scala 72:15]
node _T_4538 = mux(_T_4537, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4539 = and(_T_4538, way_status_out[51]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4540 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4541 = bits(_T_4540, 0, 0) @[Bitwise.scala 72:15]
node _T_4542 = mux(_T_4541, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4543 = and(_T_4542, way_status_out[52]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4544 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4545 = bits(_T_4544, 0, 0) @[Bitwise.scala 72:15]
node _T_4546 = mux(_T_4545, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4547 = and(_T_4546, way_status_out[53]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4548 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4549 = bits(_T_4548, 0, 0) @[Bitwise.scala 72:15]
node _T_4550 = mux(_T_4549, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4551 = and(_T_4550, way_status_out[54]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4552 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4553 = bits(_T_4552, 0, 0) @[Bitwise.scala 72:15]
node _T_4554 = mux(_T_4553, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4555 = and(_T_4554, way_status_out[55]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4556 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4557 = bits(_T_4556, 0, 0) @[Bitwise.scala 72:15]
node _T_4558 = mux(_T_4557, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4559 = and(_T_4558, way_status_out[56]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4560 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4561 = bits(_T_4560, 0, 0) @[Bitwise.scala 72:15]
node _T_4562 = mux(_T_4561, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4563 = and(_T_4562, way_status_out[57]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4564 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4565 = bits(_T_4564, 0, 0) @[Bitwise.scala 72:15]
node _T_4566 = mux(_T_4565, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4567 = and(_T_4566, way_status_out[58]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4568 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4569 = bits(_T_4568, 0, 0) @[Bitwise.scala 72:15]
node _T_4570 = mux(_T_4569, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4571 = and(_T_4570, way_status_out[59]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4572 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4573 = bits(_T_4572, 0, 0) @[Bitwise.scala 72:15]
node _T_4574 = mux(_T_4573, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4575 = and(_T_4574, way_status_out[60]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4576 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4577 = bits(_T_4576, 0, 0) @[Bitwise.scala 72:15]
node _T_4578 = mux(_T_4577, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4579 = and(_T_4578, way_status_out[61]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4580 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4581 = bits(_T_4580, 0, 0) @[Bitwise.scala 72:15]
node _T_4582 = mux(_T_4581, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4583 = and(_T_4582, way_status_out[62]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4584 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4585 = bits(_T_4584, 0, 0) @[Bitwise.scala 72:15]
node _T_4586 = mux(_T_4585, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4587 = and(_T_4586, way_status_out[63]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4588 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4589 = bits(_T_4588, 0, 0) @[Bitwise.scala 72:15]
node _T_4590 = mux(_T_4589, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4591 = and(_T_4590, way_status_out[64]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4592 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4593 = bits(_T_4592, 0, 0) @[Bitwise.scala 72:15]
node _T_4594 = mux(_T_4593, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4595 = and(_T_4594, way_status_out[65]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4596 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4597 = bits(_T_4596, 0, 0) @[Bitwise.scala 72:15]
node _T_4598 = mux(_T_4597, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4599 = and(_T_4598, way_status_out[66]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4601 = bits(_T_4600, 0, 0) @[Bitwise.scala 72:15]
node _T_4602 = mux(_T_4601, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4603 = and(_T_4602, way_status_out[67]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4604 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4605 = bits(_T_4604, 0, 0) @[Bitwise.scala 72:15]
node _T_4606 = mux(_T_4605, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4607 = and(_T_4606, way_status_out[68]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4608 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4609 = bits(_T_4608, 0, 0) @[Bitwise.scala 72:15]
node _T_4610 = mux(_T_4609, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4611 = and(_T_4610, way_status_out[69]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4612 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4613 = bits(_T_4612, 0, 0) @[Bitwise.scala 72:15]
node _T_4614 = mux(_T_4613, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4615 = and(_T_4614, way_status_out[70]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4616 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4617 = bits(_T_4616, 0, 0) @[Bitwise.scala 72:15]
node _T_4618 = mux(_T_4617, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4619 = and(_T_4618, way_status_out[71]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4621 = bits(_T_4620, 0, 0) @[Bitwise.scala 72:15]
node _T_4622 = mux(_T_4621, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4623 = and(_T_4622, way_status_out[72]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4624 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4625 = bits(_T_4624, 0, 0) @[Bitwise.scala 72:15]
node _T_4626 = mux(_T_4625, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4627 = and(_T_4626, way_status_out[73]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4628 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4629 = bits(_T_4628, 0, 0) @[Bitwise.scala 72:15]
node _T_4630 = mux(_T_4629, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4631 = and(_T_4630, way_status_out[74]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4632 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4633 = bits(_T_4632, 0, 0) @[Bitwise.scala 72:15]
node _T_4634 = mux(_T_4633, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4635 = and(_T_4634, way_status_out[75]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4636 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4637 = bits(_T_4636, 0, 0) @[Bitwise.scala 72:15]
node _T_4638 = mux(_T_4637, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4639 = and(_T_4638, way_status_out[76]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4640 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4641 = bits(_T_4640, 0, 0) @[Bitwise.scala 72:15]
node _T_4642 = mux(_T_4641, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4643 = and(_T_4642, way_status_out[77]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4644 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4645 = bits(_T_4644, 0, 0) @[Bitwise.scala 72:15]
node _T_4646 = mux(_T_4645, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4647 = and(_T_4646, way_status_out[78]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4648 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4649 = bits(_T_4648, 0, 0) @[Bitwise.scala 72:15]
node _T_4650 = mux(_T_4649, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4651 = and(_T_4650, way_status_out[79]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4652 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4653 = bits(_T_4652, 0, 0) @[Bitwise.scala 72:15]
node _T_4654 = mux(_T_4653, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4655 = and(_T_4654, way_status_out[80]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4656 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4657 = bits(_T_4656, 0, 0) @[Bitwise.scala 72:15]
node _T_4658 = mux(_T_4657, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4659 = and(_T_4658, way_status_out[81]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4660 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4661 = bits(_T_4660, 0, 0) @[Bitwise.scala 72:15]
node _T_4662 = mux(_T_4661, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4663 = and(_T_4662, way_status_out[82]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4664 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4665 = bits(_T_4664, 0, 0) @[Bitwise.scala 72:15]
node _T_4666 = mux(_T_4665, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4667 = and(_T_4666, way_status_out[83]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4668 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4669 = bits(_T_4668, 0, 0) @[Bitwise.scala 72:15]
node _T_4670 = mux(_T_4669, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4671 = and(_T_4670, way_status_out[84]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4673 = bits(_T_4672, 0, 0) @[Bitwise.scala 72:15]
node _T_4674 = mux(_T_4673, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4675 = and(_T_4674, way_status_out[85]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4677 = bits(_T_4676, 0, 0) @[Bitwise.scala 72:15]
node _T_4678 = mux(_T_4677, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4679 = and(_T_4678, way_status_out[86]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4681 = bits(_T_4680, 0, 0) @[Bitwise.scala 72:15]
node _T_4682 = mux(_T_4681, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4683 = and(_T_4682, way_status_out[87]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4685 = bits(_T_4684, 0, 0) @[Bitwise.scala 72:15]
node _T_4686 = mux(_T_4685, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4687 = and(_T_4686, way_status_out[88]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4689 = bits(_T_4688, 0, 0) @[Bitwise.scala 72:15]
node _T_4690 = mux(_T_4689, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4691 = and(_T_4690, way_status_out[89]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4693 = bits(_T_4692, 0, 0) @[Bitwise.scala 72:15]
node _T_4694 = mux(_T_4693, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4695 = and(_T_4694, way_status_out[90]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4697 = bits(_T_4696, 0, 0) @[Bitwise.scala 72:15]
node _T_4698 = mux(_T_4697, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4699 = and(_T_4698, way_status_out[91]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4701 = bits(_T_4700, 0, 0) @[Bitwise.scala 72:15]
node _T_4702 = mux(_T_4701, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4703 = and(_T_4702, way_status_out[92]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4705 = bits(_T_4704, 0, 0) @[Bitwise.scala 72:15]
node _T_4706 = mux(_T_4705, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4707 = and(_T_4706, way_status_out[93]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4709 = bits(_T_4708, 0, 0) @[Bitwise.scala 72:15]
node _T_4710 = mux(_T_4709, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4711 = and(_T_4710, way_status_out[94]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4713 = bits(_T_4712, 0, 0) @[Bitwise.scala 72:15]
node _T_4714 = mux(_T_4713, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4715 = and(_T_4714, way_status_out[95]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4717 = bits(_T_4716, 0, 0) @[Bitwise.scala 72:15]
node _T_4718 = mux(_T_4717, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4719 = and(_T_4718, way_status_out[96]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4721 = bits(_T_4720, 0, 0) @[Bitwise.scala 72:15]
node _T_4722 = mux(_T_4721, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4723 = and(_T_4722, way_status_out[97]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4725 = bits(_T_4724, 0, 0) @[Bitwise.scala 72:15]
node _T_4726 = mux(_T_4725, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4727 = and(_T_4726, way_status_out[98]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4729 = bits(_T_4728, 0, 0) @[Bitwise.scala 72:15]
node _T_4730 = mux(_T_4729, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4731 = and(_T_4730, way_status_out[99]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4733 = bits(_T_4732, 0, 0) @[Bitwise.scala 72:15]
node _T_4734 = mux(_T_4733, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4735 = and(_T_4734, way_status_out[100]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4737 = bits(_T_4736, 0, 0) @[Bitwise.scala 72:15]
node _T_4738 = mux(_T_4737, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4739 = and(_T_4738, way_status_out[101]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4741 = bits(_T_4740, 0, 0) @[Bitwise.scala 72:15]
node _T_4742 = mux(_T_4741, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4743 = and(_T_4742, way_status_out[102]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4745 = bits(_T_4744, 0, 0) @[Bitwise.scala 72:15]
node _T_4746 = mux(_T_4745, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4747 = and(_T_4746, way_status_out[103]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4749 = bits(_T_4748, 0, 0) @[Bitwise.scala 72:15]
node _T_4750 = mux(_T_4749, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4751 = and(_T_4750, way_status_out[104]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4753 = bits(_T_4752, 0, 0) @[Bitwise.scala 72:15]
node _T_4754 = mux(_T_4753, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4755 = and(_T_4754, way_status_out[105]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4757 = bits(_T_4756, 0, 0) @[Bitwise.scala 72:15]
node _T_4758 = mux(_T_4757, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4759 = and(_T_4758, way_status_out[106]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4761 = bits(_T_4760, 0, 0) @[Bitwise.scala 72:15]
node _T_4762 = mux(_T_4761, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4763 = and(_T_4762, way_status_out[107]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4765 = bits(_T_4764, 0, 0) @[Bitwise.scala 72:15]
node _T_4766 = mux(_T_4765, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4767 = and(_T_4766, way_status_out[108]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4769 = bits(_T_4768, 0, 0) @[Bitwise.scala 72:15]
node _T_4770 = mux(_T_4769, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4771 = and(_T_4770, way_status_out[109]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4773 = bits(_T_4772, 0, 0) @[Bitwise.scala 72:15]
node _T_4774 = mux(_T_4773, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4775 = and(_T_4774, way_status_out[110]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4777 = bits(_T_4776, 0, 0) @[Bitwise.scala 72:15]
node _T_4778 = mux(_T_4777, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4779 = and(_T_4778, way_status_out[111]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4781 = bits(_T_4780, 0, 0) @[Bitwise.scala 72:15]
node _T_4782 = mux(_T_4781, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4783 = and(_T_4782, way_status_out[112]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4785 = bits(_T_4784, 0, 0) @[Bitwise.scala 72:15]
node _T_4786 = mux(_T_4785, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4787 = and(_T_4786, way_status_out[113]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4789 = bits(_T_4788, 0, 0) @[Bitwise.scala 72:15]
node _T_4790 = mux(_T_4789, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4791 = and(_T_4790, way_status_out[114]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4793 = bits(_T_4792, 0, 0) @[Bitwise.scala 72:15]
node _T_4794 = mux(_T_4793, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4795 = and(_T_4794, way_status_out[115]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4797 = bits(_T_4796, 0, 0) @[Bitwise.scala 72:15]
node _T_4798 = mux(_T_4797, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4799 = and(_T_4798, way_status_out[116]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4801 = bits(_T_4800, 0, 0) @[Bitwise.scala 72:15]
node _T_4802 = mux(_T_4801, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4803 = and(_T_4802, way_status_out[117]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4804 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4805 = bits(_T_4804, 0, 0) @[Bitwise.scala 72:15]
node _T_4806 = mux(_T_4805, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4807 = and(_T_4806, way_status_out[118]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4808 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4809 = bits(_T_4808, 0, 0) @[Bitwise.scala 72:15]
node _T_4810 = mux(_T_4809, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4811 = and(_T_4810, way_status_out[119]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4812 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4813 = bits(_T_4812, 0, 0) @[Bitwise.scala 72:15]
node _T_4814 = mux(_T_4813, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4815 = and(_T_4814, way_status_out[120]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4817 = bits(_T_4816, 0, 0) @[Bitwise.scala 72:15]
node _T_4818 = mux(_T_4817, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4819 = and(_T_4818, way_status_out[121]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4820 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4821 = bits(_T_4820, 0, 0) @[Bitwise.scala 72:15]
node _T_4822 = mux(_T_4821, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4823 = and(_T_4822, way_status_out[122]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4825 = bits(_T_4824, 0, 0) @[Bitwise.scala 72:15]
node _T_4826 = mux(_T_4825, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4827 = and(_T_4826, way_status_out[123]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4829 = bits(_T_4828, 0, 0) @[Bitwise.scala 72:15]
node _T_4830 = mux(_T_4829, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4831 = and(_T_4830, way_status_out[124]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4833 = bits(_T_4832, 0, 0) @[Bitwise.scala 72:15]
node _T_4834 = mux(_T_4833, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4835 = and(_T_4834, way_status_out[125]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4837 = bits(_T_4836, 0, 0) @[Bitwise.scala 72:15]
node _T_4838 = mux(_T_4837, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4839 = and(_T_4838, way_status_out[126]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 757:114]
node _T_4841 = bits(_T_4840, 0, 0) @[Bitwise.scala 72:15]
node _T_4842 = mux(_T_4841, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_4843 = and(_T_4842, way_status_out[127]) @[el2_ifu_mem_ctl.scala 757:122]
node _T_4844 = cat(_T_4843, _T_4839) @[Cat.scala 29:58]
node _T_4845 = cat(_T_4844, _T_4835) @[Cat.scala 29:58]
node _T_4846 = cat(_T_4845, _T_4831) @[Cat.scala 29:58]
node _T_4847 = cat(_T_4846, _T_4827) @[Cat.scala 29:58]
node _T_4848 = cat(_T_4847, _T_4823) @[Cat.scala 29:58]
node _T_4849 = cat(_T_4848, _T_4819) @[Cat.scala 29:58]
node _T_4850 = cat(_T_4849, _T_4815) @[Cat.scala 29:58]
node _T_4851 = cat(_T_4850, _T_4811) @[Cat.scala 29:58]
node _T_4852 = cat(_T_4851, _T_4807) @[Cat.scala 29:58]
node _T_4853 = cat(_T_4852, _T_4803) @[Cat.scala 29:58]
node _T_4854 = cat(_T_4853, _T_4799) @[Cat.scala 29:58]
node _T_4855 = cat(_T_4854, _T_4795) @[Cat.scala 29:58]
node _T_4856 = cat(_T_4855, _T_4791) @[Cat.scala 29:58]
node _T_4857 = cat(_T_4856, _T_4787) @[Cat.scala 29:58]
node _T_4858 = cat(_T_4857, _T_4783) @[Cat.scala 29:58]
node _T_4859 = cat(_T_4858, _T_4779) @[Cat.scala 29:58]
node _T_4860 = cat(_T_4859, _T_4775) @[Cat.scala 29:58]
node _T_4861 = cat(_T_4860, _T_4771) @[Cat.scala 29:58]
node _T_4862 = cat(_T_4861, _T_4767) @[Cat.scala 29:58]
node _T_4863 = cat(_T_4862, _T_4763) @[Cat.scala 29:58]
node _T_4864 = cat(_T_4863, _T_4759) @[Cat.scala 29:58]
node _T_4865 = cat(_T_4864, _T_4755) @[Cat.scala 29:58]
node _T_4866 = cat(_T_4865, _T_4751) @[Cat.scala 29:58]
node _T_4867 = cat(_T_4866, _T_4747) @[Cat.scala 29:58]
node _T_4868 = cat(_T_4867, _T_4743) @[Cat.scala 29:58]
node _T_4869 = cat(_T_4868, _T_4739) @[Cat.scala 29:58]
node _T_4870 = cat(_T_4869, _T_4735) @[Cat.scala 29:58]
node _T_4871 = cat(_T_4870, _T_4731) @[Cat.scala 29:58]
node _T_4872 = cat(_T_4871, _T_4727) @[Cat.scala 29:58]
node _T_4873 = cat(_T_4872, _T_4723) @[Cat.scala 29:58]
node _T_4874 = cat(_T_4873, _T_4719) @[Cat.scala 29:58]
node _T_4875 = cat(_T_4874, _T_4715) @[Cat.scala 29:58]
node _T_4876 = cat(_T_4875, _T_4711) @[Cat.scala 29:58]
node _T_4877 = cat(_T_4876, _T_4707) @[Cat.scala 29:58]
node _T_4878 = cat(_T_4877, _T_4703) @[Cat.scala 29:58]
node _T_4879 = cat(_T_4878, _T_4699) @[Cat.scala 29:58]
node _T_4880 = cat(_T_4879, _T_4695) @[Cat.scala 29:58]
node _T_4881 = cat(_T_4880, _T_4691) @[Cat.scala 29:58]
node _T_4882 = cat(_T_4881, _T_4687) @[Cat.scala 29:58]
node _T_4883 = cat(_T_4882, _T_4683) @[Cat.scala 29:58]
node _T_4884 = cat(_T_4883, _T_4679) @[Cat.scala 29:58]
node _T_4885 = cat(_T_4884, _T_4675) @[Cat.scala 29:58]
node _T_4886 = cat(_T_4885, _T_4671) @[Cat.scala 29:58]
node _T_4887 = cat(_T_4886, _T_4667) @[Cat.scala 29:58]
node _T_4888 = cat(_T_4887, _T_4663) @[Cat.scala 29:58]
node _T_4889 = cat(_T_4888, _T_4659) @[Cat.scala 29:58]
node _T_4890 = cat(_T_4889, _T_4655) @[Cat.scala 29:58]
node _T_4891 = cat(_T_4890, _T_4651) @[Cat.scala 29:58]
node _T_4892 = cat(_T_4891, _T_4647) @[Cat.scala 29:58]
node _T_4893 = cat(_T_4892, _T_4643) @[Cat.scala 29:58]
node _T_4894 = cat(_T_4893, _T_4639) @[Cat.scala 29:58]
node _T_4895 = cat(_T_4894, _T_4635) @[Cat.scala 29:58]
node _T_4896 = cat(_T_4895, _T_4631) @[Cat.scala 29:58]
node _T_4897 = cat(_T_4896, _T_4627) @[Cat.scala 29:58]
node _T_4898 = cat(_T_4897, _T_4623) @[Cat.scala 29:58]
node _T_4899 = cat(_T_4898, _T_4619) @[Cat.scala 29:58]
node _T_4900 = cat(_T_4899, _T_4615) @[Cat.scala 29:58]
node _T_4901 = cat(_T_4900, _T_4611) @[Cat.scala 29:58]
node _T_4902 = cat(_T_4901, _T_4607) @[Cat.scala 29:58]
node _T_4903 = cat(_T_4902, _T_4603) @[Cat.scala 29:58]
node _T_4904 = cat(_T_4903, _T_4599) @[Cat.scala 29:58]
node _T_4905 = cat(_T_4904, _T_4595) @[Cat.scala 29:58]
node _T_4906 = cat(_T_4905, _T_4591) @[Cat.scala 29:58]
node _T_4907 = cat(_T_4906, _T_4587) @[Cat.scala 29:58]
node _T_4908 = cat(_T_4907, _T_4583) @[Cat.scala 29:58]
node _T_4909 = cat(_T_4908, _T_4579) @[Cat.scala 29:58]
node _T_4910 = cat(_T_4909, _T_4575) @[Cat.scala 29:58]
node _T_4911 = cat(_T_4910, _T_4571) @[Cat.scala 29:58]
node _T_4912 = cat(_T_4911, _T_4567) @[Cat.scala 29:58]
node _T_4913 = cat(_T_4912, _T_4563) @[Cat.scala 29:58]
node _T_4914 = cat(_T_4913, _T_4559) @[Cat.scala 29:58]
node _T_4915 = cat(_T_4914, _T_4555) @[Cat.scala 29:58]
node _T_4916 = cat(_T_4915, _T_4551) @[Cat.scala 29:58]
node _T_4917 = cat(_T_4916, _T_4547) @[Cat.scala 29:58]
node _T_4918 = cat(_T_4917, _T_4543) @[Cat.scala 29:58]
node _T_4919 = cat(_T_4918, _T_4539) @[Cat.scala 29:58]
node _T_4920 = cat(_T_4919, _T_4535) @[Cat.scala 29:58]
node _T_4921 = cat(_T_4920, _T_4531) @[Cat.scala 29:58]
node _T_4922 = cat(_T_4921, _T_4527) @[Cat.scala 29:58]
node _T_4923 = cat(_T_4922, _T_4523) @[Cat.scala 29:58]
node _T_4924 = cat(_T_4923, _T_4519) @[Cat.scala 29:58]
node _T_4925 = cat(_T_4924, _T_4515) @[Cat.scala 29:58]
node _T_4926 = cat(_T_4925, _T_4511) @[Cat.scala 29:58]
node _T_4927 = cat(_T_4926, _T_4507) @[Cat.scala 29:58]
node _T_4928 = cat(_T_4927, _T_4503) @[Cat.scala 29:58]
node _T_4929 = cat(_T_4928, _T_4499) @[Cat.scala 29:58]
node _T_4930 = cat(_T_4929, _T_4495) @[Cat.scala 29:58]
node _T_4931 = cat(_T_4930, _T_4491) @[Cat.scala 29:58]
node _T_4932 = cat(_T_4931, _T_4487) @[Cat.scala 29:58]
node _T_4933 = cat(_T_4932, _T_4483) @[Cat.scala 29:58]
node _T_4934 = cat(_T_4933, _T_4479) @[Cat.scala 29:58]
node _T_4935 = cat(_T_4934, _T_4475) @[Cat.scala 29:58]
node _T_4936 = cat(_T_4935, _T_4471) @[Cat.scala 29:58]
node _T_4937 = cat(_T_4936, _T_4467) @[Cat.scala 29:58]
node _T_4938 = cat(_T_4937, _T_4463) @[Cat.scala 29:58]
node _T_4939 = cat(_T_4938, _T_4459) @[Cat.scala 29:58]
node _T_4940 = cat(_T_4939, _T_4455) @[Cat.scala 29:58]
node _T_4941 = cat(_T_4940, _T_4451) @[Cat.scala 29:58]
node _T_4942 = cat(_T_4941, _T_4447) @[Cat.scala 29:58]
node _T_4943 = cat(_T_4942, _T_4443) @[Cat.scala 29:58]
node _T_4944 = cat(_T_4943, _T_4439) @[Cat.scala 29:58]
node _T_4945 = cat(_T_4944, _T_4435) @[Cat.scala 29:58]
node _T_4946 = cat(_T_4945, _T_4431) @[Cat.scala 29:58]
node _T_4947 = cat(_T_4946, _T_4427) @[Cat.scala 29:58]
node _T_4948 = cat(_T_4947, _T_4423) @[Cat.scala 29:58]
node _T_4949 = cat(_T_4948, _T_4419) @[Cat.scala 29:58]
node _T_4950 = cat(_T_4949, _T_4415) @[Cat.scala 29:58]
node _T_4951 = cat(_T_4950, _T_4411) @[Cat.scala 29:58]
node _T_4952 = cat(_T_4951, _T_4407) @[Cat.scala 29:58]
node _T_4953 = cat(_T_4952, _T_4403) @[Cat.scala 29:58]
node _T_4954 = cat(_T_4953, _T_4399) @[Cat.scala 29:58]
node _T_4955 = cat(_T_4954, _T_4395) @[Cat.scala 29:58]
node _T_4956 = cat(_T_4955, _T_4391) @[Cat.scala 29:58]
node _T_4957 = cat(_T_4956, _T_4387) @[Cat.scala 29:58]
node _T_4958 = cat(_T_4957, _T_4383) @[Cat.scala 29:58]
node _T_4959 = cat(_T_4958, _T_4379) @[Cat.scala 29:58]
node _T_4960 = cat(_T_4959, _T_4375) @[Cat.scala 29:58]
node _T_4961 = cat(_T_4960, _T_4371) @[Cat.scala 29:58]
node _T_4962 = cat(_T_4961, _T_4367) @[Cat.scala 29:58]
node _T_4963 = cat(_T_4962, _T_4363) @[Cat.scala 29:58]
node _T_4964 = cat(_T_4963, _T_4359) @[Cat.scala 29:58]
node _T_4965 = cat(_T_4964, _T_4355) @[Cat.scala 29:58]
node _T_4966 = cat(_T_4965, _T_4351) @[Cat.scala 29:58]
node _T_4967 = cat(_T_4966, _T_4347) @[Cat.scala 29:58]
node _T_4968 = cat(_T_4967, _T_4343) @[Cat.scala 29:58]
node _T_4969 = cat(_T_4968, _T_4339) @[Cat.scala 29:58]
node _T_4970 = cat(_T_4969, _T_4335) @[Cat.scala 29:58]
way_status <= _T_4970 @[el2_ifu_mem_ctl.scala 757:14]
node _T_4971 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 758:59]
node _T_4972 = and(_T_4971, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 758:81]
node _T_4973 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 759:21]
node _T_4974 = bits(ic_rw_addr, 11, 5) @[el2_ifu_mem_ctl.scala 759:82]
node ifu_ic_rw_int_addr_w_debug = mux(_T_4972, _T_4973, _T_4974) @[el2_ifu_mem_ctl.scala 758:39]
reg _T_4975 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 760:58]
_T_4975 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 760:58]
ifu_ic_rw_int_addr_ff <= _T_4975 @[el2_ifu_mem_ctl.scala 760:25]
wire ifu_tag_wren : UInt<2>
ifu_tag_wren <= UInt<1>("h00")
wire ic_debug_tag_wr_en : UInt<2>
ic_debug_tag_wr_en <= UInt<1>("h00")
node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 763:43]
reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 764:55]
ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 764:55]
node _T_4976 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 765:48]
node _T_4977 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 765:92]
node ic_valid_w_debug = mux(_T_4976, _T_4977, ic_valid) @[el2_ifu_mem_ctl.scala 765:29]
reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 766:51]
ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 766:51]
io.test <= ic_valid_ff @[el2_ifu_mem_ctl.scala 767:11]
Clk enable removed from predictor
2020-10-07 12:35:34 +08:00