17412 lines
1.1 MiB
Plaintext
17412 lines
1.1 MiB
Plaintext
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit dec :
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module dec_ib_ctl :
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input clock : Clock
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input reset : Reset
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output io : {flip ifu_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, flip ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_fence_d : UInt<1>}
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io.dec_i0_icaf_f1_d <= io.ifu_ib.ifu_i0_icaf_f1 @[dec_ib_ctl.scala 29:31]
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io.dec_i0_dbecc_d <= io.ifu_ib.ifu_i0_dbecc @[dec_ib_ctl.scala 30:31]
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io.dec_i0_icaf_d <= io.ifu_ib.ifu_i0_icaf @[dec_ib_ctl.scala 31:31]
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io.ib_exu.dec_i0_pc_d <= io.ifu_ib.ifu_i0_pc @[dec_ib_ctl.scala 32:31]
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io.dec_i0_pc4_d <= io.ifu_ib.ifu_i0_pc4 @[dec_ib_ctl.scala 33:31]
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io.dec_i0_icaf_type_d <= io.ifu_ib.ifu_i0_icaf_type @[dec_ib_ctl.scala 34:31]
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io.dec_i0_brp.bits.ret <= io.ifu_ib.i0_brp.bits.ret @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.way <= io.ifu_ib.i0_brp.bits.way @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.prett <= io.ifu_ib.i0_brp.bits.prett @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.bank <= io.ifu_ib.i0_brp.bits.bank @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.br_start_error <= io.ifu_ib.i0_brp.bits.br_start_error @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.br_error <= io.ifu_ib.i0_brp.bits.br_error @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.hist <= io.ifu_ib.i0_brp.bits.hist @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.bits.toffset <= io.ifu_ib.i0_brp.bits.toffset @[dec_ib_ctl.scala 35:31]
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io.dec_i0_brp.valid <= io.ifu_ib.i0_brp.valid @[dec_ib_ctl.scala 35:31]
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io.dec_i0_bp_index <= io.ifu_ib.ifu_i0_bp_index @[dec_ib_ctl.scala 36:31]
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io.dec_i0_bp_fghr <= io.ifu_ib.ifu_i0_bp_fghr @[dec_ib_ctl.scala 37:31]
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io.dec_i0_bp_btag <= io.ifu_ib.ifu_i0_bp_btag @[dec_ib_ctl.scala 38:31]
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node _T = neq(io.dbg_ib.dbg_cmd_type, UInt<2>("h02")) @[dec_ib_ctl.scala 52:74]
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node debug_valid = and(io.dbg_ib.dbg_cmd_valid, _T) @[dec_ib_ctl.scala 52:48]
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node _T_1 = eq(io.dbg_ib.dbg_cmd_write, UInt<1>("h00")) @[dec_ib_ctl.scala 53:38]
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node debug_read = and(debug_valid, _T_1) @[dec_ib_ctl.scala 53:36]
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node debug_write = and(debug_valid, io.dbg_ib.dbg_cmd_write) @[dec_ib_ctl.scala 54:36]
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node _T_2 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 56:62]
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node debug_read_gpr = and(debug_read, _T_2) @[dec_ib_ctl.scala 56:37]
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node _T_3 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 57:62]
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node debug_write_gpr = and(debug_write, _T_3) @[dec_ib_ctl.scala 57:37]
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node _T_4 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 58:62]
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node debug_read_csr = and(debug_read, _T_4) @[dec_ib_ctl.scala 58:37]
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node _T_5 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 59:62]
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node debug_write_csr = and(debug_write, _T_5) @[dec_ib_ctl.scala 59:37]
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node dreg = bits(io.dbg_ib.dbg_cmd_addr, 4, 0) @[dec_ib_ctl.scala 61:47]
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node dcsr = bits(io.dbg_ib.dbg_cmd_addr, 11, 0) @[dec_ib_ctl.scala 62:47]
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node _T_6 = bits(debug_read_gpr, 0, 0) @[dec_ib_ctl.scala 65:34]
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node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
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node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
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node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
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node _T_10 = bits(debug_write_gpr, 0, 0) @[dec_ib_ctl.scala 66:41]
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node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
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node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
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node _T_13 = bits(debug_read_csr, 0, 0) @[dec_ib_ctl.scala 67:40]
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node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
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node _T_15 = bits(debug_write_csr, 0, 0) @[dec_ib_ctl.scala 68:41]
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node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
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node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
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node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
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node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
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wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
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ib0_debug_in <= _T_23 @[Mux.scala 27:72]
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node _T_24 = or(debug_write_gpr, debug_write_csr) @[dec_ib_ctl.scala 72:54]
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io.ib_exu.dec_debug_wdata_rs1_d <= _T_24 @[dec_ib_ctl.scala 72:35]
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node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[dec_ib_ctl.scala 75:51]
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node _T_26 = and(debug_write_csr, _T_25) @[dec_ib_ctl.scala 75:43]
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io.dec_debug_fence_d <= _T_26 @[dec_ib_ctl.scala 75:24]
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node _T_27 = or(io.ifu_ib.ifu_i0_valid, debug_valid) @[dec_ib_ctl.scala 77:48]
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io.dec_ib0_valid_d <= _T_27 @[dec_ib_ctl.scala 77:22]
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node _T_28 = bits(debug_valid, 0, 0) @[dec_ib_ctl.scala 78:41]
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node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_ib.ifu_i0_instr) @[dec_ib_ctl.scala 78:28]
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io.dec_i0_instr_d <= _T_29 @[dec_ib_ctl.scala 78:22]
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module dec_dec_ctl :
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input clock : Clock
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input reset : Reset
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output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}}
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node _T = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 20:23]
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node _T_1 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 20:35]
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node _T_2 = or(_T, _T_1) @[dec_dec_ctl.scala 20:27]
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node _T_3 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 20:49]
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node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_dec_ctl.scala 20:42]
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node _T_5 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 20:60]
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node _T_6 = and(_T_4, _T_5) @[dec_dec_ctl.scala 20:53]
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node _T_7 = or(_T_2, _T_6) @[dec_dec_ctl.scala 20:39]
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node _T_8 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 20:75]
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node _T_9 = eq(_T_8, UInt<1>("h00")) @[dec_dec_ctl.scala 20:68]
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node _T_10 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 20:85]
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node _T_11 = and(_T_9, _T_10) @[dec_dec_ctl.scala 20:78]
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node _T_12 = or(_T_7, _T_11) @[dec_dec_ctl.scala 20:65]
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io.out.alu <= _T_12 @[dec_dec_ctl.scala 20:14]
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node _T_13 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
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node _T_14 = eq(_T_13, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_15 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
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node _T_16 = eq(_T_15, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_17 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_18 = eq(_T_17, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_19 = and(_T_14, _T_16) @[dec_dec_ctl.scala 17:17]
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node _T_20 = and(_T_19, _T_18) @[dec_dec_ctl.scala 17:17]
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node _T_21 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
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node _T_22 = eq(_T_21, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_23 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
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node _T_24 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_26 = and(_T_22, _T_23) @[dec_dec_ctl.scala 17:17]
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node _T_27 = and(_T_26, _T_25) @[dec_dec_ctl.scala 17:17]
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node _T_28 = or(_T_20, _T_27) @[dec_dec_ctl.scala 21:43]
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node _T_29 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
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node _T_30 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
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node _T_31 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_33 = and(_T_29, _T_30) @[dec_dec_ctl.scala 17:17]
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node _T_34 = and(_T_33, _T_32) @[dec_dec_ctl.scala 17:17]
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node _T_35 = or(_T_28, _T_34) @[dec_dec_ctl.scala 21:70]
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node _T_36 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_38 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
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node _T_39 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_40 = eq(_T_39, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_41 = and(_T_37, _T_38) @[dec_dec_ctl.scala 17:17]
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node _T_42 = and(_T_41, _T_40) @[dec_dec_ctl.scala 17:17]
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node _T_43 = or(_T_35, _T_42) @[dec_dec_ctl.scala 22:29]
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node _T_44 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
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node _T_45 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
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node _T_46 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_47 = eq(_T_46, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_48 = and(_T_44, _T_45) @[dec_dec_ctl.scala 17:17]
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node _T_49 = and(_T_48, _T_47) @[dec_dec_ctl.scala 17:17]
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node _T_50 = or(_T_43, _T_49) @[dec_dec_ctl.scala 22:56]
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node _T_51 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
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node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_53 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
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node _T_54 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_55 = eq(_T_54, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_56 = and(_T_52, _T_53) @[dec_dec_ctl.scala 17:17]
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node _T_57 = and(_T_56, _T_55) @[dec_dec_ctl.scala 17:17]
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node _T_58 = or(_T_50, _T_57) @[dec_dec_ctl.scala 23:29]
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node _T_59 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
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node _T_60 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
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node _T_61 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_63 = and(_T_59, _T_60) @[dec_dec_ctl.scala 17:17]
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node _T_64 = and(_T_63, _T_62) @[dec_dec_ctl.scala 17:17]
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node _T_65 = or(_T_58, _T_64) @[dec_dec_ctl.scala 23:55]
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node _T_66 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
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node _T_67 = eq(_T_66, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_68 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
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node _T_69 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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node _T_70 = eq(_T_69, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_71 = and(_T_67, _T_68) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_72 = and(_T_71, _T_70) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_73 = or(_T_65, _T_72) @[dec_dec_ctl.scala 24:29]
|
||
|
|
node _T_74 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_75 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_76 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_77 = eq(_T_76, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_78 = and(_T_74, _T_75) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_79 = and(_T_78, _T_77) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_80 = or(_T_73, _T_79) @[dec_dec_ctl.scala 24:55]
|
||
|
|
node _T_81 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_83 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_84 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_86 = and(_T_82, _T_83) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_87 = and(_T_86, _T_85) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_88 = or(_T_80, _T_87) @[dec_dec_ctl.scala 25:29]
|
||
|
|
node _T_89 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_90 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_91 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_93 = and(_T_89, _T_90) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_94 = and(_T_93, _T_92) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_95 = or(_T_88, _T_94) @[dec_dec_ctl.scala 25:55]
|
||
|
|
node _T_96 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_97 = eq(_T_96, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_98 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_99 = eq(_T_98, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_100 = and(_T_97, _T_99) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_101 = or(_T_95, _T_100) @[dec_dec_ctl.scala 26:29]
|
||
|
|
node _T_102 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_103 = eq(_T_102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_104 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_105 = eq(_T_104, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_106 = and(_T_103, _T_105) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_107 = or(_T_101, _T_106) @[dec_dec_ctl.scala 26:51]
|
||
|
|
io.out.rs1 <= _T_107 @[dec_dec_ctl.scala 21:14]
|
||
|
|
node _T_108 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_109 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_111 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_113 = and(_T_108, _T_110) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_114 = and(_T_113, _T_112) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_115 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_117 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_118 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_119 = eq(_T_118, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_120 = and(_T_116, _T_117) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_121 = and(_T_120, _T_119) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_122 = or(_T_114, _T_121) @[dec_dec_ctl.scala 27:40]
|
||
|
|
io.out.rs2 <= _T_122 @[dec_dec_ctl.scala 27:14]
|
||
|
|
node _T_123 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_124 = eq(_T_123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_125 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_127 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_128 = and(_T_124, _T_126) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_129 = and(_T_128, _T_127) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_130 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_131 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_133 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_134 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_135 = eq(_T_134, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_136 = and(_T_130, _T_132) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_137 = and(_T_136, _T_133) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_138 = and(_T_137, _T_135) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_139 = or(_T_129, _T_138) @[dec_dec_ctl.scala 28:42]
|
||
|
|
node _T_140 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_141 = eq(_T_140, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_142 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_143 = eq(_T_142, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_144 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_145 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_146 = and(_T_141, _T_143) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_147 = and(_T_146, _T_144) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_148 = and(_T_147, _T_145) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_149 = or(_T_139, _T_148) @[dec_dec_ctl.scala 28:70]
|
||
|
|
node _T_150 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_151 = eq(_T_150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_152 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_153 = eq(_T_152, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_154 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_155 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_156 = eq(_T_155, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_157 = and(_T_151, _T_153) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_158 = and(_T_157, _T_154) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_159 = and(_T_158, _T_156) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_160 = or(_T_149, _T_159) @[dec_dec_ctl.scala 29:32]
|
||
|
|
io.out.imm12 <= _T_160 @[dec_dec_ctl.scala 28:16]
|
||
|
|
node _T_161 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 30:24]
|
||
|
|
node _T_162 = eq(_T_161, UInt<1>("h00")) @[dec_dec_ctl.scala 30:17]
|
||
|
|
node _T_163 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 30:37]
|
||
|
|
node _T_164 = eq(_T_163, UInt<1>("h00")) @[dec_dec_ctl.scala 30:30]
|
||
|
|
node _T_165 = and(_T_162, _T_164) @[dec_dec_ctl.scala 30:28]
|
||
|
|
node _T_166 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 30:51]
|
||
|
|
node _T_167 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 30:63]
|
||
|
|
node _T_168 = and(_T_166, _T_167) @[dec_dec_ctl.scala 30:55]
|
||
|
|
node _T_169 = or(_T_165, _T_168) @[dec_dec_ctl.scala 30:42]
|
||
|
|
node _T_170 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 30:76]
|
||
|
|
node _T_171 = or(_T_169, _T_170) @[dec_dec_ctl.scala 30:68]
|
||
|
|
io.out.rd <= _T_171 @[dec_dec_ctl.scala 30:13]
|
||
|
|
node _T_172 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_173 = eq(_T_172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_174 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_175 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_177 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_178 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_180 = and(_T_173, _T_174) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_181 = and(_T_180, _T_176) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_182 = and(_T_181, _T_177) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_183 = and(_T_182, _T_179) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.shimm5 <= _T_183 @[dec_dec_ctl.scala 31:17]
|
||
|
|
node _T_184 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 32:26]
|
||
|
|
node _T_185 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 32:36]
|
||
|
|
node _T_186 = and(_T_184, _T_185) @[dec_dec_ctl.scala 32:29]
|
||
|
|
node _T_187 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 32:50]
|
||
|
|
node _T_188 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 32:60]
|
||
|
|
node _T_189 = and(_T_187, _T_188) @[dec_dec_ctl.scala 32:53]
|
||
|
|
node _T_190 = or(_T_186, _T_189) @[dec_dec_ctl.scala 32:41]
|
||
|
|
io.out.imm20 <= _T_190 @[dec_dec_ctl.scala 32:16]
|
||
|
|
node _T_191 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 33:24]
|
||
|
|
node _T_192 = eq(_T_191, UInt<1>("h00")) @[dec_dec_ctl.scala 33:17]
|
||
|
|
node _T_193 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 33:37]
|
||
|
|
node _T_194 = eq(_T_193, UInt<1>("h00")) @[dec_dec_ctl.scala 33:30]
|
||
|
|
node _T_195 = and(_T_192, _T_194) @[dec_dec_ctl.scala 33:28]
|
||
|
|
node _T_196 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 33:49]
|
||
|
|
node _T_197 = and(_T_195, _T_196) @[dec_dec_ctl.scala 33:41]
|
||
|
|
node _T_198 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 33:63]
|
||
|
|
node _T_199 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 33:75]
|
||
|
|
node _T_200 = and(_T_198, _T_199) @[dec_dec_ctl.scala 33:67]
|
||
|
|
node _T_201 = or(_T_197, _T_200) @[dec_dec_ctl.scala 33:54]
|
||
|
|
io.out.pc <= _T_201 @[dec_dec_ctl.scala 33:13]
|
||
|
|
node _T_202 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_203 = eq(_T_202, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_204 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_205 = eq(_T_204, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_206 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_208 = and(_T_203, _T_205) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_209 = and(_T_208, _T_207) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.load <= _T_209 @[dec_dec_ctl.scala 34:15]
|
||
|
|
node _T_210 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_211 = eq(_T_210, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_212 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_213 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_215 = and(_T_211, _T_212) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_216 = and(_T_215, _T_214) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.store <= _T_216 @[dec_dec_ctl.scala 35:16]
|
||
|
|
node _T_217 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_218 = eq(_T_217, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_219 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_220 = eq(_T_219, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_221 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_222 = eq(_T_221, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_223 = and(_T_218, _T_220) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_224 = and(_T_223, _T_222) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.lsu <= _T_224 @[dec_dec_ctl.scala 36:14]
|
||
|
|
node _T_225 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_227 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_228 = eq(_T_227, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_229 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_230 = eq(_T_229, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_231 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_232 = eq(_T_231, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_233 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_234 = and(_T_226, _T_228) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_235 = and(_T_234, _T_230) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_236 = and(_T_235, _T_232) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_237 = and(_T_236, _T_233) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_238 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_240 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_241 = eq(_T_240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_242 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_243 = and(_T_239, _T_241) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_244 = and(_T_243, _T_242) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_245 = or(_T_237, _T_244) @[dec_dec_ctl.scala 37:49]
|
||
|
|
node _T_246 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_247 = eq(_T_246, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_248 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_250 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_251 = eq(_T_250, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_252 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_254 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_256 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_258 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_259 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_260 = eq(_T_259, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_261 = and(_T_247, _T_249) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_262 = and(_T_261, _T_251) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_263 = and(_T_262, _T_253) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_264 = and(_T_263, _T_255) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_265 = and(_T_264, _T_257) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_266 = and(_T_265, _T_258) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_267 = and(_T_266, _T_260) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_268 = or(_T_245, _T_267) @[dec_dec_ctl.scala 37:74]
|
||
|
|
io.out.add <= _T_268 @[dec_dec_ctl.scala 37:14]
|
||
|
|
node _T_269 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_270 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_271 = eq(_T_270, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_272 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_273 = eq(_T_272, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_274 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_275 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_276 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_277 = eq(_T_276, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_278 = and(_T_269, _T_271) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_279 = and(_T_278, _T_273) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_280 = and(_T_279, _T_274) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_281 = and(_T_280, _T_275) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_282 = and(_T_281, _T_277) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_283 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_284 = eq(_T_283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_285 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_286 = eq(_T_285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_287 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_288 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_290 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_291 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_292 = eq(_T_291, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_293 = and(_T_284, _T_286) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_294 = and(_T_293, _T_287) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_295 = and(_T_294, _T_289) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_296 = and(_T_295, _T_290) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_297 = and(_T_296, _T_292) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_298 = or(_T_282, _T_297) @[dec_dec_ctl.scala 39:49]
|
||
|
|
node _T_299 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_300 = eq(_T_299, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_301 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_302 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_303 = eq(_T_302, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_304 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_305 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_307 = and(_T_300, _T_301) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_308 = and(_T_307, _T_303) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_309 = and(_T_308, _T_304) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_310 = and(_T_309, _T_306) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_311 = or(_T_298, _T_310) @[dec_dec_ctl.scala 39:85]
|
||
|
|
node _T_312 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_313 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_315 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_316 = eq(_T_315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_317 = and(_T_312, _T_314) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_318 = and(_T_317, _T_316) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_319 = or(_T_311, _T_318) @[dec_dec_ctl.scala 40:35]
|
||
|
|
io.out.sub <= _T_319 @[dec_dec_ctl.scala 39:14]
|
||
|
|
node _T_320 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_321 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_322 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_323 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_324 = eq(_T_323, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_325 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_326 = eq(_T_325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_327 = and(_T_320, _T_321) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_328 = and(_T_327, _T_322) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_329 = and(_T_328, _T_324) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_330 = and(_T_329, _T_326) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_331 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_332 = eq(_T_331, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_333 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_334 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_335 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_336 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_337 = eq(_T_336, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_338 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_339 = eq(_T_338, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_340 = and(_T_332, _T_333) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_341 = and(_T_340, _T_334) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_342 = and(_T_341, _T_335) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_343 = and(_T_342, _T_337) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_344 = and(_T_343, _T_339) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_345 = or(_T_330, _T_344) @[dec_dec_ctl.scala 41:48]
|
||
|
|
io.out.land <= _T_345 @[dec_dec_ctl.scala 41:15]
|
||
|
|
node _T_346 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_347 = eq(_T_346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_348 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_349 = and(_T_347, _T_348) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_350 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_351 = eq(_T_350, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_352 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_353 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_354 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_356 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_358 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_360 = and(_T_351, _T_352) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_361 = and(_T_360, _T_353) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_362 = and(_T_361, _T_355) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_363 = and(_T_362, _T_357) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_364 = and(_T_363, _T_359) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_365 = or(_T_349, _T_364) @[dec_dec_ctl.scala 42:37]
|
||
|
|
node _T_366 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_367 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_368 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_369 = and(_T_366, _T_367) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_370 = and(_T_369, _T_368) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_371 = or(_T_365, _T_370) @[dec_dec_ctl.scala 42:74]
|
||
|
|
node _T_372 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_373 = eq(_T_372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_374 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_376 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_377 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_378 = and(_T_373, _T_375) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_379 = and(_T_378, _T_376) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_380 = and(_T_379, _T_377) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_381 = or(_T_371, _T_380) @[dec_dec_ctl.scala 43:26]
|
||
|
|
node _T_382 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_383 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_384 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_385 = eq(_T_384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_386 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_387 = eq(_T_386, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_388 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_389 = eq(_T_388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_390 = and(_T_382, _T_383) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_391 = and(_T_390, _T_385) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_392 = and(_T_391, _T_387) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_393 = and(_T_392, _T_389) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_394 = or(_T_381, _T_393) @[dec_dec_ctl.scala 43:55]
|
||
|
|
io.out.lor <= _T_394 @[dec_dec_ctl.scala 42:14]
|
||
|
|
node _T_395 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_397 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_398 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_399 = eq(_T_398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_400 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_401 = eq(_T_400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_402 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_403 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_405 = and(_T_396, _T_397) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_406 = and(_T_405, _T_399) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_407 = and(_T_406, _T_401) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_408 = and(_T_407, _T_402) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_409 = and(_T_408, _T_404) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_410 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_411 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_412 = eq(_T_411, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_413 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_414 = eq(_T_413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_415 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_416 = eq(_T_415, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_417 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_418 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_420 = and(_T_410, _T_412) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_421 = and(_T_420, _T_414) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_422 = and(_T_421, _T_416) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_423 = and(_T_422, _T_417) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_424 = and(_T_423, _T_419) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_425 = or(_T_409, _T_424) @[dec_dec_ctl.scala 45:53]
|
||
|
|
io.out.lxor <= _T_425 @[dec_dec_ctl.scala 45:15]
|
||
|
|
node _T_426 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_427 = eq(_T_426, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_428 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_429 = eq(_T_428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_430 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_431 = eq(_T_430, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_432 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_433 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_434 = eq(_T_433, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_435 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_436 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_438 = and(_T_427, _T_429) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_439 = and(_T_438, _T_431) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_440 = and(_T_439, _T_432) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_441 = and(_T_440, _T_434) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_442 = and(_T_441, _T_435) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_443 = and(_T_442, _T_437) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.sll <= _T_443 @[dec_dec_ctl.scala 46:14]
|
||
|
|
node _T_444 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_445 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_446 = eq(_T_445, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_447 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_448 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_449 = eq(_T_448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_450 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_452 = eq(_T_451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_453 = and(_T_444, _T_446) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_454 = and(_T_453, _T_447) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_455 = and(_T_454, _T_449) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_456 = and(_T_455, _T_450) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_457 = and(_T_456, _T_452) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.sra <= _T_457 @[dec_dec_ctl.scala 47:14]
|
||
|
|
node _T_458 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_459 = eq(_T_458, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_460 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_461 = eq(_T_460, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_462 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_463 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_464 = eq(_T_463, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_465 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_466 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_468 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_469 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_470 = eq(_T_469, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_471 = and(_T_459, _T_461) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_472 = and(_T_471, _T_462) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_473 = and(_T_472, _T_464) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_474 = and(_T_473, _T_465) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_475 = and(_T_474, _T_467) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_476 = and(_T_475, _T_468) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_477 = and(_T_476, _T_470) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.srl <= _T_477 @[dec_dec_ctl.scala 48:14]
|
||
|
|
node _T_478 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_479 = eq(_T_478, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_480 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_482 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_483 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_485 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_486 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_487 = eq(_T_486, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_488 = and(_T_479, _T_481) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_489 = and(_T_488, _T_482) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_490 = and(_T_489, _T_484) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_491 = and(_T_490, _T_485) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_492 = and(_T_491, _T_487) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_493 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_494 = eq(_T_493, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_495 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_496 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_498 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_499 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_500 = eq(_T_499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_501 = and(_T_494, _T_495) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_502 = and(_T_501, _T_497) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_503 = and(_T_502, _T_498) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_504 = and(_T_503, _T_500) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_505 = or(_T_492, _T_504) @[dec_dec_ctl.scala 49:51]
|
||
|
|
io.out.slt <= _T_505 @[dec_dec_ctl.scala 49:14]
|
||
|
|
node _T_506 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_507 = eq(_T_506, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_508 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_509 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_510 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_511 = eq(_T_510, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_512 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_513 = eq(_T_512, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_514 = and(_T_507, _T_508) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_515 = and(_T_514, _T_509) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_516 = and(_T_515, _T_511) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_517 = and(_T_516, _T_513) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_518 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_519 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_520 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_521 = eq(_T_520, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_522 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_523 = eq(_T_522, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_524 = and(_T_518, _T_519) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_525 = and(_T_524, _T_521) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_526 = and(_T_525, _T_523) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_527 = or(_T_517, _T_526) @[dec_dec_ctl.scala 50:51]
|
||
|
|
node _T_528 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_529 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_530 = eq(_T_529, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_531 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_533 = and(_T_528, _T_530) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_534 = and(_T_533, _T_532) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_535 = or(_T_527, _T_534) @[dec_dec_ctl.scala 50:79]
|
||
|
|
node _T_536 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_537 = eq(_T_536, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_538 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_540 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_541 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_542 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_543 = eq(_T_542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_544 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_545 = eq(_T_544, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_546 = and(_T_537, _T_539) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_547 = and(_T_546, _T_540) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_548 = and(_T_547, _T_541) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_549 = and(_T_548, _T_543) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_550 = and(_T_549, _T_545) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_551 = or(_T_535, _T_550) @[dec_dec_ctl.scala 51:29]
|
||
|
|
node _T_552 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_553 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_554 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_555 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_557 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_558 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_560 = and(_T_552, _T_553) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_561 = and(_T_560, _T_554) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_562 = and(_T_561, _T_556) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_563 = and(_T_562, _T_557) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_564 = and(_T_563, _T_559) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_565 = or(_T_551, _T_564) @[dec_dec_ctl.scala 51:66]
|
||
|
|
io.out.unsign <= _T_565 @[dec_dec_ctl.scala 50:17]
|
||
|
|
node _T_566 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_567 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_569 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_570 = eq(_T_569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_571 = and(_T_566, _T_568) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_572 = and(_T_571, _T_570) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.condbr <= _T_572 @[dec_dec_ctl.scala 53:17]
|
||
|
|
node _T_573 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_574 = eq(_T_573, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_575 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_576 = eq(_T_575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_577 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_578 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_579 = eq(_T_578, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_580 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_582 = and(_T_574, _T_576) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_583 = and(_T_582, _T_577) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_584 = and(_T_583, _T_579) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_585 = and(_T_584, _T_581) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.beq <= _T_585 @[dec_dec_ctl.scala 54:14]
|
||
|
|
node _T_586 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_587 = eq(_T_586, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_588 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_589 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_590 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_591 = eq(_T_590, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_592 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_593 = eq(_T_592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_594 = and(_T_587, _T_588) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_595 = and(_T_594, _T_589) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_596 = and(_T_595, _T_591) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_597 = and(_T_596, _T_593) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.bne <= _T_597 @[dec_dec_ctl.scala 55:14]
|
||
|
|
node _T_598 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_599 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_600 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_601 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_603 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_605 = and(_T_598, _T_599) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_606 = and(_T_605, _T_600) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_607 = and(_T_606, _T_602) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_608 = and(_T_607, _T_604) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.bge <= _T_608 @[dec_dec_ctl.scala 56:14]
|
||
|
|
node _T_609 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_610 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_611 = eq(_T_610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_612 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_613 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_614 = eq(_T_613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_615 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_616 = eq(_T_615, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_617 = and(_T_609, _T_611) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_618 = and(_T_617, _T_612) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_619 = and(_T_618, _T_614) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_620 = and(_T_619, _T_616) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.blt <= _T_620 @[dec_dec_ctl.scala 57:14]
|
||
|
|
node _T_621 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_622 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_623 = and(_T_621, _T_622) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.jal <= _T_623 @[dec_dec_ctl.scala 58:14]
|
||
|
|
node _T_624 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_625 = eq(_T_624, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_626 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_627 = eq(_T_626, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_628 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_629 = eq(_T_628, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_630 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_632 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_634 = and(_T_625, _T_627) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_635 = and(_T_634, _T_629) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_636 = and(_T_635, _T_631) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_637 = and(_T_636, _T_633) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.by <= _T_637 @[dec_dec_ctl.scala 59:13]
|
||
|
|
node _T_638 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_639 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_640 = eq(_T_639, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_641 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_642 = eq(_T_641, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_643 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_644 = eq(_T_643, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_645 = and(_T_638, _T_640) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_646 = and(_T_645, _T_642) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_647 = and(_T_646, _T_644) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.half <= _T_647 @[dec_dec_ctl.scala 60:15]
|
||
|
|
node _T_648 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_649 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_650 = eq(_T_649, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_651 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_652 = eq(_T_651, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_653 = and(_T_648, _T_650) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_654 = and(_T_653, _T_652) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.word <= _T_654 @[dec_dec_ctl.scala 61:15]
|
||
|
|
node _T_655 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_656 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_657 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_658 = and(_T_655, _T_656) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_659 = and(_T_658, _T_657) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_660 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_661 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_662 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_663 = and(_T_660, _T_661) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_664 = and(_T_663, _T_662) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_665 = or(_T_659, _T_664) @[dec_dec_ctl.scala 62:44]
|
||
|
|
node _T_666 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_667 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_668 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_669 = and(_T_666, _T_667) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_670 = and(_T_669, _T_668) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_671 = or(_T_665, _T_670) @[dec_dec_ctl.scala 62:67]
|
||
|
|
node _T_672 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_673 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_674 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_675 = and(_T_672, _T_673) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_676 = and(_T_675, _T_674) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_677 = or(_T_671, _T_676) @[dec_dec_ctl.scala 63:26]
|
||
|
|
node _T_678 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_679 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_680 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_681 = and(_T_678, _T_679) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_682 = and(_T_681, _T_680) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_683 = or(_T_677, _T_682) @[dec_dec_ctl.scala 63:49]
|
||
|
|
node _T_684 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_685 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_686 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_687 = and(_T_684, _T_685) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_688 = and(_T_687, _T_686) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_689 = or(_T_683, _T_688) @[dec_dec_ctl.scala 63:73]
|
||
|
|
io.out.csr_read <= _T_689 @[dec_dec_ctl.scala 62:19]
|
||
|
|
node _T_690 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_691 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_692 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_693 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_694 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_695 = and(_T_690, _T_691) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_696 = and(_T_695, _T_692) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_697 = and(_T_696, _T_693) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_698 = and(_T_697, _T_694) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_699 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_700 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_701 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_702 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_703 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_704 = and(_T_699, _T_700) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_705 = and(_T_704, _T_701) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_706 = and(_T_705, _T_702) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_707 = and(_T_706, _T_703) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_708 = or(_T_698, _T_707) @[dec_dec_ctl.scala 65:49]
|
||
|
|
node _T_709 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_710 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_711 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_712 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_713 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_714 = and(_T_709, _T_710) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_715 = and(_T_714, _T_711) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_716 = and(_T_715, _T_712) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_717 = and(_T_716, _T_713) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_718 = or(_T_708, _T_717) @[dec_dec_ctl.scala 65:79]
|
||
|
|
node _T_719 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_720 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_721 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_722 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_723 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_724 = and(_T_719, _T_720) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_725 = and(_T_724, _T_721) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_726 = and(_T_725, _T_722) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_727 = and(_T_726, _T_723) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_728 = or(_T_718, _T_727) @[dec_dec_ctl.scala 66:33]
|
||
|
|
node _T_729 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_730 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_731 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_732 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_733 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_734 = and(_T_729, _T_730) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_735 = and(_T_734, _T_731) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_736 = and(_T_735, _T_732) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_737 = and(_T_736, _T_733) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_738 = or(_T_728, _T_737) @[dec_dec_ctl.scala 66:63]
|
||
|
|
io.out.csr_clr <= _T_738 @[dec_dec_ctl.scala 65:18]
|
||
|
|
node _T_739 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_740 = eq(_T_739, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_741 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_742 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_743 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_744 = and(_T_740, _T_741) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_745 = and(_T_744, _T_742) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_746 = and(_T_745, _T_743) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.csr_write <= _T_746 @[dec_dec_ctl.scala 68:20]
|
||
|
|
node _T_747 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_748 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_749 = eq(_T_748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_750 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_751 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_752 = and(_T_747, _T_749) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_753 = and(_T_752, _T_750) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_754 = and(_T_753, _T_751) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_755 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_756 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_757 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_758 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_759 = and(_T_755, _T_756) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_760 = and(_T_759, _T_757) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_761 = and(_T_760, _T_758) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_762 = or(_T_754, _T_761) @[dec_dec_ctl.scala 69:47]
|
||
|
|
node _T_763 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_764 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_765 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_766 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_767 = and(_T_763, _T_764) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_768 = and(_T_767, _T_765) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_769 = and(_T_768, _T_766) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_770 = or(_T_762, _T_769) @[dec_dec_ctl.scala 69:74]
|
||
|
|
node _T_771 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_772 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_773 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_774 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_775 = and(_T_771, _T_772) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_776 = and(_T_775, _T_773) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_777 = and(_T_776, _T_774) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_778 = or(_T_770, _T_777) @[dec_dec_ctl.scala 70:30]
|
||
|
|
node _T_779 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_780 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_781 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_782 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_783 = and(_T_779, _T_780) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_784 = and(_T_783, _T_781) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_785 = and(_T_784, _T_782) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_786 = or(_T_778, _T_785) @[dec_dec_ctl.scala 70:57]
|
||
|
|
node _T_787 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_788 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_789 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_790 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_791 = and(_T_787, _T_788) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_792 = and(_T_791, _T_789) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_793 = and(_T_792, _T_790) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_794 = or(_T_786, _T_793) @[dec_dec_ctl.scala 71:30]
|
||
|
|
io.out.csr_imm <= _T_794 @[dec_dec_ctl.scala 69:18]
|
||
|
|
node _T_795 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_796 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_798 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_799 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_800 = and(_T_795, _T_797) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_801 = and(_T_800, _T_798) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_802 = and(_T_801, _T_799) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_803 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_804 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_805 = eq(_T_804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_806 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_807 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_808 = and(_T_803, _T_805) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_809 = and(_T_808, _T_806) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_810 = and(_T_809, _T_807) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_811 = or(_T_802, _T_810) @[dec_dec_ctl.scala 72:47]
|
||
|
|
node _T_812 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_813 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_815 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_816 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_817 = and(_T_812, _T_814) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_818 = and(_T_817, _T_815) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_819 = and(_T_818, _T_816) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_820 = or(_T_811, _T_819) @[dec_dec_ctl.scala 72:75]
|
||
|
|
node _T_821 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_822 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_823 = eq(_T_822, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_824 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_825 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_826 = and(_T_821, _T_823) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_827 = and(_T_826, _T_824) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_828 = and(_T_827, _T_825) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_829 = or(_T_820, _T_828) @[dec_dec_ctl.scala 73:31]
|
||
|
|
node _T_830 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_831 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_832 = eq(_T_831, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_833 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_834 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_835 = and(_T_830, _T_832) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_836 = and(_T_835, _T_833) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_837 = and(_T_836, _T_834) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_838 = or(_T_829, _T_837) @[dec_dec_ctl.scala 73:59]
|
||
|
|
io.out.csr_set <= _T_838 @[dec_dec_ctl.scala 72:18]
|
||
|
|
node _T_839 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_840 = eq(_T_839, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_841 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_842 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_843 = eq(_T_842, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_844 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_845 = eq(_T_844, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_846 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_847 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_848 = and(_T_840, _T_841) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_849 = and(_T_848, _T_843) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_850 = and(_T_849, _T_845) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_851 = and(_T_850, _T_846) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_852 = and(_T_851, _T_847) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.ebreak <= _T_852 @[dec_dec_ctl.scala 75:17]
|
||
|
|
node _T_853 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_854 = eq(_T_853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_855 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_856 = eq(_T_855, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_857 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_859 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_861 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_862 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_863 = and(_T_854, _T_856) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_864 = and(_T_863, _T_858) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_865 = and(_T_864, _T_860) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_866 = and(_T_865, _T_861) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_867 = and(_T_866, _T_862) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.ecall <= _T_867 @[dec_dec_ctl.scala 76:16]
|
||
|
|
node _T_868 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_869 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_870 = eq(_T_869, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_871 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_872 = eq(_T_871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_873 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_874 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_875 = and(_T_868, _T_870) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_876 = and(_T_875, _T_872) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_877 = and(_T_876, _T_873) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_878 = and(_T_877, _T_874) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.mret <= _T_878 @[dec_dec_ctl.scala 77:15]
|
||
|
|
node _T_879 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_880 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_881 = eq(_T_880, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_882 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_883 = eq(_T_882, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_884 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_885 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_886 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_887 = eq(_T_886, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_888 = and(_T_879, _T_881) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_889 = and(_T_888, _T_883) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_890 = and(_T_889, _T_884) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_891 = and(_T_890, _T_885) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_892 = and(_T_891, _T_887) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.mul <= _T_892 @[dec_dec_ctl.scala 78:14]
|
||
|
|
node _T_893 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_894 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_896 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_897 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_898 = eq(_T_897, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_899 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_900 = eq(_T_899, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_901 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_902 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_903 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_904 = eq(_T_903, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_905 = and(_T_893, _T_895) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_906 = and(_T_905, _T_896) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_907 = and(_T_906, _T_898) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_908 = and(_T_907, _T_900) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_909 = and(_T_908, _T_901) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_910 = and(_T_909, _T_902) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_911 = and(_T_910, _T_904) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_912 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_913 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_914 = eq(_T_913, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_915 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_917 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_918 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_919 = eq(_T_918, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_920 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_921 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_922 = eq(_T_921, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_923 = and(_T_912, _T_914) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_924 = and(_T_923, _T_916) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_925 = and(_T_924, _T_917) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_926 = and(_T_925, _T_919) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_927 = and(_T_926, _T_920) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_928 = and(_T_927, _T_922) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_929 = or(_T_911, _T_928) @[dec_dec_ctl.scala 79:61]
|
||
|
|
io.out.rs1_sign <= _T_929 @[dec_dec_ctl.scala 79:19]
|
||
|
|
node _T_930 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_931 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_932 = eq(_T_931, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_933 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_934 = eq(_T_933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_935 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_936 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_937 = eq(_T_936, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_938 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_939 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_940 = eq(_T_939, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_941 = and(_T_930, _T_932) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_942 = and(_T_941, _T_934) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_943 = and(_T_942, _T_935) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_944 = and(_T_943, _T_937) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_945 = and(_T_944, _T_938) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_946 = and(_T_945, _T_940) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.rs2_sign <= _T_946 @[dec_dec_ctl.scala 81:19]
|
||
|
|
node _T_947 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_948 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_950 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_952 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_953 = eq(_T_952, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_954 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_955 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_956 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_957 = eq(_T_956, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_958 = and(_T_947, _T_949) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_959 = and(_T_958, _T_951) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_960 = and(_T_959, _T_953) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_961 = and(_T_960, _T_954) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_962 = and(_T_961, _T_955) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_963 = and(_T_962, _T_957) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.low <= _T_963 @[dec_dec_ctl.scala 82:14]
|
||
|
|
node _T_964 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_965 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_966 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_967 = eq(_T_966, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_968 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_969 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_970 = eq(_T_969, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_971 = and(_T_964, _T_965) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_972 = and(_T_971, _T_967) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_973 = and(_T_972, _T_968) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_974 = and(_T_973, _T_970) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.div <= _T_974 @[dec_dec_ctl.scala 83:14]
|
||
|
|
node _T_975 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_976 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_977 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_978 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_979 = eq(_T_978, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_980 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_981 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_983 = and(_T_975, _T_976) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_984 = and(_T_983, _T_977) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_985 = and(_T_984, _T_979) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_986 = and(_T_985, _T_980) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_987 = and(_T_986, _T_982) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.rem <= _T_987 @[dec_dec_ctl.scala 84:14]
|
||
|
|
node _T_988 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_989 = eq(_T_988, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_990 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_991 = and(_T_989, _T_990) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.fence <= _T_991 @[dec_dec_ctl.scala 85:16]
|
||
|
|
node _T_992 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_993 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_995 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_996 = and(_T_992, _T_994) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_997 = and(_T_996, _T_995) @[dec_dec_ctl.scala 17:17]
|
||
|
|
io.out.fence_i <= _T_997 @[dec_dec_ctl.scala 86:18]
|
||
|
|
node _T_998 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_999 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1000 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1002 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1004 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1005 = and(_T_998, _T_999) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1006 = and(_T_1005, _T_1001) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1007 = and(_T_1006, _T_1003) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1008 = and(_T_1007, _T_1004) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1009 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1010 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1011 = and(_T_1009, _T_1010) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1012 = or(_T_1008, _T_1011) @[dec_dec_ctl.scala 87:51]
|
||
|
|
node _T_1013 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1015 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1016 = eq(_T_1015, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1017 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1018 = and(_T_1014, _T_1016) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1019 = and(_T_1018, _T_1017) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1020 = or(_T_1012, _T_1019) @[dec_dec_ctl.scala 87:72]
|
||
|
|
node _T_1021 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1023 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1024 = and(_T_1022, _T_1023) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1025 = or(_T_1020, _T_1024) @[dec_dec_ctl.scala 88:29]
|
||
|
|
io.out.pm_alu <= _T_1025 @[dec_dec_ctl.scala 87:17]
|
||
|
|
node _T_1026 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1028 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1029 = and(_T_1027, _T_1028) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1030 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1032 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1033 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1034 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1035 = and(_T_1031, _T_1032) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1036 = and(_T_1035, _T_1033) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1037 = and(_T_1036, _T_1034) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1038 = or(_T_1029, _T_1037) @[dec_dec_ctl.scala 89:41]
|
||
|
|
node _T_1039 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1041 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1042 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1043 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1044 = and(_T_1040, _T_1041) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1045 = and(_T_1044, _T_1042) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1046 = and(_T_1045, _T_1043) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1047 = or(_T_1038, _T_1046) @[dec_dec_ctl.scala 89:68]
|
||
|
|
node _T_1048 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1050 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1051 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1052 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1053 = and(_T_1049, _T_1050) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1054 = and(_T_1053, _T_1051) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1055 = and(_T_1054, _T_1052) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1056 = or(_T_1047, _T_1055) @[dec_dec_ctl.scala 90:30]
|
||
|
|
node _T_1057 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1059 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1060 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1061 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1062 = and(_T_1058, _T_1059) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1063 = and(_T_1062, _T_1060) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1064 = and(_T_1063, _T_1061) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1065 = or(_T_1056, _T_1064) @[dec_dec_ctl.scala 90:57]
|
||
|
|
node _T_1066 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1068 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1069 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1070 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1071 = and(_T_1067, _T_1068) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1072 = and(_T_1071, _T_1069) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1073 = and(_T_1072, _T_1070) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1074 = or(_T_1065, _T_1073) @[dec_dec_ctl.scala 91:31]
|
||
|
|
node _T_1075 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1076 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1077 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1078 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1079 = and(_T_1075, _T_1076) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1080 = and(_T_1079, _T_1077) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1081 = and(_T_1080, _T_1078) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1082 = or(_T_1074, _T_1081) @[dec_dec_ctl.scala 91:59]
|
||
|
|
node _T_1083 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1084 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1085 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1087 = and(_T_1083, _T_1084) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1088 = and(_T_1087, _T_1085) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1089 = and(_T_1088, _T_1086) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1090 = or(_T_1082, _T_1089) @[dec_dec_ctl.scala 92:30]
|
||
|
|
node _T_1091 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1092 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1093 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1094 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1095 = and(_T_1091, _T_1092) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1096 = and(_T_1095, _T_1093) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1097 = and(_T_1096, _T_1094) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1098 = or(_T_1090, _T_1097) @[dec_dec_ctl.scala 92:57]
|
||
|
|
node _T_1099 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1100 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1101 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1102 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1103 = and(_T_1099, _T_1100) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1104 = and(_T_1103, _T_1101) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1105 = and(_T_1104, _T_1102) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1106 = or(_T_1098, _T_1105) @[dec_dec_ctl.scala 93:30]
|
||
|
|
node _T_1107 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1108 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1109 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1110 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1111 = and(_T_1107, _T_1108) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1112 = and(_T_1111, _T_1109) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1113 = and(_T_1112, _T_1110) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1114 = or(_T_1106, _T_1113) @[dec_dec_ctl.scala 93:57]
|
||
|
|
io.out.presync <= _T_1114 @[dec_dec_ctl.scala 89:18]
|
||
|
|
node _T_1115 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1116 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1118 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1119 = and(_T_1115, _T_1117) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1120 = and(_T_1119, _T_1118) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1121 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1123 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1125 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1127 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1128 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1129 = and(_T_1122, _T_1124) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1130 = and(_T_1129, _T_1126) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1131 = and(_T_1130, _T_1127) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1132 = and(_T_1131, _T_1128) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1133 = or(_T_1120, _T_1132) @[dec_dec_ctl.scala 95:45]
|
||
|
|
node _T_1134 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1135 = eq(_T_1134, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1136 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1137 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1138 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1139 = and(_T_1135, _T_1136) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1140 = and(_T_1139, _T_1137) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1141 = and(_T_1140, _T_1138) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1142 = or(_T_1133, _T_1141) @[dec_dec_ctl.scala 95:78]
|
||
|
|
node _T_1143 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1145 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1146 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1147 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1148 = and(_T_1144, _T_1145) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1149 = and(_T_1148, _T_1146) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1150 = and(_T_1149, _T_1147) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1151 = or(_T_1142, _T_1150) @[dec_dec_ctl.scala 96:30]
|
||
|
|
node _T_1152 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1154 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1155 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1156 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1157 = and(_T_1153, _T_1154) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1158 = and(_T_1157, _T_1155) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1159 = and(_T_1158, _T_1156) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1160 = or(_T_1151, _T_1159) @[dec_dec_ctl.scala 96:57]
|
||
|
|
node _T_1161 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1163 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1164 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1165 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1166 = and(_T_1162, _T_1163) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1167 = and(_T_1166, _T_1164) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1168 = and(_T_1167, _T_1165) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1169 = or(_T_1160, _T_1168) @[dec_dec_ctl.scala 97:30]
|
||
|
|
node _T_1170 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1172 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1173 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1174 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1175 = and(_T_1171, _T_1172) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1176 = and(_T_1175, _T_1173) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1177 = and(_T_1176, _T_1174) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1178 = or(_T_1169, _T_1177) @[dec_dec_ctl.scala 97:58]
|
||
|
|
node _T_1179 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1180 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1181 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1182 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1183 = and(_T_1179, _T_1180) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1184 = and(_T_1183, _T_1181) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1185 = and(_T_1184, _T_1182) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1186 = or(_T_1178, _T_1185) @[dec_dec_ctl.scala 98:31]
|
||
|
|
node _T_1187 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1188 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1189 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1190 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1191 = and(_T_1187, _T_1188) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1192 = and(_T_1191, _T_1189) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1193 = and(_T_1192, _T_1190) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1194 = or(_T_1186, _T_1193) @[dec_dec_ctl.scala 98:58]
|
||
|
|
node _T_1195 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1196 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1197 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1198 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1199 = and(_T_1195, _T_1196) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1200 = and(_T_1199, _T_1197) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1201 = and(_T_1200, _T_1198) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1202 = or(_T_1194, _T_1201) @[dec_dec_ctl.scala 99:30]
|
||
|
|
node _T_1203 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1204 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1205 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1206 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1207 = and(_T_1203, _T_1204) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1208 = and(_T_1207, _T_1205) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1209 = and(_T_1208, _T_1206) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1210 = or(_T_1202, _T_1209) @[dec_dec_ctl.scala 99:57]
|
||
|
|
node _T_1211 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1212 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1213 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1214 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1215 = and(_T_1211, _T_1212) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1216 = and(_T_1215, _T_1213) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1217 = and(_T_1216, _T_1214) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1218 = or(_T_1210, _T_1217) @[dec_dec_ctl.scala 100:30]
|
||
|
|
io.out.postsync <= _T_1218 @[dec_dec_ctl.scala 95:19]
|
||
|
|
node _T_1219 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1220 = eq(_T_1219, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1221 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1223 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1224 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1225 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1227 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1228 = eq(_T_1227, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1229 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1231 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1233 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1235 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1237 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1238 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1240 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1242 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1243 = eq(_T_1242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1244 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1246 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1247 = eq(_T_1246, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1248 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1250 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1252 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1254 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1256 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1258 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1260 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1262 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1263 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1264 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1265 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1266 = eq(_T_1265, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1267 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1269 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1270 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1271 = and(_T_1220, _T_1222) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1272 = and(_T_1271, _T_1223) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1273 = and(_T_1272, _T_1224) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1274 = and(_T_1273, _T_1226) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1275 = and(_T_1274, _T_1228) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1276 = and(_T_1275, _T_1230) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1277 = and(_T_1276, _T_1232) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1278 = and(_T_1277, _T_1234) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1279 = and(_T_1278, _T_1236) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1280 = and(_T_1279, _T_1237) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1281 = and(_T_1280, _T_1239) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1282 = and(_T_1281, _T_1241) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1283 = and(_T_1282, _T_1243) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1284 = and(_T_1283, _T_1245) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1285 = and(_T_1284, _T_1247) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1286 = and(_T_1285, _T_1249) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1287 = and(_T_1286, _T_1251) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1288 = and(_T_1287, _T_1253) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1289 = and(_T_1288, _T_1255) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1290 = and(_T_1289, _T_1257) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1291 = and(_T_1290, _T_1259) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1292 = and(_T_1291, _T_1261) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1293 = and(_T_1292, _T_1262) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1294 = and(_T_1293, _T_1263) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1295 = and(_T_1294, _T_1264) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1296 = and(_T_1295, _T_1266) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1297 = and(_T_1296, _T_1268) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1298 = and(_T_1297, _T_1269) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1299 = and(_T_1298, _T_1270) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1300 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1302 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1304 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1306 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1307 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1309 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1311 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1313 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1315 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1317 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1318 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1320 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1321 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1323 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1324 = eq(_T_1323, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1325 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1326 = eq(_T_1325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1327 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1329 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1331 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1332 = eq(_T_1331, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1333 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1334 = eq(_T_1333, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1335 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1337 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1338 = eq(_T_1337, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1339 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1340 = eq(_T_1339, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1341 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1342 = eq(_T_1341, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1343 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1344 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1345 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1346 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1348 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1350 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1351 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1352 = and(_T_1301, _T_1303) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1353 = and(_T_1352, _T_1305) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1354 = and(_T_1353, _T_1306) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1355 = and(_T_1354, _T_1308) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1356 = and(_T_1355, _T_1310) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1357 = and(_T_1356, _T_1312) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1358 = and(_T_1357, _T_1314) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1359 = and(_T_1358, _T_1316) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1360 = and(_T_1359, _T_1317) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1361 = and(_T_1360, _T_1319) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1362 = and(_T_1361, _T_1320) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1363 = and(_T_1362, _T_1322) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1364 = and(_T_1363, _T_1324) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1365 = and(_T_1364, _T_1326) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1366 = and(_T_1365, _T_1328) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1367 = and(_T_1366, _T_1330) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1368 = and(_T_1367, _T_1332) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1369 = and(_T_1368, _T_1334) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1370 = and(_T_1369, _T_1336) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1371 = and(_T_1370, _T_1338) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1372 = and(_T_1371, _T_1340) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1373 = and(_T_1372, _T_1342) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1374 = and(_T_1373, _T_1343) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1375 = and(_T_1374, _T_1344) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1376 = and(_T_1375, _T_1345) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1377 = and(_T_1376, _T_1347) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1378 = and(_T_1377, _T_1349) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1379 = and(_T_1378, _T_1350) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1380 = and(_T_1379, _T_1351) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1381 = or(_T_1299, _T_1380) @[dec_dec_ctl.scala 101:136]
|
||
|
|
node _T_1382 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1383 = eq(_T_1382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1384 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1385 = eq(_T_1384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1386 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1388 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1390 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1391 = eq(_T_1390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1392 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1394 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1396 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1398 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1400 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1402 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1404 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1406 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1408 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1410 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1412 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1414 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1416 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1418 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1420 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1422 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1424 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1426 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1427 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1428 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1430 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1432 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1433 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1434 = and(_T_1383, _T_1385) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1435 = and(_T_1434, _T_1387) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1436 = and(_T_1435, _T_1389) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1437 = and(_T_1436, _T_1391) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1438 = and(_T_1437, _T_1393) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1439 = and(_T_1438, _T_1395) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1440 = and(_T_1439, _T_1397) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1441 = and(_T_1440, _T_1399) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1442 = and(_T_1441, _T_1401) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1443 = and(_T_1442, _T_1403) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1444 = and(_T_1443, _T_1405) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1445 = and(_T_1444, _T_1407) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1446 = and(_T_1445, _T_1409) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1447 = and(_T_1446, _T_1411) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1448 = and(_T_1447, _T_1413) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1449 = and(_T_1448, _T_1415) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1450 = and(_T_1449, _T_1417) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1451 = and(_T_1450, _T_1419) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1452 = and(_T_1451, _T_1421) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1453 = and(_T_1452, _T_1423) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1454 = and(_T_1453, _T_1425) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1455 = and(_T_1454, _T_1426) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1456 = and(_T_1455, _T_1427) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1457 = and(_T_1456, _T_1429) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1458 = and(_T_1457, _T_1431) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1459 = and(_T_1458, _T_1432) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1460 = and(_T_1459, _T_1433) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1461 = or(_T_1381, _T_1460) @[dec_dec_ctl.scala 102:122]
|
||
|
|
node _T_1462 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1464 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1465 = eq(_T_1464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1466 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1467 = eq(_T_1466, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1468 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1469 = eq(_T_1468, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1470 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1472 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1473 = eq(_T_1472, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1474 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1475 = eq(_T_1474, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1476 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1478 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1479 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1481 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1482 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1483 = and(_T_1463, _T_1465) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1484 = and(_T_1483, _T_1467) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1485 = and(_T_1484, _T_1469) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1486 = and(_T_1485, _T_1471) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1487 = and(_T_1486, _T_1473) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1488 = and(_T_1487, _T_1475) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1489 = and(_T_1488, _T_1477) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1490 = and(_T_1489, _T_1478) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1491 = and(_T_1490, _T_1480) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1492 = and(_T_1491, _T_1481) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1493 = and(_T_1492, _T_1482) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1494 = or(_T_1461, _T_1493) @[dec_dec_ctl.scala 103:119]
|
||
|
|
node _T_1495 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1497 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1499 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1500 = eq(_T_1499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1501 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1502 = eq(_T_1501, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1503 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1504 = eq(_T_1503, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1505 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1507 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1509 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1511 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1513 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1515 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1517 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1519 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1520 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1521 = and(_T_1496, _T_1498) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1522 = and(_T_1521, _T_1500) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1523 = and(_T_1522, _T_1502) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1524 = and(_T_1523, _T_1504) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1525 = and(_T_1524, _T_1506) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1526 = and(_T_1525, _T_1508) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1527 = and(_T_1526, _T_1510) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1528 = and(_T_1527, _T_1512) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1529 = and(_T_1528, _T_1514) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1530 = and(_T_1529, _T_1516) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1531 = and(_T_1530, _T_1518) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1532 = and(_T_1531, _T_1519) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1533 = and(_T_1532, _T_1520) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1534 = or(_T_1494, _T_1533) @[dec_dec_ctl.scala 104:60]
|
||
|
|
node _T_1535 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1536 = eq(_T_1535, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1537 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1539 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1541 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1542 = eq(_T_1541, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1543 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1544 = eq(_T_1543, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1545 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1547 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1548 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1550 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1551 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1552 = eq(_T_1551, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1553 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1554 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1556 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1557 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1558 = and(_T_1536, _T_1538) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1559 = and(_T_1558, _T_1540) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1560 = and(_T_1559, _T_1542) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1561 = and(_T_1560, _T_1544) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1562 = and(_T_1561, _T_1546) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1563 = and(_T_1562, _T_1547) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1564 = and(_T_1563, _T_1549) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1565 = and(_T_1564, _T_1550) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1566 = and(_T_1565, _T_1552) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1567 = and(_T_1566, _T_1553) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1568 = and(_T_1567, _T_1555) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1569 = and(_T_1568, _T_1556) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1570 = and(_T_1569, _T_1557) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1571 = or(_T_1534, _T_1570) @[dec_dec_ctl.scala 105:69]
|
||
|
|
node _T_1572 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1574 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1575 = eq(_T_1574, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1576 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1578 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1579 = eq(_T_1578, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1580 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1581 = eq(_T_1580, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1582 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1584 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1586 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1587 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1588 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1590 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1591 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1592 = and(_T_1573, _T_1575) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1593 = and(_T_1592, _T_1577) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1594 = and(_T_1593, _T_1579) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1595 = and(_T_1594, _T_1581) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1596 = and(_T_1595, _T_1583) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1597 = and(_T_1596, _T_1585) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1598 = and(_T_1597, _T_1586) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1599 = and(_T_1598, _T_1587) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1600 = and(_T_1599, _T_1589) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1601 = and(_T_1600, _T_1590) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1602 = and(_T_1601, _T_1591) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1603 = or(_T_1571, _T_1602) @[dec_dec_ctl.scala 106:66]
|
||
|
|
node _T_1604 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1606 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1607 = eq(_T_1606, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1608 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1609 = eq(_T_1608, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1610 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1611 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1614 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1615 = eq(_T_1614, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1616 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1617 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1618 = and(_T_1605, _T_1607) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1619 = and(_T_1618, _T_1609) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1620 = and(_T_1619, _T_1610) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1621 = and(_T_1620, _T_1611) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1622 = and(_T_1621, _T_1613) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1623 = and(_T_1622, _T_1615) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1624 = and(_T_1623, _T_1616) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1625 = and(_T_1624, _T_1617) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1626 = or(_T_1603, _T_1625) @[dec_dec_ctl.scala 107:58]
|
||
|
|
node _T_1627 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1628 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1629 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1630 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1632 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1633 = eq(_T_1632, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1634 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1636 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1637 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1638 = and(_T_1627, _T_1628) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1639 = and(_T_1638, _T_1629) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1640 = and(_T_1639, _T_1631) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1641 = and(_T_1640, _T_1633) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1642 = and(_T_1641, _T_1635) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1643 = and(_T_1642, _T_1636) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1644 = and(_T_1643, _T_1637) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1645 = or(_T_1626, _T_1644) @[dec_dec_ctl.scala 108:46]
|
||
|
|
node _T_1646 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1647 = eq(_T_1646, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1648 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1650 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1652 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1653 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1655 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1656 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1657 = and(_T_1647, _T_1649) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1658 = and(_T_1657, _T_1651) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1659 = and(_T_1658, _T_1652) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1660 = and(_T_1659, _T_1654) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1661 = and(_T_1660, _T_1655) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1662 = and(_T_1661, _T_1656) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1663 = or(_T_1645, _T_1662) @[dec_dec_ctl.scala 109:40]
|
||
|
|
node _T_1664 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1666 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1668 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1669 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1671 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1672 = eq(_T_1671, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1673 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1675 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1676 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1677 = and(_T_1665, _T_1667) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1678 = and(_T_1677, _T_1668) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1679 = and(_T_1678, _T_1670) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1680 = and(_T_1679, _T_1672) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1681 = and(_T_1680, _T_1674) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1682 = and(_T_1681, _T_1675) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1683 = and(_T_1682, _T_1676) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1684 = or(_T_1663, _T_1683) @[dec_dec_ctl.scala 110:39]
|
||
|
|
node _T_1685 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1686 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1687 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1688 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1689 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1691 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1693 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1694 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1695 = and(_T_1685, _T_1686) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1696 = and(_T_1695, _T_1687) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1697 = and(_T_1696, _T_1688) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1698 = and(_T_1697, _T_1690) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1699 = and(_T_1698, _T_1692) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1700 = and(_T_1699, _T_1693) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1701 = and(_T_1700, _T_1694) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1702 = or(_T_1684, _T_1701) @[dec_dec_ctl.scala 111:43]
|
||
|
|
node _T_1703 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1704 = eq(_T_1703, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1705 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1706 = eq(_T_1705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1707 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1708 = eq(_T_1707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1709 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1711 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1712 = eq(_T_1711, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1713 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1715 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1717 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1718 = eq(_T_1717, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1719 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1720 = eq(_T_1719, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1721 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1722 = eq(_T_1721, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1723 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1725 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1727 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1729 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1731 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1733 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1735 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1737 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1739 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1741 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1743 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1745 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1747 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1749 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1751 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1753 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1755 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1757 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1758 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1759 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1760 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1761 = and(_T_1704, _T_1706) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1762 = and(_T_1761, _T_1708) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1763 = and(_T_1762, _T_1710) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1764 = and(_T_1763, _T_1712) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1765 = and(_T_1764, _T_1714) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1766 = and(_T_1765, _T_1716) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1767 = and(_T_1766, _T_1718) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1768 = and(_T_1767, _T_1720) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1769 = and(_T_1768, _T_1722) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1770 = and(_T_1769, _T_1724) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1771 = and(_T_1770, _T_1726) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1772 = and(_T_1771, _T_1728) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1773 = and(_T_1772, _T_1730) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1774 = and(_T_1773, _T_1732) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1775 = and(_T_1774, _T_1734) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1776 = and(_T_1775, _T_1736) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1777 = and(_T_1776, _T_1738) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1778 = and(_T_1777, _T_1740) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1779 = and(_T_1778, _T_1742) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1780 = and(_T_1779, _T_1744) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1781 = and(_T_1780, _T_1746) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1782 = and(_T_1781, _T_1748) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1783 = and(_T_1782, _T_1750) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1784 = and(_T_1783, _T_1752) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1785 = and(_T_1784, _T_1754) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1786 = and(_T_1785, _T_1756) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1787 = and(_T_1786, _T_1757) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1788 = and(_T_1787, _T_1758) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1789 = and(_T_1788, _T_1759) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1790 = and(_T_1789, _T_1760) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1791 = or(_T_1702, _T_1790) @[dec_dec_ctl.scala 112:39]
|
||
|
|
node _T_1792 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1793 = eq(_T_1792, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1794 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1796 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1798 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1799 = eq(_T_1798, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1800 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1802 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1803 = eq(_T_1802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1804 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1806 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1807 = eq(_T_1806, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1808 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1809 = eq(_T_1808, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1810 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1811 = eq(_T_1810, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1812 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1813 = eq(_T_1812, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1814 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1815 = eq(_T_1814, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1816 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1817 = eq(_T_1816, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1818 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1820 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1822 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1824 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1826 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1828 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1830 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1832 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1833 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1834 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1835 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1836 = and(_T_1793, _T_1795) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1837 = and(_T_1836, _T_1797) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1838 = and(_T_1837, _T_1799) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1839 = and(_T_1838, _T_1801) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1840 = and(_T_1839, _T_1803) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1841 = and(_T_1840, _T_1805) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1842 = and(_T_1841, _T_1807) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1843 = and(_T_1842, _T_1809) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1844 = and(_T_1843, _T_1811) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1845 = and(_T_1844, _T_1813) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1846 = and(_T_1845, _T_1815) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1847 = and(_T_1846, _T_1817) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1848 = and(_T_1847, _T_1819) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1849 = and(_T_1848, _T_1821) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1850 = and(_T_1849, _T_1823) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1851 = and(_T_1850, _T_1825) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1852 = and(_T_1851, _T_1827) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1853 = and(_T_1852, _T_1829) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1854 = and(_T_1853, _T_1831) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1855 = and(_T_1854, _T_1832) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1856 = and(_T_1855, _T_1833) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1857 = and(_T_1856, _T_1834) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1858 = and(_T_1857, _T_1835) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1859 = or(_T_1791, _T_1858) @[dec_dec_ctl.scala 113:130]
|
||
|
|
node _T_1860 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1861 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1862 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1863 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1864 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1866 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1867 = eq(_T_1866, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1868 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1869 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1870 = and(_T_1860, _T_1861) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1871 = and(_T_1870, _T_1862) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1872 = and(_T_1871, _T_1863) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1873 = and(_T_1872, _T_1865) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1874 = and(_T_1873, _T_1867) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1875 = and(_T_1874, _T_1868) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1876 = and(_T_1875, _T_1869) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1877 = or(_T_1859, _T_1876) @[dec_dec_ctl.scala 114:102]
|
||
|
|
node _T_1878 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1879 = eq(_T_1878, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1880 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1881 = eq(_T_1880, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1882 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1884 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1885 = eq(_T_1884, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1886 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1887 = eq(_T_1886, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1888 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1889 = eq(_T_1888, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1890 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1891 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1892 = and(_T_1879, _T_1881) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1893 = and(_T_1892, _T_1883) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1894 = and(_T_1893, _T_1885) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1895 = and(_T_1894, _T_1887) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1896 = and(_T_1895, _T_1889) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1897 = and(_T_1896, _T_1890) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1898 = and(_T_1897, _T_1891) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1899 = or(_T_1877, _T_1898) @[dec_dec_ctl.scala 115:39]
|
||
|
|
node _T_1900 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1901 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1902 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1903 = eq(_T_1902, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1904 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1905 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1906 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1907 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1908 = and(_T_1900, _T_1901) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1909 = and(_T_1908, _T_1903) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1910 = and(_T_1909, _T_1904) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1911 = and(_T_1910, _T_1905) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1912 = and(_T_1911, _T_1906) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1913 = and(_T_1912, _T_1907) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1914 = or(_T_1899, _T_1913) @[dec_dec_ctl.scala 116:43]
|
||
|
|
node _T_1915 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1916 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1917 = eq(_T_1916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1918 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1920 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1921 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1922 = eq(_T_1921, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1923 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1924 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1925 = and(_T_1915, _T_1917) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1926 = and(_T_1925, _T_1919) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1927 = and(_T_1926, _T_1920) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1928 = and(_T_1927, _T_1922) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1929 = and(_T_1928, _T_1923) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1930 = and(_T_1929, _T_1924) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1931 = or(_T_1914, _T_1930) @[dec_dec_ctl.scala 117:35]
|
||
|
|
node _T_1932 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1934 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1936 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1937 = eq(_T_1936, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1938 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1940 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1942 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1943 = eq(_T_1942, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1944 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1945 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1946 = and(_T_1933, _T_1935) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1947 = and(_T_1946, _T_1937) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1948 = and(_T_1947, _T_1939) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1949 = and(_T_1948, _T_1941) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1950 = and(_T_1949, _T_1943) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1951 = and(_T_1950, _T_1944) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1952 = and(_T_1951, _T_1945) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1953 = or(_T_1931, _T_1952) @[dec_dec_ctl.scala 118:38]
|
||
|
|
node _T_1954 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1956 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1957 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
||
|
|
node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
||
|
|
node _T_1959 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1960 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1961 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
||
|
|
node _T_1962 = and(_T_1955, _T_1956) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1963 = and(_T_1962, _T_1958) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1964 = and(_T_1963, _T_1959) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1965 = and(_T_1964, _T_1960) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1966 = and(_T_1965, _T_1961) @[dec_dec_ctl.scala 17:17]
|
||
|
|
node _T_1967 = or(_T_1953, _T_1966) @[dec_dec_ctl.scala 119:44]
|
||
|
|
io.out.legal <= _T_1967 @[dec_dec_ctl.scala 101:16]
|
||
|
|
|
||
|
|
extmodule gated_latch_1 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_1 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_2 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_2 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_3 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_3 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_4 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_4 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_5 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_5 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_6 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_6 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_7 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_7 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_8 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_8 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_9 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_9 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_10 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_10 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_11 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_11 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_11 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_12 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_12 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_12 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_13 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_13 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_13 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_14 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_14 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_14 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_15 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_15 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_15 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_16 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_16 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_16 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_17 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_17 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_17 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_18 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_18 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_18 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_19 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_19 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_19 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
module dec_decode_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits
|
||
|
|
|
||
|
|
wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
_T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
|
||
|
|
io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 95:25]
|
||
|
|
io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 95:25]
|
||
|
|
wire leak1_i1_stall_in : UInt<1>
|
||
|
|
leak1_i1_stall_in <= UInt<1>("h00")
|
||
|
|
wire leak1_i0_stall_in : UInt<1>
|
||
|
|
leak1_i0_stall_in <= UInt<1>("h00")
|
||
|
|
wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 99:37]
|
||
|
|
wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 100:37]
|
||
|
|
wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 101:37]
|
||
|
|
wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:37]
|
||
|
|
wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:37]
|
||
|
|
wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:37]
|
||
|
|
wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 105:37]
|
||
|
|
wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 106:37]
|
||
|
|
wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:37]
|
||
|
|
wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:37]
|
||
|
|
wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:37]
|
||
|
|
wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 110:37]
|
||
|
|
wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 111:37]
|
||
|
|
wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:37]
|
||
|
|
wire i0_rs1_depth_d : UInt<2>
|
||
|
|
i0_rs1_depth_d <= UInt<1>("h00")
|
||
|
|
wire i0_rs2_depth_d : UInt<2>
|
||
|
|
i0_rs2_depth_d <= UInt<1>("h00")
|
||
|
|
wire cam_wen : UInt<4>
|
||
|
|
cam_wen <= UInt<1>("h00")
|
||
|
|
wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 116:37]
|
||
|
|
wire cam_write : UInt<1>
|
||
|
|
cam_write <= UInt<1>("h00")
|
||
|
|
wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 118:37]
|
||
|
|
wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 119:37]
|
||
|
|
wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 120:37]
|
||
|
|
wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 121:37]
|
||
|
|
wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 122:37]
|
||
|
|
wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 123:37]
|
||
|
|
wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 124:37]
|
||
|
|
wire i0_rs1bypass : UInt<3>
|
||
|
|
i0_rs1bypass <= UInt<1>("h00")
|
||
|
|
wire i0_rs2bypass : UInt<3>
|
||
|
|
i0_rs2bypass <= UInt<1>("h00")
|
||
|
|
wire illegal_lockout : UInt<1>
|
||
|
|
illegal_lockout <= UInt<1>("h00")
|
||
|
|
wire postsync_stall : UInt<1>
|
||
|
|
postsync_stall <= UInt<1>("h00")
|
||
|
|
wire ps_stall_in : UInt<1>
|
||
|
|
ps_stall_in <= UInt<1>("h00")
|
||
|
|
wire i0_pipe_en : UInt<4>
|
||
|
|
i0_pipe_en <= UInt<1>("h00")
|
||
|
|
wire i0_load_block_d : UInt<1>
|
||
|
|
i0_load_block_d <= UInt<1>("h00")
|
||
|
|
wire load_ldst_bypass_d : UInt<1>
|
||
|
|
load_ldst_bypass_d <= UInt<1>("h00")
|
||
|
|
wire store_data_bypass_d : UInt<1>
|
||
|
|
store_data_bypass_d <= UInt<1>("h00")
|
||
|
|
wire store_data_bypass_m : UInt<1>
|
||
|
|
store_data_bypass_m <= UInt<1>("h00")
|
||
|
|
wire tlu_wr_pause_r1 : UInt<1>
|
||
|
|
tlu_wr_pause_r1 <= UInt<1>("h00")
|
||
|
|
wire tlu_wr_pause_r2 : UInt<1>
|
||
|
|
tlu_wr_pause_r2 <= UInt<1>("h00")
|
||
|
|
wire leak1_i1_stall : UInt<1>
|
||
|
|
leak1_i1_stall <= UInt<1>("h00")
|
||
|
|
wire leak1_i0_stall : UInt<1>
|
||
|
|
leak1_i0_stall <= UInt<1>("h00")
|
||
|
|
wire pause_stall : UInt<1>
|
||
|
|
pause_stall <= UInt<1>("h00")
|
||
|
|
wire flush_final_r : UInt<1>
|
||
|
|
flush_final_r <= UInt<1>("h00")
|
||
|
|
wire illegal_lockout_in : UInt<1>
|
||
|
|
illegal_lockout_in <= UInt<1>("h00")
|
||
|
|
wire lsu_idle : UInt<1>
|
||
|
|
lsu_idle <= UInt<1>("h00")
|
||
|
|
wire pause_state_in : UInt<1>
|
||
|
|
pause_state_in <= UInt<1>("h00")
|
||
|
|
wire leak1_mode : UInt<1>
|
||
|
|
leak1_mode <= UInt<1>("h00")
|
||
|
|
wire i0_pcall : UInt<1>
|
||
|
|
i0_pcall <= UInt<1>("h00")
|
||
|
|
wire i0_pja : UInt<1>
|
||
|
|
i0_pja <= UInt<1>("h00")
|
||
|
|
wire i0_pret : UInt<1>
|
||
|
|
i0_pret <= UInt<1>("h00")
|
||
|
|
wire i0_legal_decode_d : UInt<1>
|
||
|
|
i0_legal_decode_d <= UInt<1>("h00")
|
||
|
|
wire i0_pcall_raw : UInt<1>
|
||
|
|
i0_pcall_raw <= UInt<1>("h00")
|
||
|
|
wire i0_pja_raw : UInt<1>
|
||
|
|
i0_pja_raw <= UInt<1>("h00")
|
||
|
|
wire i0_pret_raw : UInt<1>
|
||
|
|
i0_pret_raw <= UInt<1>("h00")
|
||
|
|
wire i0_br_offset : UInt<12>
|
||
|
|
i0_br_offset <= UInt<1>("h00")
|
||
|
|
wire i0_csr_write_only_d : UInt<1>
|
||
|
|
i0_csr_write_only_d <= UInt<1>("h00")
|
||
|
|
wire i0_jal : UInt<1>
|
||
|
|
i0_jal <= UInt<1>("h00")
|
||
|
|
wire i0_wen_r : UInt<1>
|
||
|
|
i0_wen_r <= UInt<1>("h00")
|
||
|
|
wire i0_x_ctl_en : UInt<1>
|
||
|
|
i0_x_ctl_en <= UInt<1>("h00")
|
||
|
|
wire i0_r_ctl_en : UInt<1>
|
||
|
|
i0_r_ctl_en <= UInt<1>("h00")
|
||
|
|
wire i0_wb_ctl_en : UInt<1>
|
||
|
|
i0_wb_ctl_en <= UInt<1>("h00")
|
||
|
|
wire i0_x_data_en : UInt<1>
|
||
|
|
i0_x_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_r_data_en : UInt<1>
|
||
|
|
i0_r_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_wb_data_en : UInt<1>
|
||
|
|
i0_wb_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_wb1_data_en : UInt<1>
|
||
|
|
i0_wb1_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_nonblock_load_stall : UInt<1>
|
||
|
|
i0_nonblock_load_stall <= UInt<1>("h00")
|
||
|
|
wire csr_read : UInt<1>
|
||
|
|
csr_read <= UInt<1>("h00")
|
||
|
|
wire lsu_decode_d : UInt<1>
|
||
|
|
lsu_decode_d <= UInt<1>("h00")
|
||
|
|
wire mul_decode_d : UInt<1>
|
||
|
|
mul_decode_d <= UInt<1>("h00")
|
||
|
|
wire div_decode_d : UInt<1>
|
||
|
|
div_decode_d <= UInt<1>("h00")
|
||
|
|
wire write_csr_data : UInt<32>
|
||
|
|
write_csr_data <= UInt<1>("h00")
|
||
|
|
wire i0_result_corr_r : UInt<32>
|
||
|
|
i0_result_corr_r <= UInt<1>("h00")
|
||
|
|
wire presync_stall : UInt<1>
|
||
|
|
presync_stall <= UInt<1>("h00")
|
||
|
|
wire i0_nonblock_div_stall : UInt<1>
|
||
|
|
i0_nonblock_div_stall <= UInt<1>("h00")
|
||
|
|
wire debug_fence : UInt<1>
|
||
|
|
debug_fence <= UInt<1>("h00")
|
||
|
|
wire i0_immed_d : UInt<32>
|
||
|
|
i0_immed_d <= UInt<1>("h00")
|
||
|
|
wire i0_result_x : UInt<32>
|
||
|
|
i0_result_x <= UInt<1>("h00")
|
||
|
|
wire i0_result_r : UInt<32>
|
||
|
|
i0_result_r <= UInt<1>("h00")
|
||
|
|
node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 178:54]
|
||
|
|
node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 179:54]
|
||
|
|
node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 178:89]
|
||
|
|
node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 180:54]
|
||
|
|
node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 179:89]
|
||
|
|
node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 181:54]
|
||
|
|
node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 180:89]
|
||
|
|
node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 182:54]
|
||
|
|
node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 181:89]
|
||
|
|
node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 183:54]
|
||
|
|
node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 182:89]
|
||
|
|
node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 184:54]
|
||
|
|
node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 183:89]
|
||
|
|
node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 185:54]
|
||
|
|
node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 184:89]
|
||
|
|
node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 186:54]
|
||
|
|
node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 185:89]
|
||
|
|
node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 189:57]
|
||
|
|
inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr.io.en <= _T_17 @[lib.scala 345:16]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||
|
|
node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 192:80]
|
||
|
|
node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 192:78]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 193:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 194:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 195:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 196:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 197:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 198:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 199:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 200:55]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 201:55]
|
||
|
|
node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 202:71]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 202:55]
|
||
|
|
node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 203:92]
|
||
|
|
node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 203:107]
|
||
|
|
node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 203:120]
|
||
|
|
node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 203:73]
|
||
|
|
node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 203:71]
|
||
|
|
node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 206:97]
|
||
|
|
node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 206:72]
|
||
|
|
node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 206:131]
|
||
|
|
node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 206:101]
|
||
|
|
node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 206:151]
|
||
|
|
node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 206:149]
|
||
|
|
node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 207:72]
|
||
|
|
node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 207:99]
|
||
|
|
node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 207:97]
|
||
|
|
node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 208:87]
|
||
|
|
node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 208:104]
|
||
|
|
node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 208:126]
|
||
|
|
node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 209:72]
|
||
|
|
node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 209:94]
|
||
|
|
node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 209:92]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 209:56]
|
||
|
|
node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 210:94]
|
||
|
|
node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 210:116]
|
||
|
|
node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 210:114]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 210:56]
|
||
|
|
io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 211:56]
|
||
|
|
io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 212:56]
|
||
|
|
node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 213:72]
|
||
|
|
node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:111]
|
||
|
|
node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 213:109]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 214:56]
|
||
|
|
io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 215:56]
|
||
|
|
io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 216:56]
|
||
|
|
node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 222:43]
|
||
|
|
i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 224:23]
|
||
|
|
i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 224:23]
|
||
|
|
node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 225:25]
|
||
|
|
node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 225:43]
|
||
|
|
when _T_42 : @[dec_decode_ctl.scala 225:50]
|
||
|
|
wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
_T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
|
||
|
|
i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 226:23]
|
||
|
|
i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 227:23]
|
||
|
|
i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 228:23]
|
||
|
|
i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 229:23]
|
||
|
|
i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 230:23]
|
||
|
|
i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 231:23]
|
||
|
|
i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 232:23]
|
||
|
|
skip @[dec_decode_ctl.scala 225:50]
|
||
|
|
io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 236:36]
|
||
|
|
node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 239:54]
|
||
|
|
node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 239:65]
|
||
|
|
node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 239:74]
|
||
|
|
node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 240:65]
|
||
|
|
node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 240:69]
|
||
|
|
node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 240:40]
|
||
|
|
node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 240:85]
|
||
|
|
node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 241:65]
|
||
|
|
node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 241:69]
|
||
|
|
node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 241:85]
|
||
|
|
node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 242:40]
|
||
|
|
io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 244:37]
|
||
|
|
io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 245:37]
|
||
|
|
io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 247:37]
|
||
|
|
io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 248:37]
|
||
|
|
io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 249:37]
|
||
|
|
io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 250:37]
|
||
|
|
io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 251:37]
|
||
|
|
io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 252:37]
|
||
|
|
io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 253:37]
|
||
|
|
io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 254:37]
|
||
|
|
io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 255:37]
|
||
|
|
io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 256:37]
|
||
|
|
io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 257:37]
|
||
|
|
io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 258:37]
|
||
|
|
io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 259:37]
|
||
|
|
io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 260:37]
|
||
|
|
io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 261:37]
|
||
|
|
io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 262:37]
|
||
|
|
io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 263:37]
|
||
|
|
node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
|
||
|
|
node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 267:137]
|
||
|
|
node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 267:158]
|
||
|
|
node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
|
||
|
|
node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120]
|
||
|
|
node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 267:129]
|
||
|
|
node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 267:126]
|
||
|
|
node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 267:137]
|
||
|
|
node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 267:158]
|
||
|
|
node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
|
||
|
|
node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120]
|
||
|
|
node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129]
|
||
|
|
node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 267:126]
|
||
|
|
node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 267:120]
|
||
|
|
node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 267:129]
|
||
|
|
node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 267:126]
|
||
|
|
node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 267:137]
|
||
|
|
node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 267:158]
|
||
|
|
node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
|
||
|
|
node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120]
|
||
|
|
node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129]
|
||
|
|
node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 267:126]
|
||
|
|
node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 267:120]
|
||
|
|
node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 267:129]
|
||
|
|
node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 267:126]
|
||
|
|
node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 267:120]
|
||
|
|
node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 267:129]
|
||
|
|
node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 267:126]
|
||
|
|
node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 267:137]
|
||
|
|
node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 267:158]
|
||
|
|
node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_84 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_85 = or(_T_81, _T_82) @[Mux.scala 27:72]
|
||
|
|
node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72]
|
||
|
|
node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72]
|
||
|
|
wire _T_88 : UInt<4> @[Mux.scala 27:72]
|
||
|
|
_T_88 <= _T_87 @[Mux.scala 27:72]
|
||
|
|
cam_wen <= _T_88 @[dec_decode_ctl.scala 267:11]
|
||
|
|
cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 269:25]
|
||
|
|
node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 270:67]
|
||
|
|
node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 275:76]
|
||
|
|
node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 278:48]
|
||
|
|
node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 278:31]
|
||
|
|
node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 282:129]
|
||
|
|
reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_90 : @[Reg.scala 28:19]
|
||
|
|
nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 283:56]
|
||
|
|
node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 285:66]
|
||
|
|
node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 285:45]
|
||
|
|
node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 285:87]
|
||
|
|
cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 285:26]
|
||
|
|
node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 286:67]
|
||
|
|
node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 286:45]
|
||
|
|
node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 286:88]
|
||
|
|
cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 286:27]
|
||
|
|
wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 288:11]
|
||
|
|
node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 290:32]
|
||
|
|
when _T_98 : @[dec_decode_ctl.scala 290:39]
|
||
|
|
cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
|
||
|
|
skip @[dec_decode_ctl.scala 290:39]
|
||
|
|
node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 293:17]
|
||
|
|
node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 293:21]
|
||
|
|
when _T_100 : @[dec_decode_ctl.scala 293:28]
|
||
|
|
cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
|
||
|
|
cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
|
||
|
|
cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
|
||
|
|
cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
|
||
|
|
skip @[dec_decode_ctl.scala 293:28]
|
||
|
|
else : @[dec_decode_ctl.scala 298:131]
|
||
|
|
node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 298:37]
|
||
|
|
node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
|
||
|
|
node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 298:85]
|
||
|
|
node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 298:64]
|
||
|
|
node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
|
||
|
|
node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 298:105]
|
||
|
|
node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 298:44]
|
||
|
|
when _T_107 : @[dec_decode_ctl.scala 298:131]
|
||
|
|
cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
|
||
|
|
skip @[dec_decode_ctl.scala 298:131]
|
||
|
|
else : @[dec_decode_ctl.scala 300:16]
|
||
|
|
cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 301:22]
|
||
|
|
skip @[dec_decode_ctl.scala 300:16]
|
||
|
|
node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
|
||
|
|
node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 303:92]
|
||
|
|
node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 303:44]
|
||
|
|
node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
|
||
|
|
node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 303:113]
|
||
|
|
when _T_112 : @[dec_decode_ctl.scala 303:135]
|
||
|
|
cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
|
||
|
|
skip @[dec_decode_ctl.scala 303:135]
|
||
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
|
||
|
|
cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
|
||
|
|
skip @[dec_decode_ctl.scala 307:32]
|
||
|
|
wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 311:47]
|
||
|
|
cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 311:15]
|
||
|
|
node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 312:46]
|
||
|
|
node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 312:71]
|
||
|
|
nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 312:28]
|
||
|
|
node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 285:66]
|
||
|
|
node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 285:45]
|
||
|
|
node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 285:87]
|
||
|
|
cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 285:26]
|
||
|
|
node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 286:67]
|
||
|
|
node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 286:45]
|
||
|
|
node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 286:88]
|
||
|
|
cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 286:27]
|
||
|
|
wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 288:11]
|
||
|
|
node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 290:32]
|
||
|
|
when _T_124 : @[dec_decode_ctl.scala 290:39]
|
||
|
|
cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
|
||
|
|
skip @[dec_decode_ctl.scala 290:39]
|
||
|
|
node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 293:17]
|
||
|
|
node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 293:21]
|
||
|
|
when _T_126 : @[dec_decode_ctl.scala 293:28]
|
||
|
|
cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
|
||
|
|
cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
|
||
|
|
cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
|
||
|
|
cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
|
||
|
|
skip @[dec_decode_ctl.scala 293:28]
|
||
|
|
else : @[dec_decode_ctl.scala 298:131]
|
||
|
|
node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 298:37]
|
||
|
|
node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
|
||
|
|
node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 298:85]
|
||
|
|
node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 298:64]
|
||
|
|
node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
|
||
|
|
node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 298:105]
|
||
|
|
node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 298:44]
|
||
|
|
when _T_133 : @[dec_decode_ctl.scala 298:131]
|
||
|
|
cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
|
||
|
|
skip @[dec_decode_ctl.scala 298:131]
|
||
|
|
else : @[dec_decode_ctl.scala 300:16]
|
||
|
|
cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 301:22]
|
||
|
|
skip @[dec_decode_ctl.scala 300:16]
|
||
|
|
node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
|
||
|
|
node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 303:92]
|
||
|
|
node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 303:44]
|
||
|
|
node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
|
||
|
|
node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 303:113]
|
||
|
|
when _T_138 : @[dec_decode_ctl.scala 303:135]
|
||
|
|
cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
|
||
|
|
skip @[dec_decode_ctl.scala 303:135]
|
||
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
|
||
|
|
cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
|
||
|
|
skip @[dec_decode_ctl.scala 307:32]
|
||
|
|
wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 311:47]
|
||
|
|
cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 311:15]
|
||
|
|
node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 312:46]
|
||
|
|
node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 312:71]
|
||
|
|
nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 312:28]
|
||
|
|
node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 285:66]
|
||
|
|
node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 285:45]
|
||
|
|
node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 285:87]
|
||
|
|
cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 285:26]
|
||
|
|
node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 286:67]
|
||
|
|
node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 286:45]
|
||
|
|
node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 286:88]
|
||
|
|
cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 286:27]
|
||
|
|
wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 288:11]
|
||
|
|
node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 290:32]
|
||
|
|
when _T_150 : @[dec_decode_ctl.scala 290:39]
|
||
|
|
cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
|
||
|
|
skip @[dec_decode_ctl.scala 290:39]
|
||
|
|
node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 293:17]
|
||
|
|
node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 293:21]
|
||
|
|
when _T_152 : @[dec_decode_ctl.scala 293:28]
|
||
|
|
cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
|
||
|
|
cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
|
||
|
|
cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
|
||
|
|
cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
|
||
|
|
skip @[dec_decode_ctl.scala 293:28]
|
||
|
|
else : @[dec_decode_ctl.scala 298:131]
|
||
|
|
node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 298:37]
|
||
|
|
node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
|
||
|
|
node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 298:85]
|
||
|
|
node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 298:64]
|
||
|
|
node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
|
||
|
|
node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 298:105]
|
||
|
|
node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 298:44]
|
||
|
|
when _T_159 : @[dec_decode_ctl.scala 298:131]
|
||
|
|
cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
|
||
|
|
skip @[dec_decode_ctl.scala 298:131]
|
||
|
|
else : @[dec_decode_ctl.scala 300:16]
|
||
|
|
cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 301:22]
|
||
|
|
skip @[dec_decode_ctl.scala 300:16]
|
||
|
|
node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
|
||
|
|
node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 303:92]
|
||
|
|
node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 303:44]
|
||
|
|
node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
|
||
|
|
node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 303:113]
|
||
|
|
when _T_164 : @[dec_decode_ctl.scala 303:135]
|
||
|
|
cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
|
||
|
|
skip @[dec_decode_ctl.scala 303:135]
|
||
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
|
||
|
|
cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
|
||
|
|
skip @[dec_decode_ctl.scala 307:32]
|
||
|
|
wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 311:47]
|
||
|
|
cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 311:15]
|
||
|
|
node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 312:46]
|
||
|
|
node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 312:71]
|
||
|
|
nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 312:28]
|
||
|
|
node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 285:66]
|
||
|
|
node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 285:45]
|
||
|
|
node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 285:87]
|
||
|
|
cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 285:26]
|
||
|
|
node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 286:67]
|
||
|
|
node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 286:45]
|
||
|
|
node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 286:88]
|
||
|
|
cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 286:27]
|
||
|
|
wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
_T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
|
||
|
|
cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 287:14]
|
||
|
|
cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 288:11]
|
||
|
|
cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 288:11]
|
||
|
|
node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 290:32]
|
||
|
|
when _T_176 : @[dec_decode_ctl.scala 290:39]
|
||
|
|
cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
|
||
|
|
skip @[dec_decode_ctl.scala 290:39]
|
||
|
|
node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 293:17]
|
||
|
|
node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 293:21]
|
||
|
|
when _T_178 : @[dec_decode_ctl.scala 293:28]
|
||
|
|
cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
|
||
|
|
cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
|
||
|
|
cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
|
||
|
|
cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
|
||
|
|
skip @[dec_decode_ctl.scala 293:28]
|
||
|
|
else : @[dec_decode_ctl.scala 298:131]
|
||
|
|
node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 298:37]
|
||
|
|
node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
|
||
|
|
node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 298:85]
|
||
|
|
node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 298:64]
|
||
|
|
node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
|
||
|
|
node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 298:105]
|
||
|
|
node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 298:44]
|
||
|
|
when _T_185 : @[dec_decode_ctl.scala 298:131]
|
||
|
|
cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
|
||
|
|
skip @[dec_decode_ctl.scala 298:131]
|
||
|
|
else : @[dec_decode_ctl.scala 300:16]
|
||
|
|
cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 301:22]
|
||
|
|
cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 301:22]
|
||
|
|
skip @[dec_decode_ctl.scala 300:16]
|
||
|
|
node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
|
||
|
|
node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 303:92]
|
||
|
|
node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 303:44]
|
||
|
|
node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
|
||
|
|
node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 303:113]
|
||
|
|
when _T_190 : @[dec_decode_ctl.scala 303:135]
|
||
|
|
cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
|
||
|
|
skip @[dec_decode_ctl.scala 303:135]
|
||
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
|
||
|
|
cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
|
||
|
|
skip @[dec_decode_ctl.scala 307:32]
|
||
|
|
wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
_T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
|
||
|
|
reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 311:47]
|
||
|
|
_T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 311:47]
|
||
|
|
cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 311:15]
|
||
|
|
cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 311:15]
|
||
|
|
node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 312:46]
|
||
|
|
node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 312:71]
|
||
|
|
nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 312:28]
|
||
|
|
io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 315:29]
|
||
|
|
node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 317:49]
|
||
|
|
node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 317:81]
|
||
|
|
node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 318:108]
|
||
|
|
node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 318:108]
|
||
|
|
node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 318:108]
|
||
|
|
node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 318:112]
|
||
|
|
node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 318:77]
|
||
|
|
node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 318:122]
|
||
|
|
node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 318:119]
|
||
|
|
io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 318:28]
|
||
|
|
node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 319:54]
|
||
|
|
node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:66]
|
||
|
|
node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 319:110]
|
||
|
|
node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 319:161]
|
||
|
|
node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:173]
|
||
|
|
node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 319:217]
|
||
|
|
node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 319:142]
|
||
|
|
i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 321:26]
|
||
|
|
node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 323:88]
|
||
|
|
node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:137]
|
||
|
|
node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
|
||
|
|
node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 323:152]
|
||
|
|
node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:214]
|
||
|
|
node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
|
||
|
|
node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 323:229]
|
||
|
|
node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 323:88]
|
||
|
|
node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:137]
|
||
|
|
node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
|
||
|
|
node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 323:152]
|
||
|
|
node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:214]
|
||
|
|
node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
|
||
|
|
node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 323:229]
|
||
|
|
node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 323:88]
|
||
|
|
node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:137]
|
||
|
|
node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
|
||
|
|
node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 323:152]
|
||
|
|
node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:214]
|
||
|
|
node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
|
||
|
|
node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 323:229]
|
||
|
|
node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 323:88]
|
||
|
|
node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:137]
|
||
|
|
node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
|
||
|
|
node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 323:152]
|
||
|
|
node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:214]
|
||
|
|
node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
|
||
|
|
node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 323:229]
|
||
|
|
node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 324:69]
|
||
|
|
node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 324:69]
|
||
|
|
node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 324:69]
|
||
|
|
node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 324:102]
|
||
|
|
node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 324:102]
|
||
|
|
node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 324:102]
|
||
|
|
node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 324:134]
|
||
|
|
node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 324:134]
|
||
|
|
node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 324:134]
|
||
|
|
io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 325:29]
|
||
|
|
node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 326:38]
|
||
|
|
node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 326:51]
|
||
|
|
i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 326:25]
|
||
|
|
node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 335:34]
|
||
|
|
node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 335:32]
|
||
|
|
node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 347:16]
|
||
|
|
node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 347:30]
|
||
|
|
node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 348:6]
|
||
|
|
node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 348:16]
|
||
|
|
node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 348:30]
|
||
|
|
node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 349:18]
|
||
|
|
node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 349:16]
|
||
|
|
node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 349:30]
|
||
|
|
node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16]
|
||
|
|
node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16]
|
||
|
|
node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16]
|
||
|
|
node _T_267 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_266) @[Mux.scala 98:16]
|
||
|
|
node _T_268 = mux(_T_263, UInt<4>("h05"), _T_267) @[Mux.scala 98:16]
|
||
|
|
node _T_269 = mux(_T_260, UInt<4>("h06"), _T_268) @[Mux.scala 98:16]
|
||
|
|
node _T_270 = mux(_T_257, UInt<4>("h07"), _T_269) @[Mux.scala 98:16]
|
||
|
|
node _T_271 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_270) @[Mux.scala 98:16]
|
||
|
|
node _T_272 = mux(i0_dp.ecall, UInt<4>("h09"), _T_271) @[Mux.scala 98:16]
|
||
|
|
node _T_273 = mux(i0_dp.fence, UInt<4>("h0a"), _T_272) @[Mux.scala 98:16]
|
||
|
|
node _T_274 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_273) @[Mux.scala 98:16]
|
||
|
|
node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16]
|
||
|
|
node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16]
|
||
|
|
node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16]
|
||
|
|
node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 339:49]
|
||
|
|
d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 339:21]
|
||
|
|
inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 356:22]
|
||
|
|
i0_dec.clock <= clock
|
||
|
|
i0_dec.reset <= reset
|
||
|
|
i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 357:16]
|
||
|
|
i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 358:12]
|
||
|
|
i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 358:12]
|
||
|
|
reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 360:45]
|
||
|
|
_T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 360:45]
|
||
|
|
lsu_idle <= _T_279 @[dec_decode_ctl.scala 360:11]
|
||
|
|
node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 363:73]
|
||
|
|
node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 363:71]
|
||
|
|
node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 363:53]
|
||
|
|
leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 363:21]
|
||
|
|
reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 364:56]
|
||
|
|
_T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 364:56]
|
||
|
|
leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 364:21]
|
||
|
|
leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 365:14]
|
||
|
|
node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 366:53]
|
||
|
|
node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 366:91]
|
||
|
|
node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 366:89]
|
||
|
|
node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 366:71]
|
||
|
|
leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 366:21]
|
||
|
|
reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 367:56]
|
||
|
|
_T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 367:56]
|
||
|
|
leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 367:21]
|
||
|
|
node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 371:29]
|
||
|
|
node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 371:36]
|
||
|
|
node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 371:46]
|
||
|
|
node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 371:53]
|
||
|
|
node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58]
|
||
|
|
node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58]
|
||
|
|
node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58]
|
||
|
|
node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 372:46]
|
||
|
|
node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 372:51]
|
||
|
|
node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:71]
|
||
|
|
node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 372:79]
|
||
|
|
node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:104]
|
||
|
|
node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 372:112]
|
||
|
|
node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 372:33]
|
||
|
|
node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 373:47]
|
||
|
|
node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 373:76]
|
||
|
|
node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 373:98]
|
||
|
|
node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 373:89]
|
||
|
|
node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 373:65]
|
||
|
|
node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 374:47]
|
||
|
|
node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 374:76]
|
||
|
|
node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 374:98]
|
||
|
|
node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 374:89]
|
||
|
|
node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 374:67]
|
||
|
|
node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 374:65]
|
||
|
|
node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 375:38]
|
||
|
|
i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 375:20]
|
||
|
|
node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 376:38]
|
||
|
|
i0_pcall <= _T_311 @[dec_decode_ctl.scala 376:20]
|
||
|
|
node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 377:38]
|
||
|
|
i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 377:20]
|
||
|
|
node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 378:38]
|
||
|
|
i0_pja <= _T_313 @[dec_decode_ctl.scala 378:20]
|
||
|
|
node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 379:41]
|
||
|
|
node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 379:55]
|
||
|
|
node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 379:75]
|
||
|
|
node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 379:90]
|
||
|
|
node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 379:97]
|
||
|
|
node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 379:103]
|
||
|
|
node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 379:113]
|
||
|
|
node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58]
|
||
|
|
node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58]
|
||
|
|
node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58]
|
||
|
|
node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 379:26]
|
||
|
|
i0_br_offset <= _T_324 @[dec_decode_ctl.scala 379:20]
|
||
|
|
node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 381:37]
|
||
|
|
node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 381:65]
|
||
|
|
node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 381:55]
|
||
|
|
node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 381:89]
|
||
|
|
node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 381:111]
|
||
|
|
node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 381:101]
|
||
|
|
node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 381:79]
|
||
|
|
node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 382:32]
|
||
|
|
i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 382:15]
|
||
|
|
node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 383:32]
|
||
|
|
i0_pret <= _T_332 @[dec_decode_ctl.scala 383:15]
|
||
|
|
node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:35]
|
||
|
|
node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 384:32]
|
||
|
|
node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:52]
|
||
|
|
node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 384:50]
|
||
|
|
node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:67]
|
||
|
|
node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 384:65]
|
||
|
|
i0_jal <= _T_338 @[dec_decode_ctl.scala 384:15]
|
||
|
|
io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 387:29]
|
||
|
|
io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 388:34]
|
||
|
|
io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 389:34]
|
||
|
|
io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 391:32]
|
||
|
|
io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 392:37]
|
||
|
|
io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 393:37]
|
||
|
|
io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 394:37]
|
||
|
|
reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 396:69]
|
||
|
|
_T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 396:69]
|
||
|
|
io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 396:34]
|
||
|
|
wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
_T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
|
||
|
|
io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 398:12]
|
||
|
|
io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 398:12]
|
||
|
|
when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 399:40]
|
||
|
|
io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 400:29]
|
||
|
|
io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 401:29]
|
||
|
|
io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 402:29]
|
||
|
|
io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 403:24]
|
||
|
|
skip @[dec_decode_ctl.scala 399:40]
|
||
|
|
else : @[dec_decode_ctl.scala 404:15]
|
||
|
|
io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 405:35]
|
||
|
|
io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 406:40]
|
||
|
|
io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 407:40]
|
||
|
|
io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 408:40]
|
||
|
|
io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 409:40]
|
||
|
|
io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 410:40]
|
||
|
|
io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 411:40]
|
||
|
|
io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 412:40]
|
||
|
|
io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 413:40]
|
||
|
|
io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 414:40]
|
||
|
|
skip @[dec_decode_ctl.scala 404:15]
|
||
|
|
io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 418:29]
|
||
|
|
node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 419:56]
|
||
|
|
node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 419:36]
|
||
|
|
csr_read <= _T_342 @[dec_decode_ctl.scala 419:18]
|
||
|
|
node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 421:42]
|
||
|
|
node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 421:40]
|
||
|
|
node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 422:61]
|
||
|
|
node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 422:41]
|
||
|
|
node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 423:59]
|
||
|
|
node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 423:39]
|
||
|
|
node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 424:59]
|
||
|
|
node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 424:39]
|
||
|
|
node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 426:41]
|
||
|
|
node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 426:39]
|
||
|
|
i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 426:23]
|
||
|
|
node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 427:42]
|
||
|
|
node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 427:58]
|
||
|
|
io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 427:24]
|
||
|
|
node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 430:30]
|
||
|
|
io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 430:24]
|
||
|
|
io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 431:23]
|
||
|
|
node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 435:39]
|
||
|
|
node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 435:53]
|
||
|
|
node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 435:51]
|
||
|
|
io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 435:20]
|
||
|
|
node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 438:50]
|
||
|
|
node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 438:85]
|
||
|
|
node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 438:64]
|
||
|
|
node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 438:100]
|
||
|
|
node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 438:118]
|
||
|
|
node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 438:132]
|
||
|
|
node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 438:130]
|
||
|
|
io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 438:27]
|
||
|
|
reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 440:52]
|
||
|
|
csr_read_x <= csr_read @[dec_decode_ctl.scala 440:52]
|
||
|
|
reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 441:51]
|
||
|
|
csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 441:51]
|
||
|
|
reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:51]
|
||
|
|
csr_set_x <= csr_set_d @[dec_decode_ctl.scala 442:51]
|
||
|
|
reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 443:53]
|
||
|
|
csr_write_x <= csr_write_d @[dec_decode_ctl.scala 443:53]
|
||
|
|
reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 444:51]
|
||
|
|
csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 444:51]
|
||
|
|
node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 447:27]
|
||
|
|
node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 447:48]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_1.io.en <= _T_363 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
csrimm_x <= _T_362 @[lib.scala 374:16]
|
||
|
|
node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 448:62]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_2.io.en <= _T_364 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
csr_rddata_x <= io.dec_csr_rddata_d @[lib.scala 374:16]
|
||
|
|
node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 451:15]
|
||
|
|
wire _T_366 : UInt<1>[27] @[lib.scala 12:48]
|
||
|
|
_T_366[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[16] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[17] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[18] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[19] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[20] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[21] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[22] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[23] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[24] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[25] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_366[26] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_370 = cat(_T_369, _T_366[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_371 = cat(_T_370, _T_366[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_372 = cat(_T_371, _T_366[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_373 = cat(_T_372, _T_366[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_374 = cat(_T_373, _T_366[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_375 = cat(_T_374, _T_366[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_376 = cat(_T_375, _T_366[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_377 = cat(_T_376, _T_366[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_378 = cat(_T_377, _T_366[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_379 = cat(_T_378, _T_366[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_380 = cat(_T_379, _T_366[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_381 = cat(_T_380, _T_366[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_382 = cat(_T_381, _T_366[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_383 = cat(_T_382, _T_366[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_384 = cat(_T_383, _T_366[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_385 = cat(_T_384, _T_366[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_386 = cat(_T_385, _T_366[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_387 = cat(_T_386, _T_366[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_388 = cat(_T_387, _T_366[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_389 = cat(_T_388, _T_366[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 451:53]
|
||
|
|
node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58]
|
||
|
|
node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 452:16]
|
||
|
|
node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 452:5]
|
||
|
|
node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_398 = mux(_T_396, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72]
|
||
|
|
wire csr_mask_x : UInt<32> @[Mux.scala 27:72]
|
||
|
|
csr_mask_x <= _T_399 @[Mux.scala 27:72]
|
||
|
|
node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 455:38]
|
||
|
|
node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 455:35]
|
||
|
|
node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 456:35]
|
||
|
|
node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_406 = or(_T_403, _T_404) @[Mux.scala 27:72]
|
||
|
|
node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72]
|
||
|
|
wire write_csr_data_x : UInt @[Mux.scala 27:72]
|
||
|
|
write_csr_data_x <= _T_407 @[Mux.scala 27:72]
|
||
|
|
node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 459:49]
|
||
|
|
node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 459:47]
|
||
|
|
node _T_410 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 459:145]
|
||
|
|
node _T_412 = cat(_T_410, _T_411) @[Cat.scala 29:58]
|
||
|
|
node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 459:109]
|
||
|
|
node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 459:91]
|
||
|
|
node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 459:76]
|
||
|
|
node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 460:44]
|
||
|
|
node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 460:61]
|
||
|
|
node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 460:59]
|
||
|
|
pause_state_in <= _T_417 @[dec_decode_ctl.scala 460:18]
|
||
|
|
reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 461:50]
|
||
|
|
_T_418 <= pause_state_in @[dec_decode_ctl.scala 461:50]
|
||
|
|
pause_stall <= _T_418 @[dec_decode_ctl.scala 461:15]
|
||
|
|
io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 462:22]
|
||
|
|
reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 463:55]
|
||
|
|
_T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 463:55]
|
||
|
|
tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 463:19]
|
||
|
|
reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 464:55]
|
||
|
|
_T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 464:55]
|
||
|
|
tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 464:19]
|
||
|
|
node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 466:44]
|
||
|
|
node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 466:64]
|
||
|
|
node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 466:61]
|
||
|
|
node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 466:41]
|
||
|
|
io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 466:25]
|
||
|
|
node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 469:59]
|
||
|
|
node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 469:59]
|
||
|
|
node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 470:8]
|
||
|
|
node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 469:30]
|
||
|
|
node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 471:34]
|
||
|
|
node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 471:46]
|
||
|
|
node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 471:61]
|
||
|
|
node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 471:75]
|
||
|
|
node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 471:99]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_3.io.en <= csr_data_wen @[lib.scala 371:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_432 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_432 <= write_csr_data_in @[lib.scala 374:16]
|
||
|
|
write_csr_data <= _T_432 @[dec_decode_ctl.scala 472:18]
|
||
|
|
node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 478:49]
|
||
|
|
node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 478:30]
|
||
|
|
io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 478:24]
|
||
|
|
node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 480:43]
|
||
|
|
node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 480:63]
|
||
|
|
node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 482:76]
|
||
|
|
node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 482:48]
|
||
|
|
node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 483:76]
|
||
|
|
node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 483:48]
|
||
|
|
node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 484:40]
|
||
|
|
debug_fence <= _T_438 @[dec_decode_ctl.scala 484:21]
|
||
|
|
node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 487:34]
|
||
|
|
node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 487:57]
|
||
|
|
node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 487:73]
|
||
|
|
node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 487:91]
|
||
|
|
node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 490:36]
|
||
|
|
node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 490:60]
|
||
|
|
node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 490:104]
|
||
|
|
node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 490:112]
|
||
|
|
node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 490:99]
|
||
|
|
node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 490:76]
|
||
|
|
node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 492:34]
|
||
|
|
io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 493:24]
|
||
|
|
node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 494:40]
|
||
|
|
node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 494:51]
|
||
|
|
node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 494:37]
|
||
|
|
wire _T_449 : UInt<1>[16] @[lib.scala 12:48]
|
||
|
|
_T_449[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_449[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_450 = cat(_T_449[0], _T_449[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_451 = cat(_T_450, _T_449[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_452 = cat(_T_451, _T_449[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_453 = cat(_T_452, _T_449[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_454 = cat(_T_453, _T_449[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_455 = cat(_T_454, _T_449[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_456 = cat(_T_455, _T_449[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_457 = cat(_T_456, _T_449[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_458 = cat(_T_457, _T_449[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_459 = cat(_T_458, _T_449[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_460 = cat(_T_459, _T_449[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_461 = cat(_T_460, _T_449[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_462 = cat(_T_461, _T_449[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_463 = cat(_T_462, _T_449[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_464 = cat(_T_463, _T_449[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_465 = cat(_T_464, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58]
|
||
|
|
node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 495:27]
|
||
|
|
node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 498:57]
|
||
|
|
node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 498:55]
|
||
|
|
node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 499:44]
|
||
|
|
node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 499:42]
|
||
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_4.clock <= clock
|
||
|
|
rvclkhdr_4.reset <= reset
|
||
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_4.io.en <= illegal_inst_en @[lib.scala 371:17]
|
||
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_468 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_468 <= i0_inst_d @[lib.scala 374:16]
|
||
|
|
io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 500:23]
|
||
|
|
node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 501:40]
|
||
|
|
node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 501:61]
|
||
|
|
node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 501:59]
|
||
|
|
illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 501:22]
|
||
|
|
reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 502:54]
|
||
|
|
_T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 502:54]
|
||
|
|
illegal_lockout <= _T_472 @[dec_decode_ctl.scala 502:19]
|
||
|
|
node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 503:42]
|
||
|
|
node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 505:40]
|
||
|
|
node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 505:59]
|
||
|
|
node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 505:92]
|
||
|
|
node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 505:106]
|
||
|
|
node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 506:20]
|
||
|
|
node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 506:45]
|
||
|
|
node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 506:62]
|
||
|
|
node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 507:19]
|
||
|
|
node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 507:36]
|
||
|
|
node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 507:34]
|
||
|
|
node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 506:79]
|
||
|
|
node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 507:47]
|
||
|
|
node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 507:72]
|
||
|
|
node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 508:21]
|
||
|
|
node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 508:45]
|
||
|
|
node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 510:65]
|
||
|
|
node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 510:39]
|
||
|
|
node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 511:63]
|
||
|
|
node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 511:38]
|
||
|
|
node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 512:38]
|
||
|
|
node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 512:57]
|
||
|
|
node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 516:54]
|
||
|
|
node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 516:52]
|
||
|
|
node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:71]
|
||
|
|
node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 516:69]
|
||
|
|
node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:99]
|
||
|
|
node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 516:97]
|
||
|
|
io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 516:30]
|
||
|
|
node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 517:46]
|
||
|
|
node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 517:44]
|
||
|
|
node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:63]
|
||
|
|
node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 517:61]
|
||
|
|
node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:91]
|
||
|
|
node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 517:89]
|
||
|
|
node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 518:46]
|
||
|
|
io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 521:28]
|
||
|
|
node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:51]
|
||
|
|
node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 522:49]
|
||
|
|
io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 522:27]
|
||
|
|
node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 523:47]
|
||
|
|
io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 523:29]
|
||
|
|
node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 524:46]
|
||
|
|
io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 524:29]
|
||
|
|
node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 528:41]
|
||
|
|
node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 529:31]
|
||
|
|
node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 531:37]
|
||
|
|
presync_stall <= _T_505 @[dec_decode_ctl.scala 531:22]
|
||
|
|
reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 532:53]
|
||
|
|
_T_506 <= ps_stall_in @[dec_decode_ctl.scala 532:53]
|
||
|
|
postsync_stall <= _T_506 @[dec_decode_ctl.scala 532:18]
|
||
|
|
node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 534:64]
|
||
|
|
node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 534:62]
|
||
|
|
node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 534:47]
|
||
|
|
node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 534:96]
|
||
|
|
node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 534:77]
|
||
|
|
ps_stall_in <= _T_511 @[dec_decode_ctl.scala 534:15]
|
||
|
|
node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 536:58]
|
||
|
|
io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 536:34]
|
||
|
|
node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 538:40]
|
||
|
|
lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 538:16]
|
||
|
|
node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 539:40]
|
||
|
|
mul_decode_d <= _T_514 @[dec_decode_ctl.scala 539:16]
|
||
|
|
node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 540:40]
|
||
|
|
div_decode_d <= _T_515 @[dec_decode_ctl.scala 540:16]
|
||
|
|
node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 542:45]
|
||
|
|
node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 542:43]
|
||
|
|
io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 542:29]
|
||
|
|
d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 545:26]
|
||
|
|
node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 546:40]
|
||
|
|
d_t.icaf <= _T_518 @[dec_decode_ctl.scala 546:26]
|
||
|
|
node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 547:50]
|
||
|
|
d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 547:26]
|
||
|
|
d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 548:26]
|
||
|
|
node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 550:44]
|
||
|
|
node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 550:61]
|
||
|
|
d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 550:26]
|
||
|
|
d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 553:26]
|
||
|
|
d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 554:26]
|
||
|
|
d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 555:26]
|
||
|
|
wire _T_522 : UInt<1>[4] @[lib.scala 12:48]
|
||
|
|
_T_522[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
|
||
|
|
_T_522[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
|
||
|
|
_T_522[2] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
|
||
|
|
_T_522[3] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
|
||
|
|
node _T_523 = cat(_T_522[0], _T_522[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_524 = cat(_T_523, _T_522[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_525 = cat(_T_524, _T_522[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 557:56]
|
||
|
|
d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 557:26]
|
||
|
|
node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 560:33]
|
||
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 378:23]
|
||
|
|
rvclkhdr_5.clock <= clock
|
||
|
|
rvclkhdr_5.reset <= reset
|
||
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 380:18]
|
||
|
|
rvclkhdr_5.io.en <= _T_527 @[lib.scala 381:17]
|
||
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 382:24]
|
||
|
|
wire _T_528 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 384:33]
|
||
|
|
_T_528.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.pmu_divide <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.i0trigger <= UInt<4>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.fence_i <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.icaf_type <= UInt<2>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.icaf_f1 <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.icaf <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_528.legal <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
reg _T_529 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_528)) @[lib.scala 384:16]
|
||
|
|
_T_529.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[lib.scala 384:16]
|
||
|
|
_T_529.pmu_divide <= d_t.pmu_divide @[lib.scala 384:16]
|
||
|
|
_T_529.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[lib.scala 384:16]
|
||
|
|
_T_529.pmu_i0_itype <= d_t.pmu_i0_itype @[lib.scala 384:16]
|
||
|
|
_T_529.i0trigger <= d_t.i0trigger @[lib.scala 384:16]
|
||
|
|
_T_529.fence_i <= d_t.fence_i @[lib.scala 384:16]
|
||
|
|
_T_529.icaf_type <= d_t.icaf_type @[lib.scala 384:16]
|
||
|
|
_T_529.icaf_f1 <= d_t.icaf_f1 @[lib.scala 384:16]
|
||
|
|
_T_529.icaf <= d_t.icaf @[lib.scala 384:16]
|
||
|
|
_T_529.legal <= d_t.legal @[lib.scala 384:16]
|
||
|
|
x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 560:7]
|
||
|
|
x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 562:10]
|
||
|
|
x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 562:10]
|
||
|
|
wire _T_530 : UInt<1>[4] @[lib.scala 12:48]
|
||
|
|
_T_530[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
||
|
|
_T_530[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
||
|
|
_T_530[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
||
|
|
_T_530[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
||
|
|
node _T_531 = cat(_T_530[0], _T_530[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_532 = cat(_T_531, _T_530[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_533 = cat(_T_532, _T_530[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_534 = not(_T_533) @[dec_decode_ctl.scala 563:39]
|
||
|
|
node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 563:37]
|
||
|
|
x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 563:20]
|
||
|
|
node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 565:36]
|
||
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 378:23]
|
||
|
|
rvclkhdr_6.clock <= clock
|
||
|
|
rvclkhdr_6.reset <= reset
|
||
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 380:18]
|
||
|
|
rvclkhdr_6.io.en <= _T_536 @[lib.scala 381:17]
|
||
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 382:24]
|
||
|
|
wire _T_537 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 384:33]
|
||
|
|
_T_537.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.pmu_divide <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.i0trigger <= UInt<4>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.fence_i <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.icaf_type <= UInt<2>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.icaf_f1 <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.icaf <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_537.legal <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
reg _T_538 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_537)) @[lib.scala 384:16]
|
||
|
|
_T_538.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[lib.scala 384:16]
|
||
|
|
_T_538.pmu_divide <= x_t_in.pmu_divide @[lib.scala 384:16]
|
||
|
|
_T_538.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[lib.scala 384:16]
|
||
|
|
_T_538.pmu_i0_itype <= x_t_in.pmu_i0_itype @[lib.scala 384:16]
|
||
|
|
_T_538.i0trigger <= x_t_in.i0trigger @[lib.scala 384:16]
|
||
|
|
_T_538.fence_i <= x_t_in.fence_i @[lib.scala 384:16]
|
||
|
|
_T_538.icaf_type <= x_t_in.icaf_type @[lib.scala 384:16]
|
||
|
|
_T_538.icaf_f1 <= x_t_in.icaf_f1 @[lib.scala 384:16]
|
||
|
|
_T_538.icaf <= x_t_in.icaf @[lib.scala 384:16]
|
||
|
|
_T_538.legal <= x_t_in.legal @[lib.scala 384:16]
|
||
|
|
r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 565:7]
|
||
|
|
r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 565:7]
|
||
|
|
reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 566:36]
|
||
|
|
lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 566:36]
|
||
|
|
reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 567:37]
|
||
|
|
lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 567:37]
|
||
|
|
r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 569:10]
|
||
|
|
r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 569:10]
|
||
|
|
node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 571:61]
|
||
|
|
wire _T_540 : UInt<1>[4] @[lib.scala 12:48]
|
||
|
|
_T_540[0] <= _T_539 @[lib.scala 12:48]
|
||
|
|
_T_540[1] <= _T_539 @[lib.scala 12:48]
|
||
|
|
_T_540[2] <= _T_539 @[lib.scala 12:48]
|
||
|
|
_T_540[3] <= _T_539 @[lib.scala 12:48]
|
||
|
|
node _T_541 = cat(_T_540[0], _T_540[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_542 = cat(_T_541, _T_540[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_543 = cat(_T_542, _T_540[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 571:82]
|
||
|
|
node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 571:105]
|
||
|
|
r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 571:33]
|
||
|
|
r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 572:33]
|
||
|
|
node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 574:35]
|
||
|
|
when _T_546 : @[dec_decode_ctl.scala 574:43]
|
||
|
|
wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
_T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
|
||
|
|
r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 574:51]
|
||
|
|
r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 574:51]
|
||
|
|
skip @[dec_decode_ctl.scala 574:43]
|
||
|
|
io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 576:39]
|
||
|
|
io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 576:39]
|
||
|
|
node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 577:58]
|
||
|
|
io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 577:39]
|
||
|
|
reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 580:52]
|
||
|
|
_T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 580:52]
|
||
|
|
flush_final_r <= _T_549 @[dec_decode_ctl.scala 580:17]
|
||
|
|
node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 582:54]
|
||
|
|
node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 582:52]
|
||
|
|
node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:68]
|
||
|
|
node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 582:66]
|
||
|
|
node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:96]
|
||
|
|
node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 582:94]
|
||
|
|
io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 582:30]
|
||
|
|
node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 584:16]
|
||
|
|
i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 584:11]
|
||
|
|
node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 585:16]
|
||
|
|
i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 585:11]
|
||
|
|
node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 586:16]
|
||
|
|
i0r.rd <= _T_558 @[dec_decode_ctl.scala 586:11]
|
||
|
|
node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 588:60]
|
||
|
|
node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 588:49]
|
||
|
|
io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 588:35]
|
||
|
|
node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 589:60]
|
||
|
|
node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 589:49]
|
||
|
|
io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 589:35]
|
||
|
|
node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 590:48]
|
||
|
|
node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 590:37]
|
||
|
|
io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 591:19]
|
||
|
|
io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 592:19]
|
||
|
|
node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 594:38]
|
||
|
|
node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 595:27]
|
||
|
|
node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 595:38]
|
||
|
|
node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 599:5]
|
||
|
|
node _T_566 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_567 = mux(_T_565, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72]
|
||
|
|
wire _T_569 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_569 <= _T_568 @[Mux.scala 27:72]
|
||
|
|
io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 597:32]
|
||
|
|
node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 602:38]
|
||
|
|
wire _T_571 : UInt<1>[20] @[lib.scala 12:48]
|
||
|
|
_T_571[0] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[1] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[2] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[3] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[4] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[5] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[6] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[7] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[8] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[9] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[10] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[11] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[12] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[13] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[14] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[15] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[16] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[17] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[18] <= _T_570 @[lib.scala 12:48]
|
||
|
|
_T_571[19] <= _T_570 @[lib.scala 12:48]
|
||
|
|
node _T_572 = cat(_T_571[0], _T_571[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_573 = cat(_T_572, _T_571[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_574 = cat(_T_573, _T_571[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_575 = cat(_T_574, _T_571[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_576 = cat(_T_575, _T_571[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_577 = cat(_T_576, _T_571[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_578 = cat(_T_577, _T_571[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_579 = cat(_T_578, _T_571[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_580 = cat(_T_579, _T_571[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_581 = cat(_T_580, _T_571[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_582 = cat(_T_581, _T_571[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_583 = cat(_T_582, _T_571[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_584 = cat(_T_583, _T_571[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_585 = cat(_T_584, _T_571[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_586 = cat(_T_585, _T_571[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_587 = cat(_T_586, _T_571[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_588 = cat(_T_587, _T_571[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_589 = cat(_T_588, _T_571[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_590 = cat(_T_589, _T_571[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 602:46]
|
||
|
|
node _T_592 = cat(_T_590, _T_591) @[Cat.scala 29:58]
|
||
|
|
wire _T_593 : UInt<1>[27] @[lib.scala 12:48]
|
||
|
|
_T_593[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[16] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[17] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[18] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[19] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[20] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[21] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[22] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[23] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[24] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[25] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_593[26] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_594 = cat(_T_593[0], _T_593[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_595 = cat(_T_594, _T_593[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_596 = cat(_T_595, _T_593[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_597 = cat(_T_596, _T_593[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_598 = cat(_T_597, _T_593[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_599 = cat(_T_598, _T_593[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_600 = cat(_T_599, _T_593[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_601 = cat(_T_600, _T_593[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_602 = cat(_T_601, _T_593[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_603 = cat(_T_602, _T_593[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_604 = cat(_T_603, _T_593[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_605 = cat(_T_604, _T_593[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_606 = cat(_T_605, _T_593[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_607 = cat(_T_606, _T_593[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_608 = cat(_T_607, _T_593[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_609 = cat(_T_608, _T_593[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_610 = cat(_T_609, _T_593[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_611 = cat(_T_610, _T_593[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_612 = cat(_T_611, _T_593[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_613 = cat(_T_612, _T_593[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_614 = cat(_T_613, _T_593[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_615 = cat(_T_614, _T_593[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_616 = cat(_T_615, _T_593[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_617 = cat(_T_616, _T_593[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_618 = cat(_T_617, _T_593[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_619 = cat(_T_618, _T_593[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 603:43]
|
||
|
|
node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58]
|
||
|
|
node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 604:38]
|
||
|
|
wire _T_623 : UInt<1>[12] @[lib.scala 12:48]
|
||
|
|
_T_623[0] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[1] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[2] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[3] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[4] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[5] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[6] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[7] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[8] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[9] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[10] <= _T_622 @[lib.scala 12:48]
|
||
|
|
_T_623[11] <= _T_622 @[lib.scala 12:48]
|
||
|
|
node _T_624 = cat(_T_623[0], _T_623[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_625 = cat(_T_624, _T_623[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_626 = cat(_T_625, _T_623[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_627 = cat(_T_626, _T_623[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_628 = cat(_T_627, _T_623[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_629 = cat(_T_628, _T_623[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_630 = cat(_T_629, _T_623[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_631 = cat(_T_630, _T_623[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_632 = cat(_T_631, _T_623[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_633 = cat(_T_632, _T_623[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_634 = cat(_T_633, _T_623[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 604:46]
|
||
|
|
node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 604:56]
|
||
|
|
node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 604:63]
|
||
|
|
node _T_638 = cat(_T_637, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_639 = cat(_T_634, _T_635) @[Cat.scala 29:58]
|
||
|
|
node _T_640 = cat(_T_639, _T_636) @[Cat.scala 29:58]
|
||
|
|
node _T_641 = cat(_T_640, _T_638) @[Cat.scala 29:58]
|
||
|
|
node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 605:30]
|
||
|
|
wire _T_643 : UInt<1>[12] @[lib.scala 12:48]
|
||
|
|
_T_643[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_643[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_644 = cat(_T_643[0], _T_643[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_645 = cat(_T_644, _T_643[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_646 = cat(_T_645, _T_643[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_647 = cat(_T_646, _T_643[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_648 = cat(_T_647, _T_643[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_649 = cat(_T_648, _T_643[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_650 = cat(_T_649, _T_643[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_651 = cat(_T_650, _T_643[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_652 = cat(_T_651, _T_643[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_653 = cat(_T_652, _T_643[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_654 = cat(_T_653, _T_643[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_655 = cat(_T_642, _T_654) @[Cat.scala 29:58]
|
||
|
|
node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 606:26]
|
||
|
|
node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 606:43]
|
||
|
|
wire _T_658 : UInt<1>[27] @[lib.scala 12:48]
|
||
|
|
_T_658[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[16] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[17] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[18] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[19] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[20] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[21] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[22] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[23] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[24] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[25] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_658[26] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_659 = cat(_T_658[0], _T_658[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_660 = cat(_T_659, _T_658[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_661 = cat(_T_660, _T_658[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_662 = cat(_T_661, _T_658[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_663 = cat(_T_662, _T_658[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_664 = cat(_T_663, _T_658[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_665 = cat(_T_664, _T_658[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_666 = cat(_T_665, _T_658[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_667 = cat(_T_666, _T_658[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_668 = cat(_T_667, _T_658[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_669 = cat(_T_668, _T_658[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_670 = cat(_T_669, _T_658[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_671 = cat(_T_670, _T_658[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_672 = cat(_T_671, _T_658[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_673 = cat(_T_672, _T_658[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_674 = cat(_T_673, _T_658[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_675 = cat(_T_674, _T_658[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_676 = cat(_T_675, _T_658[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_677 = cat(_T_676, _T_658[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_678 = cat(_T_677, _T_658[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_679 = cat(_T_678, _T_658[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_680 = cat(_T_679, _T_658[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_681 = cat(_T_680, _T_658[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_682 = cat(_T_681, _T_658[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_683 = cat(_T_682, _T_658[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_684 = cat(_T_683, _T_658[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 606:72]
|
||
|
|
node _T_686 = cat(_T_684, _T_685) @[Cat.scala 29:58]
|
||
|
|
node _T_687 = mux(i0_dp.imm12, _T_592, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_688 = mux(i0_dp.shimm5, _T_621, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_689 = mux(i0_jalimm20, _T_641, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_690 = mux(i0_uiimm20, _T_655, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_691 = mux(_T_657, _T_686, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_692 = or(_T_687, _T_688) @[Mux.scala 27:72]
|
||
|
|
node _T_693 = or(_T_692, _T_689) @[Mux.scala 27:72]
|
||
|
|
node _T_694 = or(_T_693, _T_690) @[Mux.scala 27:72]
|
||
|
|
node _T_695 = or(_T_694, _T_691) @[Mux.scala 27:72]
|
||
|
|
wire _T_696 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_696 <= _T_695 @[Mux.scala 27:72]
|
||
|
|
i0_immed_d <= _T_696 @[dec_decode_ctl.scala 601:14]
|
||
|
|
node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 608:54]
|
||
|
|
i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 608:24]
|
||
|
|
node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 610:44]
|
||
|
|
i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 610:29]
|
||
|
|
node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 611:44]
|
||
|
|
i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 611:29]
|
||
|
|
node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 612:44]
|
||
|
|
i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 612:29]
|
||
|
|
wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 614:70]
|
||
|
|
_T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70]
|
||
|
|
_T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70]
|
||
|
|
_T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70]
|
||
|
|
node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 614:92]
|
||
|
|
reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_701)) @[Reg.scala 27:20]
|
||
|
|
when _T_702 : @[Reg.scala 28:19]
|
||
|
|
i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23]
|
||
|
|
i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23]
|
||
|
|
i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 615:70]
|
||
|
|
_T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70]
|
||
|
|
_T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70]
|
||
|
|
_T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70]
|
||
|
|
node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 615:92]
|
||
|
|
reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_703)) @[Reg.scala 27:20]
|
||
|
|
when _T_704 : @[Reg.scala 28:19]
|
||
|
|
i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23]
|
||
|
|
i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23]
|
||
|
|
i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 616:91]
|
||
|
|
reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 616:80]
|
||
|
|
_T_706 <= _T_705 @[dec_decode_ctl.scala 616:80]
|
||
|
|
node _T_707 = cat(io.dec_aln.dec_i0_decode_d, _T_706) @[Cat.scala 29:58]
|
||
|
|
i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 616:14]
|
||
|
|
node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 618:43]
|
||
|
|
node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 618:49]
|
||
|
|
node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 618:53]
|
||
|
|
i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 618:29]
|
||
|
|
node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 619:43]
|
||
|
|
node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 619:49]
|
||
|
|
node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 619:53]
|
||
|
|
i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 619:29]
|
||
|
|
node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 620:43]
|
||
|
|
node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 620:49]
|
||
|
|
node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 620:53]
|
||
|
|
i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 620:29]
|
||
|
|
node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 621:44]
|
||
|
|
node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 621:50]
|
||
|
|
i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 621:29]
|
||
|
|
node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 622:44]
|
||
|
|
node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 622:50]
|
||
|
|
i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 622:29]
|
||
|
|
node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 623:44]
|
||
|
|
node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 623:50]
|
||
|
|
i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 623:29]
|
||
|
|
node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 624:44]
|
||
|
|
node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 624:50]
|
||
|
|
i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 624:29]
|
||
|
|
node _T_725 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
|
||
|
|
io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 626:38]
|
||
|
|
node _T_726 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
|
||
|
|
io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 627:38]
|
||
|
|
d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 629:34]
|
||
|
|
node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 630:50]
|
||
|
|
d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 630:34]
|
||
|
|
d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 631:27]
|
||
|
|
node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 633:50]
|
||
|
|
d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 633:34]
|
||
|
|
node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 634:50]
|
||
|
|
d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 634:34]
|
||
|
|
node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 635:50]
|
||
|
|
d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 635:34]
|
||
|
|
node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 637:61]
|
||
|
|
d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 637:34]
|
||
|
|
node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 638:58]
|
||
|
|
d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 638:34]
|
||
|
|
node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 639:40]
|
||
|
|
d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 639:34]
|
||
|
|
node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 641:34]
|
||
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 378:23]
|
||
|
|
rvclkhdr_7.clock <= clock
|
||
|
|
rvclkhdr_7.reset <= reset
|
||
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 380:18]
|
||
|
|
rvclkhdr_7.io.en <= _T_734 @[lib.scala 381:17]
|
||
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 382:24]
|
||
|
|
wire _T_735 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33]
|
||
|
|
_T_735.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33]
|
||
|
|
_T_735.valid <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
reg _T_736 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_735)) @[lib.scala 384:16]
|
||
|
|
_T_736.bits.csrwaddr <= d_d.bits.csrwaddr @[lib.scala 384:16]
|
||
|
|
_T_736.bits.csrwonly <= d_d.bits.csrwonly @[lib.scala 384:16]
|
||
|
|
_T_736.bits.csrwen <= d_d.bits.csrwen @[lib.scala 384:16]
|
||
|
|
_T_736.bits.i0v <= d_d.bits.i0v @[lib.scala 384:16]
|
||
|
|
_T_736.bits.i0div <= d_d.bits.i0div @[lib.scala 384:16]
|
||
|
|
_T_736.bits.i0store <= d_d.bits.i0store @[lib.scala 384:16]
|
||
|
|
_T_736.bits.i0load <= d_d.bits.i0load @[lib.scala 384:16]
|
||
|
|
_T_736.bits.i0rd <= d_d.bits.i0rd @[lib.scala 384:16]
|
||
|
|
_T_736.valid <= d_d.valid @[lib.scala 384:16]
|
||
|
|
x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 641:7]
|
||
|
|
x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 641:7]
|
||
|
|
wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 642:20]
|
||
|
|
x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 643:10]
|
||
|
|
x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 643:10]
|
||
|
|
node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 644:49]
|
||
|
|
node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 644:47]
|
||
|
|
node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 644:78]
|
||
|
|
node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 644:76]
|
||
|
|
x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 644:27]
|
||
|
|
node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 645:35]
|
||
|
|
node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 645:33]
|
||
|
|
node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 645:64]
|
||
|
|
node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 645:62]
|
||
|
|
x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 645:20]
|
||
|
|
node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:36]
|
||
|
|
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 378:23]
|
||
|
|
rvclkhdr_8.clock <= clock
|
||
|
|
rvclkhdr_8.reset <= reset
|
||
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 380:18]
|
||
|
|
rvclkhdr_8.io.en <= _T_745 @[lib.scala 381:17]
|
||
|
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 382:24]
|
||
|
|
wire _T_746 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33]
|
||
|
|
_T_746.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33]
|
||
|
|
_T_746.valid <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
reg _T_747 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_746)) @[lib.scala 384:16]
|
||
|
|
_T_747.bits.csrwaddr <= x_d_in.bits.csrwaddr @[lib.scala 384:16]
|
||
|
|
_T_747.bits.csrwonly <= x_d_in.bits.csrwonly @[lib.scala 384:16]
|
||
|
|
_T_747.bits.csrwen <= x_d_in.bits.csrwen @[lib.scala 384:16]
|
||
|
|
_T_747.bits.i0v <= x_d_in.bits.i0v @[lib.scala 384:16]
|
||
|
|
_T_747.bits.i0div <= x_d_in.bits.i0div @[lib.scala 384:16]
|
||
|
|
_T_747.bits.i0store <= x_d_in.bits.i0store @[lib.scala 384:16]
|
||
|
|
_T_747.bits.i0load <= x_d_in.bits.i0load @[lib.scala 384:16]
|
||
|
|
_T_747.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 384:16]
|
||
|
|
_T_747.valid <= x_d_in.valid @[lib.scala 384:16]
|
||
|
|
r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 647:7]
|
||
|
|
r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 648:10]
|
||
|
|
r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 649:22]
|
||
|
|
node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:51]
|
||
|
|
node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 651:49]
|
||
|
|
r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 651:27]
|
||
|
|
node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 652:37]
|
||
|
|
node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 652:35]
|
||
|
|
r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 652:20]
|
||
|
|
node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 653:51]
|
||
|
|
node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 653:49]
|
||
|
|
r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 653:27]
|
||
|
|
node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 654:51]
|
||
|
|
node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 654:49]
|
||
|
|
r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 654:27]
|
||
|
|
node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 656:37]
|
||
|
|
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 378:23]
|
||
|
|
rvclkhdr_9.clock <= clock
|
||
|
|
rvclkhdr_9.reset <= reset
|
||
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 380:18]
|
||
|
|
rvclkhdr_9.io.en <= _T_756 @[lib.scala 381:17]
|
||
|
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 382:24]
|
||
|
|
wire _T_757 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33]
|
||
|
|
_T_757.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33]
|
||
|
|
_T_757.valid <= UInt<1>("h00") @[lib.scala 384:33]
|
||
|
|
reg _T_758 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_757)) @[lib.scala 384:16]
|
||
|
|
_T_758.bits.csrwaddr <= r_d_in.bits.csrwaddr @[lib.scala 384:16]
|
||
|
|
_T_758.bits.csrwonly <= r_d_in.bits.csrwonly @[lib.scala 384:16]
|
||
|
|
_T_758.bits.csrwen <= r_d_in.bits.csrwen @[lib.scala 384:16]
|
||
|
|
_T_758.bits.i0v <= r_d_in.bits.i0v @[lib.scala 384:16]
|
||
|
|
_T_758.bits.i0div <= r_d_in.bits.i0div @[lib.scala 384:16]
|
||
|
|
_T_758.bits.i0store <= r_d_in.bits.i0store @[lib.scala 384:16]
|
||
|
|
_T_758.bits.i0load <= r_d_in.bits.i0load @[lib.scala 384:16]
|
||
|
|
_T_758.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 384:16]
|
||
|
|
_T_758.valid <= r_d_in.valid @[lib.scala 384:16]
|
||
|
|
wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 656:7]
|
||
|
|
wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 656:7]
|
||
|
|
io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 658:27]
|
||
|
|
node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 659:47]
|
||
|
|
node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 659:45]
|
||
|
|
i0_wen_r <= _T_760 @[dec_decode_ctl.scala 659:25]
|
||
|
|
node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 660:49]
|
||
|
|
node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 660:47]
|
||
|
|
node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 660:70]
|
||
|
|
node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 660:68]
|
||
|
|
io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 660:32]
|
||
|
|
io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 661:26]
|
||
|
|
node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 663:57]
|
||
|
|
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_10.clock <= clock
|
||
|
|
rvclkhdr_10.reset <= reset
|
||
|
|
rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_10.io.en <= _T_765 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
i0_result_r_raw <= i0_result_x @[lib.scala 374:16]
|
||
|
|
node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 669:47]
|
||
|
|
node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 669:66]
|
||
|
|
node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 669:32]
|
||
|
|
i0_result_x <= _T_768 @[dec_decode_ctl.scala 669:26]
|
||
|
|
i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 670:26]
|
||
|
|
node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 674:42]
|
||
|
|
node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 674:61]
|
||
|
|
node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 674:27]
|
||
|
|
i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 674:21]
|
||
|
|
node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 675:73]
|
||
|
|
node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 675:71]
|
||
|
|
node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 675:85]
|
||
|
|
wire _T_775 : UInt<1>[10] @[lib.scala 12:48]
|
||
|
|
_T_775[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_775[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_776 = cat(_T_775[0], _T_775[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_777 = cat(_T_776, _T_775[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_778 = cat(_T_777, _T_775[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_779 = cat(_T_778, _T_775[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_780 = cat(_T_779, _T_775[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_781 = cat(_T_780, _T_775[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_782 = cat(_T_781, _T_775[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_783 = cat(_T_782, _T_775[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_784 = cat(_T_783, _T_775[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_785 = cat(_T_784, io.dec_i0_pc4_d) @[Cat.scala 29:58]
|
||
|
|
node _T_786 = cat(_T_785, i0_ap_pc2) @[Cat.scala 29:58]
|
||
|
|
node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 675:38]
|
||
|
|
io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 675:32]
|
||
|
|
wire last_br_immed_d : UInt<12>
|
||
|
|
last_br_immed_d <= UInt<1>("h00")
|
||
|
|
node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 677:59]
|
||
|
|
wire _T_789 : UInt<1>[10] @[lib.scala 12:48]
|
||
|
|
_T_789[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
_T_789[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
||
|
|
node _T_790 = cat(_T_789[0], _T_789[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_791 = cat(_T_790, _T_789[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_792 = cat(_T_791, _T_789[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_793 = cat(_T_792, _T_789[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_794 = cat(_T_793, _T_789[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_795 = cat(_T_794, _T_789[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_796 = cat(_T_795, _T_789[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_797 = cat(_T_796, _T_789[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_798 = cat(_T_797, _T_789[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_799 = cat(_T_798, io.dec_i0_pc4_d) @[Cat.scala 29:58]
|
||
|
|
node _T_800 = cat(_T_799, i0_ap_pc2) @[Cat.scala 29:58]
|
||
|
|
node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 677:25]
|
||
|
|
last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 677:19]
|
||
|
|
wire last_br_immed_x : UInt<12>
|
||
|
|
last_br_immed_x <= UInt<1>("h00")
|
||
|
|
node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 679:58]
|
||
|
|
inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_11.clock <= clock
|
||
|
|
rvclkhdr_11.reset <= reset
|
||
|
|
rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_11.io.en <= _T_802 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_803 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_803 <= last_br_immed_d @[lib.scala 374:16]
|
||
|
|
last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 679:19]
|
||
|
|
node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 683:45]
|
||
|
|
node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 683:76]
|
||
|
|
node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 683:58]
|
||
|
|
node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 685:48]
|
||
|
|
node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 685:77]
|
||
|
|
node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 685:60]
|
||
|
|
node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 686:21]
|
||
|
|
node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 686:33]
|
||
|
|
node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 685:94]
|
||
|
|
node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 687:21]
|
||
|
|
node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 687:33]
|
||
|
|
node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 687:60]
|
||
|
|
node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 686:62]
|
||
|
|
node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 691:51]
|
||
|
|
node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 692:26]
|
||
|
|
node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 692:24]
|
||
|
|
node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 692:56]
|
||
|
|
node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 692:39]
|
||
|
|
node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 692:77]
|
||
|
|
node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 691:65]
|
||
|
|
node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 694:61]
|
||
|
|
io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 694:37]
|
||
|
|
node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 695:55]
|
||
|
|
node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 697:62]
|
||
|
|
node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 697:60]
|
||
|
|
node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 697:81]
|
||
|
|
node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 697:79]
|
||
|
|
node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 697:39]
|
||
|
|
reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 699:54]
|
||
|
|
_T_826 <= div_active_in @[dec_decode_ctl.scala 699:54]
|
||
|
|
io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 699:21]
|
||
|
|
node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 702:60]
|
||
|
|
node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 702:99]
|
||
|
|
node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 702:80]
|
||
|
|
node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 703:36]
|
||
|
|
node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 703:75]
|
||
|
|
node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 703:56]
|
||
|
|
node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 702:113]
|
||
|
|
i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 702:26]
|
||
|
|
node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 705:59]
|
||
|
|
reg _T_835 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_834 : @[Reg.scala 28:19]
|
||
|
|
_T_835 <= i0r.rd @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 705:19]
|
||
|
|
node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 712:34]
|
||
|
|
node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 712:57]
|
||
|
|
inst rvclkhdr_12 of rvclkhdr_12 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_12.clock <= clock
|
||
|
|
rvclkhdr_12.reset <= reset
|
||
|
|
rvclkhdr_12.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_12.io.en <= _T_837 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
div_inst <= _T_836 @[lib.scala 374:16]
|
||
|
|
node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 713:49]
|
||
|
|
inst rvclkhdr_13 of rvclkhdr_13 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_13.clock <= clock
|
||
|
|
rvclkhdr_13.reset <= reset
|
||
|
|
rvclkhdr_13.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_13.io.en <= _T_838 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
i0_inst_x <= i0_inst_d @[lib.scala 374:16]
|
||
|
|
node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 714:49]
|
||
|
|
inst rvclkhdr_14 of rvclkhdr_14 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_14.clock <= clock
|
||
|
|
rvclkhdr_14.reset <= reset
|
||
|
|
rvclkhdr_14.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_14.io.en <= _T_839 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
i0_inst_r <= i0_inst_x @[lib.scala 374:16]
|
||
|
|
node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 716:50]
|
||
|
|
inst rvclkhdr_15 of rvclkhdr_15 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_15.clock <= clock
|
||
|
|
rvclkhdr_15.reset <= reset
|
||
|
|
rvclkhdr_15.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_15.io.en <= _T_840 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
i0_inst_wb <= i0_inst_r @[lib.scala 374:16]
|
||
|
|
node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 717:53]
|
||
|
|
inst rvclkhdr_16 of rvclkhdr_16 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_16.clock <= clock
|
||
|
|
rvclkhdr_16.reset <= reset
|
||
|
|
rvclkhdr_16.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_16.io.en <= _T_841 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_842 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_842 <= i0_inst_wb @[lib.scala 374:16]
|
||
|
|
io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 717:22]
|
||
|
|
node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 718:53]
|
||
|
|
inst rvclkhdr_17 of rvclkhdr_17 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_17.clock <= clock
|
||
|
|
rvclkhdr_17.reset <= reset
|
||
|
|
rvclkhdr_17.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_17.io.en <= _T_843 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
i0_pc_wb <= io.dec_tlu_i0_pc_r @[lib.scala 374:16]
|
||
|
|
node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 720:49]
|
||
|
|
inst rvclkhdr_18 of rvclkhdr_18 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_18.clock <= clock
|
||
|
|
rvclkhdr_18.reset <= reset
|
||
|
|
rvclkhdr_18.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_18.io.en <= _T_844 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_845 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_845 <= i0_pc_wb @[lib.scala 374:16]
|
||
|
|
io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 720:20]
|
||
|
|
node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 721:64]
|
||
|
|
inst rvclkhdr_19 of rvclkhdr_19 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_19.clock <= clock
|
||
|
|
rvclkhdr_19.reset <= reset
|
||
|
|
rvclkhdr_19.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_19.io.en <= _T_846 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[lib.scala 374:16]
|
||
|
|
io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 723:27]
|
||
|
|
node _T_847 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_848 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_849 = bits(_T_847, 12, 1) @[lib.scala 68:24]
|
||
|
|
node _T_850 = bits(_T_848, 12, 1) @[lib.scala 68:40]
|
||
|
|
node _T_851 = add(_T_849, _T_850) @[lib.scala 68:31]
|
||
|
|
node _T_852 = bits(_T_847, 31, 13) @[lib.scala 69:20]
|
||
|
|
node _T_853 = add(_T_852, UInt<1>("h01")) @[lib.scala 69:27]
|
||
|
|
node _T_854 = tail(_T_853, 1) @[lib.scala 69:27]
|
||
|
|
node _T_855 = bits(_T_847, 31, 13) @[lib.scala 70:20]
|
||
|
|
node _T_856 = sub(_T_855, UInt<1>("h01")) @[lib.scala 70:27]
|
||
|
|
node _T_857 = tail(_T_856, 1) @[lib.scala 70:27]
|
||
|
|
node _T_858 = bits(_T_848, 12, 12) @[lib.scala 71:22]
|
||
|
|
node _T_859 = bits(_T_851, 12, 12) @[lib.scala 72:39]
|
||
|
|
node _T_860 = eq(_T_859, UInt<1>("h00")) @[lib.scala 72:28]
|
||
|
|
node _T_861 = xor(_T_858, _T_860) @[lib.scala 72:26]
|
||
|
|
node _T_862 = bits(_T_861, 0, 0) @[lib.scala 72:64]
|
||
|
|
node _T_863 = bits(_T_847, 31, 13) @[lib.scala 72:76]
|
||
|
|
node _T_864 = eq(_T_858, UInt<1>("h00")) @[lib.scala 73:20]
|
||
|
|
node _T_865 = bits(_T_851, 12, 12) @[lib.scala 73:39]
|
||
|
|
node _T_866 = and(_T_864, _T_865) @[lib.scala 73:26]
|
||
|
|
node _T_867 = bits(_T_866, 0, 0) @[lib.scala 73:64]
|
||
|
|
node _T_868 = bits(_T_851, 12, 12) @[lib.scala 74:39]
|
||
|
|
node _T_869 = eq(_T_868, UInt<1>("h00")) @[lib.scala 74:28]
|
||
|
|
node _T_870 = and(_T_858, _T_869) @[lib.scala 74:26]
|
||
|
|
node _T_871 = bits(_T_870, 0, 0) @[lib.scala 74:64]
|
||
|
|
node _T_872 = mux(_T_862, _T_863, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_873 = mux(_T_867, _T_854, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_874 = mux(_T_871, _T_857, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_875 = or(_T_872, _T_873) @[Mux.scala 27:72]
|
||
|
|
node _T_876 = or(_T_875, _T_874) @[Mux.scala 27:72]
|
||
|
|
wire _T_877 : UInt<19> @[Mux.scala 27:72]
|
||
|
|
_T_877 <= _T_876 @[Mux.scala 27:72]
|
||
|
|
node _T_878 = bits(_T_851, 11, 0) @[lib.scala 74:94]
|
||
|
|
node _T_879 = cat(_T_877, _T_878) @[Cat.scala 29:58]
|
||
|
|
node temp_pred_correct_npc_x = cat(_T_879, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 728:62]
|
||
|
|
io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 728:36]
|
||
|
|
node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 732:59]
|
||
|
|
node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 732:91]
|
||
|
|
node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 732:74]
|
||
|
|
node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 733:59]
|
||
|
|
node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 733:91]
|
||
|
|
node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 733:74]
|
||
|
|
node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 735:59]
|
||
|
|
node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 735:91]
|
||
|
|
node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 735:74]
|
||
|
|
node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 736:59]
|
||
|
|
node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 736:91]
|
||
|
|
node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 736:74]
|
||
|
|
node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 738:44]
|
||
|
|
node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 738:81]
|
||
|
|
wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 738:109]
|
||
|
|
_T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109]
|
||
|
|
_T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109]
|
||
|
|
_T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109]
|
||
|
|
node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 738:61]
|
||
|
|
node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 738:24]
|
||
|
|
i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 738:18]
|
||
|
|
i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 738:18]
|
||
|
|
i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 738:18]
|
||
|
|
node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 739:44]
|
||
|
|
node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 739:83]
|
||
|
|
node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 739:63]
|
||
|
|
node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 739:24]
|
||
|
|
i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 739:18]
|
||
|
|
node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 740:44]
|
||
|
|
node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 740:81]
|
||
|
|
wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 740:109]
|
||
|
|
_T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109]
|
||
|
|
_T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109]
|
||
|
|
_T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109]
|
||
|
|
node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 740:61]
|
||
|
|
node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 740:24]
|
||
|
|
i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 740:18]
|
||
|
|
i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 740:18]
|
||
|
|
i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 740:18]
|
||
|
|
node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 741:44]
|
||
|
|
node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 741:83]
|
||
|
|
node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 741:63]
|
||
|
|
node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 741:24]
|
||
|
|
i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 741:18]
|
||
|
|
i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 751:21]
|
||
|
|
node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 752:43]
|
||
|
|
node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 752:74]
|
||
|
|
node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 752:58]
|
||
|
|
node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 752:78]
|
||
|
|
load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 752:27]
|
||
|
|
node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 753:59]
|
||
|
|
node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 753:43]
|
||
|
|
node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 753:63]
|
||
|
|
store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 753:25]
|
||
|
|
store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 754:25]
|
||
|
|
node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 758:73]
|
||
|
|
node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 758:130]
|
||
|
|
node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 758:100]
|
||
|
|
node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 760:73]
|
||
|
|
node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 760:130]
|
||
|
|
node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 760:100]
|
||
|
|
node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:41]
|
||
|
|
node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:66]
|
||
|
|
node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 763:45]
|
||
|
|
node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:104]
|
||
|
|
node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:108]
|
||
|
|
node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 763:149]
|
||
|
|
node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:175]
|
||
|
|
node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:196]
|
||
|
|
node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 763:153]
|
||
|
|
node _T_927 = cat(_T_920, _T_922) @[Cat.scala 29:58]
|
||
|
|
node _T_928 = cat(_T_927, _T_926) @[Cat.scala 29:58]
|
||
|
|
i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 763:18]
|
||
|
|
node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:41]
|
||
|
|
node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:67]
|
||
|
|
node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 765:45]
|
||
|
|
node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:105]
|
||
|
|
node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:109]
|
||
|
|
node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 765:149]
|
||
|
|
node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:175]
|
||
|
|
node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:196]
|
||
|
|
node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 765:153]
|
||
|
|
node _T_938 = cat(_T_931, _T_933) @[Cat.scala 29:58]
|
||
|
|
node _T_939 = cat(_T_938, _T_937) @[Cat.scala 29:58]
|
||
|
|
i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 765:18]
|
||
|
|
node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:65]
|
||
|
|
node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 767:82]
|
||
|
|
node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 767:100]
|
||
|
|
node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 767:86]
|
||
|
|
node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:120]
|
||
|
|
node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 767:107]
|
||
|
|
node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 767:124]
|
||
|
|
node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 767:104]
|
||
|
|
node _T_948 = cat(_T_940, _T_947) @[Cat.scala 29:58]
|
||
|
|
io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 767:45]
|
||
|
|
node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:65]
|
||
|
|
node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 768:82]
|
||
|
|
node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 768:100]
|
||
|
|
node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 768:86]
|
||
|
|
node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:120]
|
||
|
|
node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 768:107]
|
||
|
|
node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 768:124]
|
||
|
|
node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 768:104]
|
||
|
|
node _T_957 = cat(_T_949, _T_956) @[Cat.scala 29:58]
|
||
|
|
io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 768:45]
|
||
|
|
node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 772:17]
|
||
|
|
node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 772:21]
|
||
|
|
node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:17]
|
||
|
|
node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 773:21]
|
||
|
|
node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 774:19]
|
||
|
|
node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 774:6]
|
||
|
|
node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 774:38]
|
||
|
|
node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 774:25]
|
||
|
|
node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 774:23]
|
||
|
|
node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:42]
|
||
|
|
node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 774:78]
|
||
|
|
node _T_969 = mux(_T_959, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_970 = mux(_T_961, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_971 = mux(_T_968, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_972 = or(_T_969, _T_970) @[Mux.scala 27:72]
|
||
|
|
node _T_973 = or(_T_972, _T_971) @[Mux.scala 27:72]
|
||
|
|
wire _T_974 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_974 <= _T_973 @[Mux.scala 27:72]
|
||
|
|
io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 771:42]
|
||
|
|
node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 777:17]
|
||
|
|
node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 777:21]
|
||
|
|
node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 778:17]
|
||
|
|
node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 778:21]
|
||
|
|
node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 779:19]
|
||
|
|
node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 779:6]
|
||
|
|
node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 779:38]
|
||
|
|
node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 779:25]
|
||
|
|
node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 779:23]
|
||
|
|
node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 779:42]
|
||
|
|
node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 779:78]
|
||
|
|
node _T_986 = mux(_T_976, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_987 = mux(_T_978, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_988 = mux(_T_985, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_989 = or(_T_986, _T_987) @[Mux.scala 27:72]
|
||
|
|
node _T_990 = or(_T_989, _T_988) @[Mux.scala 27:72]
|
||
|
|
wire _T_991 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_991 <= _T_990 @[Mux.scala 27:72]
|
||
|
|
io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 776:42]
|
||
|
|
node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 781:68]
|
||
|
|
node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 781:50]
|
||
|
|
node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 781:89]
|
||
|
|
node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 781:87]
|
||
|
|
node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 781:123]
|
||
|
|
node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 781:121]
|
||
|
|
node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 781:140]
|
||
|
|
io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 781:26]
|
||
|
|
node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 783:6]
|
||
|
|
node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 783:38]
|
||
|
|
node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 783:50]
|
||
|
|
node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 783:64]
|
||
|
|
node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 783:81]
|
||
|
|
node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 784:6]
|
||
|
|
node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 784:38]
|
||
|
|
node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 784:50]
|
||
|
|
node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 784:65]
|
||
|
|
node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 784:85]
|
||
|
|
node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 784:95]
|
||
|
|
node _T_1010 = cat(_T_1008, _T_1009) @[Cat.scala 29:58]
|
||
|
|
node _T_1011 = mux(_T_1002, _T_1003, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1012 = mux(_T_1007, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1013 = or(_T_1011, _T_1012) @[Mux.scala 27:72]
|
||
|
|
wire _T_1014 : UInt<12> @[Mux.scala 27:72]
|
||
|
|
_T_1014 <= _T_1013 @[Mux.scala 27:72]
|
||
|
|
io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 782:23]
|
||
|
|
|
||
|
|
extmodule gated_latch_20 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_20 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_20 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_21 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_21 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_21 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_22 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_22 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_22 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_23 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_23 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_23 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_24 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_24 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_24 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_25 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_25 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_25 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_26 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_26 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_26 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_27 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_27 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_27 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_28 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_28 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_28 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_29 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_29 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_29 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_30 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_30 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_30 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_31 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_31 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_31 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_32 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_32 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_32 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_33 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_33 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_33 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_34 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_34 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_34 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_35 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_35 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_35 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_36 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_36 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_36 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_37 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_37 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_37 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_38 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_38 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_38 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_39 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_39 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_39 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_40 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_40 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_40 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_41 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_41 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_41 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_42 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_42 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_42 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_43 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_43 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_43 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_44 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_44 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_44 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_45 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_45 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_45 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_46 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_46 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_46 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_47 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_47 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_47 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_48 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_48 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_48 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_49 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_49 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_49 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_50 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_50 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_50 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
module dec_gpr_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, flip scan_mode : UInt<1>, flip gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}
|
||
|
|
|
||
|
|
wire w0v : UInt<1>[32] @[dec_gpr_ctl.scala 27:30]
|
||
|
|
w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
w0v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
||
|
|
wire w1v : UInt<1>[32] @[dec_gpr_ctl.scala 30:30]
|
||
|
|
w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
w1v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
||
|
|
wire w2v : UInt<1>[32] @[dec_gpr_ctl.scala 33:30]
|
||
|
|
w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
w2v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
||
|
|
wire gpr_in : UInt<32>[32] @[dec_gpr_ctl.scala 36:30]
|
||
|
|
gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
gpr_in[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
||
|
|
wire gpr_out : UInt<32>[32] @[dec_gpr_ctl.scala 39:30]
|
||
|
|
gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
gpr_out[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
||
|
|
wire gpr_wr_en : UInt<32>
|
||
|
|
gpr_wr_en <= UInt<1>("h00")
|
||
|
|
w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 43:15]
|
||
|
|
w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 44:15]
|
||
|
|
w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 45:15]
|
||
|
|
gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 46:19]
|
||
|
|
gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 47:18]
|
||
|
|
io.gpr_exu.gpr_i0_rs1_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 48:32]
|
||
|
|
io.gpr_exu.gpr_i0_rs2_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 49:32]
|
||
|
|
node _T = eq(io.waddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_1 = and(io.wen0, _T) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[1] <= _T_1 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_3 = and(io.wen1, _T_2) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[1] <= _T_3 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_5 = and(io.wen2, _T_4) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[1] <= _T_5 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_8 = and(_T_7, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_11 = and(_T_10, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_12 = or(_T_8, _T_11) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_15 = and(_T_14, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_16 = or(_T_12, _T_15) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[1] <= _T_16 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_18 = and(io.wen0, _T_17) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[2] <= _T_18 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_20 = and(io.wen1, _T_19) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[2] <= _T_20 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_22 = and(io.wen2, _T_21) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[2] <= _T_22 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_25 = and(_T_24, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_28 = and(_T_27, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_29 = or(_T_25, _T_28) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_32 = and(_T_31, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_33 = or(_T_29, _T_32) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[2] <= _T_33 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_35 = and(io.wen0, _T_34) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[3] <= _T_35 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_37 = and(io.wen1, _T_36) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[3] <= _T_37 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_39 = and(io.wen2, _T_38) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[3] <= _T_39 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_42 = and(_T_41, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_45 = and(_T_44, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_46 = or(_T_42, _T_45) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_49 = and(_T_48, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_50 = or(_T_46, _T_49) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[3] <= _T_50 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_52 = and(io.wen0, _T_51) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[4] <= _T_52 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_54 = and(io.wen1, _T_53) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[4] <= _T_54 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_56 = and(io.wen2, _T_55) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[4] <= _T_56 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_59 = and(_T_58, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_62 = and(_T_61, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_63 = or(_T_59, _T_62) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_66 = and(_T_65, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_67 = or(_T_63, _T_66) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[4] <= _T_67 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_69 = and(io.wen0, _T_68) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[5] <= _T_69 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_71 = and(io.wen1, _T_70) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[5] <= _T_71 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_73 = and(io.wen2, _T_72) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[5] <= _T_73 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_76 = and(_T_75, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_79 = and(_T_78, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_80 = or(_T_76, _T_79) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_83 = and(_T_82, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_84 = or(_T_80, _T_83) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[5] <= _T_84 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_86 = and(io.wen0, _T_85) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[6] <= _T_86 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_88 = and(io.wen1, _T_87) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[6] <= _T_88 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_90 = and(io.wen2, _T_89) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[6] <= _T_90 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_93 = and(_T_92, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_96 = and(_T_95, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_97 = or(_T_93, _T_96) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_100 = and(_T_99, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_101 = or(_T_97, _T_100) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[6] <= _T_101 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_103 = and(io.wen0, _T_102) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[7] <= _T_103 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_105 = and(io.wen1, _T_104) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[7] <= _T_105 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_107 = and(io.wen2, _T_106) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[7] <= _T_107 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_110 = and(_T_109, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_113 = and(_T_112, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_114 = or(_T_110, _T_113) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_117 = and(_T_116, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_118 = or(_T_114, _T_117) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[7] <= _T_118 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_120 = and(io.wen0, _T_119) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[8] <= _T_120 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_122 = and(io.wen1, _T_121) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[8] <= _T_122 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_124 = and(io.wen2, _T_123) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[8] <= _T_124 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_127 = and(_T_126, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_130 = and(_T_129, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_131 = or(_T_127, _T_130) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_134 = and(_T_133, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_135 = or(_T_131, _T_134) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[8] <= _T_135 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_137 = and(io.wen0, _T_136) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[9] <= _T_137 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_139 = and(io.wen1, _T_138) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[9] <= _T_139 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_141 = and(io.wen2, _T_140) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[9] <= _T_141 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_144 = and(_T_143, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_147 = and(_T_146, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_148 = or(_T_144, _T_147) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_151 = and(_T_150, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_152 = or(_T_148, _T_151) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[9] <= _T_152 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_154 = and(io.wen0, _T_153) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[10] <= _T_154 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_156 = and(io.wen1, _T_155) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[10] <= _T_156 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_158 = and(io.wen2, _T_157) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[10] <= _T_158 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_161 = and(_T_160, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_164 = and(_T_163, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_165 = or(_T_161, _T_164) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_168 = and(_T_167, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_169 = or(_T_165, _T_168) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[10] <= _T_169 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_171 = and(io.wen0, _T_170) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[11] <= _T_171 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_173 = and(io.wen1, _T_172) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[11] <= _T_173 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_175 = and(io.wen2, _T_174) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[11] <= _T_175 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_178 = and(_T_177, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_181 = and(_T_180, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_182 = or(_T_178, _T_181) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_185 = and(_T_184, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_186 = or(_T_182, _T_185) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[11] <= _T_186 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_188 = and(io.wen0, _T_187) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[12] <= _T_188 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_190 = and(io.wen1, _T_189) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[12] <= _T_190 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_192 = and(io.wen2, _T_191) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[12] <= _T_192 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_195 = and(_T_194, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_198 = and(_T_197, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_199 = or(_T_195, _T_198) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_202 = and(_T_201, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_203 = or(_T_199, _T_202) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[12] <= _T_203 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_205 = and(io.wen0, _T_204) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[13] <= _T_205 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_207 = and(io.wen1, _T_206) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[13] <= _T_207 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_209 = and(io.wen2, _T_208) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[13] <= _T_209 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_212 = and(_T_211, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_215 = and(_T_214, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_216 = or(_T_212, _T_215) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_219 = and(_T_218, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_220 = or(_T_216, _T_219) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[13] <= _T_220 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_222 = and(io.wen0, _T_221) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[14] <= _T_222 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_224 = and(io.wen1, _T_223) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[14] <= _T_224 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_226 = and(io.wen2, _T_225) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[14] <= _T_226 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_229 = and(_T_228, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_232 = and(_T_231, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_233 = or(_T_229, _T_232) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_236 = and(_T_235, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_237 = or(_T_233, _T_236) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[14] <= _T_237 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_239 = and(io.wen0, _T_238) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[15] <= _T_239 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_241 = and(io.wen1, _T_240) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[15] <= _T_241 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_243 = and(io.wen2, _T_242) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[15] <= _T_243 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_246 = and(_T_245, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_249 = and(_T_248, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_250 = or(_T_246, _T_249) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_253 = and(_T_252, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_254 = or(_T_250, _T_253) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[15] <= _T_254 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_256 = and(io.wen0, _T_255) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[16] <= _T_256 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_258 = and(io.wen1, _T_257) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[16] <= _T_258 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_260 = and(io.wen2, _T_259) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[16] <= _T_260 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_263 = and(_T_262, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_266 = and(_T_265, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_267 = or(_T_263, _T_266) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_270 = and(_T_269, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_271 = or(_T_267, _T_270) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[16] <= _T_271 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_273 = and(io.wen0, _T_272) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[17] <= _T_273 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_275 = and(io.wen1, _T_274) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[17] <= _T_275 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_277 = and(io.wen2, _T_276) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[17] <= _T_277 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_280 = and(_T_279, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_283 = and(_T_282, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_284 = or(_T_280, _T_283) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_287 = and(_T_286, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_288 = or(_T_284, _T_287) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[17] <= _T_288 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_290 = and(io.wen0, _T_289) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[18] <= _T_290 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_292 = and(io.wen1, _T_291) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[18] <= _T_292 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_294 = and(io.wen2, _T_293) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[18] <= _T_294 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_297 = and(_T_296, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_300 = and(_T_299, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_301 = or(_T_297, _T_300) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_304 = and(_T_303, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_305 = or(_T_301, _T_304) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[18] <= _T_305 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_307 = and(io.wen0, _T_306) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[19] <= _T_307 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_309 = and(io.wen1, _T_308) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[19] <= _T_309 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_311 = and(io.wen2, _T_310) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[19] <= _T_311 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_314 = and(_T_313, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_317 = and(_T_316, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_318 = or(_T_314, _T_317) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_321 = and(_T_320, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_322 = or(_T_318, _T_321) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[19] <= _T_322 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_324 = and(io.wen0, _T_323) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[20] <= _T_324 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_326 = and(io.wen1, _T_325) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[20] <= _T_326 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_328 = and(io.wen2, _T_327) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[20] <= _T_328 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_331 = and(_T_330, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_334 = and(_T_333, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_335 = or(_T_331, _T_334) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_338 = and(_T_337, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_339 = or(_T_335, _T_338) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[20] <= _T_339 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_341 = and(io.wen0, _T_340) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[21] <= _T_341 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_343 = and(io.wen1, _T_342) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[21] <= _T_343 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_345 = and(io.wen2, _T_344) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[21] <= _T_345 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_348 = and(_T_347, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_351 = and(_T_350, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_352 = or(_T_348, _T_351) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_355 = and(_T_354, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_356 = or(_T_352, _T_355) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[21] <= _T_356 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_358 = and(io.wen0, _T_357) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[22] <= _T_358 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_360 = and(io.wen1, _T_359) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[22] <= _T_360 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_362 = and(io.wen2, _T_361) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[22] <= _T_362 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_365 = and(_T_364, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_368 = and(_T_367, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_369 = or(_T_365, _T_368) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_372 = and(_T_371, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_373 = or(_T_369, _T_372) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[22] <= _T_373 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_375 = and(io.wen0, _T_374) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[23] <= _T_375 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_377 = and(io.wen1, _T_376) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[23] <= _T_377 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_379 = and(io.wen2, _T_378) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[23] <= _T_379 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_382 = and(_T_381, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_385 = and(_T_384, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_386 = or(_T_382, _T_385) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_389 = and(_T_388, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_390 = or(_T_386, _T_389) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[23] <= _T_390 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_392 = and(io.wen0, _T_391) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[24] <= _T_392 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_394 = and(io.wen1, _T_393) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[24] <= _T_394 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_396 = and(io.wen2, _T_395) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[24] <= _T_396 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_399 = and(_T_398, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_402 = and(_T_401, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_403 = or(_T_399, _T_402) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_406 = and(_T_405, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_407 = or(_T_403, _T_406) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[24] <= _T_407 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_409 = and(io.wen0, _T_408) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[25] <= _T_409 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_411 = and(io.wen1, _T_410) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[25] <= _T_411 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_413 = and(io.wen2, _T_412) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[25] <= _T_413 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_416 = and(_T_415, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_419 = and(_T_418, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_420 = or(_T_416, _T_419) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_423 = and(_T_422, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_424 = or(_T_420, _T_423) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[25] <= _T_424 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_426 = and(io.wen0, _T_425) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[26] <= _T_426 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_428 = and(io.wen1, _T_427) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[26] <= _T_428 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_430 = and(io.wen2, _T_429) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[26] <= _T_430 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_433 = and(_T_432, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_436 = and(_T_435, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_437 = or(_T_433, _T_436) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_440 = and(_T_439, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_441 = or(_T_437, _T_440) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[26] <= _T_441 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_443 = and(io.wen0, _T_442) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[27] <= _T_443 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_445 = and(io.wen1, _T_444) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[27] <= _T_445 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_447 = and(io.wen2, _T_446) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[27] <= _T_447 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_450 = and(_T_449, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_453 = and(_T_452, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_454 = or(_T_450, _T_453) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_457 = and(_T_456, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_458 = or(_T_454, _T_457) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[27] <= _T_458 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_460 = and(io.wen0, _T_459) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[28] <= _T_460 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_462 = and(io.wen1, _T_461) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[28] <= _T_462 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_464 = and(io.wen2, _T_463) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[28] <= _T_464 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_467 = and(_T_466, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_470 = and(_T_469, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_471 = or(_T_467, _T_470) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_474 = and(_T_473, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_475 = or(_T_471, _T_474) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[28] <= _T_475 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_477 = and(io.wen0, _T_476) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[29] <= _T_477 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_479 = and(io.wen1, _T_478) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[29] <= _T_479 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_481 = and(io.wen2, _T_480) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[29] <= _T_481 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_484 = and(_T_483, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_487 = and(_T_486, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_488 = or(_T_484, _T_487) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_491 = and(_T_490, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_492 = or(_T_488, _T_491) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[29] <= _T_492 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_494 = and(io.wen0, _T_493) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[30] <= _T_494 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_496 = and(io.wen1, _T_495) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[30] <= _T_496 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_498 = and(io.wen2, _T_497) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[30] <= _T_498 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_501 = and(_T_500, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_504 = and(_T_503, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_505 = or(_T_501, _T_504) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_508 = and(_T_507, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_509 = or(_T_505, _T_508) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[30] <= _T_509 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 52:45]
|
||
|
|
node _T_511 = and(io.wen0, _T_510) @[dec_gpr_ctl.scala 52:33]
|
||
|
|
w0v[31] <= _T_511 @[dec_gpr_ctl.scala 52:21]
|
||
|
|
node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 53:45]
|
||
|
|
node _T_513 = and(io.wen1, _T_512) @[dec_gpr_ctl.scala 53:33]
|
||
|
|
w1v[31] <= _T_513 @[dec_gpr_ctl.scala 53:21]
|
||
|
|
node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[dec_gpr_ctl.scala 54:45]
|
||
|
|
node _T_515 = and(io.wen2, _T_514) @[dec_gpr_ctl.scala 54:33]
|
||
|
|
w2v[31] <= _T_515 @[dec_gpr_ctl.scala 54:21]
|
||
|
|
node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_518 = and(_T_517, io.wd0) @[dec_gpr_ctl.scala 55:42]
|
||
|
|
node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_521 = and(_T_520, io.wd1) @[dec_gpr_ctl.scala 55:71]
|
||
|
|
node _T_522 = or(_T_518, _T_521) @[dec_gpr_ctl.scala 55:52]
|
||
|
|
node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_525 = and(_T_524, io.wd2) @[dec_gpr_ctl.scala 55:100]
|
||
|
|
node _T_526 = or(_T_522, _T_525) @[dec_gpr_ctl.scala 55:81]
|
||
|
|
gpr_in[31] <= _T_526 @[dec_gpr_ctl.scala 55:21]
|
||
|
|
node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58]
|
||
|
|
node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58]
|
||
|
|
node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58]
|
||
|
|
node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58]
|
||
|
|
node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58]
|
||
|
|
node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58]
|
||
|
|
node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58]
|
||
|
|
node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58]
|
||
|
|
node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58]
|
||
|
|
node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58]
|
||
|
|
node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58]
|
||
|
|
node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58]
|
||
|
|
node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58]
|
||
|
|
node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58]
|
||
|
|
node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58]
|
||
|
|
node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58]
|
||
|
|
node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58]
|
||
|
|
node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58]
|
||
|
|
node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58]
|
||
|
|
node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58]
|
||
|
|
node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58]
|
||
|
|
node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58]
|
||
|
|
node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58]
|
||
|
|
node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58]
|
||
|
|
node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58]
|
||
|
|
node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58]
|
||
|
|
node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58]
|
||
|
|
node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58]
|
||
|
|
node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58]
|
||
|
|
node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58]
|
||
|
|
node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58]
|
||
|
|
node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58]
|
||
|
|
node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58]
|
||
|
|
node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58]
|
||
|
|
node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58]
|
||
|
|
node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58]
|
||
|
|
node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58]
|
||
|
|
node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58]
|
||
|
|
node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58]
|
||
|
|
node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58]
|
||
|
|
node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58]
|
||
|
|
node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58]
|
||
|
|
node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58]
|
||
|
|
node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58]
|
||
|
|
node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58]
|
||
|
|
node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58]
|
||
|
|
node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58]
|
||
|
|
node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58]
|
||
|
|
node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58]
|
||
|
|
node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58]
|
||
|
|
node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58]
|
||
|
|
node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58]
|
||
|
|
node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58]
|
||
|
|
node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58]
|
||
|
|
node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58]
|
||
|
|
node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58]
|
||
|
|
node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58]
|
||
|
|
node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58]
|
||
|
|
node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58]
|
||
|
|
node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58]
|
||
|
|
node _T_589 = or(_T_557, _T_588) @[dec_gpr_ctl.scala 57:57]
|
||
|
|
node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58]
|
||
|
|
node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58]
|
||
|
|
node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58]
|
||
|
|
node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58]
|
||
|
|
node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58]
|
||
|
|
node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58]
|
||
|
|
node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58]
|
||
|
|
node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58]
|
||
|
|
node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58]
|
||
|
|
node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58]
|
||
|
|
node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58]
|
||
|
|
node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58]
|
||
|
|
node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58]
|
||
|
|
node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58]
|
||
|
|
node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58]
|
||
|
|
node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58]
|
||
|
|
node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58]
|
||
|
|
node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58]
|
||
|
|
node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58]
|
||
|
|
node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58]
|
||
|
|
node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58]
|
||
|
|
node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58]
|
||
|
|
node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58]
|
||
|
|
node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58]
|
||
|
|
node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58]
|
||
|
|
node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58]
|
||
|
|
node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58]
|
||
|
|
node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58]
|
||
|
|
node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58]
|
||
|
|
node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58]
|
||
|
|
node _T_621 = or(_T_589, _T_620) @[dec_gpr_ctl.scala 57:95]
|
||
|
|
gpr_wr_en <= _T_621 @[dec_gpr_ctl.scala 57:18]
|
||
|
|
node _T_622 = bits(gpr_wr_en, 1, 1) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr of rvclkhdr_20 @[lib.scala 368:23]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr.io.en <= _T_622 @[lib.scala 371:17]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_623 <= gpr_in[1] @[lib.scala 374:16]
|
||
|
|
gpr_out[1] <= _T_623 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_624 = bits(gpr_wr_en, 2, 2) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_21 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_1.io.en <= _T_624 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_625 <= gpr_in[2] @[lib.scala 374:16]
|
||
|
|
gpr_out[2] <= _T_625 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_626 = bits(gpr_wr_en, 3, 3) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_22 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_2.io.en <= _T_626 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_627 <= gpr_in[3] @[lib.scala 374:16]
|
||
|
|
gpr_out[3] <= _T_627 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_628 = bits(gpr_wr_en, 4, 4) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_23 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_3.io.en <= _T_628 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_629 <= gpr_in[4] @[lib.scala 374:16]
|
||
|
|
gpr_out[4] <= _T_629 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_630 = bits(gpr_wr_en, 5, 5) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_4 of rvclkhdr_24 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_4.clock <= clock
|
||
|
|
rvclkhdr_4.reset <= reset
|
||
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_4.io.en <= _T_630 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_631 <= gpr_in[5] @[lib.scala 374:16]
|
||
|
|
gpr_out[5] <= _T_631 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_632 = bits(gpr_wr_en, 6, 6) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_5 of rvclkhdr_25 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_5.clock <= clock
|
||
|
|
rvclkhdr_5.reset <= reset
|
||
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_5.io.en <= _T_632 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_633 <= gpr_in[6] @[lib.scala 374:16]
|
||
|
|
gpr_out[6] <= _T_633 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_634 = bits(gpr_wr_en, 7, 7) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_6 of rvclkhdr_26 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_6.clock <= clock
|
||
|
|
rvclkhdr_6.reset <= reset
|
||
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_6.io.en <= _T_634 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_635 <= gpr_in[7] @[lib.scala 374:16]
|
||
|
|
gpr_out[7] <= _T_635 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_636 = bits(gpr_wr_en, 8, 8) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_7 of rvclkhdr_27 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_7.clock <= clock
|
||
|
|
rvclkhdr_7.reset <= reset
|
||
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_7.io.en <= _T_636 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_637 <= gpr_in[8] @[lib.scala 374:16]
|
||
|
|
gpr_out[8] <= _T_637 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_638 = bits(gpr_wr_en, 9, 9) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_8 of rvclkhdr_28 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_8.clock <= clock
|
||
|
|
rvclkhdr_8.reset <= reset
|
||
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_8.io.en <= _T_638 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_639 <= gpr_in[9] @[lib.scala 374:16]
|
||
|
|
gpr_out[9] <= _T_639 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_640 = bits(gpr_wr_en, 10, 10) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_9 of rvclkhdr_29 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_9.clock <= clock
|
||
|
|
rvclkhdr_9.reset <= reset
|
||
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_9.io.en <= _T_640 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_641 <= gpr_in[10] @[lib.scala 374:16]
|
||
|
|
gpr_out[10] <= _T_641 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_642 = bits(gpr_wr_en, 11, 11) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_10 of rvclkhdr_30 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_10.clock <= clock
|
||
|
|
rvclkhdr_10.reset <= reset
|
||
|
|
rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_10.io.en <= _T_642 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_643 <= gpr_in[11] @[lib.scala 374:16]
|
||
|
|
gpr_out[11] <= _T_643 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_644 = bits(gpr_wr_en, 12, 12) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_11 of rvclkhdr_31 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_11.clock <= clock
|
||
|
|
rvclkhdr_11.reset <= reset
|
||
|
|
rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_11.io.en <= _T_644 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_645 <= gpr_in[12] @[lib.scala 374:16]
|
||
|
|
gpr_out[12] <= _T_645 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_646 = bits(gpr_wr_en, 13, 13) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_12 of rvclkhdr_32 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_12.clock <= clock
|
||
|
|
rvclkhdr_12.reset <= reset
|
||
|
|
rvclkhdr_12.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_12.io.en <= _T_646 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_647 <= gpr_in[13] @[lib.scala 374:16]
|
||
|
|
gpr_out[13] <= _T_647 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_648 = bits(gpr_wr_en, 14, 14) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_13 of rvclkhdr_33 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_13.clock <= clock
|
||
|
|
rvclkhdr_13.reset <= reset
|
||
|
|
rvclkhdr_13.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_13.io.en <= _T_648 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_649 <= gpr_in[14] @[lib.scala 374:16]
|
||
|
|
gpr_out[14] <= _T_649 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_650 = bits(gpr_wr_en, 15, 15) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_14 of rvclkhdr_34 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_14.clock <= clock
|
||
|
|
rvclkhdr_14.reset <= reset
|
||
|
|
rvclkhdr_14.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_14.io.en <= _T_650 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_651 <= gpr_in[15] @[lib.scala 374:16]
|
||
|
|
gpr_out[15] <= _T_651 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_652 = bits(gpr_wr_en, 16, 16) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_15 of rvclkhdr_35 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_15.clock <= clock
|
||
|
|
rvclkhdr_15.reset <= reset
|
||
|
|
rvclkhdr_15.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_15.io.en <= _T_652 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_653 <= gpr_in[16] @[lib.scala 374:16]
|
||
|
|
gpr_out[16] <= _T_653 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_654 = bits(gpr_wr_en, 17, 17) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_16 of rvclkhdr_36 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_16.clock <= clock
|
||
|
|
rvclkhdr_16.reset <= reset
|
||
|
|
rvclkhdr_16.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_16.io.en <= _T_654 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_655 <= gpr_in[17] @[lib.scala 374:16]
|
||
|
|
gpr_out[17] <= _T_655 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_656 = bits(gpr_wr_en, 18, 18) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_17 of rvclkhdr_37 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_17.clock <= clock
|
||
|
|
rvclkhdr_17.reset <= reset
|
||
|
|
rvclkhdr_17.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_17.io.en <= _T_656 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_657 <= gpr_in[18] @[lib.scala 374:16]
|
||
|
|
gpr_out[18] <= _T_657 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_658 = bits(gpr_wr_en, 19, 19) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_18 of rvclkhdr_38 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_18.clock <= clock
|
||
|
|
rvclkhdr_18.reset <= reset
|
||
|
|
rvclkhdr_18.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_18.io.en <= _T_658 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_659 <= gpr_in[19] @[lib.scala 374:16]
|
||
|
|
gpr_out[19] <= _T_659 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_660 = bits(gpr_wr_en, 20, 20) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_19 of rvclkhdr_39 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_19.clock <= clock
|
||
|
|
rvclkhdr_19.reset <= reset
|
||
|
|
rvclkhdr_19.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_19.io.en <= _T_660 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_661 <= gpr_in[20] @[lib.scala 374:16]
|
||
|
|
gpr_out[20] <= _T_661 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_662 = bits(gpr_wr_en, 21, 21) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_20 of rvclkhdr_40 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_20.clock <= clock
|
||
|
|
rvclkhdr_20.reset <= reset
|
||
|
|
rvclkhdr_20.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_20.io.en <= _T_662 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_663 <= gpr_in[21] @[lib.scala 374:16]
|
||
|
|
gpr_out[21] <= _T_663 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_664 = bits(gpr_wr_en, 22, 22) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_21 of rvclkhdr_41 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_21.clock <= clock
|
||
|
|
rvclkhdr_21.reset <= reset
|
||
|
|
rvclkhdr_21.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_21.io.en <= _T_664 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_665 <= gpr_in[22] @[lib.scala 374:16]
|
||
|
|
gpr_out[22] <= _T_665 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_666 = bits(gpr_wr_en, 23, 23) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_22 of rvclkhdr_42 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_22.clock <= clock
|
||
|
|
rvclkhdr_22.reset <= reset
|
||
|
|
rvclkhdr_22.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_22.io.en <= _T_666 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_667 <= gpr_in[23] @[lib.scala 374:16]
|
||
|
|
gpr_out[23] <= _T_667 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_668 = bits(gpr_wr_en, 24, 24) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_23 of rvclkhdr_43 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_23.clock <= clock
|
||
|
|
rvclkhdr_23.reset <= reset
|
||
|
|
rvclkhdr_23.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_23.io.en <= _T_668 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_669 <= gpr_in[24] @[lib.scala 374:16]
|
||
|
|
gpr_out[24] <= _T_669 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_670 = bits(gpr_wr_en, 25, 25) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_24 of rvclkhdr_44 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_24.clock <= clock
|
||
|
|
rvclkhdr_24.reset <= reset
|
||
|
|
rvclkhdr_24.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_24.io.en <= _T_670 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_671 <= gpr_in[25] @[lib.scala 374:16]
|
||
|
|
gpr_out[25] <= _T_671 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_672 = bits(gpr_wr_en, 26, 26) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_25 of rvclkhdr_45 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_25.clock <= clock
|
||
|
|
rvclkhdr_25.reset <= reset
|
||
|
|
rvclkhdr_25.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_25.io.en <= _T_672 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_673 <= gpr_in[26] @[lib.scala 374:16]
|
||
|
|
gpr_out[26] <= _T_673 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_674 = bits(gpr_wr_en, 27, 27) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_26 of rvclkhdr_46 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_26.clock <= clock
|
||
|
|
rvclkhdr_26.reset <= reset
|
||
|
|
rvclkhdr_26.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_26.io.en <= _T_674 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_675 <= gpr_in[27] @[lib.scala 374:16]
|
||
|
|
gpr_out[27] <= _T_675 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_676 = bits(gpr_wr_en, 28, 28) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_27 of rvclkhdr_47 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_27.clock <= clock
|
||
|
|
rvclkhdr_27.reset <= reset
|
||
|
|
rvclkhdr_27.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_27.io.en <= _T_676 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_677 <= gpr_in[28] @[lib.scala 374:16]
|
||
|
|
gpr_out[28] <= _T_677 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_678 = bits(gpr_wr_en, 29, 29) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_28 of rvclkhdr_48 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_28.clock <= clock
|
||
|
|
rvclkhdr_28.reset <= reset
|
||
|
|
rvclkhdr_28.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_28.io.en <= _T_678 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_679 <= gpr_in[29] @[lib.scala 374:16]
|
||
|
|
gpr_out[29] <= _T_679 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_680 = bits(gpr_wr_en, 30, 30) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_29 of rvclkhdr_49 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_29.clock <= clock
|
||
|
|
rvclkhdr_29.reset <= reset
|
||
|
|
rvclkhdr_29.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_29.io.en <= _T_680 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_681 <= gpr_in[30] @[lib.scala 374:16]
|
||
|
|
gpr_out[30] <= _T_681 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_682 = bits(gpr_wr_en, 31, 31) @[dec_gpr_ctl.scala 61:49]
|
||
|
|
inst rvclkhdr_30 of rvclkhdr_50 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_30.clock <= clock
|
||
|
|
rvclkhdr_30.reset <= reset
|
||
|
|
rvclkhdr_30.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_30.io.en <= _T_682 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_683 <= gpr_in[31] @[lib.scala 374:16]
|
||
|
|
gpr_out[31] <= _T_683 @[dec_gpr_ctl.scala 61:21]
|
||
|
|
node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_685 = bits(_T_684, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_687 = bits(_T_686, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_689 = bits(_T_688, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_691 = bits(_T_690, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_693 = bits(_T_692, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_695 = bits(_T_694, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_697 = bits(_T_696, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_699 = bits(_T_698, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_701 = bits(_T_700, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_703 = bits(_T_702, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_705 = bits(_T_704, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_707 = bits(_T_706, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_709 = bits(_T_708, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_711 = bits(_T_710, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_713 = bits(_T_712, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_715 = bits(_T_714, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_717 = bits(_T_716, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_719 = bits(_T_718, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_721 = bits(_T_720, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_723 = bits(_T_722, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_725 = bits(_T_724, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_727 = bits(_T_726, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_729 = bits(_T_728, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_731 = bits(_T_730, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_733 = bits(_T_732, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_735 = bits(_T_734, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_737 = bits(_T_736, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_739 = bits(_T_738, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_741 = bits(_T_740, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_743 = bits(_T_742, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 64:72]
|
||
|
|
node _T_745 = bits(_T_744, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
||
|
|
node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72]
|
||
|
|
node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72]
|
||
|
|
node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72]
|
||
|
|
node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72]
|
||
|
|
node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72]
|
||
|
|
node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72]
|
||
|
|
node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72]
|
||
|
|
node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72]
|
||
|
|
node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72]
|
||
|
|
node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72]
|
||
|
|
node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72]
|
||
|
|
node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72]
|
||
|
|
node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72]
|
||
|
|
node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72]
|
||
|
|
node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72]
|
||
|
|
node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72]
|
||
|
|
node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72]
|
||
|
|
node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72]
|
||
|
|
node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72]
|
||
|
|
node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72]
|
||
|
|
node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72]
|
||
|
|
node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72]
|
||
|
|
node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72]
|
||
|
|
node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72]
|
||
|
|
node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72]
|
||
|
|
node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72]
|
||
|
|
node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72]
|
||
|
|
node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72]
|
||
|
|
node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72]
|
||
|
|
node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72]
|
||
|
|
wire _T_807 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_807 <= _T_806 @[Mux.scala 27:72]
|
||
|
|
io.gpr_exu.gpr_i0_rs1_d <= _T_807 @[dec_gpr_ctl.scala 64:32]
|
||
|
|
node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_809 = bits(_T_808, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_811 = bits(_T_810, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_813 = bits(_T_812, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_815 = bits(_T_814, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_817 = bits(_T_816, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_819 = bits(_T_818, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_821 = bits(_T_820, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_823 = bits(_T_822, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_825 = bits(_T_824, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_827 = bits(_T_826, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_829 = bits(_T_828, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_831 = bits(_T_830, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_833 = bits(_T_832, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_835 = bits(_T_834, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_837 = bits(_T_836, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_839 = bits(_T_838, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_841 = bits(_T_840, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_843 = bits(_T_842, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_845 = bits(_T_844, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_847 = bits(_T_846, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_849 = bits(_T_848, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_851 = bits(_T_850, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_853 = bits(_T_852, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_855 = bits(_T_854, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_857 = bits(_T_856, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_859 = bits(_T_858, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_861 = bits(_T_860, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_863 = bits(_T_862, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_865 = bits(_T_864, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_867 = bits(_T_866, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 65:72]
|
||
|
|
node _T_869 = bits(_T_868, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
||
|
|
node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72]
|
||
|
|
node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72]
|
||
|
|
node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72]
|
||
|
|
node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72]
|
||
|
|
node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72]
|
||
|
|
node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72]
|
||
|
|
node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72]
|
||
|
|
node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72]
|
||
|
|
node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72]
|
||
|
|
node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72]
|
||
|
|
node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72]
|
||
|
|
node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72]
|
||
|
|
node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72]
|
||
|
|
node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72]
|
||
|
|
node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72]
|
||
|
|
node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72]
|
||
|
|
node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72]
|
||
|
|
node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72]
|
||
|
|
node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72]
|
||
|
|
node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72]
|
||
|
|
node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72]
|
||
|
|
node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72]
|
||
|
|
node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72]
|
||
|
|
node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72]
|
||
|
|
node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72]
|
||
|
|
node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72]
|
||
|
|
node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72]
|
||
|
|
node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72]
|
||
|
|
node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72]
|
||
|
|
node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72]
|
||
|
|
wire _T_931 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_931 <= _T_930 @[Mux.scala 27:72]
|
||
|
|
io.gpr_exu.gpr_i0_rs2_d <= _T_931 @[dec_gpr_ctl.scala 65:32]
|
||
|
|
|
||
|
|
extmodule gated_latch_51 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_51 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_51 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_52 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_52 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_52 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_53 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_53 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_53 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_54 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_54 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_54 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
module dec_timer_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>}
|
||
|
|
|
||
|
|
wire mitctl1 : UInt<4>
|
||
|
|
mitctl1 <= UInt<1>("h00")
|
||
|
|
wire mitctl0 : UInt<3>
|
||
|
|
mitctl0 <= UInt<1>("h00")
|
||
|
|
wire mitb1 : UInt<32>
|
||
|
|
mitb1 <= UInt<1>("h00")
|
||
|
|
wire mitb0 : UInt<32>
|
||
|
|
mitb0 <= UInt<1>("h00")
|
||
|
|
wire mitcnt1 : UInt<32>
|
||
|
|
mitcnt1 <= UInt<1>("h00")
|
||
|
|
wire mitcnt0 : UInt<32>
|
||
|
|
mitcnt0 <= UInt<1>("h00")
|
||
|
|
node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2672:36]
|
||
|
|
node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2673:36]
|
||
|
|
io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2675:31]
|
||
|
|
io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2676:31]
|
||
|
|
node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2683:72]
|
||
|
|
node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2683:49]
|
||
|
|
node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2685:37]
|
||
|
|
node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2685:56]
|
||
|
|
node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2685:85]
|
||
|
|
node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2685:76]
|
||
|
|
node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2685:53]
|
||
|
|
node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2685:112]
|
||
|
|
node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2685:147]
|
||
|
|
node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2685:138]
|
||
|
|
node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2685:109]
|
||
|
|
node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2685:173]
|
||
|
|
node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2685:171]
|
||
|
|
node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2686:35]
|
||
|
|
node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2686:35]
|
||
|
|
node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2687:44]
|
||
|
|
node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2687:74]
|
||
|
|
node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2687:60]
|
||
|
|
node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2687:29]
|
||
|
|
node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2688:59]
|
||
|
|
node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2688:76]
|
||
|
|
node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2688:93]
|
||
|
|
inst rvclkhdr of rvclkhdr_51 @[lib.scala 368:23]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr.io.en <= _T_17 @[lib.scala 371:17]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_18 <= mitcnt0_ns @[lib.scala 374:16]
|
||
|
|
mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2688:25]
|
||
|
|
node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2695:72]
|
||
|
|
node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2695:49]
|
||
|
|
node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2697:37]
|
||
|
|
node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2697:56]
|
||
|
|
node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2697:85]
|
||
|
|
node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2697:76]
|
||
|
|
node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2697:53]
|
||
|
|
node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2697:112]
|
||
|
|
node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2697:147]
|
||
|
|
node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2697:138]
|
||
|
|
node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2697:109]
|
||
|
|
node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2697:173]
|
||
|
|
node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2697:171]
|
||
|
|
node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2700:68]
|
||
|
|
node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2700:60]
|
||
|
|
node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2700:72]
|
||
|
|
node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58]
|
||
|
|
node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2700:35]
|
||
|
|
node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2700:35]
|
||
|
|
node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2701:45]
|
||
|
|
node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2701:75]
|
||
|
|
node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2701:61]
|
||
|
|
node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2701:30]
|
||
|
|
node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2702:60]
|
||
|
|
node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2702:77]
|
||
|
|
node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2702:94]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_52 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_1.io.en <= _T_41 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_42 <= mitcnt1_ns @[lib.scala 374:16]
|
||
|
|
mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2702:25]
|
||
|
|
node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2709:70]
|
||
|
|
node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2709:47]
|
||
|
|
node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2710:38]
|
||
|
|
node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2710:71]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_53 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_2.io.en <= _T_45 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
mitb0_b <= _T_44 @[lib.scala 374:16]
|
||
|
|
node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2711:22]
|
||
|
|
mitb0 <= _T_46 @[dec_tlu_ctl.scala 2711:19]
|
||
|
|
node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2718:69]
|
||
|
|
node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2718:47]
|
||
|
|
node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2719:29]
|
||
|
|
node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2719:62]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_54 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_3.io.en <= _T_49 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
mitb1_b <= _T_48 @[lib.scala 374:16]
|
||
|
|
node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2720:18]
|
||
|
|
mitb1 <= _T_50 @[dec_tlu_ctl.scala 2720:15]
|
||
|
|
node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2731:72]
|
||
|
|
node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2731:49]
|
||
|
|
node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2732:45]
|
||
|
|
node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2732:72]
|
||
|
|
node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2732:86]
|
||
|
|
node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2732:31]
|
||
|
|
node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2734:41]
|
||
|
|
node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2734:30]
|
||
|
|
reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2735:60]
|
||
|
|
mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2735:60]
|
||
|
|
node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2736:78]
|
||
|
|
reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:67]
|
||
|
|
_T_57 <= _T_56 @[dec_tlu_ctl.scala 2736:67]
|
||
|
|
node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2736:90]
|
||
|
|
node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58]
|
||
|
|
mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2736:31]
|
||
|
|
node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2746:71]
|
||
|
|
node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2746:49]
|
||
|
|
node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2747:45]
|
||
|
|
node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2747:71]
|
||
|
|
node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2747:85]
|
||
|
|
node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2747:31]
|
||
|
|
node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2748:40]
|
||
|
|
node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2748:29]
|
||
|
|
reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2749:55]
|
||
|
|
mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2749:55]
|
||
|
|
node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2750:63]
|
||
|
|
reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:52]
|
||
|
|
_T_66 <= _T_65 @[dec_tlu_ctl.scala 2750:52]
|
||
|
|
node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2750:75]
|
||
|
|
node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58]
|
||
|
|
mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2750:16]
|
||
|
|
node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2752:51]
|
||
|
|
node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2752:68]
|
||
|
|
node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2752:83]
|
||
|
|
node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2752:98]
|
||
|
|
node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2752:115]
|
||
|
|
io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2752:33]
|
||
|
|
node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2754:25]
|
||
|
|
node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2754:44]
|
||
|
|
node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2755:32]
|
||
|
|
node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2756:30]
|
||
|
|
node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2757:30]
|
||
|
|
node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2758:32]
|
||
|
|
node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58]
|
||
|
|
node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2759:32]
|
||
|
|
node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58]
|
||
|
|
node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_86 = mux(_T_76, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_87 = mux(_T_77, mitb0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_88 = mux(_T_78, mitb1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_89 = mux(_T_79, _T_81, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_90 = mux(_T_82, _T_84, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_91 = or(_T_85, _T_86) @[Mux.scala 27:72]
|
||
|
|
node _T_92 = or(_T_91, _T_87) @[Mux.scala 27:72]
|
||
|
|
node _T_93 = or(_T_92, _T_88) @[Mux.scala 27:72]
|
||
|
|
node _T_94 = or(_T_93, _T_89) @[Mux.scala 27:72]
|
||
|
|
node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72]
|
||
|
|
wire _T_96 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_96 <= _T_95 @[Mux.scala 27:72]
|
||
|
|
io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2753:33]
|
||
|
|
|
||
|
|
extmodule gated_latch_55 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_55 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_55 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_56 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_56 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_56 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_57 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_57 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_57 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_58 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_58 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_58 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_59 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_59 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_59 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_60 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_60 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_60 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_61 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_61 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_61 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_62 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_62 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_62 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_63 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_63 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_63 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_64 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_64 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_64 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_65 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_65 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_65 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_66 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_66 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_66 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_67 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_67 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_67 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_68 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_68 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_68 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_69 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_69 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_69 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_70 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_70 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_70 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_71 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_71 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_71 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_72 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_72 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_72 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_73 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_73 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_73 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_74 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_74 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_74 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_75 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_75 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_75 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_76 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_76 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_76 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_77 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_77 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_77 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_78 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_78 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_78 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_79 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_79 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_79 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_80 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_80 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_80 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_81 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_81 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_81 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_82 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_82 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_82 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_83 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_83 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_83 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_84 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_84 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_84 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_85 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_85 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_85 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_86 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_86 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_86 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_87 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_87 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_87 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_88 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_88 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_88 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_89 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_89 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_89 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_90 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_90 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_90 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_91 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_91 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_91 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_92 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_92 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_92 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_93 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_93 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_93 @[lib.scala 334:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||
|
|
|
||
|
|
module csr_tlu :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_f
|
||
|
|
|
||
|
|
wire miccme_ce_req : UInt<1>
|
||
|
|
miccme_ce_req <= UInt<1>("h00")
|
||
|
|
wire mice_ce_req : UInt<1>
|
||
|
|
mice_ce_req <= UInt<1>("h00")
|
||
|
|
wire mdccme_ce_req : UInt<1>
|
||
|
|
mdccme_ce_req <= UInt<1>("h00")
|
||
|
|
wire pc_r_d1 : UInt<31>
|
||
|
|
pc_r_d1 <= UInt<1>("h00")
|
||
|
|
wire mpmc_b_ns : UInt<1>
|
||
|
|
mpmc_b_ns <= UInt<1>("h00")
|
||
|
|
wire mpmc_b : UInt<1>
|
||
|
|
mpmc_b <= UInt<1>("h00")
|
||
|
|
wire wr_mcycleh_r : UInt<1>
|
||
|
|
wr_mcycleh_r <= UInt<1>("h00")
|
||
|
|
wire mcycleh : UInt<32>
|
||
|
|
mcycleh <= UInt<1>("h00")
|
||
|
|
wire minstretl_inc : UInt<33>
|
||
|
|
minstretl_inc <= UInt<1>("h00")
|
||
|
|
wire wr_minstreth_r : UInt<1>
|
||
|
|
wr_minstreth_r <= UInt<1>("h00")
|
||
|
|
wire minstretl : UInt<32>
|
||
|
|
minstretl <= UInt<1>("h00")
|
||
|
|
wire minstreth_inc : UInt<32>
|
||
|
|
minstreth_inc <= UInt<1>("h00")
|
||
|
|
wire minstreth : UInt<32>
|
||
|
|
minstreth <= UInt<1>("h00")
|
||
|
|
wire mfdc_ns : UInt<15>
|
||
|
|
mfdc_ns <= UInt<1>("h00")
|
||
|
|
wire mfdc_int : UInt<15>
|
||
|
|
mfdc_int <= UInt<1>("h00")
|
||
|
|
wire mhpmc6_incr : UInt<64>
|
||
|
|
mhpmc6_incr <= UInt<1>("h00")
|
||
|
|
wire mhpmc5_incr : UInt<64>
|
||
|
|
mhpmc5_incr <= UInt<1>("h00")
|
||
|
|
wire mhpmc4_incr : UInt<64>
|
||
|
|
mhpmc4_incr <= UInt<1>("h00")
|
||
|
|
wire perfcnt_halted : UInt<1>
|
||
|
|
perfcnt_halted <= UInt<1>("h00")
|
||
|
|
wire mhpmc3_incr : UInt<64>
|
||
|
|
mhpmc3_incr <= UInt<1>("h00")
|
||
|
|
wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1393:41]
|
||
|
|
wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1394:65]
|
||
|
|
wire wr_meicpct_r : UInt<1>
|
||
|
|
wr_meicpct_r <= UInt<1>("h00")
|
||
|
|
wire force_halt_ctr_f : UInt<32>
|
||
|
|
force_halt_ctr_f <= UInt<1>("h00")
|
||
|
|
wire mdccmect_inc : UInt<27>
|
||
|
|
mdccmect_inc <= UInt<1>("h00")
|
||
|
|
wire miccmect_inc : UInt<27>
|
||
|
|
miccmect_inc <= UInt<1>("h00")
|
||
|
|
wire micect_inc : UInt<27>
|
||
|
|
micect_inc <= UInt<1>("h00")
|
||
|
|
wire mdseac_en : UInt<1>
|
||
|
|
mdseac_en <= UInt<1>("h00")
|
||
|
|
wire mie : UInt<6>
|
||
|
|
mie <= UInt<1>("h00")
|
||
|
|
wire mcyclel : UInt<32>
|
||
|
|
mcyclel <= UInt<1>("h00")
|
||
|
|
wire mscratch : UInt<32>
|
||
|
|
mscratch <= UInt<1>("h00")
|
||
|
|
wire mcause : UInt<32>
|
||
|
|
mcause <= UInt<1>("h00")
|
||
|
|
wire mscause : UInt<4>
|
||
|
|
mscause <= UInt<1>("h00")
|
||
|
|
wire mtval : UInt<32>
|
||
|
|
mtval <= UInt<1>("h00")
|
||
|
|
wire meicurpl : UInt<4>
|
||
|
|
meicurpl <= UInt<1>("h00")
|
||
|
|
wire meicidpl : UInt<4>
|
||
|
|
meicidpl <= UInt<1>("h00")
|
||
|
|
wire meipt : UInt<4>
|
||
|
|
meipt <= UInt<1>("h00")
|
||
|
|
wire mfdc : UInt<19>
|
||
|
|
mfdc <= UInt<1>("h00")
|
||
|
|
wire mtsel : UInt<2>
|
||
|
|
mtsel <= UInt<1>("h00")
|
||
|
|
wire micect : UInt<32>
|
||
|
|
micect <= UInt<1>("h00")
|
||
|
|
wire miccmect : UInt<32>
|
||
|
|
miccmect <= UInt<1>("h00")
|
||
|
|
wire mdccmect : UInt<32>
|
||
|
|
mdccmect <= UInt<1>("h00")
|
||
|
|
wire mhpmc3h : UInt<32>
|
||
|
|
mhpmc3h <= UInt<1>("h00")
|
||
|
|
wire mhpmc3 : UInt<32>
|
||
|
|
mhpmc3 <= UInt<1>("h00")
|
||
|
|
wire mhpmc4h : UInt<32>
|
||
|
|
mhpmc4h <= UInt<1>("h00")
|
||
|
|
wire mhpmc4 : UInt<32>
|
||
|
|
mhpmc4 <= UInt<1>("h00")
|
||
|
|
wire mhpmc5h : UInt<32>
|
||
|
|
mhpmc5h <= UInt<1>("h00")
|
||
|
|
wire mhpmc5 : UInt<32>
|
||
|
|
mhpmc5 <= UInt<1>("h00")
|
||
|
|
wire mhpmc6h : UInt<32>
|
||
|
|
mhpmc6h <= UInt<1>("h00")
|
||
|
|
wire mhpmc6 : UInt<32>
|
||
|
|
mhpmc6 <= UInt<1>("h00")
|
||
|
|
wire mhpme3 : UInt<10>
|
||
|
|
mhpme3 <= UInt<1>("h00")
|
||
|
|
wire mhpme4 : UInt<10>
|
||
|
|
mhpme4 <= UInt<1>("h00")
|
||
|
|
wire mhpme5 : UInt<10>
|
||
|
|
mhpme5 <= UInt<1>("h00")
|
||
|
|
wire mhpme6 : UInt<10>
|
||
|
|
mhpme6 <= UInt<1>("h00")
|
||
|
|
wire mfdht : UInt<6>
|
||
|
|
mfdht <= UInt<1>("h00")
|
||
|
|
wire mfdhs : UInt<2>
|
||
|
|
mfdhs <= UInt<1>("h00")
|
||
|
|
wire mcountinhibit : UInt<7>
|
||
|
|
mcountinhibit <= UInt<1>("h00")
|
||
|
|
wire mpmc : UInt<1>
|
||
|
|
mpmc <= UInt<1>("h00")
|
||
|
|
wire dicad1 : UInt<32>
|
||
|
|
dicad1 <= UInt<1>("h00")
|
||
|
|
node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1449:45]
|
||
|
|
node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1449:43]
|
||
|
|
node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1449:68]
|
||
|
|
node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1449:66]
|
||
|
|
io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1449:23]
|
||
|
|
node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1450:64]
|
||
|
|
node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1450:71]
|
||
|
|
node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1450:42]
|
||
|
|
node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1453:28]
|
||
|
|
node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1453:39]
|
||
|
|
node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1456:5]
|
||
|
|
node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1456:19]
|
||
|
|
node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1456:44]
|
||
|
|
node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1456:68]
|
||
|
|
node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1456:68]
|
||
|
|
node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1457:18]
|
||
|
|
node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1457:43]
|
||
|
|
node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1457:76]
|
||
|
|
node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:17]
|
||
|
|
node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1458:15]
|
||
|
|
node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1458:41]
|
||
|
|
node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1458:70]
|
||
|
|
node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58]
|
||
|
|
node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1459:26]
|
||
|
|
node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1459:50]
|
||
|
|
node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58]
|
||
|
|
node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1460:20]
|
||
|
|
node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1460:18]
|
||
|
|
node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1460:44]
|
||
|
|
node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1460:77]
|
||
|
|
node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1460:101]
|
||
|
|
node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58]
|
||
|
|
node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:5]
|
||
|
|
node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:21]
|
||
|
|
node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1461:19]
|
||
|
|
node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:46]
|
||
|
|
node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1461:44]
|
||
|
|
node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:59]
|
||
|
|
node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1461:57]
|
||
|
|
node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1461:81]
|
||
|
|
node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_42 = mux(_T_22, _T_24, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_43 = mux(_T_27, _T_30, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_44 = mux(_T_38, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_45 = or(_T_39, _T_40) @[Mux.scala 27:72]
|
||
|
|
node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72]
|
||
|
|
node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72]
|
||
|
|
node _T_48 = or(_T_47, _T_43) @[Mux.scala 27:72]
|
||
|
|
node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72]
|
||
|
|
wire mstatus_ns : UInt<2> @[Mux.scala 27:72]
|
||
|
|
mstatus_ns <= _T_49 @[Mux.scala 27:72]
|
||
|
|
node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1464:33]
|
||
|
|
node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1464:33]
|
||
|
|
node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1464:50]
|
||
|
|
node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1464:90]
|
||
|
|
node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1464:81]
|
||
|
|
node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1464:47]
|
||
|
|
io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1464:20]
|
||
|
|
reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1466:11]
|
||
|
|
_T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1466:11]
|
||
|
|
io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1465:13]
|
||
|
|
node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1475:62]
|
||
|
|
node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1475:69]
|
||
|
|
node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1475:40]
|
||
|
|
node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1476:40]
|
||
|
|
node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1476:68]
|
||
|
|
node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58]
|
||
|
|
node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1477:42]
|
||
|
|
inst rvclkhdr of rvclkhdr_59 @[lib.scala 368:23]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr.io.en <= _T_61 @[lib.scala 371:17]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_62 <= mtvec_ns @[lib.scala 374:16]
|
||
|
|
io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1477:11]
|
||
|
|
node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1489:30]
|
||
|
|
node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1489:46]
|
||
|
|
node _T_64 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58]
|
||
|
|
node _T_65 = cat(_T_64, io.soft_int_sync) @[Cat.scala 29:58]
|
||
|
|
node _T_66 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58]
|
||
|
|
node _T_67 = cat(_T_66, io.dec_timer_t1_pulse) @[Cat.scala 29:58]
|
||
|
|
node mip_ns = cat(_T_67, _T_65) @[Cat.scala 29:58]
|
||
|
|
reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1493:11]
|
||
|
|
_T_68 <= mip_ns @[dec_tlu_ctl.scala 1493:11]
|
||
|
|
io.mip <= _T_68 @[dec_tlu_ctl.scala 1492:9]
|
||
|
|
node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1505:60]
|
||
|
|
node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1505:67]
|
||
|
|
node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1505:38]
|
||
|
|
node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1506:28]
|
||
|
|
node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1506:59]
|
||
|
|
node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1506:88]
|
||
|
|
node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1506:113]
|
||
|
|
node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1506:137]
|
||
|
|
node _T_76 = cat(_T_74, _T_75) @[Cat.scala 29:58]
|
||
|
|
node _T_77 = cat(_T_72, _T_73) @[Cat.scala 29:58]
|
||
|
|
node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
|
||
|
|
node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1506:18]
|
||
|
|
io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1506:12]
|
||
|
|
reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1508:11]
|
||
|
|
_T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1508:11]
|
||
|
|
mie <= _T_80 @[dec_tlu_ctl.scala 1507:6]
|
||
|
|
node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1515:63]
|
||
|
|
node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1515:54]
|
||
|
|
node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1517:64]
|
||
|
|
node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1517:71]
|
||
|
|
node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1517:42]
|
||
|
|
node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1519:80]
|
||
|
|
node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1519:71]
|
||
|
|
node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1519:46]
|
||
|
|
node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1519:94]
|
||
|
|
node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1519:136]
|
||
|
|
node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1519:121]
|
||
|
|
node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1519:24]
|
||
|
|
wire mcyclel_inc : UInt<33>
|
||
|
|
mcyclel_inc <= UInt<1>("h00")
|
||
|
|
node _T_90 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58]
|
||
|
|
node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1523:25]
|
||
|
|
mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1523:14]
|
||
|
|
node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1524:36]
|
||
|
|
node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1524:76]
|
||
|
|
node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1524:22]
|
||
|
|
node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1525:32]
|
||
|
|
node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1525:37]
|
||
|
|
node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1526:46]
|
||
|
|
node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1526:72]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_60 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_1.io.en <= _T_96 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_97 <= mcyclel_ns @[lib.scala 374:16]
|
||
|
|
mcyclel <= _T_97 @[dec_tlu_ctl.scala 1526:10]
|
||
|
|
node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1527:71]
|
||
|
|
node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1527:69]
|
||
|
|
reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1527:54]
|
||
|
|
mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1527:54]
|
||
|
|
node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1533:61]
|
||
|
|
node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1533:68]
|
||
|
|
node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1533:39]
|
||
|
|
wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1533:15]
|
||
|
|
node _T_103 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58]
|
||
|
|
node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1535:28]
|
||
|
|
node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1535:28]
|
||
|
|
node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1536:36]
|
||
|
|
node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1536:22]
|
||
|
|
node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1538:46]
|
||
|
|
node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1538:64]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_61 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_2.io.en <= _T_107 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_108 <= mcycleh_ns @[lib.scala 374:16]
|
||
|
|
mcycleh <= _T_108 @[dec_tlu_ctl.scala 1538:10]
|
||
|
|
node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1552:72]
|
||
|
|
node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1552:85]
|
||
|
|
node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1552:113]
|
||
|
|
node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1552:143]
|
||
|
|
node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1552:128]
|
||
|
|
node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1552:148]
|
||
|
|
node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1552:58]
|
||
|
|
node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1552:56]
|
||
|
|
node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1554:66]
|
||
|
|
node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1554:73]
|
||
|
|
node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1554:44]
|
||
|
|
node _T_118 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58]
|
||
|
|
node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1556:29]
|
||
|
|
minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1556:16]
|
||
|
|
node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1557:36]
|
||
|
|
node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1558:52]
|
||
|
|
node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1558:70]
|
||
|
|
node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1560:40]
|
||
|
|
node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1560:83]
|
||
|
|
node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1560:24]
|
||
|
|
node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1561:51]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_62 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_3.io.en <= _T_123 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_124 <= minstretl_ns @[lib.scala 374:16]
|
||
|
|
minstretl <= _T_124 @[dec_tlu_ctl.scala 1561:12]
|
||
|
|
reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1562:56]
|
||
|
|
minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1562:56]
|
||
|
|
node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1563:75]
|
||
|
|
node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1563:73]
|
||
|
|
reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1563:56]
|
||
|
|
minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1563:56]
|
||
|
|
node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1571:64]
|
||
|
|
node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1571:71]
|
||
|
|
node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1571:42]
|
||
|
|
node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1571:87]
|
||
|
|
wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1571:17]
|
||
|
|
node _T_131 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58]
|
||
|
|
node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1574:29]
|
||
|
|
node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1574:29]
|
||
|
|
minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1574:16]
|
||
|
|
node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1575:41]
|
||
|
|
node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1575:25]
|
||
|
|
node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1577:55]
|
||
|
|
node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1577:73]
|
||
|
|
inst rvclkhdr_4 of rvclkhdr_63 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_4.clock <= clock
|
||
|
|
rvclkhdr_4.reset <= reset
|
||
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_4.io.en <= _T_136 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_137 <= minstreth_ns @[lib.scala 374:16]
|
||
|
|
minstreth <= _T_137 @[dec_tlu_ctl.scala 1577:12]
|
||
|
|
node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1585:65]
|
||
|
|
node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1585:72]
|
||
|
|
node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1585:43]
|
||
|
|
node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1587:55]
|
||
|
|
inst rvclkhdr_5 of rvclkhdr_64 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_5.clock <= clock
|
||
|
|
rvclkhdr_5.reset <= reset
|
||
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_5.io.en <= _T_140 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_141 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
|
||
|
|
mscratch <= _T_141 @[dec_tlu_ctl.scala 1587:11]
|
||
|
|
node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1596:22]
|
||
|
|
node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1596:47]
|
||
|
|
node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1596:45]
|
||
|
|
node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1596:72]
|
||
|
|
node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:24]
|
||
|
|
node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1597:47]
|
||
|
|
node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:75]
|
||
|
|
node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1597:73]
|
||
|
|
node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:23]
|
||
|
|
node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:40]
|
||
|
|
node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1598:38]
|
||
|
|
node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1601:26]
|
||
|
|
node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1602:13]
|
||
|
|
node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1602:35]
|
||
|
|
node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1602:55]
|
||
|
|
node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1603:28]
|
||
|
|
node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1604:27]
|
||
|
|
node _T_156 = mux(_T_150, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_157 = mux(_T_153, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_158 = mux(_T_154, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_159 = mux(_T_155, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_160 = or(_T_156, _T_157) @[Mux.scala 27:72]
|
||
|
|
node _T_161 = or(_T_160, _T_158) @[Mux.scala 27:72]
|
||
|
|
node _T_162 = or(_T_161, _T_159) @[Mux.scala 27:72]
|
||
|
|
wire _T_163 : UInt<31> @[Mux.scala 27:72]
|
||
|
|
_T_163 <= _T_162 @[Mux.scala 27:72]
|
||
|
|
io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1600:11]
|
||
|
|
node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1606:48]
|
||
|
|
node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1606:66]
|
||
|
|
node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1606:86]
|
||
|
|
inst rvclkhdr_6 of rvclkhdr_65 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_6.clock <= clock
|
||
|
|
rvclkhdr_6.reset <= reset
|
||
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_6.io.en <= _T_166 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_167 <= io.npc_r @[lib.scala 374:16]
|
||
|
|
io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1606:14]
|
||
|
|
node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1609:21]
|
||
|
|
node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1609:44]
|
||
|
|
node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1609:69]
|
||
|
|
node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1613:22]
|
||
|
|
node _T_171 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_172 = mux(_T_170, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72]
|
||
|
|
wire pc_r : UInt<31> @[Mux.scala 27:72]
|
||
|
|
pc_r <= _T_173 @[Mux.scala 27:72]
|
||
|
|
inst rvclkhdr_7 of rvclkhdr_66 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_7.clock <= clock
|
||
|
|
rvclkhdr_7.reset <= reset
|
||
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_7.io.en <= pc0_valid_r @[lib.scala 371:17]
|
||
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_174 <= pc_r @[lib.scala 374:16]
|
||
|
|
pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1615:10]
|
||
|
|
node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1617:61]
|
||
|
|
node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1617:68]
|
||
|
|
node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1617:39]
|
||
|
|
node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1620:27]
|
||
|
|
node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1620:48]
|
||
|
|
node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1620:80]
|
||
|
|
node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1621:25]
|
||
|
|
node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1622:15]
|
||
|
|
node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1622:13]
|
||
|
|
node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1622:39]
|
||
|
|
node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1622:104]
|
||
|
|
node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1623:3]
|
||
|
|
node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1623:16]
|
||
|
|
node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1623:14]
|
||
|
|
node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1623:40]
|
||
|
|
node _T_189 = mux(_T_179, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_190 = mux(_T_180, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_191 = mux(_T_183, _T_184, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_192 = mux(_T_188, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_193 = or(_T_189, _T_190) @[Mux.scala 27:72]
|
||
|
|
node _T_194 = or(_T_193, _T_191) @[Mux.scala 27:72]
|
||
|
|
node _T_195 = or(_T_194, _T_192) @[Mux.scala 27:72]
|
||
|
|
wire mepc_ns : UInt<31> @[Mux.scala 27:72]
|
||
|
|
mepc_ns <= _T_195 @[Mux.scala 27:72]
|
||
|
|
reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1625:47]
|
||
|
|
_T_196 <= mepc_ns @[dec_tlu_ctl.scala 1625:47]
|
||
|
|
io.mepc <= _T_196 @[dec_tlu_ctl.scala 1625:10]
|
||
|
|
node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1632:65]
|
||
|
|
node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1632:72]
|
||
|
|
node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1632:43]
|
||
|
|
node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1633:53]
|
||
|
|
node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1633:67]
|
||
|
|
node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1634:52]
|
||
|
|
node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1634:66]
|
||
|
|
node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1635:51]
|
||
|
|
node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1635:84]
|
||
|
|
node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1635:65]
|
||
|
|
node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1641:53]
|
||
|
|
node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1641:76]
|
||
|
|
node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1641:99]
|
||
|
|
node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1641:82]
|
||
|
|
node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1641:80]
|
||
|
|
node mcause_fir_error_type = cat(_T_203, _T_207) @[Cat.scala 29:58]
|
||
|
|
node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1644:52]
|
||
|
|
node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1645:51]
|
||
|
|
node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1646:50]
|
||
|
|
node _T_211 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_212 = cat(_T_211, mcause_fir_error_type) @[Cat.scala 29:58]
|
||
|
|
node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1647:56]
|
||
|
|
node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1647:54]
|
||
|
|
node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1647:70]
|
||
|
|
node _T_216 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_217 = cat(_T_216, io.exc_cause_r) @[Cat.scala 29:58]
|
||
|
|
node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1648:46]
|
||
|
|
node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1648:44]
|
||
|
|
node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1648:70]
|
||
|
|
node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1649:32]
|
||
|
|
node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1649:47]
|
||
|
|
node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1649:45]
|
||
|
|
node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1649:71]
|
||
|
|
node _T_225 = mux(_T_208, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_226 = mux(_T_209, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_227 = mux(_T_210, _T_212, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_228 = mux(_T_215, _T_217, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_229 = mux(_T_220, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_230 = mux(_T_224, mcause, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_231 = or(_T_225, _T_226) @[Mux.scala 27:72]
|
||
|
|
node _T_232 = or(_T_231, _T_227) @[Mux.scala 27:72]
|
||
|
|
node _T_233 = or(_T_232, _T_228) @[Mux.scala 27:72]
|
||
|
|
node _T_234 = or(_T_233, _T_229) @[Mux.scala 27:72]
|
||
|
|
node _T_235 = or(_T_234, _T_230) @[Mux.scala 27:72]
|
||
|
|
wire mcause_ns : UInt<32> @[Mux.scala 27:72]
|
||
|
|
mcause_ns <= _T_235 @[Mux.scala 27:72]
|
||
|
|
reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1651:49]
|
||
|
|
_T_236 <= mcause_ns @[dec_tlu_ctl.scala 1651:49]
|
||
|
|
mcause <= _T_236 @[dec_tlu_ctl.scala 1651:12]
|
||
|
|
node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1658:64]
|
||
|
|
node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1658:71]
|
||
|
|
node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1658:42]
|
||
|
|
node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1660:56]
|
||
|
|
node _T_240 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58]
|
||
|
|
node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1660:24]
|
||
|
|
node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1663:36]
|
||
|
|
node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1664:40]
|
||
|
|
node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1665:32]
|
||
|
|
node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1666:34]
|
||
|
|
node _T_245 = mux(_T_241, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_246 = mux(_T_242, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_247 = mux(_T_243, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_248 = mux(_T_244, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_249 = or(_T_245, _T_246) @[Mux.scala 27:72]
|
||
|
|
node _T_250 = or(_T_249, _T_247) @[Mux.scala 27:72]
|
||
|
|
node _T_251 = or(_T_250, _T_248) @[Mux.scala 27:72]
|
||
|
|
wire mscause_type : UInt<4> @[Mux.scala 27:72]
|
||
|
|
mscause_type <= _T_251 @[Mux.scala 27:72]
|
||
|
|
node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1670:48]
|
||
|
|
node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1671:40]
|
||
|
|
node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1671:38]
|
||
|
|
node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1671:64]
|
||
|
|
node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1671:103]
|
||
|
|
node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1672:25]
|
||
|
|
node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1672:41]
|
||
|
|
node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1672:39]
|
||
|
|
node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1672:65]
|
||
|
|
node _T_261 = mux(_T_252, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_262 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_263 = mux(_T_260, mscause, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_264 = or(_T_261, _T_262) @[Mux.scala 27:72]
|
||
|
|
node _T_265 = or(_T_264, _T_263) @[Mux.scala 27:72]
|
||
|
|
wire mscause_ns : UInt<4> @[Mux.scala 27:72]
|
||
|
|
mscause_ns <= _T_265 @[Mux.scala 27:72]
|
||
|
|
reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1674:47]
|
||
|
|
_T_266 <= mscause_ns @[dec_tlu_ctl.scala 1674:47]
|
||
|
|
mscause <= _T_266 @[dec_tlu_ctl.scala 1674:10]
|
||
|
|
node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1681:62]
|
||
|
|
node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1681:69]
|
||
|
|
node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1681:40]
|
||
|
|
node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1682:83]
|
||
|
|
node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1682:81]
|
||
|
|
node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1682:64]
|
||
|
|
node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1682:106]
|
||
|
|
node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1682:49]
|
||
|
|
node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1682:140]
|
||
|
|
node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1682:138]
|
||
|
|
node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1683:72]
|
||
|
|
node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1683:55]
|
||
|
|
node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1683:98]
|
||
|
|
node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1683:96]
|
||
|
|
node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1684:51]
|
||
|
|
node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1684:68]
|
||
|
|
node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1684:66]
|
||
|
|
node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1685:50]
|
||
|
|
node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1685:73]
|
||
|
|
node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1685:71]
|
||
|
|
node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1686:46]
|
||
|
|
node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1686:44]
|
||
|
|
node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1686:68]
|
||
|
|
node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1686:66]
|
||
|
|
node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1686:92]
|
||
|
|
node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1686:90]
|
||
|
|
node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1686:115]
|
||
|
|
node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1686:113]
|
||
|
|
node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1690:25]
|
||
|
|
node _T_290 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1691:31]
|
||
|
|
node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1691:83]
|
||
|
|
node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1691:83]
|
||
|
|
node _T_294 = cat(_T_293, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1692:27]
|
||
|
|
node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1693:26]
|
||
|
|
node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1694:18]
|
||
|
|
node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1694:16]
|
||
|
|
node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1694:48]
|
||
|
|
node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1695:5]
|
||
|
|
node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1695:20]
|
||
|
|
node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1695:18]
|
||
|
|
node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1695:34]
|
||
|
|
node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1695:32]
|
||
|
|
node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1695:56]
|
||
|
|
node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1695:54]
|
||
|
|
node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1695:80]
|
||
|
|
node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1695:78]
|
||
|
|
node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1695:97]
|
||
|
|
node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1695:95]
|
||
|
|
node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1695:119]
|
||
|
|
node _T_312 = mux(_T_289, _T_290, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_313 = mux(_T_291, _T_294, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_314 = mux(_T_295, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_315 = mux(_T_296, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_316 = mux(_T_299, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_317 = mux(_T_311, mtval, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_318 = or(_T_312, _T_313) @[Mux.scala 27:72]
|
||
|
|
node _T_319 = or(_T_318, _T_314) @[Mux.scala 27:72]
|
||
|
|
node _T_320 = or(_T_319, _T_315) @[Mux.scala 27:72]
|
||
|
|
node _T_321 = or(_T_320, _T_316) @[Mux.scala 27:72]
|
||
|
|
node _T_322 = or(_T_321, _T_317) @[Mux.scala 27:72]
|
||
|
|
wire mtval_ns : UInt<32> @[Mux.scala 27:72]
|
||
|
|
mtval_ns <= _T_322 @[Mux.scala 27:72]
|
||
|
|
reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1697:46]
|
||
|
|
_T_323 <= mtval_ns @[dec_tlu_ctl.scala 1697:46]
|
||
|
|
mtval <= _T_323 @[dec_tlu_ctl.scala 1697:8]
|
||
|
|
node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1712:61]
|
||
|
|
node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1712:68]
|
||
|
|
node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1712:39]
|
||
|
|
node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1714:39]
|
||
|
|
node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1714:55]
|
||
|
|
inst rvclkhdr_8 of rvclkhdr_67 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_8.clock <= clock
|
||
|
|
rvclkhdr_8.reset <= reset
|
||
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_8.io.en <= _T_327 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
mcgc <= _T_326 @[lib.scala 374:16]
|
||
|
|
node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1716:38]
|
||
|
|
io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1716:31]
|
||
|
|
node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1717:38]
|
||
|
|
io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1717:31]
|
||
|
|
node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1718:38]
|
||
|
|
io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1718:31]
|
||
|
|
node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1719:38]
|
||
|
|
io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1719:31]
|
||
|
|
node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1720:38]
|
||
|
|
io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1720:31]
|
||
|
|
node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1721:38]
|
||
|
|
io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1721:31]
|
||
|
|
node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1722:38]
|
||
|
|
io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1722:31]
|
||
|
|
node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1723:38]
|
||
|
|
io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1723:31]
|
||
|
|
node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1742:61]
|
||
|
|
node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1742:68]
|
||
|
|
node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1742:39]
|
||
|
|
node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1746:39]
|
||
|
|
inst rvclkhdr_9 of rvclkhdr_68 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_9.clock <= clock
|
||
|
|
rvclkhdr_9.reset <= reset
|
||
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_9.io.en <= _T_338 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_339 <= mfdc_ns @[lib.scala 374:16]
|
||
|
|
mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1746:11]
|
||
|
|
node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1751:40]
|
||
|
|
node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1751:20]
|
||
|
|
node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1751:67]
|
||
|
|
node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1751:95]
|
||
|
|
node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1751:75]
|
||
|
|
node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1751:119]
|
||
|
|
node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58]
|
||
|
|
node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58]
|
||
|
|
node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58]
|
||
|
|
mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1751:13]
|
||
|
|
node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1752:29]
|
||
|
|
node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1752:20]
|
||
|
|
node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1752:55]
|
||
|
|
node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1752:72]
|
||
|
|
node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1752:63]
|
||
|
|
node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1752:85]
|
||
|
|
node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58]
|
||
|
|
node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58]
|
||
|
|
node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58]
|
||
|
|
mfdc <= _T_358 @[dec_tlu_ctl.scala 1752:13]
|
||
|
|
node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1760:46]
|
||
|
|
io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1760:39]
|
||
|
|
node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1761:46]
|
||
|
|
io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1761:39]
|
||
|
|
node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1762:46]
|
||
|
|
io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1762:39]
|
||
|
|
node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1763:46]
|
||
|
|
io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1763:39]
|
||
|
|
node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1764:46]
|
||
|
|
io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1764:39]
|
||
|
|
node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1765:46]
|
||
|
|
io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1765:39]
|
||
|
|
node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1766:46]
|
||
|
|
io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1766:39]
|
||
|
|
node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1775:70]
|
||
|
|
node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1775:77]
|
||
|
|
node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1775:48]
|
||
|
|
node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1775:89]
|
||
|
|
node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1775:87]
|
||
|
|
node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1775:113]
|
||
|
|
node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1775:111]
|
||
|
|
io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1775:24]
|
||
|
|
node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1782:61]
|
||
|
|
node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1782:68]
|
||
|
|
node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1782:39]
|
||
|
|
node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1785:39]
|
||
|
|
node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1785:64]
|
||
|
|
node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1785:91]
|
||
|
|
node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1785:71]
|
||
|
|
node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1785:69]
|
||
|
|
node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1786:41]
|
||
|
|
node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1786:66]
|
||
|
|
node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1786:93]
|
||
|
|
node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1786:73]
|
||
|
|
node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1786:71]
|
||
|
|
node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1787:41]
|
||
|
|
node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1787:66]
|
||
|
|
node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1787:93]
|
||
|
|
node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1787:73]
|
||
|
|
node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1787:71]
|
||
|
|
node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1788:41]
|
||
|
|
node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1788:66]
|
||
|
|
node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1788:93]
|
||
|
|
node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1788:73]
|
||
|
|
node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1788:71]
|
||
|
|
node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1789:41]
|
||
|
|
node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1789:66]
|
||
|
|
node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1789:93]
|
||
|
|
node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1789:73]
|
||
|
|
node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1789:71]
|
||
|
|
node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1790:41]
|
||
|
|
node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1790:66]
|
||
|
|
node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1790:93]
|
||
|
|
node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1790:73]
|
||
|
|
node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1790:71]
|
||
|
|
node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1791:41]
|
||
|
|
node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1791:66]
|
||
|
|
node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1791:93]
|
||
|
|
node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1791:73]
|
||
|
|
node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1791:71]
|
||
|
|
node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1792:41]
|
||
|
|
node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1792:66]
|
||
|
|
node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1792:93]
|
||
|
|
node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1792:73]
|
||
|
|
node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1792:71]
|
||
|
|
node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1793:41]
|
||
|
|
node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1793:66]
|
||
|
|
node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1793:93]
|
||
|
|
node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1793:73]
|
||
|
|
node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1793:71]
|
||
|
|
node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1794:41]
|
||
|
|
node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1794:66]
|
||
|
|
node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1794:93]
|
||
|
|
node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1794:73]
|
||
|
|
node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1794:71]
|
||
|
|
node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1795:41]
|
||
|
|
node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1795:66]
|
||
|
|
node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1795:93]
|
||
|
|
node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1795:73]
|
||
|
|
node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1795:71]
|
||
|
|
node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1796:41]
|
||
|
|
node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1796:66]
|
||
|
|
node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1796:93]
|
||
|
|
node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1796:73]
|
||
|
|
node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1796:70]
|
||
|
|
node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1797:41]
|
||
|
|
node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1797:66]
|
||
|
|
node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1797:93]
|
||
|
|
node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1797:73]
|
||
|
|
node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1797:70]
|
||
|
|
node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1798:41]
|
||
|
|
node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1798:66]
|
||
|
|
node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1798:93]
|
||
|
|
node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1798:73]
|
||
|
|
node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1798:70]
|
||
|
|
node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1799:41]
|
||
|
|
node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1799:66]
|
||
|
|
node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1799:93]
|
||
|
|
node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1799:73]
|
||
|
|
node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1799:70]
|
||
|
|
node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1800:41]
|
||
|
|
node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1800:66]
|
||
|
|
node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1800:93]
|
||
|
|
node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1800:73]
|
||
|
|
node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1800:70]
|
||
|
|
node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58]
|
||
|
|
node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58]
|
||
|
|
node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58]
|
||
|
|
node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58]
|
||
|
|
node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58]
|
||
|
|
node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58]
|
||
|
|
node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58]
|
||
|
|
node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58]
|
||
|
|
node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58]
|
||
|
|
node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58]
|
||
|
|
node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58]
|
||
|
|
node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58]
|
||
|
|
node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58]
|
||
|
|
node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58]
|
||
|
|
node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58]
|
||
|
|
node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58]
|
||
|
|
node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58]
|
||
|
|
node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58]
|
||
|
|
node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58]
|
||
|
|
node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58]
|
||
|
|
node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58]
|
||
|
|
node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58]
|
||
|
|
node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58]
|
||
|
|
node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58]
|
||
|
|
node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58]
|
||
|
|
node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58]
|
||
|
|
node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58]
|
||
|
|
node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58]
|
||
|
|
node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58]
|
||
|
|
node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58]
|
||
|
|
node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58]
|
||
|
|
node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1803:38]
|
||
|
|
inst rvclkhdr_10 of rvclkhdr_69 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_10.clock <= clock
|
||
|
|
rvclkhdr_10.reset <= reset
|
||
|
|
rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
mrac <= mrac_in @[lib.scala 374:16]
|
||
|
|
io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1805:21]
|
||
|
|
node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1813:62]
|
||
|
|
node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1813:69]
|
||
|
|
node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1813:40]
|
||
|
|
node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1823:59]
|
||
|
|
node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1823:57]
|
||
|
|
node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1823:35]
|
||
|
|
io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1823:22]
|
||
|
|
node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1825:49]
|
||
|
|
node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1825:86]
|
||
|
|
node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1825:84]
|
||
|
|
node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1825:111]
|
||
|
|
node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1825:109]
|
||
|
|
mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1825:12]
|
||
|
|
node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1827:64]
|
||
|
|
inst rvclkhdr_11 of rvclkhdr_70 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_11.clock <= clock
|
||
|
|
rvclkhdr_11.reset <= reset
|
||
|
|
rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16]
|
||
|
|
node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1836:61]
|
||
|
|
node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1836:68]
|
||
|
|
node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1836:39]
|
||
|
|
node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1840:51]
|
||
|
|
node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1840:30]
|
||
|
|
node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1840:57]
|
||
|
|
node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1840:55]
|
||
|
|
node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1840:89]
|
||
|
|
node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1840:87]
|
||
|
|
io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1840:17]
|
||
|
|
wire fw_halted_ns : UInt<1>
|
||
|
|
fw_halted_ns <= UInt<1>("h00")
|
||
|
|
reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1842:48]
|
||
|
|
fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1842:48]
|
||
|
|
node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1843:34]
|
||
|
|
node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1843:49]
|
||
|
|
node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1843:47]
|
||
|
|
fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1843:15]
|
||
|
|
node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1844:29]
|
||
|
|
node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1844:57]
|
||
|
|
node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1844:37]
|
||
|
|
node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1844:62]
|
||
|
|
node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1844:18]
|
||
|
|
mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1844:12]
|
||
|
|
reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1846:44]
|
||
|
|
_T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1846:44]
|
||
|
|
mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1846:9]
|
||
|
|
node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1849:10]
|
||
|
|
mpmc <= _T_514 @[dec_tlu_ctl.scala 1849:7]
|
||
|
|
node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1858:40]
|
||
|
|
node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1858:48]
|
||
|
|
node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1858:92]
|
||
|
|
node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1858:19]
|
||
|
|
node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1860:63]
|
||
|
|
node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1860:70]
|
||
|
|
node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1860:41]
|
||
|
|
node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58]
|
||
|
|
node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1861:23]
|
||
|
|
node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1861:23]
|
||
|
|
micect_inc <= _T_522 @[dec_tlu_ctl.scala 1861:13]
|
||
|
|
node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1862:35]
|
||
|
|
node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1862:75]
|
||
|
|
node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58]
|
||
|
|
node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1862:95]
|
||
|
|
node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58]
|
||
|
|
node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1862:22]
|
||
|
|
node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1864:42]
|
||
|
|
node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1864:61]
|
||
|
|
inst rvclkhdr_12 of rvclkhdr_71 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_12.clock <= clock
|
||
|
|
rvclkhdr_12.reset <= reset
|
||
|
|
rvclkhdr_12.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_530 <= micect_ns @[lib.scala 374:16]
|
||
|
|
micect <= _T_530 @[dec_tlu_ctl.scala 1864:9]
|
||
|
|
node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1866:48]
|
||
|
|
node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1866:39]
|
||
|
|
node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1866:79]
|
||
|
|
node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58]
|
||
|
|
node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1866:57]
|
||
|
|
node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1866:88]
|
||
|
|
mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1866:14]
|
||
|
|
node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1875:69]
|
||
|
|
node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1875:76]
|
||
|
|
node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1875:47]
|
||
|
|
node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1876:26]
|
||
|
|
node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1876:70]
|
||
|
|
node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58]
|
||
|
|
node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1876:33]
|
||
|
|
node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1876:33]
|
||
|
|
miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1876:15]
|
||
|
|
node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1877:45]
|
||
|
|
node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1877:85]
|
||
|
|
node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58]
|
||
|
|
node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1877:107]
|
||
|
|
node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58]
|
||
|
|
node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1877:30]
|
||
|
|
node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1879:48]
|
||
|
|
node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1879:69]
|
||
|
|
node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1879:93]
|
||
|
|
inst rvclkhdr_13 of rvclkhdr_72 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_13.clock <= clock
|
||
|
|
rvclkhdr_13.reset <= reset
|
||
|
|
rvclkhdr_13.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_552 <= miccmect_ns @[lib.scala 374:16]
|
||
|
|
miccmect <= _T_552 @[dec_tlu_ctl.scala 1879:11]
|
||
|
|
node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1881:51]
|
||
|
|
node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1881:40]
|
||
|
|
node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1881:84]
|
||
|
|
node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58]
|
||
|
|
node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1881:60]
|
||
|
|
node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1881:93]
|
||
|
|
miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1881:15]
|
||
|
|
node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1890:69]
|
||
|
|
node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1890:76]
|
||
|
|
node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1890:47]
|
||
|
|
node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1891:26]
|
||
|
|
node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58]
|
||
|
|
node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1891:33]
|
||
|
|
node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1891:33]
|
||
|
|
mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1891:15]
|
||
|
|
node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1892:45]
|
||
|
|
node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1892:85]
|
||
|
|
node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58]
|
||
|
|
node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1892:107]
|
||
|
|
node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58]
|
||
|
|
node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1892:30]
|
||
|
|
node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1894:49]
|
||
|
|
node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1894:81]
|
||
|
|
inst rvclkhdr_14 of rvclkhdr_73 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_14.clock <= clock
|
||
|
|
rvclkhdr_14.reset <= reset
|
||
|
|
rvclkhdr_14.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_572 <= mdccmect_ns @[lib.scala 374:16]
|
||
|
|
mdccmect <= _T_572 @[dec_tlu_ctl.scala 1894:11]
|
||
|
|
node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1896:52]
|
||
|
|
node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1896:41]
|
||
|
|
node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1896:85]
|
||
|
|
node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58]
|
||
|
|
node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1896:61]
|
||
|
|
node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1896:94]
|
||
|
|
mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1896:16]
|
||
|
|
node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1906:62]
|
||
|
|
node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1906:69]
|
||
|
|
node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1906:40]
|
||
|
|
node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1908:32]
|
||
|
|
node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1908:59]
|
||
|
|
node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1908:20]
|
||
|
|
reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1910:43]
|
||
|
|
_T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1910:43]
|
||
|
|
mfdht <= _T_583 @[dec_tlu_ctl.scala 1910:8]
|
||
|
|
node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1919:62]
|
||
|
|
node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1919:69]
|
||
|
|
node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1919:40]
|
||
|
|
node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1921:32]
|
||
|
|
node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1921:60]
|
||
|
|
node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1922:43]
|
||
|
|
node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1922:41]
|
||
|
|
node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1922:65]
|
||
|
|
node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1922:78]
|
||
|
|
node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1922:98]
|
||
|
|
node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58]
|
||
|
|
node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1922:21]
|
||
|
|
node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1921:20]
|
||
|
|
node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1924:71]
|
||
|
|
node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1924:92]
|
||
|
|
reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_596 : @[Reg.scala 28:19]
|
||
|
|
_T_597 <= mfdhs_ns @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
mfdhs <= _T_597 @[dec_tlu_ctl.scala 1924:8]
|
||
|
|
node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1926:47]
|
||
|
|
node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1926:74]
|
||
|
|
node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1926:74]
|
||
|
|
node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1927:48]
|
||
|
|
node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1927:27]
|
||
|
|
node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1926:26]
|
||
|
|
node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1929:81]
|
||
|
|
reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_603 : @[Reg.scala 28:19]
|
||
|
|
_T_604 <= force_halt_ctr @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1929:19]
|
||
|
|
node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:24]
|
||
|
|
node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1931:79]
|
||
|
|
node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1931:71]
|
||
|
|
node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1931:48]
|
||
|
|
node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1931:87]
|
||
|
|
node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1931:28]
|
||
|
|
io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1931:16]
|
||
|
|
node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1939:62]
|
||
|
|
node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1939:69]
|
||
|
|
node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1939:40]
|
||
|
|
node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1941:40]
|
||
|
|
node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1941:59]
|
||
|
|
inst rvclkhdr_15 of rvclkhdr_74 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_15.clock <= clock
|
||
|
|
rvclkhdr_15.reset <= reset
|
||
|
|
rvclkhdr_15.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
meivt <= _T_613 @[lib.scala 374:16]
|
||
|
|
node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1953:49]
|
||
|
|
inst rvclkhdr_16 of rvclkhdr_75 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_16.clock <= clock
|
||
|
|
rvclkhdr_16.reset <= reset
|
||
|
|
rvclkhdr_16.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
meihap <= io.pic_claimid @[lib.scala 374:16]
|
||
|
|
node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58]
|
||
|
|
io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1954:20]
|
||
|
|
node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1963:65]
|
||
|
|
node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1963:72]
|
||
|
|
node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1963:43]
|
||
|
|
node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1964:38]
|
||
|
|
node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1964:65]
|
||
|
|
node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1964:23]
|
||
|
|
reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1966:46]
|
||
|
|
_T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1966:46]
|
||
|
|
meicurpl <= _T_621 @[dec_tlu_ctl.scala 1966:11]
|
||
|
|
io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1968:22]
|
||
|
|
node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1978:66]
|
||
|
|
node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1978:73]
|
||
|
|
node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1978:44]
|
||
|
|
node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1978:88]
|
||
|
|
node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1980:37]
|
||
|
|
node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1981:38]
|
||
|
|
node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1981:65]
|
||
|
|
node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1981:23]
|
||
|
|
node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1980:23]
|
||
|
|
reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1983:44]
|
||
|
|
_T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1983:44]
|
||
|
|
meicidpl <= _T_629 @[dec_tlu_ctl.scala 1983:11]
|
||
|
|
node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1990:62]
|
||
|
|
node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1990:69]
|
||
|
|
node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1990:40]
|
||
|
|
node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1990:83]
|
||
|
|
wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1990:15]
|
||
|
|
node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1999:62]
|
||
|
|
node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1999:69]
|
||
|
|
node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1999:40]
|
||
|
|
node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2000:32]
|
||
|
|
node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2000:59]
|
||
|
|
node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2000:20]
|
||
|
|
reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2002:43]
|
||
|
|
_T_638 <= meipt_ns @[dec_tlu_ctl.scala 2002:43]
|
||
|
|
meipt <= _T_638 @[dec_tlu_ctl.scala 2002:8]
|
||
|
|
io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2004:19]
|
||
|
|
node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2030:89]
|
||
|
|
node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2030:66]
|
||
|
|
node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2033:31]
|
||
|
|
node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2033:29]
|
||
|
|
node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2033:63]
|
||
|
|
node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2033:61]
|
||
|
|
node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2033:98]
|
||
|
|
node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2033:96]
|
||
|
|
node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2033:118]
|
||
|
|
node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:48]
|
||
|
|
node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2034:46]
|
||
|
|
node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:80]
|
||
|
|
node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2034:78]
|
||
|
|
node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2034:114]
|
||
|
|
node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:77]
|
||
|
|
node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2035:75]
|
||
|
|
node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2035:111]
|
||
|
|
node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2036:108]
|
||
|
|
node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72]
|
||
|
|
node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72]
|
||
|
|
node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72]
|
||
|
|
wire dcsr_cause : UInt<3> @[Mux.scala 27:72]
|
||
|
|
dcsr_cause <= _T_662 @[Mux.scala 27:72]
|
||
|
|
node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2038:46]
|
||
|
|
node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2038:91]
|
||
|
|
node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2038:98]
|
||
|
|
node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2038:69]
|
||
|
|
node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2044:69]
|
||
|
|
node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2044:75]
|
||
|
|
node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2044:59]
|
||
|
|
node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2045:59]
|
||
|
|
node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2045:78]
|
||
|
|
node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2045:56]
|
||
|
|
node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2047:48]
|
||
|
|
node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2048:44]
|
||
|
|
node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2048:64]
|
||
|
|
node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2048:91]
|
||
|
|
node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58]
|
||
|
|
node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58]
|
||
|
|
node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58]
|
||
|
|
node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2049:18]
|
||
|
|
node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2049:49]
|
||
|
|
node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2049:84]
|
||
|
|
node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2049:110]
|
||
|
|
node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2049:154]
|
||
|
|
node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2049:145]
|
||
|
|
node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2049:178]
|
||
|
|
node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58]
|
||
|
|
node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58]
|
||
|
|
node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58]
|
||
|
|
node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58]
|
||
|
|
node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58]
|
||
|
|
node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58]
|
||
|
|
node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58]
|
||
|
|
node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2049:211]
|
||
|
|
node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2049:245]
|
||
|
|
node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58]
|
||
|
|
node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58]
|
||
|
|
node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58]
|
||
|
|
node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2049:7]
|
||
|
|
node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2048:19]
|
||
|
|
node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2051:54]
|
||
|
|
node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2051:66]
|
||
|
|
node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2051:94]
|
||
|
|
node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2051:109]
|
||
|
|
inst rvclkhdr_17 of rvclkhdr_76 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_17.clock <= clock
|
||
|
|
rvclkhdr_17.reset <= reset
|
||
|
|
rvclkhdr_17.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_701 <= dcsr_ns @[lib.scala 374:16]
|
||
|
|
io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2051:10]
|
||
|
|
node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2059:45]
|
||
|
|
node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2059:90]
|
||
|
|
node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2059:97]
|
||
|
|
node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2059:68]
|
||
|
|
node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2060:44]
|
||
|
|
node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2060:42]
|
||
|
|
node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2060:67]
|
||
|
|
node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2060:65]
|
||
|
|
node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2064:21]
|
||
|
|
node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2064:39]
|
||
|
|
node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2064:37]
|
||
|
|
node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2064:56]
|
||
|
|
node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2064:68]
|
||
|
|
node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2064:97]
|
||
|
|
node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2065:68]
|
||
|
|
node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:33]
|
||
|
|
node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2066:49]
|
||
|
|
node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2066:68]
|
||
|
|
node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72]
|
||
|
|
node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72]
|
||
|
|
wire dpc_ns : UInt<31> @[Mux.scala 27:72]
|
||
|
|
dpc_ns <= _T_722 @[Mux.scala 27:72]
|
||
|
|
node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:36]
|
||
|
|
node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:53]
|
||
|
|
node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2068:72]
|
||
|
|
inst rvclkhdr_18 of rvclkhdr_77 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_18.clock <= clock
|
||
|
|
rvclkhdr_18.reset <= reset
|
||
|
|
rvclkhdr_18.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_726 <= dpc_ns @[lib.scala 374:16]
|
||
|
|
io.dpc <= _T_726 @[dec_tlu_ctl.scala 2068:9]
|
||
|
|
node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2082:43]
|
||
|
|
node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2082:68]
|
||
|
|
node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2082:96]
|
||
|
|
node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58]
|
||
|
|
node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58]
|
||
|
|
node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:50]
|
||
|
|
node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:95]
|
||
|
|
node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2083:102]
|
||
|
|
node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2083:73]
|
||
|
|
node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2085:50]
|
||
|
|
inst rvclkhdr_19 of rvclkhdr_78 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_19.clock <= clock
|
||
|
|
rvclkhdr_19.reset <= reset
|
||
|
|
rvclkhdr_19.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
dicawics <= dicawics_ns @[lib.scala 374:16]
|
||
|
|
node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2101:48]
|
||
|
|
node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2101:93]
|
||
|
|
node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2101:100]
|
||
|
|
node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2101:71]
|
||
|
|
node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2102:34]
|
||
|
|
node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2102:21]
|
||
|
|
node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2104:46]
|
||
|
|
node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2104:79]
|
||
|
|
inst rvclkhdr_20 of rvclkhdr_79 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_20.clock <= clock
|
||
|
|
rvclkhdr_20.reset <= reset
|
||
|
|
rvclkhdr_20.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
dicad0 <= dicad0_ns @[lib.scala 374:16]
|
||
|
|
node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2114:49]
|
||
|
|
node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2114:94]
|
||
|
|
node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2114:101]
|
||
|
|
node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2114:72]
|
||
|
|
node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2116:36]
|
||
|
|
node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2116:88]
|
||
|
|
node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2116:22]
|
||
|
|
node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2118:48]
|
||
|
|
node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2118:81]
|
||
|
|
inst rvclkhdr_21 of rvclkhdr_80 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_21.clock <= clock
|
||
|
|
rvclkhdr_21.reset <= reset
|
||
|
|
rvclkhdr_21.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
dicad0h <= dicad0h_ns @[lib.scala 374:16]
|
||
|
|
wire _T_748 : UInt<7>
|
||
|
|
_T_748 <= UInt<1>("h00")
|
||
|
|
node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2126:48]
|
||
|
|
node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2126:93]
|
||
|
|
node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2126:100]
|
||
|
|
node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2126:71]
|
||
|
|
node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2128:34]
|
||
|
|
node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2128:61]
|
||
|
|
node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:91]
|
||
|
|
node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2128:21]
|
||
|
|
node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2130:78]
|
||
|
|
node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2130:111]
|
||
|
|
reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_758 : @[Reg.scala 28:19]
|
||
|
|
_T_759 <= _T_756 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
_T_748 <= _T_759 @[dec_tlu_ctl.scala 2130:13]
|
||
|
|
node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58]
|
||
|
|
dicad1 <= _T_760 @[dec_tlu_ctl.scala 2131:9]
|
||
|
|
node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2153:69]
|
||
|
|
node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2153:83]
|
||
|
|
node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2153:97]
|
||
|
|
node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58]
|
||
|
|
node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58]
|
||
|
|
io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2153:56]
|
||
|
|
io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2156:41]
|
||
|
|
node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2158:52]
|
||
|
|
node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2158:75]
|
||
|
|
node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2158:98]
|
||
|
|
node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2158:96]
|
||
|
|
node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2158:142]
|
||
|
|
node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2158:149]
|
||
|
|
node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2158:120]
|
||
|
|
node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2159:52]
|
||
|
|
node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2159:97]
|
||
|
|
node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:104]
|
||
|
|
node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2159:75]
|
||
|
|
reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2161:58]
|
||
|
|
icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2161:58]
|
||
|
|
reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58]
|
||
|
|
icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2162:58]
|
||
|
|
io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2164:41]
|
||
|
|
io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2165:41]
|
||
|
|
node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:62]
|
||
|
|
node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2173:69]
|
||
|
|
node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2173:40]
|
||
|
|
node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2174:32]
|
||
|
|
node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2174:59]
|
||
|
|
node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2174:20]
|
||
|
|
reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2176:43]
|
||
|
|
_T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2176:43]
|
||
|
|
mtsel <= _T_779 @[dec_tlu_ctl.scala 2176:8]
|
||
|
|
node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2211:38]
|
||
|
|
node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2211:64]
|
||
|
|
node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2211:44]
|
||
|
|
node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2211:42]
|
||
|
|
node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2213:40]
|
||
|
|
node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:66]
|
||
|
|
node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2213:46]
|
||
|
|
node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2213:44]
|
||
|
|
node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2215:41]
|
||
|
|
node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2215:46]
|
||
|
|
node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2215:90]
|
||
|
|
node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2215:69]
|
||
|
|
node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:47]
|
||
|
|
node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:52]
|
||
|
|
node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2217:94]
|
||
|
|
node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2217:136]
|
||
|
|
node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2218:43]
|
||
|
|
node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2218:83]
|
||
|
|
node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58]
|
||
|
|
node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58]
|
||
|
|
node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58]
|
||
|
|
node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58]
|
||
|
|
node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58]
|
||
|
|
node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58]
|
||
|
|
node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58]
|
||
|
|
node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92]
|
||
|
|
node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99]
|
||
|
|
node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2221:70]
|
||
|
|
node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2221:121]
|
||
|
|
node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2221:112]
|
||
|
|
node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2221:154]
|
||
|
|
node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2221:138]
|
||
|
|
node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170]
|
||
|
|
node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2221:135]
|
||
|
|
node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92]
|
||
|
|
node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99]
|
||
|
|
node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2221:70]
|
||
|
|
node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2221:121]
|
||
|
|
node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2221:112]
|
||
|
|
node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2221:154]
|
||
|
|
node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2221:138]
|
||
|
|
node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170]
|
||
|
|
node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2221:135]
|
||
|
|
node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92]
|
||
|
|
node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99]
|
||
|
|
node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2221:70]
|
||
|
|
node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2221:121]
|
||
|
|
node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2221:112]
|
||
|
|
node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2221:154]
|
||
|
|
node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2221:138]
|
||
|
|
node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170]
|
||
|
|
node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2221:135]
|
||
|
|
node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92]
|
||
|
|
node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99]
|
||
|
|
node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2221:70]
|
||
|
|
node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2221:121]
|
||
|
|
node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2221:112]
|
||
|
|
node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2221:154]
|
||
|
|
node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2221:138]
|
||
|
|
node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170]
|
||
|
|
node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2221:135]
|
||
|
|
wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2221:42]
|
||
|
|
wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2221:42]
|
||
|
|
wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2221:42]
|
||
|
|
wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2221:42]
|
||
|
|
wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2221:42]
|
||
|
|
node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2222:68]
|
||
|
|
node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:111]
|
||
|
|
node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2222:135]
|
||
|
|
node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2222:156]
|
||
|
|
node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2222:139]
|
||
|
|
node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2222:176]
|
||
|
|
node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58]
|
||
|
|
node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58]
|
||
|
|
node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2222:49]
|
||
|
|
node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2222:68]
|
||
|
|
node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:111]
|
||
|
|
node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2222:135]
|
||
|
|
node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2222:156]
|
||
|
|
node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2222:139]
|
||
|
|
node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2222:176]
|
||
|
|
node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58]
|
||
|
|
node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58]
|
||
|
|
node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2222:49]
|
||
|
|
node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2222:68]
|
||
|
|
node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:111]
|
||
|
|
node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2222:135]
|
||
|
|
node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2222:156]
|
||
|
|
node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2222:139]
|
||
|
|
node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2222:176]
|
||
|
|
node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58]
|
||
|
|
node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58]
|
||
|
|
node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2222:49]
|
||
|
|
node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2222:68]
|
||
|
|
node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:111]
|
||
|
|
node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2222:135]
|
||
|
|
node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2222:156]
|
||
|
|
node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2222:139]
|
||
|
|
node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2222:176]
|
||
|
|
node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58]
|
||
|
|
node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58]
|
||
|
|
node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2222:49]
|
||
|
|
wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2222:40]
|
||
|
|
mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2222:40]
|
||
|
|
mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2222:40]
|
||
|
|
mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2222:40]
|
||
|
|
mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2222:40]
|
||
|
|
reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
_T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2224:39]
|
||
|
|
reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
_T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2224:39]
|
||
|
|
reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
_T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2224:39]
|
||
|
|
reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
_T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2224:74]
|
||
|
|
io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2224:39]
|
||
|
|
node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2227:58]
|
||
|
|
node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2227:104]
|
||
|
|
node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2227:142]
|
||
|
|
node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2227:174]
|
||
|
|
node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2227:206]
|
||
|
|
node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2227:238]
|
||
|
|
node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58]
|
||
|
|
node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58]
|
||
|
|
node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58]
|
||
|
|
node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58]
|
||
|
|
node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58]
|
||
|
|
node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58]
|
||
|
|
node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58]
|
||
|
|
node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2227:58]
|
||
|
|
node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2227:104]
|
||
|
|
node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2227:142]
|
||
|
|
node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2227:174]
|
||
|
|
node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2227:206]
|
||
|
|
node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2227:238]
|
||
|
|
node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58]
|
||
|
|
node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58]
|
||
|
|
node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58]
|
||
|
|
node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58]
|
||
|
|
node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58]
|
||
|
|
node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58]
|
||
|
|
node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58]
|
||
|
|
node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2227:58]
|
||
|
|
node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2227:104]
|
||
|
|
node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2227:142]
|
||
|
|
node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2227:174]
|
||
|
|
node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2227:206]
|
||
|
|
node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2227:238]
|
||
|
|
node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58]
|
||
|
|
node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58]
|
||
|
|
node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58]
|
||
|
|
node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58]
|
||
|
|
node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58]
|
||
|
|
node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58]
|
||
|
|
node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58]
|
||
|
|
node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2227:58]
|
||
|
|
node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2227:104]
|
||
|
|
node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2227:142]
|
||
|
|
node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2227:174]
|
||
|
|
node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2227:206]
|
||
|
|
node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2227:238]
|
||
|
|
node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58]
|
||
|
|
node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58]
|
||
|
|
node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58]
|
||
|
|
node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58]
|
||
|
|
node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58]
|
||
|
|
node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58]
|
||
|
|
node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58]
|
||
|
|
node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72]
|
||
|
|
node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72]
|
||
|
|
node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72]
|
||
|
|
wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72]
|
||
|
|
mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72]
|
||
|
|
node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2229:58]
|
||
|
|
io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2229:40]
|
||
|
|
node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2230:61]
|
||
|
|
io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2230:43]
|
||
|
|
node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2231:58]
|
||
|
|
io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2231:40]
|
||
|
|
node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2232:58]
|
||
|
|
io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2232:40]
|
||
|
|
node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2233:58]
|
||
|
|
io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2233:40]
|
||
|
|
node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2234:58]
|
||
|
|
io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2234:40]
|
||
|
|
node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2229:58]
|
||
|
|
io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2229:40]
|
||
|
|
node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2230:61]
|
||
|
|
io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2230:43]
|
||
|
|
node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2231:58]
|
||
|
|
io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2231:40]
|
||
|
|
node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2232:58]
|
||
|
|
io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2232:40]
|
||
|
|
node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2233:58]
|
||
|
|
io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2233:40]
|
||
|
|
node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2234:58]
|
||
|
|
io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2234:40]
|
||
|
|
node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2229:58]
|
||
|
|
io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2229:40]
|
||
|
|
node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2230:61]
|
||
|
|
io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2230:43]
|
||
|
|
node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2231:58]
|
||
|
|
io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2231:40]
|
||
|
|
node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2232:58]
|
||
|
|
io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2232:40]
|
||
|
|
node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2233:58]
|
||
|
|
io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2233:40]
|
||
|
|
node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2234:58]
|
||
|
|
io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2234:40]
|
||
|
|
node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2229:58]
|
||
|
|
io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2229:40]
|
||
|
|
node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2230:61]
|
||
|
|
io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2230:43]
|
||
|
|
node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2231:58]
|
||
|
|
io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2231:40]
|
||
|
|
node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2232:58]
|
||
|
|
io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2232:40]
|
||
|
|
node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2233:58]
|
||
|
|
io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2233:40]
|
||
|
|
node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2234:58]
|
||
|
|
io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2234:40]
|
||
|
|
node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91]
|
||
|
|
node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98]
|
||
|
|
node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2241:69]
|
||
|
|
node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2241:120]
|
||
|
|
node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2241:111]
|
||
|
|
node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2241:153]
|
||
|
|
node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2241:137]
|
||
|
|
node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169]
|
||
|
|
node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2241:134]
|
||
|
|
node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91]
|
||
|
|
node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98]
|
||
|
|
node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2241:69]
|
||
|
|
node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2241:120]
|
||
|
|
node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2241:111]
|
||
|
|
node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2241:153]
|
||
|
|
node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2241:137]
|
||
|
|
node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169]
|
||
|
|
node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2241:134]
|
||
|
|
node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91]
|
||
|
|
node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98]
|
||
|
|
node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2241:69]
|
||
|
|
node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2241:120]
|
||
|
|
node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2241:111]
|
||
|
|
node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2241:153]
|
||
|
|
node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2241:137]
|
||
|
|
node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169]
|
||
|
|
node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2241:134]
|
||
|
|
node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91]
|
||
|
|
node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98]
|
||
|
|
node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2241:69]
|
||
|
|
node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2241:120]
|
||
|
|
node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2241:111]
|
||
|
|
node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2241:153]
|
||
|
|
node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2241:137]
|
||
|
|
node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169]
|
||
|
|
node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2241:134]
|
||
|
|
wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2241:42]
|
||
|
|
wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2241:42]
|
||
|
|
wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2241:42]
|
||
|
|
wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2241:42]
|
||
|
|
wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2241:42]
|
||
|
|
node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2242:84]
|
||
|
|
inst rvclkhdr_22 of rvclkhdr_81 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_22.clock <= clock
|
||
|
|
rvclkhdr_22.reset <= reset
|
||
|
|
rvclkhdr_22.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
|
||
|
|
mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2242:36]
|
||
|
|
node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2242:84]
|
||
|
|
inst rvclkhdr_23 of rvclkhdr_82 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_23.clock <= clock
|
||
|
|
rvclkhdr_23.reset <= reset
|
||
|
|
rvclkhdr_23.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
|
||
|
|
mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2242:36]
|
||
|
|
node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2242:84]
|
||
|
|
inst rvclkhdr_24 of rvclkhdr_83 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_24.clock <= clock
|
||
|
|
rvclkhdr_24.reset <= reset
|
||
|
|
rvclkhdr_24.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
|
||
|
|
mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2242:36]
|
||
|
|
node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2242:84]
|
||
|
|
inst rvclkhdr_25 of rvclkhdr_84 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_25.clock <= clock
|
||
|
|
rvclkhdr_25.reset <= reset
|
||
|
|
rvclkhdr_25.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
|
||
|
|
mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2242:36]
|
||
|
|
node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2246:57]
|
||
|
|
node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2246:57]
|
||
|
|
node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2246:57]
|
||
|
|
node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2246:57]
|
||
|
|
node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72]
|
||
|
|
node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72]
|
||
|
|
node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72]
|
||
|
|
wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72]
|
||
|
|
mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72]
|
||
|
|
io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2247:51]
|
||
|
|
io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2247:51]
|
||
|
|
io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2247:51]
|
||
|
|
io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2247:51]
|
||
|
|
mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2257:15]
|
||
|
|
mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2258:15]
|
||
|
|
mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2259:15]
|
||
|
|
mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2260:15]
|
||
|
|
node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2266:59]
|
||
|
|
wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2267:24]
|
||
|
|
wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2268:27]
|
||
|
|
node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2272:38]
|
||
|
|
node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2272:24]
|
||
|
|
node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34]
|
||
|
|
node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2273:62]
|
||
|
|
node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34]
|
||
|
|
node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2274:62]
|
||
|
|
node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34]
|
||
|
|
node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2275:62]
|
||
|
|
node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34]
|
||
|
|
node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2276:62]
|
||
|
|
node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96]
|
||
|
|
node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2276:94]
|
||
|
|
node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34]
|
||
|
|
node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2277:62]
|
||
|
|
node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96]
|
||
|
|
node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2277:94]
|
||
|
|
node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117]
|
||
|
|
node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2277:115]
|
||
|
|
node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34]
|
||
|
|
node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2278:62]
|
||
|
|
node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94]
|
||
|
|
node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117]
|
||
|
|
node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2278:115]
|
||
|
|
node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34]
|
||
|
|
node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2279:62]
|
||
|
|
node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34]
|
||
|
|
node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2280:62]
|
||
|
|
node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34]
|
||
|
|
node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2281:62]
|
||
|
|
node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34]
|
||
|
|
node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2282:62]
|
||
|
|
node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91]
|
||
|
|
node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34]
|
||
|
|
node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2283:62]
|
||
|
|
node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105]
|
||
|
|
node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34]
|
||
|
|
node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2284:62]
|
||
|
|
node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91]
|
||
|
|
node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34]
|
||
|
|
node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2285:62]
|
||
|
|
node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91]
|
||
|
|
node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34]
|
||
|
|
node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2286:62]
|
||
|
|
node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
|
||
|
|
node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100]
|
||
|
|
node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34]
|
||
|
|
node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2287:62]
|
||
|
|
node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
|
||
|
|
node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142]
|
||
|
|
node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2287:101]
|
||
|
|
node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34]
|
||
|
|
node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2288:59]
|
||
|
|
node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89]
|
||
|
|
node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34]
|
||
|
|
node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2289:59]
|
||
|
|
node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89]
|
||
|
|
node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34]
|
||
|
|
node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2290:59]
|
||
|
|
node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89]
|
||
|
|
node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34]
|
||
|
|
node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2291:59]
|
||
|
|
node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89]
|
||
|
|
node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34]
|
||
|
|
node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2292:59]
|
||
|
|
node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89]
|
||
|
|
node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34]
|
||
|
|
node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2293:59]
|
||
|
|
node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89]
|
||
|
|
node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34]
|
||
|
|
node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2294:59]
|
||
|
|
node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89]
|
||
|
|
node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34]
|
||
|
|
node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2295:59]
|
||
|
|
node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89]
|
||
|
|
node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34]
|
||
|
|
node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2296:59]
|
||
|
|
node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89]
|
||
|
|
node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34]
|
||
|
|
node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2297:59]
|
||
|
|
node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89]
|
||
|
|
node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122]
|
||
|
|
node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2297:101]
|
||
|
|
node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34]
|
||
|
|
node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2298:62]
|
||
|
|
node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95]
|
||
|
|
node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34]
|
||
|
|
node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2299:62]
|
||
|
|
node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97]
|
||
|
|
node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34]
|
||
|
|
node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2300:62]
|
||
|
|
node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110]
|
||
|
|
node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34]
|
||
|
|
node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2301:62]
|
||
|
|
node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34]
|
||
|
|
node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2302:62]
|
||
|
|
node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34]
|
||
|
|
node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2303:62]
|
||
|
|
node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34]
|
||
|
|
node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2304:62]
|
||
|
|
node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34]
|
||
|
|
node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2305:62]
|
||
|
|
node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34]
|
||
|
|
node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2306:62]
|
||
|
|
node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34]
|
||
|
|
node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2307:62]
|
||
|
|
node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34]
|
||
|
|
node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2308:62]
|
||
|
|
node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98]
|
||
|
|
node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120]
|
||
|
|
node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34]
|
||
|
|
node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2309:62]
|
||
|
|
node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92]
|
||
|
|
node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117]
|
||
|
|
node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34]
|
||
|
|
node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2310:62]
|
||
|
|
node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34]
|
||
|
|
node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2311:62]
|
||
|
|
node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34]
|
||
|
|
node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2312:62]
|
||
|
|
node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97]
|
||
|
|
node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129]
|
||
|
|
node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34]
|
||
|
|
node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2313:62]
|
||
|
|
node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34]
|
||
|
|
node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2314:62]
|
||
|
|
node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34]
|
||
|
|
node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2315:62]
|
||
|
|
node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34]
|
||
|
|
node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2316:62]
|
||
|
|
node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34]
|
||
|
|
node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2317:62]
|
||
|
|
node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34]
|
||
|
|
node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2318:62]
|
||
|
|
node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34]
|
||
|
|
node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2319:62]
|
||
|
|
node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34]
|
||
|
|
node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2320:62]
|
||
|
|
node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2320:73]
|
||
|
|
node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34]
|
||
|
|
node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2321:62]
|
||
|
|
node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2321:73]
|
||
|
|
node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107]
|
||
|
|
node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118]
|
||
|
|
node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2321:113]
|
||
|
|
node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2321:125]
|
||
|
|
node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2321:98]
|
||
|
|
node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34]
|
||
|
|
node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2322:62]
|
||
|
|
node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91]
|
||
|
|
node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34]
|
||
|
|
node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2323:62]
|
||
|
|
node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94]
|
||
|
|
node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34]
|
||
|
|
node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2324:62]
|
||
|
|
node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94]
|
||
|
|
node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34]
|
||
|
|
node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2326:62]
|
||
|
|
node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34]
|
||
|
|
node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2327:62]
|
||
|
|
node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34]
|
||
|
|
node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2328:62]
|
||
|
|
node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34]
|
||
|
|
node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2329:62]
|
||
|
|
node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34]
|
||
|
|
node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2330:62]
|
||
|
|
node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72]
|
||
|
|
node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72]
|
||
|
|
node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72]
|
||
|
|
node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72]
|
||
|
|
node _T_1255 = or(_T_1254, _T_1199) @[Mux.scala 27:72]
|
||
|
|
node _T_1256 = or(_T_1255, _T_1200) @[Mux.scala 27:72]
|
||
|
|
node _T_1257 = or(_T_1256, _T_1201) @[Mux.scala 27:72]
|
||
|
|
node _T_1258 = or(_T_1257, _T_1202) @[Mux.scala 27:72]
|
||
|
|
node _T_1259 = or(_T_1258, _T_1203) @[Mux.scala 27:72]
|
||
|
|
node _T_1260 = or(_T_1259, _T_1204) @[Mux.scala 27:72]
|
||
|
|
node _T_1261 = or(_T_1260, _T_1205) @[Mux.scala 27:72]
|
||
|
|
node _T_1262 = or(_T_1261, _T_1206) @[Mux.scala 27:72]
|
||
|
|
node _T_1263 = or(_T_1262, _T_1207) @[Mux.scala 27:72]
|
||
|
|
node _T_1264 = or(_T_1263, _T_1208) @[Mux.scala 27:72]
|
||
|
|
node _T_1265 = or(_T_1264, _T_1209) @[Mux.scala 27:72]
|
||
|
|
node _T_1266 = or(_T_1265, _T_1210) @[Mux.scala 27:72]
|
||
|
|
node _T_1267 = or(_T_1266, _T_1211) @[Mux.scala 27:72]
|
||
|
|
node _T_1268 = or(_T_1267, _T_1212) @[Mux.scala 27:72]
|
||
|
|
node _T_1269 = or(_T_1268, _T_1213) @[Mux.scala 27:72]
|
||
|
|
node _T_1270 = or(_T_1269, _T_1214) @[Mux.scala 27:72]
|
||
|
|
node _T_1271 = or(_T_1270, _T_1215) @[Mux.scala 27:72]
|
||
|
|
node _T_1272 = or(_T_1271, _T_1216) @[Mux.scala 27:72]
|
||
|
|
node _T_1273 = or(_T_1272, _T_1217) @[Mux.scala 27:72]
|
||
|
|
node _T_1274 = or(_T_1273, _T_1218) @[Mux.scala 27:72]
|
||
|
|
node _T_1275 = or(_T_1274, _T_1219) @[Mux.scala 27:72]
|
||
|
|
node _T_1276 = or(_T_1275, _T_1220) @[Mux.scala 27:72]
|
||
|
|
node _T_1277 = or(_T_1276, _T_1221) @[Mux.scala 27:72]
|
||
|
|
node _T_1278 = or(_T_1277, _T_1222) @[Mux.scala 27:72]
|
||
|
|
node _T_1279 = or(_T_1278, _T_1223) @[Mux.scala 27:72]
|
||
|
|
node _T_1280 = or(_T_1279, _T_1224) @[Mux.scala 27:72]
|
||
|
|
node _T_1281 = or(_T_1280, _T_1225) @[Mux.scala 27:72]
|
||
|
|
node _T_1282 = or(_T_1281, _T_1226) @[Mux.scala 27:72]
|
||
|
|
node _T_1283 = or(_T_1282, _T_1227) @[Mux.scala 27:72]
|
||
|
|
node _T_1284 = or(_T_1283, _T_1228) @[Mux.scala 27:72]
|
||
|
|
node _T_1285 = or(_T_1284, _T_1229) @[Mux.scala 27:72]
|
||
|
|
node _T_1286 = or(_T_1285, _T_1230) @[Mux.scala 27:72]
|
||
|
|
node _T_1287 = or(_T_1286, _T_1231) @[Mux.scala 27:72]
|
||
|
|
node _T_1288 = or(_T_1287, _T_1232) @[Mux.scala 27:72]
|
||
|
|
node _T_1289 = or(_T_1288, _T_1233) @[Mux.scala 27:72]
|
||
|
|
node _T_1290 = or(_T_1289, _T_1234) @[Mux.scala 27:72]
|
||
|
|
node _T_1291 = or(_T_1290, _T_1235) @[Mux.scala 27:72]
|
||
|
|
node _T_1292 = or(_T_1291, _T_1236) @[Mux.scala 27:72]
|
||
|
|
node _T_1293 = or(_T_1292, _T_1237) @[Mux.scala 27:72]
|
||
|
|
node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72]
|
||
|
|
node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72]
|
||
|
|
node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72]
|
||
|
|
node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72]
|
||
|
|
node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72]
|
||
|
|
node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72]
|
||
|
|
node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72]
|
||
|
|
node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72]
|
||
|
|
node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72]
|
||
|
|
node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72]
|
||
|
|
node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72]
|
||
|
|
node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72]
|
||
|
|
node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72]
|
||
|
|
wire _T_1307 : UInt<1> @[Mux.scala 27:72]
|
||
|
|
_T_1307 <= _T_1306 @[Mux.scala 27:72]
|
||
|
|
node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2272:44]
|
||
|
|
mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2272:19]
|
||
|
|
node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2272:38]
|
||
|
|
node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2272:24]
|
||
|
|
node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34]
|
||
|
|
node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2273:62]
|
||
|
|
node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34]
|
||
|
|
node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2274:62]
|
||
|
|
node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34]
|
||
|
|
node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2275:62]
|
||
|
|
node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34]
|
||
|
|
node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2276:62]
|
||
|
|
node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96]
|
||
|
|
node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2276:94]
|
||
|
|
node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34]
|
||
|
|
node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2277:62]
|
||
|
|
node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96]
|
||
|
|
node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2277:94]
|
||
|
|
node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117]
|
||
|
|
node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2277:115]
|
||
|
|
node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34]
|
||
|
|
node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2278:62]
|
||
|
|
node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94]
|
||
|
|
node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117]
|
||
|
|
node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2278:115]
|
||
|
|
node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34]
|
||
|
|
node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2279:62]
|
||
|
|
node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34]
|
||
|
|
node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2280:62]
|
||
|
|
node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34]
|
||
|
|
node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2281:62]
|
||
|
|
node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34]
|
||
|
|
node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2282:62]
|
||
|
|
node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91]
|
||
|
|
node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34]
|
||
|
|
node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2283:62]
|
||
|
|
node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105]
|
||
|
|
node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34]
|
||
|
|
node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2284:62]
|
||
|
|
node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91]
|
||
|
|
node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34]
|
||
|
|
node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2285:62]
|
||
|
|
node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91]
|
||
|
|
node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34]
|
||
|
|
node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2286:62]
|
||
|
|
node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
|
||
|
|
node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100]
|
||
|
|
node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34]
|
||
|
|
node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2287:62]
|
||
|
|
node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
|
||
|
|
node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142]
|
||
|
|
node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2287:101]
|
||
|
|
node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34]
|
||
|
|
node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2288:59]
|
||
|
|
node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89]
|
||
|
|
node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34]
|
||
|
|
node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2289:59]
|
||
|
|
node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89]
|
||
|
|
node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34]
|
||
|
|
node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2290:59]
|
||
|
|
node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89]
|
||
|
|
node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34]
|
||
|
|
node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2291:59]
|
||
|
|
node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89]
|
||
|
|
node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34]
|
||
|
|
node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2292:59]
|
||
|
|
node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89]
|
||
|
|
node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34]
|
||
|
|
node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2293:59]
|
||
|
|
node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89]
|
||
|
|
node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34]
|
||
|
|
node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2294:59]
|
||
|
|
node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89]
|
||
|
|
node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34]
|
||
|
|
node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2295:59]
|
||
|
|
node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89]
|
||
|
|
node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34]
|
||
|
|
node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2296:59]
|
||
|
|
node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89]
|
||
|
|
node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34]
|
||
|
|
node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2297:59]
|
||
|
|
node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89]
|
||
|
|
node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122]
|
||
|
|
node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2297:101]
|
||
|
|
node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34]
|
||
|
|
node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2298:62]
|
||
|
|
node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95]
|
||
|
|
node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34]
|
||
|
|
node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2299:62]
|
||
|
|
node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97]
|
||
|
|
node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34]
|
||
|
|
node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2300:62]
|
||
|
|
node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110]
|
||
|
|
node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34]
|
||
|
|
node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2301:62]
|
||
|
|
node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34]
|
||
|
|
node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2302:62]
|
||
|
|
node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34]
|
||
|
|
node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2303:62]
|
||
|
|
node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34]
|
||
|
|
node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2304:62]
|
||
|
|
node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34]
|
||
|
|
node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2305:62]
|
||
|
|
node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34]
|
||
|
|
node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2306:62]
|
||
|
|
node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34]
|
||
|
|
node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2307:62]
|
||
|
|
node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34]
|
||
|
|
node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2308:62]
|
||
|
|
node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98]
|
||
|
|
node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120]
|
||
|
|
node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34]
|
||
|
|
node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2309:62]
|
||
|
|
node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92]
|
||
|
|
node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117]
|
||
|
|
node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34]
|
||
|
|
node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2310:62]
|
||
|
|
node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34]
|
||
|
|
node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2311:62]
|
||
|
|
node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34]
|
||
|
|
node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2312:62]
|
||
|
|
node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97]
|
||
|
|
node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129]
|
||
|
|
node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34]
|
||
|
|
node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2313:62]
|
||
|
|
node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34]
|
||
|
|
node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2314:62]
|
||
|
|
node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34]
|
||
|
|
node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2315:62]
|
||
|
|
node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34]
|
||
|
|
node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2316:62]
|
||
|
|
node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34]
|
||
|
|
node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2317:62]
|
||
|
|
node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34]
|
||
|
|
node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2318:62]
|
||
|
|
node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34]
|
||
|
|
node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2319:62]
|
||
|
|
node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34]
|
||
|
|
node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2320:62]
|
||
|
|
node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2320:73]
|
||
|
|
node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34]
|
||
|
|
node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2321:62]
|
||
|
|
node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2321:73]
|
||
|
|
node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107]
|
||
|
|
node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118]
|
||
|
|
node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2321:113]
|
||
|
|
node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2321:125]
|
||
|
|
node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2321:98]
|
||
|
|
node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34]
|
||
|
|
node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2322:62]
|
||
|
|
node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91]
|
||
|
|
node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34]
|
||
|
|
node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2323:62]
|
||
|
|
node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94]
|
||
|
|
node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34]
|
||
|
|
node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2324:62]
|
||
|
|
node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94]
|
||
|
|
node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34]
|
||
|
|
node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2326:62]
|
||
|
|
node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34]
|
||
|
|
node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2327:62]
|
||
|
|
node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34]
|
||
|
|
node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2328:62]
|
||
|
|
node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34]
|
||
|
|
node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2329:62]
|
||
|
|
node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34]
|
||
|
|
node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2330:62]
|
||
|
|
node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72]
|
||
|
|
node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72]
|
||
|
|
node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72]
|
||
|
|
node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72]
|
||
|
|
node _T_1539 = or(_T_1538, _T_1483) @[Mux.scala 27:72]
|
||
|
|
node _T_1540 = or(_T_1539, _T_1484) @[Mux.scala 27:72]
|
||
|
|
node _T_1541 = or(_T_1540, _T_1485) @[Mux.scala 27:72]
|
||
|
|
node _T_1542 = or(_T_1541, _T_1486) @[Mux.scala 27:72]
|
||
|
|
node _T_1543 = or(_T_1542, _T_1487) @[Mux.scala 27:72]
|
||
|
|
node _T_1544 = or(_T_1543, _T_1488) @[Mux.scala 27:72]
|
||
|
|
node _T_1545 = or(_T_1544, _T_1489) @[Mux.scala 27:72]
|
||
|
|
node _T_1546 = or(_T_1545, _T_1490) @[Mux.scala 27:72]
|
||
|
|
node _T_1547 = or(_T_1546, _T_1491) @[Mux.scala 27:72]
|
||
|
|
node _T_1548 = or(_T_1547, _T_1492) @[Mux.scala 27:72]
|
||
|
|
node _T_1549 = or(_T_1548, _T_1493) @[Mux.scala 27:72]
|
||
|
|
node _T_1550 = or(_T_1549, _T_1494) @[Mux.scala 27:72]
|
||
|
|
node _T_1551 = or(_T_1550, _T_1495) @[Mux.scala 27:72]
|
||
|
|
node _T_1552 = or(_T_1551, _T_1496) @[Mux.scala 27:72]
|
||
|
|
node _T_1553 = or(_T_1552, _T_1497) @[Mux.scala 27:72]
|
||
|
|
node _T_1554 = or(_T_1553, _T_1498) @[Mux.scala 27:72]
|
||
|
|
node _T_1555 = or(_T_1554, _T_1499) @[Mux.scala 27:72]
|
||
|
|
node _T_1556 = or(_T_1555, _T_1500) @[Mux.scala 27:72]
|
||
|
|
node _T_1557 = or(_T_1556, _T_1501) @[Mux.scala 27:72]
|
||
|
|
node _T_1558 = or(_T_1557, _T_1502) @[Mux.scala 27:72]
|
||
|
|
node _T_1559 = or(_T_1558, _T_1503) @[Mux.scala 27:72]
|
||
|
|
node _T_1560 = or(_T_1559, _T_1504) @[Mux.scala 27:72]
|
||
|
|
node _T_1561 = or(_T_1560, _T_1505) @[Mux.scala 27:72]
|
||
|
|
node _T_1562 = or(_T_1561, _T_1506) @[Mux.scala 27:72]
|
||
|
|
node _T_1563 = or(_T_1562, _T_1507) @[Mux.scala 27:72]
|
||
|
|
node _T_1564 = or(_T_1563, _T_1508) @[Mux.scala 27:72]
|
||
|
|
node _T_1565 = or(_T_1564, _T_1509) @[Mux.scala 27:72]
|
||
|
|
node _T_1566 = or(_T_1565, _T_1510) @[Mux.scala 27:72]
|
||
|
|
node _T_1567 = or(_T_1566, _T_1511) @[Mux.scala 27:72]
|
||
|
|
node _T_1568 = or(_T_1567, _T_1512) @[Mux.scala 27:72]
|
||
|
|
node _T_1569 = or(_T_1568, _T_1513) @[Mux.scala 27:72]
|
||
|
|
node _T_1570 = or(_T_1569, _T_1514) @[Mux.scala 27:72]
|
||
|
|
node _T_1571 = or(_T_1570, _T_1515) @[Mux.scala 27:72]
|
||
|
|
node _T_1572 = or(_T_1571, _T_1516) @[Mux.scala 27:72]
|
||
|
|
node _T_1573 = or(_T_1572, _T_1517) @[Mux.scala 27:72]
|
||
|
|
node _T_1574 = or(_T_1573, _T_1518) @[Mux.scala 27:72]
|
||
|
|
node _T_1575 = or(_T_1574, _T_1519) @[Mux.scala 27:72]
|
||
|
|
node _T_1576 = or(_T_1575, _T_1520) @[Mux.scala 27:72]
|
||
|
|
node _T_1577 = or(_T_1576, _T_1521) @[Mux.scala 27:72]
|
||
|
|
node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72]
|
||
|
|
node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72]
|
||
|
|
node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72]
|
||
|
|
node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72]
|
||
|
|
node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72]
|
||
|
|
node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72]
|
||
|
|
node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72]
|
||
|
|
node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72]
|
||
|
|
node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72]
|
||
|
|
node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72]
|
||
|
|
node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72]
|
||
|
|
node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72]
|
||
|
|
node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72]
|
||
|
|
wire _T_1591 : UInt<1> @[Mux.scala 27:72]
|
||
|
|
_T_1591 <= _T_1590 @[Mux.scala 27:72]
|
||
|
|
node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2272:44]
|
||
|
|
mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2272:19]
|
||
|
|
node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2272:38]
|
||
|
|
node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2272:24]
|
||
|
|
node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34]
|
||
|
|
node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2273:62]
|
||
|
|
node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34]
|
||
|
|
node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2274:62]
|
||
|
|
node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34]
|
||
|
|
node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2275:62]
|
||
|
|
node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34]
|
||
|
|
node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2276:62]
|
||
|
|
node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96]
|
||
|
|
node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2276:94]
|
||
|
|
node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34]
|
||
|
|
node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2277:62]
|
||
|
|
node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96]
|
||
|
|
node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2277:94]
|
||
|
|
node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117]
|
||
|
|
node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2277:115]
|
||
|
|
node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34]
|
||
|
|
node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2278:62]
|
||
|
|
node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94]
|
||
|
|
node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117]
|
||
|
|
node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2278:115]
|
||
|
|
node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34]
|
||
|
|
node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2279:62]
|
||
|
|
node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34]
|
||
|
|
node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2280:62]
|
||
|
|
node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34]
|
||
|
|
node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2281:62]
|
||
|
|
node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34]
|
||
|
|
node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2282:62]
|
||
|
|
node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91]
|
||
|
|
node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34]
|
||
|
|
node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2283:62]
|
||
|
|
node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105]
|
||
|
|
node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34]
|
||
|
|
node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2284:62]
|
||
|
|
node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91]
|
||
|
|
node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34]
|
||
|
|
node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2285:62]
|
||
|
|
node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91]
|
||
|
|
node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34]
|
||
|
|
node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2286:62]
|
||
|
|
node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
|
||
|
|
node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100]
|
||
|
|
node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34]
|
||
|
|
node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2287:62]
|
||
|
|
node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
|
||
|
|
node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142]
|
||
|
|
node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2287:101]
|
||
|
|
node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34]
|
||
|
|
node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2288:59]
|
||
|
|
node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89]
|
||
|
|
node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34]
|
||
|
|
node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2289:59]
|
||
|
|
node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89]
|
||
|
|
node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34]
|
||
|
|
node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2290:59]
|
||
|
|
node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89]
|
||
|
|
node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34]
|
||
|
|
node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2291:59]
|
||
|
|
node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89]
|
||
|
|
node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34]
|
||
|
|
node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2292:59]
|
||
|
|
node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89]
|
||
|
|
node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34]
|
||
|
|
node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2293:59]
|
||
|
|
node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89]
|
||
|
|
node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34]
|
||
|
|
node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2294:59]
|
||
|
|
node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89]
|
||
|
|
node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34]
|
||
|
|
node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2295:59]
|
||
|
|
node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89]
|
||
|
|
node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34]
|
||
|
|
node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2296:59]
|
||
|
|
node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89]
|
||
|
|
node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34]
|
||
|
|
node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2297:59]
|
||
|
|
node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89]
|
||
|
|
node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122]
|
||
|
|
node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2297:101]
|
||
|
|
node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34]
|
||
|
|
node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2298:62]
|
||
|
|
node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95]
|
||
|
|
node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34]
|
||
|
|
node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2299:62]
|
||
|
|
node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97]
|
||
|
|
node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34]
|
||
|
|
node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2300:62]
|
||
|
|
node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110]
|
||
|
|
node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34]
|
||
|
|
node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2301:62]
|
||
|
|
node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34]
|
||
|
|
node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2302:62]
|
||
|
|
node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34]
|
||
|
|
node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2303:62]
|
||
|
|
node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34]
|
||
|
|
node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2304:62]
|
||
|
|
node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34]
|
||
|
|
node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2305:62]
|
||
|
|
node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34]
|
||
|
|
node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2306:62]
|
||
|
|
node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34]
|
||
|
|
node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2307:62]
|
||
|
|
node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34]
|
||
|
|
node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2308:62]
|
||
|
|
node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98]
|
||
|
|
node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120]
|
||
|
|
node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34]
|
||
|
|
node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2309:62]
|
||
|
|
node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92]
|
||
|
|
node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117]
|
||
|
|
node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34]
|
||
|
|
node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2310:62]
|
||
|
|
node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34]
|
||
|
|
node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2311:62]
|
||
|
|
node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34]
|
||
|
|
node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2312:62]
|
||
|
|
node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97]
|
||
|
|
node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129]
|
||
|
|
node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34]
|
||
|
|
node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2313:62]
|
||
|
|
node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34]
|
||
|
|
node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2314:62]
|
||
|
|
node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34]
|
||
|
|
node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2315:62]
|
||
|
|
node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34]
|
||
|
|
node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2316:62]
|
||
|
|
node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34]
|
||
|
|
node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2317:62]
|
||
|
|
node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34]
|
||
|
|
node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2318:62]
|
||
|
|
node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34]
|
||
|
|
node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2319:62]
|
||
|
|
node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34]
|
||
|
|
node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2320:62]
|
||
|
|
node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2320:73]
|
||
|
|
node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34]
|
||
|
|
node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2321:62]
|
||
|
|
node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2321:73]
|
||
|
|
node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107]
|
||
|
|
node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118]
|
||
|
|
node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2321:113]
|
||
|
|
node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2321:125]
|
||
|
|
node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2321:98]
|
||
|
|
node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34]
|
||
|
|
node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2322:62]
|
||
|
|
node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91]
|
||
|
|
node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34]
|
||
|
|
node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2323:62]
|
||
|
|
node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94]
|
||
|
|
node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34]
|
||
|
|
node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2324:62]
|
||
|
|
node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94]
|
||
|
|
node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34]
|
||
|
|
node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2326:62]
|
||
|
|
node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34]
|
||
|
|
node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2327:62]
|
||
|
|
node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34]
|
||
|
|
node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2328:62]
|
||
|
|
node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34]
|
||
|
|
node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2329:62]
|
||
|
|
node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34]
|
||
|
|
node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2330:62]
|
||
|
|
node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72]
|
||
|
|
node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72]
|
||
|
|
node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72]
|
||
|
|
node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72]
|
||
|
|
node _T_1823 = or(_T_1822, _T_1767) @[Mux.scala 27:72]
|
||
|
|
node _T_1824 = or(_T_1823, _T_1768) @[Mux.scala 27:72]
|
||
|
|
node _T_1825 = or(_T_1824, _T_1769) @[Mux.scala 27:72]
|
||
|
|
node _T_1826 = or(_T_1825, _T_1770) @[Mux.scala 27:72]
|
||
|
|
node _T_1827 = or(_T_1826, _T_1771) @[Mux.scala 27:72]
|
||
|
|
node _T_1828 = or(_T_1827, _T_1772) @[Mux.scala 27:72]
|
||
|
|
node _T_1829 = or(_T_1828, _T_1773) @[Mux.scala 27:72]
|
||
|
|
node _T_1830 = or(_T_1829, _T_1774) @[Mux.scala 27:72]
|
||
|
|
node _T_1831 = or(_T_1830, _T_1775) @[Mux.scala 27:72]
|
||
|
|
node _T_1832 = or(_T_1831, _T_1776) @[Mux.scala 27:72]
|
||
|
|
node _T_1833 = or(_T_1832, _T_1777) @[Mux.scala 27:72]
|
||
|
|
node _T_1834 = or(_T_1833, _T_1778) @[Mux.scala 27:72]
|
||
|
|
node _T_1835 = or(_T_1834, _T_1779) @[Mux.scala 27:72]
|
||
|
|
node _T_1836 = or(_T_1835, _T_1780) @[Mux.scala 27:72]
|
||
|
|
node _T_1837 = or(_T_1836, _T_1781) @[Mux.scala 27:72]
|
||
|
|
node _T_1838 = or(_T_1837, _T_1782) @[Mux.scala 27:72]
|
||
|
|
node _T_1839 = or(_T_1838, _T_1783) @[Mux.scala 27:72]
|
||
|
|
node _T_1840 = or(_T_1839, _T_1784) @[Mux.scala 27:72]
|
||
|
|
node _T_1841 = or(_T_1840, _T_1785) @[Mux.scala 27:72]
|
||
|
|
node _T_1842 = or(_T_1841, _T_1786) @[Mux.scala 27:72]
|
||
|
|
node _T_1843 = or(_T_1842, _T_1787) @[Mux.scala 27:72]
|
||
|
|
node _T_1844 = or(_T_1843, _T_1788) @[Mux.scala 27:72]
|
||
|
|
node _T_1845 = or(_T_1844, _T_1789) @[Mux.scala 27:72]
|
||
|
|
node _T_1846 = or(_T_1845, _T_1790) @[Mux.scala 27:72]
|
||
|
|
node _T_1847 = or(_T_1846, _T_1791) @[Mux.scala 27:72]
|
||
|
|
node _T_1848 = or(_T_1847, _T_1792) @[Mux.scala 27:72]
|
||
|
|
node _T_1849 = or(_T_1848, _T_1793) @[Mux.scala 27:72]
|
||
|
|
node _T_1850 = or(_T_1849, _T_1794) @[Mux.scala 27:72]
|
||
|
|
node _T_1851 = or(_T_1850, _T_1795) @[Mux.scala 27:72]
|
||
|
|
node _T_1852 = or(_T_1851, _T_1796) @[Mux.scala 27:72]
|
||
|
|
node _T_1853 = or(_T_1852, _T_1797) @[Mux.scala 27:72]
|
||
|
|
node _T_1854 = or(_T_1853, _T_1798) @[Mux.scala 27:72]
|
||
|
|
node _T_1855 = or(_T_1854, _T_1799) @[Mux.scala 27:72]
|
||
|
|
node _T_1856 = or(_T_1855, _T_1800) @[Mux.scala 27:72]
|
||
|
|
node _T_1857 = or(_T_1856, _T_1801) @[Mux.scala 27:72]
|
||
|
|
node _T_1858 = or(_T_1857, _T_1802) @[Mux.scala 27:72]
|
||
|
|
node _T_1859 = or(_T_1858, _T_1803) @[Mux.scala 27:72]
|
||
|
|
node _T_1860 = or(_T_1859, _T_1804) @[Mux.scala 27:72]
|
||
|
|
node _T_1861 = or(_T_1860, _T_1805) @[Mux.scala 27:72]
|
||
|
|
node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72]
|
||
|
|
node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72]
|
||
|
|
node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72]
|
||
|
|
node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72]
|
||
|
|
node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72]
|
||
|
|
node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72]
|
||
|
|
node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72]
|
||
|
|
node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72]
|
||
|
|
node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72]
|
||
|
|
node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72]
|
||
|
|
node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72]
|
||
|
|
node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72]
|
||
|
|
node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72]
|
||
|
|
wire _T_1875 : UInt<1> @[Mux.scala 27:72]
|
||
|
|
_T_1875 <= _T_1874 @[Mux.scala 27:72]
|
||
|
|
node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2272:44]
|
||
|
|
mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2272:19]
|
||
|
|
node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2272:38]
|
||
|
|
node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2272:24]
|
||
|
|
node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34]
|
||
|
|
node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2273:62]
|
||
|
|
node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34]
|
||
|
|
node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2274:62]
|
||
|
|
node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34]
|
||
|
|
node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2275:62]
|
||
|
|
node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34]
|
||
|
|
node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2276:62]
|
||
|
|
node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96]
|
||
|
|
node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2276:94]
|
||
|
|
node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34]
|
||
|
|
node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2277:62]
|
||
|
|
node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96]
|
||
|
|
node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2277:94]
|
||
|
|
node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117]
|
||
|
|
node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2277:115]
|
||
|
|
node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34]
|
||
|
|
node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2278:62]
|
||
|
|
node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94]
|
||
|
|
node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117]
|
||
|
|
node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2278:115]
|
||
|
|
node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34]
|
||
|
|
node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2279:62]
|
||
|
|
node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34]
|
||
|
|
node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2280:62]
|
||
|
|
node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34]
|
||
|
|
node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2281:62]
|
||
|
|
node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34]
|
||
|
|
node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2282:62]
|
||
|
|
node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91]
|
||
|
|
node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34]
|
||
|
|
node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2283:62]
|
||
|
|
node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105]
|
||
|
|
node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34]
|
||
|
|
node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2284:62]
|
||
|
|
node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91]
|
||
|
|
node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34]
|
||
|
|
node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2285:62]
|
||
|
|
node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91]
|
||
|
|
node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34]
|
||
|
|
node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2286:62]
|
||
|
|
node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
|
||
|
|
node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100]
|
||
|
|
node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34]
|
||
|
|
node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2287:62]
|
||
|
|
node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
|
||
|
|
node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142]
|
||
|
|
node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2287:101]
|
||
|
|
node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34]
|
||
|
|
node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2288:59]
|
||
|
|
node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89]
|
||
|
|
node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34]
|
||
|
|
node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2289:59]
|
||
|
|
node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89]
|
||
|
|
node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34]
|
||
|
|
node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2290:59]
|
||
|
|
node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89]
|
||
|
|
node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34]
|
||
|
|
node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2291:59]
|
||
|
|
node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89]
|
||
|
|
node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34]
|
||
|
|
node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2292:59]
|
||
|
|
node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89]
|
||
|
|
node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34]
|
||
|
|
node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2293:59]
|
||
|
|
node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89]
|
||
|
|
node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34]
|
||
|
|
node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2294:59]
|
||
|
|
node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89]
|
||
|
|
node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34]
|
||
|
|
node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2295:59]
|
||
|
|
node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89]
|
||
|
|
node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34]
|
||
|
|
node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2296:59]
|
||
|
|
node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89]
|
||
|
|
node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34]
|
||
|
|
node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2297:59]
|
||
|
|
node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89]
|
||
|
|
node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122]
|
||
|
|
node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2297:101]
|
||
|
|
node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34]
|
||
|
|
node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2298:62]
|
||
|
|
node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95]
|
||
|
|
node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34]
|
||
|
|
node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2299:62]
|
||
|
|
node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97]
|
||
|
|
node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34]
|
||
|
|
node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2300:62]
|
||
|
|
node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110]
|
||
|
|
node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34]
|
||
|
|
node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2301:62]
|
||
|
|
node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34]
|
||
|
|
node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2302:62]
|
||
|
|
node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34]
|
||
|
|
node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2303:62]
|
||
|
|
node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34]
|
||
|
|
node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2304:62]
|
||
|
|
node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34]
|
||
|
|
node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2305:62]
|
||
|
|
node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34]
|
||
|
|
node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2306:62]
|
||
|
|
node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34]
|
||
|
|
node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2307:62]
|
||
|
|
node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34]
|
||
|
|
node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2308:62]
|
||
|
|
node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98]
|
||
|
|
node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120]
|
||
|
|
node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34]
|
||
|
|
node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2309:62]
|
||
|
|
node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92]
|
||
|
|
node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117]
|
||
|
|
node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34]
|
||
|
|
node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2310:62]
|
||
|
|
node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34]
|
||
|
|
node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2311:62]
|
||
|
|
node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34]
|
||
|
|
node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2312:62]
|
||
|
|
node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97]
|
||
|
|
node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129]
|
||
|
|
node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34]
|
||
|
|
node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2313:62]
|
||
|
|
node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34]
|
||
|
|
node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2314:62]
|
||
|
|
node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34]
|
||
|
|
node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2315:62]
|
||
|
|
node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34]
|
||
|
|
node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2316:62]
|
||
|
|
node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34]
|
||
|
|
node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2317:62]
|
||
|
|
node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34]
|
||
|
|
node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2318:62]
|
||
|
|
node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34]
|
||
|
|
node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2319:62]
|
||
|
|
node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34]
|
||
|
|
node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2320:62]
|
||
|
|
node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2320:84]
|
||
|
|
node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2320:73]
|
||
|
|
node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34]
|
||
|
|
node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2321:62]
|
||
|
|
node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2321:84]
|
||
|
|
node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2321:73]
|
||
|
|
node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107]
|
||
|
|
node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118]
|
||
|
|
node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2321:113]
|
||
|
|
node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2321:125]
|
||
|
|
node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2321:98]
|
||
|
|
node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34]
|
||
|
|
node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2322:62]
|
||
|
|
node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91]
|
||
|
|
node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34]
|
||
|
|
node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2323:62]
|
||
|
|
node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94]
|
||
|
|
node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34]
|
||
|
|
node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2324:62]
|
||
|
|
node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94]
|
||
|
|
node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34]
|
||
|
|
node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2326:62]
|
||
|
|
node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34]
|
||
|
|
node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2327:62]
|
||
|
|
node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34]
|
||
|
|
node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2328:62]
|
||
|
|
node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34]
|
||
|
|
node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2329:62]
|
||
|
|
node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34]
|
||
|
|
node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2330:62]
|
||
|
|
node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72]
|
||
|
|
node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72]
|
||
|
|
node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72]
|
||
|
|
node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72]
|
||
|
|
node _T_2107 = or(_T_2106, _T_2051) @[Mux.scala 27:72]
|
||
|
|
node _T_2108 = or(_T_2107, _T_2052) @[Mux.scala 27:72]
|
||
|
|
node _T_2109 = or(_T_2108, _T_2053) @[Mux.scala 27:72]
|
||
|
|
node _T_2110 = or(_T_2109, _T_2054) @[Mux.scala 27:72]
|
||
|
|
node _T_2111 = or(_T_2110, _T_2055) @[Mux.scala 27:72]
|
||
|
|
node _T_2112 = or(_T_2111, _T_2056) @[Mux.scala 27:72]
|
||
|
|
node _T_2113 = or(_T_2112, _T_2057) @[Mux.scala 27:72]
|
||
|
|
node _T_2114 = or(_T_2113, _T_2058) @[Mux.scala 27:72]
|
||
|
|
node _T_2115 = or(_T_2114, _T_2059) @[Mux.scala 27:72]
|
||
|
|
node _T_2116 = or(_T_2115, _T_2060) @[Mux.scala 27:72]
|
||
|
|
node _T_2117 = or(_T_2116, _T_2061) @[Mux.scala 27:72]
|
||
|
|
node _T_2118 = or(_T_2117, _T_2062) @[Mux.scala 27:72]
|
||
|
|
node _T_2119 = or(_T_2118, _T_2063) @[Mux.scala 27:72]
|
||
|
|
node _T_2120 = or(_T_2119, _T_2064) @[Mux.scala 27:72]
|
||
|
|
node _T_2121 = or(_T_2120, _T_2065) @[Mux.scala 27:72]
|
||
|
|
node _T_2122 = or(_T_2121, _T_2066) @[Mux.scala 27:72]
|
||
|
|
node _T_2123 = or(_T_2122, _T_2067) @[Mux.scala 27:72]
|
||
|
|
node _T_2124 = or(_T_2123, _T_2068) @[Mux.scala 27:72]
|
||
|
|
node _T_2125 = or(_T_2124, _T_2069) @[Mux.scala 27:72]
|
||
|
|
node _T_2126 = or(_T_2125, _T_2070) @[Mux.scala 27:72]
|
||
|
|
node _T_2127 = or(_T_2126, _T_2071) @[Mux.scala 27:72]
|
||
|
|
node _T_2128 = or(_T_2127, _T_2072) @[Mux.scala 27:72]
|
||
|
|
node _T_2129 = or(_T_2128, _T_2073) @[Mux.scala 27:72]
|
||
|
|
node _T_2130 = or(_T_2129, _T_2074) @[Mux.scala 27:72]
|
||
|
|
node _T_2131 = or(_T_2130, _T_2075) @[Mux.scala 27:72]
|
||
|
|
node _T_2132 = or(_T_2131, _T_2076) @[Mux.scala 27:72]
|
||
|
|
node _T_2133 = or(_T_2132, _T_2077) @[Mux.scala 27:72]
|
||
|
|
node _T_2134 = or(_T_2133, _T_2078) @[Mux.scala 27:72]
|
||
|
|
node _T_2135 = or(_T_2134, _T_2079) @[Mux.scala 27:72]
|
||
|
|
node _T_2136 = or(_T_2135, _T_2080) @[Mux.scala 27:72]
|
||
|
|
node _T_2137 = or(_T_2136, _T_2081) @[Mux.scala 27:72]
|
||
|
|
node _T_2138 = or(_T_2137, _T_2082) @[Mux.scala 27:72]
|
||
|
|
node _T_2139 = or(_T_2138, _T_2083) @[Mux.scala 27:72]
|
||
|
|
node _T_2140 = or(_T_2139, _T_2084) @[Mux.scala 27:72]
|
||
|
|
node _T_2141 = or(_T_2140, _T_2085) @[Mux.scala 27:72]
|
||
|
|
node _T_2142 = or(_T_2141, _T_2086) @[Mux.scala 27:72]
|
||
|
|
node _T_2143 = or(_T_2142, _T_2087) @[Mux.scala 27:72]
|
||
|
|
node _T_2144 = or(_T_2143, _T_2088) @[Mux.scala 27:72]
|
||
|
|
node _T_2145 = or(_T_2144, _T_2089) @[Mux.scala 27:72]
|
||
|
|
node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72]
|
||
|
|
node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72]
|
||
|
|
node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72]
|
||
|
|
node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72]
|
||
|
|
node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72]
|
||
|
|
node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72]
|
||
|
|
node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72]
|
||
|
|
node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72]
|
||
|
|
node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72]
|
||
|
|
node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72]
|
||
|
|
node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72]
|
||
|
|
node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72]
|
||
|
|
node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72]
|
||
|
|
wire _T_2159 : UInt<1> @[Mux.scala 27:72]
|
||
|
|
_T_2159 <= _T_2158 @[Mux.scala 27:72]
|
||
|
|
node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2272:44]
|
||
|
|
mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2272:19]
|
||
|
|
reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2333:53]
|
||
|
|
_T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2333:53]
|
||
|
|
mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2333:20]
|
||
|
|
reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53]
|
||
|
|
_T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2334:53]
|
||
|
|
mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2334:20]
|
||
|
|
reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53]
|
||
|
|
_T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2335:53]
|
||
|
|
mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2335:20]
|
||
|
|
reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53]
|
||
|
|
_T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2336:53]
|
||
|
|
mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2336:20]
|
||
|
|
reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:56]
|
||
|
|
perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2337:56]
|
||
|
|
node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2340:53]
|
||
|
|
node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2340:44]
|
||
|
|
node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2340:67]
|
||
|
|
perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2340:17]
|
||
|
|
node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:70]
|
||
|
|
node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2341:61]
|
||
|
|
node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2341:37]
|
||
|
|
node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2341:104]
|
||
|
|
node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2341:120]
|
||
|
|
node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2341:136]
|
||
|
|
node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2341:152]
|
||
|
|
node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58]
|
||
|
|
node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58]
|
||
|
|
node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58]
|
||
|
|
node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2341:86]
|
||
|
|
node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2343:88]
|
||
|
|
node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2343:67]
|
||
|
|
node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2343:65]
|
||
|
|
node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2343:45]
|
||
|
|
node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2343:43]
|
||
|
|
io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2343:22]
|
||
|
|
node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2344:88]
|
||
|
|
node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2344:67]
|
||
|
|
node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2344:65]
|
||
|
|
node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2344:45]
|
||
|
|
node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2344:43]
|
||
|
|
io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2344:22]
|
||
|
|
node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2345:88]
|
||
|
|
node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2345:67]
|
||
|
|
node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2345:65]
|
||
|
|
node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2345:45]
|
||
|
|
node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2345:43]
|
||
|
|
io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2345:22]
|
||
|
|
node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2346:88]
|
||
|
|
node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2346:67]
|
||
|
|
node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2346:65]
|
||
|
|
node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2346:45]
|
||
|
|
node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2346:43]
|
||
|
|
io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2346:22]
|
||
|
|
node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2352:65]
|
||
|
|
node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2352:72]
|
||
|
|
node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2352:43]
|
||
|
|
node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2353:23]
|
||
|
|
node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2353:61]
|
||
|
|
node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2353:39]
|
||
|
|
node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2353:86]
|
||
|
|
node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2353:66]
|
||
|
|
node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2354:36]
|
||
|
|
node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2357:28]
|
||
|
|
node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2357:41]
|
||
|
|
node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58]
|
||
|
|
node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2357:49]
|
||
|
|
node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2357:49]
|
||
|
|
mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2357:14]
|
||
|
|
node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2358:36]
|
||
|
|
node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2358:76]
|
||
|
|
node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2358:21]
|
||
|
|
node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2360:42]
|
||
|
|
inst rvclkhdr_26 of rvclkhdr_85 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_26.clock <= clock
|
||
|
|
rvclkhdr_26.reset <= reset
|
||
|
|
rvclkhdr_26.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2215 <= mhpmc3_ns @[lib.scala 374:16]
|
||
|
|
mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2360:9]
|
||
|
|
node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2362:66]
|
||
|
|
node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2362:73]
|
||
|
|
node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2362:44]
|
||
|
|
node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2363:38]
|
||
|
|
node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2364:38]
|
||
|
|
node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2364:78]
|
||
|
|
node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2364:22]
|
||
|
|
node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2366:46]
|
||
|
|
inst rvclkhdr_27 of rvclkhdr_86 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_27.clock <= clock
|
||
|
|
rvclkhdr_27.reset <= reset
|
||
|
|
rvclkhdr_27.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2221 <= mhpmc3h_ns @[lib.scala 374:16]
|
||
|
|
mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2366:10]
|
||
|
|
node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2371:65]
|
||
|
|
node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2371:72]
|
||
|
|
node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2371:43]
|
||
|
|
node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2372:23]
|
||
|
|
node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2372:61]
|
||
|
|
node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2372:39]
|
||
|
|
node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2372:86]
|
||
|
|
node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2372:66]
|
||
|
|
node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2373:36]
|
||
|
|
node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2377:28]
|
||
|
|
node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2377:41]
|
||
|
|
node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58]
|
||
|
|
node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2377:49]
|
||
|
|
node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2377:49]
|
||
|
|
mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2377:14]
|
||
|
|
node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36]
|
||
|
|
node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2378:63]
|
||
|
|
node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2378:82]
|
||
|
|
node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2378:21]
|
||
|
|
node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2379:43]
|
||
|
|
inst rvclkhdr_28 of rvclkhdr_87 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_28.clock <= clock
|
||
|
|
rvclkhdr_28.reset <= reset
|
||
|
|
rvclkhdr_28.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2238 <= mhpmc4_ns @[lib.scala 374:16]
|
||
|
|
mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2379:9]
|
||
|
|
node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2381:66]
|
||
|
|
node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2381:73]
|
||
|
|
node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2381:44]
|
||
|
|
node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2382:38]
|
||
|
|
node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2383:38]
|
||
|
|
node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2383:78]
|
||
|
|
node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2383:22]
|
||
|
|
node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2384:46]
|
||
|
|
inst rvclkhdr_29 of rvclkhdr_88 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_29.clock <= clock
|
||
|
|
rvclkhdr_29.reset <= reset
|
||
|
|
rvclkhdr_29.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2244 <= mhpmc4h_ns @[lib.scala 374:16]
|
||
|
|
mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2384:10]
|
||
|
|
node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2390:65]
|
||
|
|
node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2390:72]
|
||
|
|
node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2390:43]
|
||
|
|
node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2391:23]
|
||
|
|
node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2391:61]
|
||
|
|
node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2391:39]
|
||
|
|
node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2391:86]
|
||
|
|
node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2391:66]
|
||
|
|
node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2392:36]
|
||
|
|
node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2394:28]
|
||
|
|
node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2394:41]
|
||
|
|
node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58]
|
||
|
|
node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2394:49]
|
||
|
|
node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2394:49]
|
||
|
|
mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2394:14]
|
||
|
|
node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2395:36]
|
||
|
|
node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2395:76]
|
||
|
|
node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2395:21]
|
||
|
|
node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2397:43]
|
||
|
|
inst rvclkhdr_30 of rvclkhdr_89 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_30.clock <= clock
|
||
|
|
rvclkhdr_30.reset <= reset
|
||
|
|
rvclkhdr_30.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2260 <= mhpmc5_ns @[lib.scala 374:16]
|
||
|
|
mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2397:9]
|
||
|
|
node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2399:66]
|
||
|
|
node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2399:73]
|
||
|
|
node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2399:44]
|
||
|
|
node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2400:38]
|
||
|
|
node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2401:38]
|
||
|
|
node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2401:78]
|
||
|
|
node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2401:22]
|
||
|
|
node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2403:46]
|
||
|
|
inst rvclkhdr_31 of rvclkhdr_90 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_31.clock <= clock
|
||
|
|
rvclkhdr_31.reset <= reset
|
||
|
|
rvclkhdr_31.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2266 <= mhpmc5h_ns @[lib.scala 374:16]
|
||
|
|
mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2403:10]
|
||
|
|
node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2408:65]
|
||
|
|
node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2408:72]
|
||
|
|
node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2408:43]
|
||
|
|
node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2409:23]
|
||
|
|
node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2409:61]
|
||
|
|
node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2409:39]
|
||
|
|
node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2409:86]
|
||
|
|
node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2409:66]
|
||
|
|
node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2410:36]
|
||
|
|
node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2412:28]
|
||
|
|
node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2412:41]
|
||
|
|
node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58]
|
||
|
|
node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2412:49]
|
||
|
|
node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2412:49]
|
||
|
|
mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2412:14]
|
||
|
|
node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2413:36]
|
||
|
|
node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2413:76]
|
||
|
|
node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2413:21]
|
||
|
|
node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2415:43]
|
||
|
|
inst rvclkhdr_32 of rvclkhdr_91 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_32.clock <= clock
|
||
|
|
rvclkhdr_32.reset <= reset
|
||
|
|
rvclkhdr_32.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2282 <= mhpmc6_ns @[lib.scala 374:16]
|
||
|
|
mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2415:9]
|
||
|
|
node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2417:66]
|
||
|
|
node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2417:73]
|
||
|
|
node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2417:44]
|
||
|
|
node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2418:38]
|
||
|
|
node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2419:38]
|
||
|
|
node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2419:78]
|
||
|
|
node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2419:22]
|
||
|
|
node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2421:46]
|
||
|
|
inst rvclkhdr_33 of rvclkhdr_92 @[lib.scala 368:23]
|
||
|
|
rvclkhdr_33.clock <= clock
|
||
|
|
rvclkhdr_33.reset <= reset
|
||
|
|
rvclkhdr_33.io.clk <= clock @[lib.scala 370:18]
|
||
|
|
rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17]
|
||
|
|
rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||
|
|
reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||
|
|
_T_2288 <= mhpmc6h_ns @[lib.scala 374:16]
|
||
|
|
mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2421:10]
|
||
|
|
node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:50]
|
||
|
|
node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2428:56]
|
||
|
|
node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2428:93]
|
||
|
|
node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2428:102]
|
||
|
|
node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2428:71]
|
||
|
|
node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:141]
|
||
|
|
node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2428:28]
|
||
|
|
node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2430:63]
|
||
|
|
node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2430:70]
|
||
|
|
node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2430:41]
|
||
|
|
node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2432:80]
|
||
|
|
reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_2297 : @[Reg.scala 28:19]
|
||
|
|
_T_2298 <= event_saturate_r @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2432:9]
|
||
|
|
node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2437:63]
|
||
|
|
node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2437:70]
|
||
|
|
node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2437:41]
|
||
|
|
node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2438:80]
|
||
|
|
reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_2301 : @[Reg.scala 28:19]
|
||
|
|
_T_2302 <= event_saturate_r @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2438:9]
|
||
|
|
node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2444:63]
|
||
|
|
node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2444:70]
|
||
|
|
node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2444:41]
|
||
|
|
node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2445:80]
|
||
|
|
reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_2305 : @[Reg.scala 28:19]
|
||
|
|
_T_2306 <= event_saturate_r @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2445:9]
|
||
|
|
node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:63]
|
||
|
|
node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2451:70]
|
||
|
|
node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2451:41]
|
||
|
|
node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2452:80]
|
||
|
|
reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_2309 : @[Reg.scala 28:19]
|
||
|
|
_T_2310 <= event_saturate_r @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2452:9]
|
||
|
|
node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2468:70]
|
||
|
|
node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2468:77]
|
||
|
|
node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2468:48]
|
||
|
|
node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2470:54]
|
||
|
|
wire temp_ncount0 : UInt<1>
|
||
|
|
temp_ncount0 <= _T_2313
|
||
|
|
node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2471:54]
|
||
|
|
wire temp_ncount1 : UInt<1>
|
||
|
|
temp_ncount1 <= _T_2314
|
||
|
|
node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2472:55]
|
||
|
|
wire temp_ncount6_2 : UInt<5>
|
||
|
|
temp_ncount6_2 <= _T_2315
|
||
|
|
node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2473:74]
|
||
|
|
node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2473:103]
|
||
|
|
reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_2317 : @[Reg.scala 28:19]
|
||
|
|
_T_2318 <= _T_2316 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2473:17]
|
||
|
|
node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2475:72]
|
||
|
|
node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:99]
|
||
|
|
reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_2320 : @[Reg.scala 28:19]
|
||
|
|
_T_2321 <= _T_2319 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2475:15]
|
||
|
|
node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58]
|
||
|
|
mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2476:16]
|
||
|
|
node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2483:51]
|
||
|
|
node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2483:78]
|
||
|
|
node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2483:104]
|
||
|
|
node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2483:130]
|
||
|
|
node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2484:32]
|
||
|
|
node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2484:59]
|
||
|
|
node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2484:78]
|
||
|
|
inst rvclkhdr_34 of rvclkhdr_93 @[lib.scala 343:22]
|
||
|
|
rvclkhdr_34.clock <= clock
|
||
|
|
rvclkhdr_34.reset <= reset
|
||
|
|
rvclkhdr_34.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16]
|
||
|
|
rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||
|
|
reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2486:62]
|
||
|
|
_T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2486:62]
|
||
|
|
io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2486:30]
|
||
|
|
node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2487:91]
|
||
|
|
node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2487:137]
|
||
|
|
node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2487:135]
|
||
|
|
node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2487:112]
|
||
|
|
reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62]
|
||
|
|
_T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2487:62]
|
||
|
|
io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2487:30]
|
||
|
|
reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62]
|
||
|
|
_T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2488:62]
|
||
|
|
io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2488:30]
|
||
|
|
reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62]
|
||
|
|
_T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2489:62]
|
||
|
|
io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2489:30]
|
||
|
|
io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2491:24]
|
||
|
|
node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2497:61]
|
||
|
|
node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2498:42]
|
||
|
|
node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2499:40]
|
||
|
|
node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2500:39]
|
||
|
|
node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2501:40]
|
||
|
|
node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:40]
|
||
|
|
node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2502:103]
|
||
|
|
node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:128]
|
||
|
|
node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58]
|
||
|
|
node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58]
|
||
|
|
node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
|
||
|
|
node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58]
|
||
|
|
node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58]
|
||
|
|
node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:38]
|
||
|
|
node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2503:70]
|
||
|
|
node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:96]
|
||
|
|
node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58]
|
||
|
|
node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2504:36]
|
||
|
|
node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2504:78]
|
||
|
|
node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2504:102]
|
||
|
|
node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2504:123]
|
||
|
|
node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2504:144]
|
||
|
|
node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58]
|
||
|
|
node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58]
|
||
|
|
node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58]
|
||
|
|
node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58]
|
||
|
|
node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2505:36]
|
||
|
|
node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2505:75]
|
||
|
|
node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2505:96]
|
||
|
|
node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2505:114]
|
||
|
|
node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2505:132]
|
||
|
|
node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58]
|
||
|
|
node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58]
|
||
|
|
node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58]
|
||
|
|
node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58]
|
||
|
|
node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2506:40]
|
||
|
|
node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2506:65]
|
||
|
|
node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2507:40]
|
||
|
|
node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2507:69]
|
||
|
|
node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2508:42]
|
||
|
|
node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2508:72]
|
||
|
|
node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2509:42]
|
||
|
|
node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2509:72]
|
||
|
|
node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2510:41]
|
||
|
|
node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2510:66]
|
||
|
|
node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2511:37]
|
||
|
|
node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2512:39]
|
||
|
|
node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2512:64]
|
||
|
|
node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2513:40]
|
||
|
|
node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2513:80]
|
||
|
|
node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58]
|
||
|
|
node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2514:38]
|
||
|
|
node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2514:63]
|
||
|
|
node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2515:37]
|
||
|
|
node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2515:62]
|
||
|
|
node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2516:39]
|
||
|
|
node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2516:64]
|
||
|
|
node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2517:38]
|
||
|
|
node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2518:39]
|
||
|
|
node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58]
|
||
|
|
node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2519:41]
|
||
|
|
node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2519:81]
|
||
|
|
node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58]
|
||
|
|
node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2520:41]
|
||
|
|
node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2520:81]
|
||
|
|
node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58]
|
||
|
|
node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2521:38]
|
||
|
|
node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2521:78]
|
||
|
|
node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58]
|
||
|
|
node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2522:37]
|
||
|
|
node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2522:77]
|
||
|
|
node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58]
|
||
|
|
node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2523:37]
|
||
|
|
node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2523:77]
|
||
|
|
node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58]
|
||
|
|
node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2524:37]
|
||
|
|
node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2524:85]
|
||
|
|
node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58]
|
||
|
|
node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58]
|
||
|
|
node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2525:36]
|
||
|
|
node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2526:39]
|
||
|
|
node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2526:64]
|
||
|
|
node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2527:40]
|
||
|
|
node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2527:65]
|
||
|
|
node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2528:39]
|
||
|
|
node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2528:64]
|
||
|
|
node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2529:41]
|
||
|
|
node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2529:80]
|
||
|
|
node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2529:104]
|
||
|
|
node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2529:131]
|
||
|
|
node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58]
|
||
|
|
node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58]
|
||
|
|
node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58]
|
||
|
|
node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58]
|
||
|
|
node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58]
|
||
|
|
node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2530:38]
|
||
|
|
node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2530:78]
|
||
|
|
node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58]
|
||
|
|
node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2531:40]
|
||
|
|
node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2531:74]
|
||
|
|
node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2532:40]
|
||
|
|
node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74]
|
||
|
|
node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2533:39]
|
||
|
|
node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2533:64]
|
||
|
|
node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2534:41]
|
||
|
|
node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2534:66]
|
||
|
|
node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41]
|
||
|
|
node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66]
|
||
|
|
node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2536:39]
|
||
|
|
node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2536:64]
|
||
|
|
node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2537:39]
|
||
|
|
node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2537:64]
|
||
|
|
node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2538:39]
|
||
|
|
node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2538:64]
|
||
|
|
node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2539:39]
|
||
|
|
node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2539:64]
|
||
|
|
node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2540:40]
|
||
|
|
node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2540:65]
|
||
|
|
node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2541:40]
|
||
|
|
node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2541:65]
|
||
|
|
node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2542:40]
|
||
|
|
node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2542:65]
|
||
|
|
node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2543:40]
|
||
|
|
node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2543:65]
|
||
|
|
node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2544:38]
|
||
|
|
node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2544:78]
|
||
|
|
node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58]
|
||
|
|
node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2545:38]
|
||
|
|
node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2545:78]
|
||
|
|
node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58]
|
||
|
|
node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2546:39]
|
||
|
|
node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2546:79]
|
||
|
|
node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58]
|
||
|
|
node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2547:39]
|
||
|
|
node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2547:79]
|
||
|
|
node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58]
|
||
|
|
node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2548:39]
|
||
|
|
node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2548:78]
|
||
|
|
node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58]
|
||
|
|
node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2549:39]
|
||
|
|
node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2549:78]
|
||
|
|
node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58]
|
||
|
|
node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2550:46]
|
||
|
|
node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2550:86]
|
||
|
|
node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58]
|
||
|
|
node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2551:37]
|
||
|
|
node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58]
|
||
|
|
node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2552:37]
|
||
|
|
node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2552:76]
|
||
|
|
node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72]
|
||
|
|
node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72]
|
||
|
|
node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72]
|
||
|
|
node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72]
|
||
|
|
node _T_2565 = or(_T_2564, _T_2510) @[Mux.scala 27:72]
|
||
|
|
node _T_2566 = or(_T_2565, _T_2511) @[Mux.scala 27:72]
|
||
|
|
node _T_2567 = or(_T_2566, _T_2512) @[Mux.scala 27:72]
|
||
|
|
node _T_2568 = or(_T_2567, _T_2513) @[Mux.scala 27:72]
|
||
|
|
node _T_2569 = or(_T_2568, _T_2514) @[Mux.scala 27:72]
|
||
|
|
node _T_2570 = or(_T_2569, _T_2515) @[Mux.scala 27:72]
|
||
|
|
node _T_2571 = or(_T_2570, _T_2516) @[Mux.scala 27:72]
|
||
|
|
node _T_2572 = or(_T_2571, _T_2517) @[Mux.scala 27:72]
|
||
|
|
node _T_2573 = or(_T_2572, _T_2518) @[Mux.scala 27:72]
|
||
|
|
node _T_2574 = or(_T_2573, _T_2519) @[Mux.scala 27:72]
|
||
|
|
node _T_2575 = or(_T_2574, _T_2520) @[Mux.scala 27:72]
|
||
|
|
node _T_2576 = or(_T_2575, _T_2521) @[Mux.scala 27:72]
|
||
|
|
node _T_2577 = or(_T_2576, _T_2522) @[Mux.scala 27:72]
|
||
|
|
node _T_2578 = or(_T_2577, _T_2523) @[Mux.scala 27:72]
|
||
|
|
node _T_2579 = or(_T_2578, _T_2524) @[Mux.scala 27:72]
|
||
|
|
node _T_2580 = or(_T_2579, _T_2525) @[Mux.scala 27:72]
|
||
|
|
node _T_2581 = or(_T_2580, _T_2526) @[Mux.scala 27:72]
|
||
|
|
node _T_2582 = or(_T_2581, _T_2527) @[Mux.scala 27:72]
|
||
|
|
node _T_2583 = or(_T_2582, _T_2528) @[Mux.scala 27:72]
|
||
|
|
node _T_2584 = or(_T_2583, _T_2529) @[Mux.scala 27:72]
|
||
|
|
node _T_2585 = or(_T_2584, _T_2530) @[Mux.scala 27:72]
|
||
|
|
node _T_2586 = or(_T_2585, _T_2531) @[Mux.scala 27:72]
|
||
|
|
node _T_2587 = or(_T_2586, _T_2532) @[Mux.scala 27:72]
|
||
|
|
node _T_2588 = or(_T_2587, _T_2533) @[Mux.scala 27:72]
|
||
|
|
node _T_2589 = or(_T_2588, _T_2534) @[Mux.scala 27:72]
|
||
|
|
node _T_2590 = or(_T_2589, _T_2535) @[Mux.scala 27:72]
|
||
|
|
node _T_2591 = or(_T_2590, _T_2536) @[Mux.scala 27:72]
|
||
|
|
node _T_2592 = or(_T_2591, _T_2537) @[Mux.scala 27:72]
|
||
|
|
node _T_2593 = or(_T_2592, _T_2538) @[Mux.scala 27:72]
|
||
|
|
node _T_2594 = or(_T_2593, _T_2539) @[Mux.scala 27:72]
|
||
|
|
node _T_2595 = or(_T_2594, _T_2540) @[Mux.scala 27:72]
|
||
|
|
node _T_2596 = or(_T_2595, _T_2541) @[Mux.scala 27:72]
|
||
|
|
node _T_2597 = or(_T_2596, _T_2542) @[Mux.scala 27:72]
|
||
|
|
node _T_2598 = or(_T_2597, _T_2543) @[Mux.scala 27:72]
|
||
|
|
node _T_2599 = or(_T_2598, _T_2544) @[Mux.scala 27:72]
|
||
|
|
node _T_2600 = or(_T_2599, _T_2545) @[Mux.scala 27:72]
|
||
|
|
node _T_2601 = or(_T_2600, _T_2546) @[Mux.scala 27:72]
|
||
|
|
node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72]
|
||
|
|
node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72]
|
||
|
|
node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72]
|
||
|
|
node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72]
|
||
|
|
node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72]
|
||
|
|
node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72]
|
||
|
|
node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72]
|
||
|
|
node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72]
|
||
|
|
node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72]
|
||
|
|
node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72]
|
||
|
|
node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72]
|
||
|
|
node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72]
|
||
|
|
node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72]
|
||
|
|
node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72]
|
||
|
|
wire _T_2616 : UInt @[Mux.scala 27:72]
|
||
|
|
_T_2616 <= _T_2615 @[Mux.scala 27:72]
|
||
|
|
io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2496:21]
|
||
|
|
|
||
|
|
module dec_decode_csr_read :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}}
|
||
|
|
|
||
|
|
node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2570:57]
|
||
|
|
node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2571:57]
|
||
|
|
node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2572:57]
|
||
|
|
node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2573:57]
|
||
|
|
node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2574:57]
|
||
|
|
node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2575:57]
|
||
|
|
node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2576:57]
|
||
|
|
node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2577:65]
|
||
|
|
node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2578:65]
|
||
|
|
node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2579:57]
|
||
|
|
node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2580:57]
|
||
|
|
node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2581:57]
|
||
|
|
node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2582:57]
|
||
|
|
node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2583:57]
|
||
|
|
node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2584:57]
|
||
|
|
node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2585:57]
|
||
|
|
node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2586:57]
|
||
|
|
node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2587:57]
|
||
|
|
node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2588:57]
|
||
|
|
node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2589:57]
|
||
|
|
node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2590:57]
|
||
|
|
node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2591:57]
|
||
|
|
node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2592:57]
|
||
|
|
node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2593:57]
|
||
|
|
node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2594:57]
|
||
|
|
node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2595:57]
|
||
|
|
node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2596:57]
|
||
|
|
node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2597:57]
|
||
|
|
node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2598:57]
|
||
|
|
node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2599:65]
|
||
|
|
node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2600:57]
|
||
|
|
node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2601:57]
|
||
|
|
node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2602:57]
|
||
|
|
node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2603:57]
|
||
|
|
node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2604:57]
|
||
|
|
node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2605:57]
|
||
|
|
node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2606:57]
|
||
|
|
node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2607:57]
|
||
|
|
node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2608:57]
|
||
|
|
node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2609:57]
|
||
|
|
node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2610:57]
|
||
|
|
node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2611:57]
|
||
|
|
node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2612:57]
|
||
|
|
node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2613:57]
|
||
|
|
node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2614:57]
|
||
|
|
node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2615:49]
|
||
|
|
node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2616:57]
|
||
|
|
node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2617:57]
|
||
|
|
node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2618:57]
|
||
|
|
node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2619:57]
|
||
|
|
node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2620:57]
|
||
|
|
node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2621:57]
|
||
|
|
node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2622:57]
|
||
|
|
node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2623:57]
|
||
|
|
node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2624:57]
|
||
|
|
node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2625:57]
|
||
|
|
node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2626:57]
|
||
|
|
node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2627:57]
|
||
|
|
node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2628:57]
|
||
|
|
node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2629:57]
|
||
|
|
node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2630:57]
|
||
|
|
node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2631:57]
|
||
|
|
node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2632:57]
|
||
|
|
node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2633:57]
|
||
|
|
node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2634:57]
|
||
|
|
node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2635:57]
|
||
|
|
node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2636:81]
|
||
|
|
node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2636:121]
|
||
|
|
node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2636:155]
|
||
|
|
node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2637:97]
|
||
|
|
node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2637:137]
|
||
|
|
io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2636:34]
|
||
|
|
node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2638:81]
|
||
|
|
node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2638:121]
|
||
|
|
node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2638:162]
|
||
|
|
node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2639:105]
|
||
|
|
node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2639:145]
|
||
|
|
node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2639:178]
|
||
|
|
io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2638:30]
|
||
|
|
node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2641:81]
|
||
|
|
node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2641:129]
|
||
|
|
node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2642:105]
|
||
|
|
node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2642:153]
|
||
|
|
node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2643:105]
|
||
|
|
node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2643:153]
|
||
|
|
node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2644:105]
|
||
|
|
node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2644:161]
|
||
|
|
node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2645:105]
|
||
|
|
node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2645:161]
|
||
|
|
node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2646:97]
|
||
|
|
node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2646:153]
|
||
|
|
node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2647:105]
|
||
|
|
node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2647:161]
|
||
|
|
node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2648:105]
|
||
|
|
node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2648:161]
|
||
|
|
node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2649:105]
|
||
|
|
node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2649:161]
|
||
|
|
node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2650:105]
|
||
|
|
node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2650:161]
|
||
|
|
node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2651:105]
|
||
|
|
node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2651:153]
|
||
|
|
node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2652:113]
|
||
|
|
node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185]
|
||
|
|
node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165]
|
||
|
|
node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2652:161]
|
||
|
|
node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2653:97]
|
||
|
|
node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2653:153]
|
||
|
|
node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2654:113]
|
||
|
|
node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149]
|
||
|
|
node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129]
|
||
|
|
node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106]
|
||
|
|
node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2568:198]
|
||
|
|
node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2654:169]
|
||
|
|
io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2641:26]
|
||
|
|
|
||
|
|
module dec_tlu_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, fli
|
||
|
|
|
||
|
|
wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 156:67]
|
||
|
|
wire pause_expired_wb : UInt<1>
|
||
|
|
pause_expired_wb <= UInt<1>("h00")
|
||
|
|
wire take_nmi_r_d1 : UInt<1>
|
||
|
|
take_nmi_r_d1 <= UInt<1>("h00")
|
||
|
|
wire exc_or_int_valid_r_d1 : UInt<1>
|
||
|
|
exc_or_int_valid_r_d1 <= UInt<1>("h00")
|
||
|
|
wire interrupt_valid_r_d1 : UInt<1>
|
||
|
|
interrupt_valid_r_d1 <= UInt<1>("h00")
|
||
|
|
wire tlu_flush_lower_r : UInt<1>
|
||
|
|
tlu_flush_lower_r <= UInt<1>("h00")
|
||
|
|
wire synchronous_flush_r : UInt<1>
|
||
|
|
synchronous_flush_r <= UInt<1>("h00")
|
||
|
|
wire interrupt_valid_r : UInt<1>
|
||
|
|
interrupt_valid_r <= UInt<1>("h00")
|
||
|
|
wire take_nmi : UInt<1>
|
||
|
|
take_nmi <= UInt<1>("h00")
|
||
|
|
wire take_reset : UInt<1>
|
||
|
|
take_reset <= UInt<1>("h00")
|
||
|
|
wire take_int_timer1_int : UInt<1>
|
||
|
|
take_int_timer1_int <= UInt<1>("h00")
|
||
|
|
wire take_int_timer0_int : UInt<1>
|
||
|
|
take_int_timer0_int <= UInt<1>("h00")
|
||
|
|
wire take_timer_int : UInt<1>
|
||
|
|
take_timer_int <= UInt<1>("h00")
|
||
|
|
wire take_soft_int : UInt<1>
|
||
|
|
take_soft_int <= UInt<1>("h00")
|
||
|
|
wire take_ce_int : UInt<1>
|
||
|
|
take_ce_int <= UInt<1>("h00")
|
||
|
|
wire take_ext_int_start : UInt<1>
|
||
|
|
take_ext_int_start <= UInt<1>("h00")
|
||
|
|
wire ext_int_freeze : UInt<1>
|
||
|
|
ext_int_freeze <= UInt<1>("h00")
|
||
|
|
wire ext_int_freeze_d1 : UInt<1>
|
||
|
|
ext_int_freeze_d1 <= UInt<1>("h00")
|
||
|
|
wire take_ext_int_start_d1 : UInt<1>
|
||
|
|
take_ext_int_start_d1 <= UInt<1>("h00")
|
||
|
|
wire take_ext_int_start_d2 : UInt<1>
|
||
|
|
take_ext_int_start_d2 <= UInt<1>("h00")
|
||
|
|
wire take_ext_int_start_d3 : UInt<1>
|
||
|
|
take_ext_int_start_d3 <= UInt<1>("h00")
|
||
|
|
wire fast_int_meicpct : UInt<1>
|
||
|
|
fast_int_meicpct <= UInt<1>("h00")
|
||
|
|
wire ignore_ext_int_due_to_lsu_stall : UInt<1>
|
||
|
|
ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00")
|
||
|
|
wire take_ext_int : UInt<1>
|
||
|
|
take_ext_int <= UInt<1>("h00")
|
||
|
|
wire internal_dbg_halt_timers : UInt<1>
|
||
|
|
internal_dbg_halt_timers <= UInt<1>("h00")
|
||
|
|
wire int_timer1_int_hold : UInt<1>
|
||
|
|
int_timer1_int_hold <= UInt<1>("h00")
|
||
|
|
wire int_timer0_int_hold : UInt<1>
|
||
|
|
int_timer0_int_hold <= UInt<1>("h00")
|
||
|
|
wire mhwakeup_ready : UInt<1>
|
||
|
|
mhwakeup_ready <= UInt<1>("h00")
|
||
|
|
wire ext_int_ready : UInt<1>
|
||
|
|
ext_int_ready <= UInt<1>("h00")
|
||
|
|
wire ce_int_ready : UInt<1>
|
||
|
|
ce_int_ready <= UInt<1>("h00")
|
||
|
|
wire soft_int_ready : UInt<1>
|
||
|
|
soft_int_ready <= UInt<1>("h00")
|
||
|
|
wire timer_int_ready : UInt<1>
|
||
|
|
timer_int_ready <= UInt<1>("h00")
|
||
|
|
wire ebreak_to_debug_mode_r_d1 : UInt<1>
|
||
|
|
ebreak_to_debug_mode_r_d1 <= UInt<1>("h00")
|
||
|
|
wire ebreak_to_debug_mode_r : UInt<1>
|
||
|
|
ebreak_to_debug_mode_r <= UInt<1>("h00")
|
||
|
|
wire inst_acc_r : UInt<1>
|
||
|
|
inst_acc_r <= UInt<1>("h00")
|
||
|
|
wire inst_acc_r_raw : UInt<1>
|
||
|
|
inst_acc_r_raw <= UInt<1>("h00")
|
||
|
|
wire iccm_sbecc_r : UInt<1>
|
||
|
|
iccm_sbecc_r <= UInt<1>("h00")
|
||
|
|
wire ic_perr_r : UInt<1>
|
||
|
|
ic_perr_r <= UInt<1>("h00")
|
||
|
|
wire fence_i_r : UInt<1>
|
||
|
|
fence_i_r <= UInt<1>("h00")
|
||
|
|
wire ebreak_r : UInt<1>
|
||
|
|
ebreak_r <= UInt<1>("h00")
|
||
|
|
wire ecall_r : UInt<1>
|
||
|
|
ecall_r <= UInt<1>("h00")
|
||
|
|
wire illegal_r : UInt<1>
|
||
|
|
illegal_r <= UInt<1>("h00")
|
||
|
|
wire mret_r : UInt<1>
|
||
|
|
mret_r <= UInt<1>("h00")
|
||
|
|
wire iccm_repair_state_ns : UInt<1>
|
||
|
|
iccm_repair_state_ns <= UInt<1>("h00")
|
||
|
|
wire rfpc_i0_r : UInt<1>
|
||
|
|
rfpc_i0_r <= UInt<1>("h00")
|
||
|
|
wire tlu_i0_kill_writeb_r : UInt<1>
|
||
|
|
tlu_i0_kill_writeb_r <= UInt<1>("h00")
|
||
|
|
wire lsu_exc_valid_r_d1 : UInt<1>
|
||
|
|
lsu_exc_valid_r_d1 <= UInt<1>("h00")
|
||
|
|
wire lsu_i0_exc_r_raw : UInt<1>
|
||
|
|
lsu_i0_exc_r_raw <= UInt<1>("h00")
|
||
|
|
wire mdseac_locked_f : UInt<1>
|
||
|
|
mdseac_locked_f <= UInt<1>("h00")
|
||
|
|
wire i_cpu_run_req_d1 : UInt<1>
|
||
|
|
i_cpu_run_req_d1 <= UInt<1>("h00")
|
||
|
|
wire cpu_run_ack : UInt<1>
|
||
|
|
cpu_run_ack <= UInt<1>("h00")
|
||
|
|
wire cpu_halt_status : UInt<1>
|
||
|
|
cpu_halt_status <= UInt<1>("h00")
|
||
|
|
wire cpu_halt_ack : UInt<1>
|
||
|
|
cpu_halt_ack <= UInt<1>("h00")
|
||
|
|
wire pmu_fw_tlu_halted : UInt<1>
|
||
|
|
pmu_fw_tlu_halted <= UInt<1>("h00")
|
||
|
|
wire internal_pmu_fw_halt_mode : UInt<1>
|
||
|
|
internal_pmu_fw_halt_mode <= UInt<1>("h00")
|
||
|
|
wire pmu_fw_halt_req_ns : UInt<1>
|
||
|
|
pmu_fw_halt_req_ns <= UInt<1>("h00")
|
||
|
|
wire pmu_fw_halt_req_f : UInt<1>
|
||
|
|
pmu_fw_halt_req_f <= UInt<1>("h00")
|
||
|
|
wire pmu_fw_tlu_halted_f : UInt<1>
|
||
|
|
pmu_fw_tlu_halted_f <= UInt<1>("h00")
|
||
|
|
wire int_timer0_int_hold_f : UInt<1>
|
||
|
|
int_timer0_int_hold_f <= UInt<1>("h00")
|
||
|
|
wire int_timer1_int_hold_f : UInt<1>
|
||
|
|
int_timer1_int_hold_f <= UInt<1>("h00")
|
||
|
|
wire trigger_hit_dmode_r : UInt<1>
|
||
|
|
trigger_hit_dmode_r <= UInt<1>("h00")
|
||
|
|
wire i0_trigger_hit_r : UInt<1>
|
||
|
|
i0_trigger_hit_r <= UInt<1>("h00")
|
||
|
|
wire pause_expired_r : UInt<1>
|
||
|
|
pause_expired_r <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_pmu_fw_halted : UInt<1>
|
||
|
|
dec_tlu_pmu_fw_halted <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_flush_noredir_r_d1 : UInt<1>
|
||
|
|
dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00")
|
||
|
|
wire halt_taken_f : UInt<1>
|
||
|
|
halt_taken_f <= UInt<1>("h00")
|
||
|
|
wire lsu_idle_any_f : UInt<1>
|
||
|
|
lsu_idle_any_f <= UInt<1>("h00")
|
||
|
|
wire ifu_miss_state_idle_f : UInt<1>
|
||
|
|
ifu_miss_state_idle_f <= UInt<1>("h00")
|
||
|
|
wire dbg_tlu_halted_f : UInt<1>
|
||
|
|
dbg_tlu_halted_f <= UInt<1>("h00")
|
||
|
|
wire debug_halt_req_f : UInt<1>
|
||
|
|
debug_halt_req_f <= UInt<1>("h00")
|
||
|
|
wire debug_resume_req_f : UInt<1>
|
||
|
|
debug_resume_req_f <= UInt<1>("h00")
|
||
|
|
wire trigger_hit_dmode_r_d1 : UInt<1>
|
||
|
|
trigger_hit_dmode_r_d1 <= UInt<1>("h00")
|
||
|
|
wire dcsr_single_step_done_f : UInt<1>
|
||
|
|
dcsr_single_step_done_f <= UInt<1>("h00")
|
||
|
|
wire debug_halt_req_d1 : UInt<1>
|
||
|
|
debug_halt_req_d1 <= UInt<1>("h00")
|
||
|
|
wire request_debug_mode_r_d1 : UInt<1>
|
||
|
|
request_debug_mode_r_d1 <= UInt<1>("h00")
|
||
|
|
wire request_debug_mode_done_f : UInt<1>
|
||
|
|
request_debug_mode_done_f <= UInt<1>("h00")
|
||
|
|
wire dcsr_single_step_running_f : UInt<1>
|
||
|
|
dcsr_single_step_running_f <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_flush_pause_r_d1 : UInt<1>
|
||
|
|
dec_tlu_flush_pause_r_d1 <= UInt<1>("h00")
|
||
|
|
wire dbg_halt_req_held : UInt<1>
|
||
|
|
dbg_halt_req_held <= UInt<1>("h00")
|
||
|
|
wire debug_halt_req_ns : UInt<1>
|
||
|
|
debug_halt_req_ns <= UInt<1>("h00")
|
||
|
|
wire internal_dbg_halt_mode : UInt<1>
|
||
|
|
internal_dbg_halt_mode <= UInt<1>("h00")
|
||
|
|
wire core_empty : UInt<1>
|
||
|
|
core_empty <= UInt<1>("h00")
|
||
|
|
wire dbg_halt_req_final : UInt<1>
|
||
|
|
dbg_halt_req_final <= UInt<1>("h00")
|
||
|
|
wire debug_brkpt_status_ns : UInt<1>
|
||
|
|
debug_brkpt_status_ns <= UInt<1>("h00")
|
||
|
|
wire mpc_debug_halt_ack_ns : UInt<1>
|
||
|
|
mpc_debug_halt_ack_ns <= UInt<1>("h00")
|
||
|
|
wire mpc_debug_run_ack_ns : UInt<1>
|
||
|
|
mpc_debug_run_ack_ns <= UInt<1>("h00")
|
||
|
|
wire mpc_halt_state_ns : UInt<1>
|
||
|
|
mpc_halt_state_ns <= UInt<1>("h00")
|
||
|
|
wire mpc_run_state_ns : UInt<1>
|
||
|
|
mpc_run_state_ns <= UInt<1>("h00")
|
||
|
|
wire dbg_halt_state_ns : UInt<1>
|
||
|
|
dbg_halt_state_ns <= UInt<1>("h00")
|
||
|
|
wire dbg_run_state_ns : UInt<1>
|
||
|
|
dbg_run_state_ns <= UInt<1>("h00")
|
||
|
|
wire dbg_halt_state_f : UInt<1>
|
||
|
|
dbg_halt_state_f <= UInt<1>("h00")
|
||
|
|
wire mpc_halt_state_f : UInt<1>
|
||
|
|
mpc_halt_state_f <= UInt<1>("h00")
|
||
|
|
wire nmi_int_detected : UInt<1>
|
||
|
|
nmi_int_detected <= UInt<1>("h00")
|
||
|
|
wire nmi_lsu_load_type : UInt<1>
|
||
|
|
nmi_lsu_load_type <= UInt<1>("h00")
|
||
|
|
wire nmi_lsu_store_type : UInt<1>
|
||
|
|
nmi_lsu_store_type <= UInt<1>("h00")
|
||
|
|
wire reset_delayed : UInt<1>
|
||
|
|
reset_delayed <= UInt<1>("h00")
|
||
|
|
wire debug_mode_status : UInt<1>
|
||
|
|
debug_mode_status <= UInt<1>("h00")
|
||
|
|
wire e5_valid : UInt<1>
|
||
|
|
e5_valid <= UInt<1>("h00")
|
||
|
|
wire ic_perr_r_d1 : UInt<1>
|
||
|
|
ic_perr_r_d1 <= UInt<1>("h00")
|
||
|
|
wire iccm_sbecc_r_d1 : UInt<1>
|
||
|
|
iccm_sbecc_r_d1 <= UInt<1>("h00")
|
||
|
|
wire npc_r : UInt<31>
|
||
|
|
npc_r <= UInt<1>("h00")
|
||
|
|
wire npc_r_d1 : UInt<31>
|
||
|
|
npc_r_d1 <= UInt<1>("h00")
|
||
|
|
wire mie_ns : UInt<6>
|
||
|
|
mie_ns <= UInt<1>("h00")
|
||
|
|
wire mepc : UInt<31>
|
||
|
|
mepc <= UInt<1>("h00")
|
||
|
|
wire mdseac_locked_ns : UInt<1>
|
||
|
|
mdseac_locked_ns <= UInt<1>("h00")
|
||
|
|
wire force_halt : UInt<1>
|
||
|
|
force_halt <= UInt<1>("h00")
|
||
|
|
wire dpc : UInt<31>
|
||
|
|
dpc <= UInt<1>("h00")
|
||
|
|
wire mstatus_mie_ns : UInt<1>
|
||
|
|
mstatus_mie_ns <= UInt<1>("h00")
|
||
|
|
wire dec_csr_wen_r_mod : UInt<1>
|
||
|
|
dec_csr_wen_r_mod <= UInt<1>("h00")
|
||
|
|
wire fw_halt_req : UInt<1>
|
||
|
|
fw_halt_req <= UInt<1>("h00")
|
||
|
|
wire mstatus : UInt<2>
|
||
|
|
mstatus <= UInt<1>("h00")
|
||
|
|
wire dcsr : UInt<16>
|
||
|
|
dcsr <= UInt<1>("h00")
|
||
|
|
wire mtvec : UInt<31>
|
||
|
|
mtvec <= UInt<1>("h00")
|
||
|
|
wire mip : UInt<6>
|
||
|
|
mip <= UInt<1>("h00")
|
||
|
|
wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 271:41]
|
||
|
|
wire dec_tlu_mpc_halted_only_ns : UInt<1>
|
||
|
|
dec_tlu_mpc_halted_only_ns <= UInt<1>("h00")
|
||
|
|
node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 274:39]
|
||
|
|
node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 274:57]
|
||
|
|
dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 274:36]
|
||
|
|
inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:30]
|
||
|
|
int_timers.clock <= clock
|
||
|
|
int_timers.reset <= reset
|
||
|
|
int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:57]
|
||
|
|
int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:57]
|
||
|
|
int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 278:49]
|
||
|
|
int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 279:49]
|
||
|
|
int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 280:49]
|
||
|
|
int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 281:49]
|
||
|
|
int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:57]
|
||
|
|
int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:57]
|
||
|
|
int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:57]
|
||
|
|
int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:57]
|
||
|
|
int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:57]
|
||
|
|
int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:57]
|
||
|
|
int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:49]
|
||
|
|
int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 289:49]
|
||
|
|
int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:47]
|
||
|
|
node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58]
|
||
|
|
node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58]
|
||
|
|
node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58]
|
||
|
|
node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58]
|
||
|
|
node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58]
|
||
|
|
node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58]
|
||
|
|
reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:81]
|
||
|
|
_T_8 <= _T_7 @[lib.scala 37:81]
|
||
|
|
reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58]
|
||
|
|
syncro_ff <= _T_8 @[lib.scala 37:58]
|
||
|
|
node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:67]
|
||
|
|
node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:59]
|
||
|
|
node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:59]
|
||
|
|
node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:59]
|
||
|
|
node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:59]
|
||
|
|
node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:51]
|
||
|
|
node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:51]
|
||
|
|
node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:58]
|
||
|
|
node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:74]
|
||
|
|
inst rvclkhdr of rvclkhdr_55 @[lib.scala 343:22]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr.io.en <= _T_10 @[lib.scala 345:16]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||
|
|
node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:67]
|
||
|
|
node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:88]
|
||
|
|
node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:104]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_56 @[lib.scala 343:22]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr_1.io.en <= _T_13 @[lib.scala 345:16]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||
|
|
node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:30]
|
||
|
|
node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:50]
|
||
|
|
node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:69]
|
||
|
|
node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:89]
|
||
|
|
node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:112]
|
||
|
|
node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:128]
|
||
|
|
node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:146]
|
||
|
|
node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:165]
|
||
|
|
node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:177]
|
||
|
|
node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:192]
|
||
|
|
node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:207]
|
||
|
|
node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:225]
|
||
|
|
node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:49]
|
||
|
|
node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:65]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_57 @[lib.scala 343:22]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr_2.io.en <= _T_25 @[lib.scala 345:16]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||
|
|
node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:53]
|
||
|
|
node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:71]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_58 @[lib.scala 343:22]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr_3.io.en <= _T_27 @[lib.scala 345:16]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||
|
|
reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:80]
|
||
|
|
iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:80]
|
||
|
|
reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89]
|
||
|
|
_T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:89]
|
||
|
|
ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:57]
|
||
|
|
reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:89]
|
||
|
|
_T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:89]
|
||
|
|
iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:57]
|
||
|
|
reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:97]
|
||
|
|
_T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:97]
|
||
|
|
e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:65]
|
||
|
|
reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:81]
|
||
|
|
_T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:81]
|
||
|
|
debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:49]
|
||
|
|
reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:80]
|
||
|
|
lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:80]
|
||
|
|
reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:72]
|
||
|
|
lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:72]
|
||
|
|
reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:80]
|
||
|
|
tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:80]
|
||
|
|
reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:73]
|
||
|
|
_T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:73]
|
||
|
|
io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 329:41]
|
||
|
|
reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:72]
|
||
|
|
internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:72]
|
||
|
|
reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:89]
|
||
|
|
_T_33 <= force_halt @[dec_tlu_ctl.scala 331:89]
|
||
|
|
io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:57]
|
||
|
|
io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:41]
|
||
|
|
reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:88]
|
||
|
|
reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:88]
|
||
|
|
reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88]
|
||
|
|
reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:88]
|
||
|
|
node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:64]
|
||
|
|
reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:49]
|
||
|
|
reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:72]
|
||
|
|
nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:72]
|
||
|
|
reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72]
|
||
|
|
nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:72]
|
||
|
|
reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72]
|
||
|
|
nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:72]
|
||
|
|
reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72]
|
||
|
|
nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:72]
|
||
|
|
node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 345:32]
|
||
|
|
node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 345:96]
|
||
|
|
node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 345:49]
|
||
|
|
node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 347:45]
|
||
|
|
node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 347:43]
|
||
|
|
node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 347:63]
|
||
|
|
node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 347:106]
|
||
|
|
node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 347:104]
|
||
|
|
node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 347:82]
|
||
|
|
node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 347:165]
|
||
|
|
node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 347:146]
|
||
|
|
node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 347:122]
|
||
|
|
nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 347:26]
|
||
|
|
node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 349:48]
|
||
|
|
node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:119]
|
||
|
|
node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 349:117]
|
||
|
|
node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 349:96]
|
||
|
|
node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 349:94]
|
||
|
|
node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:161]
|
||
|
|
node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 349:159]
|
||
|
|
node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 349:136]
|
||
|
|
nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 349:27]
|
||
|
|
node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 350:49]
|
||
|
|
node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 350:121]
|
||
|
|
node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 350:119]
|
||
|
|
node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 350:98]
|
||
|
|
node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 350:96]
|
||
|
|
node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 350:164]
|
||
|
|
node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 350:162]
|
||
|
|
node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 350:138]
|
||
|
|
nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 350:28]
|
||
|
|
node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 357:69]
|
||
|
|
node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 357:67]
|
||
|
|
reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 358:72]
|
||
|
|
mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 358:72]
|
||
|
|
reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 359:72]
|
||
|
|
mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 359:72]
|
||
|
|
reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:89]
|
||
|
|
_T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 360:89]
|
||
|
|
mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 360:57]
|
||
|
|
reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:88]
|
||
|
|
mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 361:88]
|
||
|
|
reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:80]
|
||
|
|
debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 362:80]
|
||
|
|
reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:80]
|
||
|
|
mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 363:80]
|
||
|
|
reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:80]
|
||
|
|
mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 364:80]
|
||
|
|
reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:89]
|
||
|
|
_T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 365:89]
|
||
|
|
dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 365:57]
|
||
|
|
reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:88]
|
||
|
|
dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 366:88]
|
||
|
|
reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:81]
|
||
|
|
_T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 367:81]
|
||
|
|
io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 367:49]
|
||
|
|
node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 371:71]
|
||
|
|
node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 371:69]
|
||
|
|
node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 372:70]
|
||
|
|
node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 372:68]
|
||
|
|
node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 374:48]
|
||
|
|
node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 374:99]
|
||
|
|
node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 374:97]
|
||
|
|
node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 374:80]
|
||
|
|
node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 374:125]
|
||
|
|
node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 374:123]
|
||
|
|
mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 374:27]
|
||
|
|
node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 375:80]
|
||
|
|
node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 375:78]
|
||
|
|
node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 375:46]
|
||
|
|
node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 375:133]
|
||
|
|
node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 375:131]
|
||
|
|
node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 375:103]
|
||
|
|
mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 375:26]
|
||
|
|
node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 377:70]
|
||
|
|
node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 377:96]
|
||
|
|
node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 377:121]
|
||
|
|
node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 377:48]
|
||
|
|
node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 377:153]
|
||
|
|
node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 377:151]
|
||
|
|
dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 377:27]
|
||
|
|
node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 378:46]
|
||
|
|
node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 378:97]
|
||
|
|
node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 378:95]
|
||
|
|
node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 378:67]
|
||
|
|
dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 378:26]
|
||
|
|
node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 381:39]
|
||
|
|
node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 381:57]
|
||
|
|
dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 381:36]
|
||
|
|
node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 384:59]
|
||
|
|
node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 385:53]
|
||
|
|
node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 385:105]
|
||
|
|
node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 385:103]
|
||
|
|
node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 385:77]
|
||
|
|
debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 385:31]
|
||
|
|
node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 388:51]
|
||
|
|
node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 388:78]
|
||
|
|
node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 388:104]
|
||
|
|
mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 388:31]
|
||
|
|
node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 389:59]
|
||
|
|
node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 389:57]
|
||
|
|
node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 389:80]
|
||
|
|
node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 389:78]
|
||
|
|
node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 389:129]
|
||
|
|
node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 389:106]
|
||
|
|
mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 389:30]
|
||
|
|
io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 392:31]
|
||
|
|
io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 393:31]
|
||
|
|
io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 394:31]
|
||
|
|
node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 397:53]
|
||
|
|
node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 397:74]
|
||
|
|
node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 398:48]
|
||
|
|
node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 398:71]
|
||
|
|
node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 398:69]
|
||
|
|
dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 398:28]
|
||
|
|
node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 401:50]
|
||
|
|
node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 401:95]
|
||
|
|
node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 401:93]
|
||
|
|
node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 401:76]
|
||
|
|
node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 401:121]
|
||
|
|
node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 401:119]
|
||
|
|
node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 401:149]
|
||
|
|
node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 401:147]
|
||
|
|
node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 403:32]
|
||
|
|
node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 403:75]
|
||
|
|
node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 403:73]
|
||
|
|
node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 403:117]
|
||
|
|
node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 403:115]
|
||
|
|
node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 403:95]
|
||
|
|
node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 403:52]
|
||
|
|
node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 408:43]
|
||
|
|
node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 408:66]
|
||
|
|
node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 408:64]
|
||
|
|
node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 408:89]
|
||
|
|
node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 408:87]
|
||
|
|
node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 408:99]
|
||
|
|
node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 408:97]
|
||
|
|
node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 408:115]
|
||
|
|
node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 408:113]
|
||
|
|
node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 408:145]
|
||
|
|
node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 408:143]
|
||
|
|
node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 411:56]
|
||
|
|
node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 411:54]
|
||
|
|
node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 411:84]
|
||
|
|
node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 411:82]
|
||
|
|
node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 411:126]
|
||
|
|
node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 411:124]
|
||
|
|
node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 411:146]
|
||
|
|
node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 411:144]
|
||
|
|
node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 411:169]
|
||
|
|
node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 411:167]
|
||
|
|
node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 411:108]
|
||
|
|
node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 415:53]
|
||
|
|
node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 415:70]
|
||
|
|
node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 415:103]
|
||
|
|
node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 415:129]
|
||
|
|
node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 415:127]
|
||
|
|
node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 415:147]
|
||
|
|
node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 415:145]
|
||
|
|
node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 415:168]
|
||
|
|
node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 415:166]
|
||
|
|
node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 415:34]
|
||
|
|
core_empty <= _T_151 @[dec_tlu_ctl.scala 415:20]
|
||
|
|
node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 421:37]
|
||
|
|
node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 421:63]
|
||
|
|
node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 421:81]
|
||
|
|
node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 421:107]
|
||
|
|
node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 421:132]
|
||
|
|
node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 424:111]
|
||
|
|
node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 424:106]
|
||
|
|
node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 424:104]
|
||
|
|
node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 424:83]
|
||
|
|
node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 424:81]
|
||
|
|
node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 424:53]
|
||
|
|
internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 424:32]
|
||
|
|
node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 426:67]
|
||
|
|
node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 426:65]
|
||
|
|
node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 431:48]
|
||
|
|
node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 431:61]
|
||
|
|
node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 431:97]
|
||
|
|
node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 431:95]
|
||
|
|
node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 431:75]
|
||
|
|
node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 432:73]
|
||
|
|
node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 432:71]
|
||
|
|
node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 432:51]
|
||
|
|
debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 432:27]
|
||
|
|
node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 433:49]
|
||
|
|
node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 433:68]
|
||
|
|
node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 435:61]
|
||
|
|
node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 435:59]
|
||
|
|
node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 435:90]
|
||
|
|
node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 435:84]
|
||
|
|
node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 435:104]
|
||
|
|
node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 435:102]
|
||
|
|
node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 437:66]
|
||
|
|
node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 437:60]
|
||
|
|
node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 437:111]
|
||
|
|
node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 437:109]
|
||
|
|
node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 437:79]
|
||
|
|
node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 439:53]
|
||
|
|
node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 442:57]
|
||
|
|
node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 442:112]
|
||
|
|
node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 442:110]
|
||
|
|
node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 442:83]
|
||
|
|
node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 444:64]
|
||
|
|
node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 444:95]
|
||
|
|
node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 444:93]
|
||
|
|
reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 447:81]
|
||
|
|
_T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 447:81]
|
||
|
|
dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 447:49]
|
||
|
|
reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 448:89]
|
||
|
|
_T_186 <= halt_taken @[dec_tlu_ctl.scala 448:89]
|
||
|
|
halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 448:57]
|
||
|
|
reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:89]
|
||
|
|
_T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 449:89]
|
||
|
|
lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 449:57]
|
||
|
|
reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:81]
|
||
|
|
_T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 450:81]
|
||
|
|
ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 450:49]
|
||
|
|
reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:89]
|
||
|
|
_T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 451:89]
|
||
|
|
dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 451:57]
|
||
|
|
reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:81]
|
||
|
|
_T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 452:81]
|
||
|
|
io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 452:49]
|
||
|
|
reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:89]
|
||
|
|
_T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 453:89]
|
||
|
|
debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 453:57]
|
||
|
|
reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:89]
|
||
|
|
_T_192 <= debug_resume_req @[dec_tlu_ctl.scala 454:89]
|
||
|
|
debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 454:57]
|
||
|
|
reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:81]
|
||
|
|
_T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 455:81]
|
||
|
|
trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 455:49]
|
||
|
|
reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:81]
|
||
|
|
_T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 456:81]
|
||
|
|
dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 456:49]
|
||
|
|
reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:89]
|
||
|
|
_T_195 <= debug_halt_req @[dec_tlu_ctl.scala 457:89]
|
||
|
|
debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 457:57]
|
||
|
|
reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:81]
|
||
|
|
dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 458:81]
|
||
|
|
reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:81]
|
||
|
|
dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 459:81]
|
||
|
|
reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:81]
|
||
|
|
_T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 460:81]
|
||
|
|
request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 460:49]
|
||
|
|
reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:73]
|
||
|
|
_T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 461:73]
|
||
|
|
request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 461:41]
|
||
|
|
reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:73]
|
||
|
|
_T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 462:73]
|
||
|
|
dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 462:41]
|
||
|
|
reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:73]
|
||
|
|
_T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 463:73]
|
||
|
|
dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 463:41]
|
||
|
|
reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:81]
|
||
|
|
_T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 464:81]
|
||
|
|
dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 464:49]
|
||
|
|
io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 467:41]
|
||
|
|
io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 468:41]
|
||
|
|
io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 469:41]
|
||
|
|
dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 470:41]
|
||
|
|
node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 473:71]
|
||
|
|
node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 473:58]
|
||
|
|
node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 473:97]
|
||
|
|
node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 473:144]
|
||
|
|
node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 473:124]
|
||
|
|
node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 473:167]
|
||
|
|
io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 473:45]
|
||
|
|
io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 475:33]
|
||
|
|
node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 478:61]
|
||
|
|
node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 478:59]
|
||
|
|
node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 478:82]
|
||
|
|
node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 478:80]
|
||
|
|
io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 478:34]
|
||
|
|
node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 480:28]
|
||
|
|
node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 480:48]
|
||
|
|
node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 480:86]
|
||
|
|
node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 480:101]
|
||
|
|
node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 480:119]
|
||
|
|
node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 480:136]
|
||
|
|
node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 480:160]
|
||
|
|
node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 480:184]
|
||
|
|
node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 480:203]
|
||
|
|
node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 480:70]
|
||
|
|
node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 480:68]
|
||
|
|
node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 480:226]
|
||
|
|
node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 480:224]
|
||
|
|
node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 480:250]
|
||
|
|
node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 480:248]
|
||
|
|
node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 480:270]
|
||
|
|
node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 480:268]
|
||
|
|
node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 480:291]
|
||
|
|
node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 480:289]
|
||
|
|
pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 480:25]
|
||
|
|
node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 482:88]
|
||
|
|
node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 482:82]
|
||
|
|
node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 482:125]
|
||
|
|
node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 482:100]
|
||
|
|
node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 482:155]
|
||
|
|
node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 482:153]
|
||
|
|
io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 482:45]
|
||
|
|
node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 483:93]
|
||
|
|
node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 483:77]
|
||
|
|
io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 483:41]
|
||
|
|
io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 486:29]
|
||
|
|
node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 487:42]
|
||
|
|
io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 487:29]
|
||
|
|
node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 500:48]
|
||
|
|
node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 500:75]
|
||
|
|
node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 500:102]
|
||
|
|
node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 500:129]
|
||
|
|
node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58]
|
||
|
|
node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58]
|
||
|
|
node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58]
|
||
|
|
node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 501:52]
|
||
|
|
node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 501:79]
|
||
|
|
node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 501:106]
|
||
|
|
node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 501:133]
|
||
|
|
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
|
||
|
|
node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58]
|
||
|
|
node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58]
|
||
|
|
node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 502:52]
|
||
|
|
node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 502:79]
|
||
|
|
node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 502:106]
|
||
|
|
node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 502:133]
|
||
|
|
node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58]
|
||
|
|
node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58]
|
||
|
|
node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58]
|
||
|
|
node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 505:45]
|
||
|
|
node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:71]
|
||
|
|
node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 505:62]
|
||
|
|
node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 505:100]
|
||
|
|
node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 505:86]
|
||
|
|
node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 505:133]
|
||
|
|
node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:159]
|
||
|
|
node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 505:150]
|
||
|
|
node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 505:188]
|
||
|
|
node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 505:174]
|
||
|
|
node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 505:222]
|
||
|
|
node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:248]
|
||
|
|
node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 505:239]
|
||
|
|
node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 505:277]
|
||
|
|
node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 505:263]
|
||
|
|
node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 505:311]
|
||
|
|
node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:337]
|
||
|
|
node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 505:328]
|
||
|
|
node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 505:366]
|
||
|
|
node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 505:352]
|
||
|
|
node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58]
|
||
|
|
node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58]
|
||
|
|
node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58]
|
||
|
|
node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 508:57]
|
||
|
|
node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 508:72]
|
||
|
|
node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 508:137]
|
||
|
|
node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 508:98]
|
||
|
|
node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 508:38]
|
||
|
|
node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 511:51]
|
||
|
|
node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 511:66]
|
||
|
|
node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 511:35]
|
||
|
|
node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 516:84]
|
||
|
|
node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 516:53]
|
||
|
|
node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 516:90]
|
||
|
|
node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 516:119]
|
||
|
|
node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 516:146]
|
||
|
|
node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 518:58]
|
||
|
|
node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 518:23]
|
||
|
|
node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 518:84]
|
||
|
|
node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 521:53]
|
||
|
|
node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 521:73]
|
||
|
|
node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 521:60]
|
||
|
|
node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 521:103]
|
||
|
|
node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 521:89]
|
||
|
|
node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 521:57]
|
||
|
|
node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 521:121]
|
||
|
|
node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 521:141]
|
||
|
|
node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 521:128]
|
||
|
|
node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 521:171]
|
||
|
|
node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 521:157]
|
||
|
|
node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 521:125]
|
||
|
|
node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 521:189]
|
||
|
|
node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 521:209]
|
||
|
|
node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 521:196]
|
||
|
|
node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 521:239]
|
||
|
|
node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 521:225]
|
||
|
|
node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 521:193]
|
||
|
|
node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 521:257]
|
||
|
|
node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 521:277]
|
||
|
|
node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 521:264]
|
||
|
|
node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 521:307]
|
||
|
|
node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 521:293]
|
||
|
|
node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 521:261]
|
||
|
|
node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58]
|
||
|
|
node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58]
|
||
|
|
node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58]
|
||
|
|
node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 524:57]
|
||
|
|
i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 526:25]
|
||
|
|
node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 530:44]
|
||
|
|
node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 530:75]
|
||
|
|
node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 530:61]
|
||
|
|
node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 530:104]
|
||
|
|
node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 530:135]
|
||
|
|
node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 530:121]
|
||
|
|
node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 530:164]
|
||
|
|
node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 530:195]
|
||
|
|
node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 530:181]
|
||
|
|
node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 530:224]
|
||
|
|
node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 530:255]
|
||
|
|
node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 530:241]
|
||
|
|
node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58]
|
||
|
|
node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58]
|
||
|
|
node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58]
|
||
|
|
node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 533:56]
|
||
|
|
node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 536:57]
|
||
|
|
node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 536:75]
|
||
|
|
node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 538:45]
|
||
|
|
trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 538:24]
|
||
|
|
node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 540:55]
|
||
|
|
node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 540:53]
|
||
|
|
node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 567:62]
|
||
|
|
node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 567:60]
|
||
|
|
node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 567:87]
|
||
|
|
node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 567:85]
|
||
|
|
node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 568:60]
|
||
|
|
node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 568:58]
|
||
|
|
node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 568:83]
|
||
|
|
node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 568:107]
|
||
|
|
node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 568:105]
|
||
|
|
reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 570:80]
|
||
|
|
i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 570:80]
|
||
|
|
reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 571:80]
|
||
|
|
i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 571:80]
|
||
|
|
reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:81]
|
||
|
|
_T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 572:81]
|
||
|
|
io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 572:49]
|
||
|
|
reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:81]
|
||
|
|
_T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 573:81]
|
||
|
|
io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 573:49]
|
||
|
|
reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:81]
|
||
|
|
_T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 574:81]
|
||
|
|
io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 574:49]
|
||
|
|
reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:68]
|
||
|
|
internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 575:68]
|
||
|
|
reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:73]
|
||
|
|
_T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 576:73]
|
||
|
|
pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 576:41]
|
||
|
|
reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:73]
|
||
|
|
_T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 577:73]
|
||
|
|
pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 577:41]
|
||
|
|
reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 578:73]
|
||
|
|
_T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 578:73]
|
||
|
|
int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 578:41]
|
||
|
|
reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 579:73]
|
||
|
|
_T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 579:73]
|
||
|
|
int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 579:41]
|
||
|
|
node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 583:52]
|
||
|
|
node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 583:50]
|
||
|
|
node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 584:48]
|
||
|
|
node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 585:72]
|
||
|
|
node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 585:70]
|
||
|
|
node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 585:49]
|
||
|
|
node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 585:95]
|
||
|
|
node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 585:93]
|
||
|
|
pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 585:23]
|
||
|
|
node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 586:85]
|
||
|
|
node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 586:83]
|
||
|
|
node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 586:105]
|
||
|
|
node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 586:103]
|
||
|
|
node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 586:52]
|
||
|
|
internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 586:30]
|
||
|
|
node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 589:45]
|
||
|
|
node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 589:58]
|
||
|
|
node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 589:73]
|
||
|
|
node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 589:71]
|
||
|
|
node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 589:121]
|
||
|
|
node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 589:119]
|
||
|
|
node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 589:96]
|
||
|
|
node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 589:143]
|
||
|
|
node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 589:141]
|
||
|
|
pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 589:22]
|
||
|
|
node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 591:38]
|
||
|
|
cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 591:17]
|
||
|
|
node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:46]
|
||
|
|
node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 592:44]
|
||
|
|
node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:91]
|
||
|
|
node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 592:89]
|
||
|
|
node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 592:111]
|
||
|
|
node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 592:109]
|
||
|
|
node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 592:65]
|
||
|
|
cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 592:20]
|
||
|
|
node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 593:41]
|
||
|
|
node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 593:88]
|
||
|
|
node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 593:68]
|
||
|
|
cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 593:16]
|
||
|
|
io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 595:27]
|
||
|
|
node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 598:66]
|
||
|
|
node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 598:84]
|
||
|
|
node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 598:101]
|
||
|
|
node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 598:125]
|
||
|
|
node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 598:172]
|
||
|
|
node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 598:149]
|
||
|
|
node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 598:191]
|
||
|
|
node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 598:216]
|
||
|
|
node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 598:214]
|
||
|
|
node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 598:45]
|
||
|
|
i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 598:21]
|
||
|
|
reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 604:89]
|
||
|
|
_T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 604:89]
|
||
|
|
mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 604:57]
|
||
|
|
reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 605:72]
|
||
|
|
lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 605:72]
|
||
|
|
node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 607:57]
|
||
|
|
node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 607:55]
|
||
|
|
lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 608:21]
|
||
|
|
node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 609:40]
|
||
|
|
node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 609:64]
|
||
|
|
node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 609:62]
|
||
|
|
node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 609:84]
|
||
|
|
node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 609:82]
|
||
|
|
reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 611:74]
|
||
|
|
_T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 611:74]
|
||
|
|
lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 611:41]
|
||
|
|
reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 612:73]
|
||
|
|
lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 612:73]
|
||
|
|
node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 613:40]
|
||
|
|
node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 613:38]
|
||
|
|
node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 614:38]
|
||
|
|
node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 615:38]
|
||
|
|
node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 619:49]
|
||
|
|
node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 619:47]
|
||
|
|
node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 619:70]
|
||
|
|
node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 619:105]
|
||
|
|
node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 619:67]
|
||
|
|
node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 622:52]
|
||
|
|
node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 622:50]
|
||
|
|
node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 622:65]
|
||
|
|
node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 622:63]
|
||
|
|
node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 622:82]
|
||
|
|
node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 622:79]
|
||
|
|
node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 622:96]
|
||
|
|
node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 622:94]
|
||
|
|
node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 622:121]
|
||
|
|
node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 622:119]
|
||
|
|
node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 622:148]
|
||
|
|
node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 622:146]
|
||
|
|
node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 625:38]
|
||
|
|
node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 625:53]
|
||
|
|
node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 625:79]
|
||
|
|
node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 625:66]
|
||
|
|
node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 625:104]
|
||
|
|
tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 625:25]
|
||
|
|
io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 626:37]
|
||
|
|
node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 631:44]
|
||
|
|
node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 631:42]
|
||
|
|
node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 631:98]
|
||
|
|
node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 631:66]
|
||
|
|
node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 631:154]
|
||
|
|
node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 631:175]
|
||
|
|
node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 631:173]
|
||
|
|
node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 631:137]
|
||
|
|
node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 631:199]
|
||
|
|
node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 631:196]
|
||
|
|
node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 631:220]
|
||
|
|
node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 631:217]
|
||
|
|
rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 631:14]
|
||
|
|
node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 634:70]
|
||
|
|
node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 634:68]
|
||
|
|
node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 634:44]
|
||
|
|
iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 634:25]
|
||
|
|
node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 640:52]
|
||
|
|
node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 640:88]
|
||
|
|
node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 640:98]
|
||
|
|
node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 640:107]
|
||
|
|
node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 640:120]
|
||
|
|
node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 640:176]
|
||
|
|
node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 640:153]
|
||
|
|
node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 640:132]
|
||
|
|
node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 640:77]
|
||
|
|
node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 640:75]
|
||
|
|
node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 643:59]
|
||
|
|
node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 643:85]
|
||
|
|
node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 643:83]
|
||
|
|
node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 644:71]
|
||
|
|
node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 644:97]
|
||
|
|
node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 644:95]
|
||
|
|
node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 645:55]
|
||
|
|
node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 645:81]
|
||
|
|
node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 645:79]
|
||
|
|
node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 645:106]
|
||
|
|
node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 645:135]
|
||
|
|
node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 645:133]
|
||
|
|
node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 645:103]
|
||
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 648:65]
|
||
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 649:57]
|
||
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 650:57]
|
||
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 651:57]
|
||
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 652:65]
|
||
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 653:65]
|
||
|
|
node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 656:51]
|
||
|
|
node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 656:64]
|
||
|
|
node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 656:90]
|
||
|
|
node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 656:88]
|
||
|
|
node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 656:115]
|
||
|
|
node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 656:110]
|
||
|
|
node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 656:108]
|
||
|
|
node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 656:132]
|
||
|
|
node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 656:130]
|
||
|
|
ebreak_r <= _T_471 @[dec_tlu_ctl.scala 656:13]
|
||
|
|
node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 657:51]
|
||
|
|
node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 657:64]
|
||
|
|
node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:90]
|
||
|
|
node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 657:88]
|
||
|
|
node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 657:110]
|
||
|
|
node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 657:108]
|
||
|
|
ecall_r <= _T_477 @[dec_tlu_ctl.scala 657:13]
|
||
|
|
node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 658:17]
|
||
|
|
node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 658:46]
|
||
|
|
node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 658:72]
|
||
|
|
node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 658:70]
|
||
|
|
node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 658:92]
|
||
|
|
node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 658:90]
|
||
|
|
illegal_r <= _T_483 @[dec_tlu_ctl.scala 658:13]
|
||
|
|
node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 659:51]
|
||
|
|
node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:64]
|
||
|
|
node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:90]
|
||
|
|
node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 659:88]
|
||
|
|
node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:110]
|
||
|
|
node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 659:108]
|
||
|
|
mret_r <= _T_489 @[dec_tlu_ctl.scala 659:13]
|
||
|
|
node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 661:50]
|
||
|
|
node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 661:76]
|
||
|
|
node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 661:74]
|
||
|
|
node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 661:97]
|
||
|
|
node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 661:95]
|
||
|
|
fence_i_r <= _T_494 @[dec_tlu_ctl.scala 661:17]
|
||
|
|
node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 662:53]
|
||
|
|
node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 662:51]
|
||
|
|
node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 662:75]
|
||
|
|
node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 662:101]
|
||
|
|
node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 662:72]
|
||
|
|
node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 662:131]
|
||
|
|
node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 662:129]
|
||
|
|
ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 662:17]
|
||
|
|
node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 663:61]
|
||
|
|
node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 663:59]
|
||
|
|
node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 663:83]
|
||
|
|
node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 663:109]
|
||
|
|
node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 663:80]
|
||
|
|
node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 663:139]
|
||
|
|
node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 663:137]
|
||
|
|
iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 663:17]
|
||
|
|
node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 664:49]
|
||
|
|
inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 664:20]
|
||
|
|
node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 665:35]
|
||
|
|
node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 665:33]
|
||
|
|
node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 665:48]
|
||
|
|
node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 665:46]
|
||
|
|
inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 665:15]
|
||
|
|
node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 668:64]
|
||
|
|
node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 668:77]
|
||
|
|
node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 668:103]
|
||
|
|
node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 668:101]
|
||
|
|
node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 668:127]
|
||
|
|
node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 668:121]
|
||
|
|
node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 668:144]
|
||
|
|
node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 668:142]
|
||
|
|
ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 668:27]
|
||
|
|
reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 670:64]
|
||
|
|
_T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 670:64]
|
||
|
|
ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 670:34]
|
||
|
|
io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 671:39]
|
||
|
|
node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 684:41]
|
||
|
|
node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 684:51]
|
||
|
|
node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 684:63]
|
||
|
|
node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 684:79]
|
||
|
|
node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 684:77]
|
||
|
|
node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 684:92]
|
||
|
|
node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 684:90]
|
||
|
|
node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 693:33]
|
||
|
|
node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 693:31]
|
||
|
|
node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 693:44]
|
||
|
|
node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 694:27]
|
||
|
|
node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 694:25]
|
||
|
|
node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 694:38]
|
||
|
|
node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 695:26]
|
||
|
|
node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 695:24]
|
||
|
|
node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 695:37]
|
||
|
|
node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 696:32]
|
||
|
|
node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 696:30]
|
||
|
|
node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 696:43]
|
||
|
|
node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 697:32]
|
||
|
|
node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 697:30]
|
||
|
|
node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 697:43]
|
||
|
|
node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 698:24]
|
||
|
|
node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 698:22]
|
||
|
|
node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 698:35]
|
||
|
|
node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 699:22]
|
||
|
|
node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 699:20]
|
||
|
|
node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 699:33]
|
||
|
|
node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 700:21]
|
||
|
|
node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 700:19]
|
||
|
|
node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 700:32]
|
||
|
|
node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 701:24]
|
||
|
|
node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 701:22]
|
||
|
|
node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 701:35]
|
||
|
|
node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 702:20]
|
||
|
|
node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 702:42]
|
||
|
|
node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 702:40]
|
||
|
|
node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 702:53]
|
||
|
|
node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 703:25]
|
||
|
|
node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 703:23]
|
||
|
|
node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 703:41]
|
||
|
|
node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 703:39]
|
||
|
|
node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 703:52]
|
||
|
|
node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 704:26]
|
||
|
|
node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 704:24]
|
||
|
|
node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 704:42]
|
||
|
|
node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 704:40]
|
||
|
|
node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 704:53]
|
||
|
|
node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 705:23]
|
||
|
|
node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 705:40]
|
||
|
|
node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 705:38]
|
||
|
|
node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 705:51]
|
||
|
|
node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 706:24]
|
||
|
|
node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 706:41]
|
||
|
|
node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 706:39]
|
||
|
|
node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 706:52]
|
||
|
|
node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_581 = mux(_T_540, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_582 = mux(_T_543, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_583 = mux(_T_546, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_584 = mux(_T_549, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_585 = mux(_T_552, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_586 = mux(_T_555, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_587 = mux(_T_559, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_588 = mux(_T_564, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_589 = mux(_T_569, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_590 = mux(_T_573, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_591 = mux(_T_577, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_592 = or(_T_578, _T_579) @[Mux.scala 27:72]
|
||
|
|
node _T_593 = or(_T_592, _T_580) @[Mux.scala 27:72]
|
||
|
|
node _T_594 = or(_T_593, _T_581) @[Mux.scala 27:72]
|
||
|
|
node _T_595 = or(_T_594, _T_582) @[Mux.scala 27:72]
|
||
|
|
node _T_596 = or(_T_595, _T_583) @[Mux.scala 27:72]
|
||
|
|
node _T_597 = or(_T_596, _T_584) @[Mux.scala 27:72]
|
||
|
|
node _T_598 = or(_T_597, _T_585) @[Mux.scala 27:72]
|
||
|
|
node _T_599 = or(_T_598, _T_586) @[Mux.scala 27:72]
|
||
|
|
node _T_600 = or(_T_599, _T_587) @[Mux.scala 27:72]
|
||
|
|
node _T_601 = or(_T_600, _T_588) @[Mux.scala 27:72]
|
||
|
|
node _T_602 = or(_T_601, _T_589) @[Mux.scala 27:72]
|
||
|
|
node _T_603 = or(_T_602, _T_590) @[Mux.scala 27:72]
|
||
|
|
node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72]
|
||
|
|
wire exc_cause_r : UInt<5> @[Mux.scala 27:72]
|
||
|
|
exc_cause_r <= _T_604 @[Mux.scala 27:72]
|
||
|
|
node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 717:24]
|
||
|
|
node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 717:49]
|
||
|
|
node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 717:71]
|
||
|
|
node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 717:66]
|
||
|
|
node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 717:92]
|
||
|
|
node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 717:84]
|
||
|
|
mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 717:20]
|
||
|
|
node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 718:23]
|
||
|
|
node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 718:48]
|
||
|
|
node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 718:70]
|
||
|
|
node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 718:65]
|
||
|
|
node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 718:91]
|
||
|
|
node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 718:83]
|
||
|
|
node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 718:104]
|
||
|
|
node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 718:102]
|
||
|
|
ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 718:20]
|
||
|
|
node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:23]
|
||
|
|
node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:48]
|
||
|
|
node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 719:70]
|
||
|
|
node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 719:65]
|
||
|
|
node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 719:91]
|
||
|
|
node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 719:83]
|
||
|
|
ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 719:20]
|
||
|
|
node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 720:23]
|
||
|
|
node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 720:48]
|
||
|
|
node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 720:70]
|
||
|
|
node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 720:65]
|
||
|
|
node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 720:91]
|
||
|
|
node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 720:83]
|
||
|
|
soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 720:20]
|
||
|
|
node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 721:23]
|
||
|
|
node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 721:48]
|
||
|
|
node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 721:70]
|
||
|
|
node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 721:65]
|
||
|
|
node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 721:91]
|
||
|
|
node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 721:83]
|
||
|
|
timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 721:20]
|
||
|
|
node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 724:57]
|
||
|
|
node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 724:49]
|
||
|
|
node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 725:34]
|
||
|
|
node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 725:47]
|
||
|
|
node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 726:57]
|
||
|
|
node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 726:49]
|
||
|
|
node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 727:34]
|
||
|
|
node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 727:47]
|
||
|
|
node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 731:52]
|
||
|
|
node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 731:74]
|
||
|
|
node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 731:98]
|
||
|
|
node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 733:72]
|
||
|
|
node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 733:49]
|
||
|
|
node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 733:121]
|
||
|
|
node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 733:147]
|
||
|
|
node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 733:145]
|
||
|
|
node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 733:168]
|
||
|
|
node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 733:166]
|
||
|
|
node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 733:190]
|
||
|
|
node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 733:188]
|
||
|
|
node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 733:94]
|
||
|
|
int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 733:24]
|
||
|
|
node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 734:72]
|
||
|
|
node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 734:49]
|
||
|
|
node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 734:121]
|
||
|
|
node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 734:147]
|
||
|
|
node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 734:145]
|
||
|
|
node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 734:168]
|
||
|
|
node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 734:166]
|
||
|
|
node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 734:190]
|
||
|
|
node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 734:188]
|
||
|
|
node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 734:94]
|
||
|
|
int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 734:24]
|
||
|
|
node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 736:59]
|
||
|
|
node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 736:57]
|
||
|
|
internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 736:29]
|
||
|
|
node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 738:55]
|
||
|
|
node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 738:81]
|
||
|
|
node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 738:52]
|
||
|
|
node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 738:107]
|
||
|
|
node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 738:135]
|
||
|
|
node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 738:155]
|
||
|
|
node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 738:166]
|
||
|
|
node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 738:191]
|
||
|
|
node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 738:214]
|
||
|
|
node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 738:238]
|
||
|
|
node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 738:247]
|
||
|
|
reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 742:62]
|
||
|
|
_T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 742:62]
|
||
|
|
take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 742:30]
|
||
|
|
reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 743:62]
|
||
|
|
_T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 743:62]
|
||
|
|
take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 743:30]
|
||
|
|
reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 744:62]
|
||
|
|
_T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 744:62]
|
||
|
|
take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 744:30]
|
||
|
|
reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 745:66]
|
||
|
|
_T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 745:66]
|
||
|
|
ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 745:34]
|
||
|
|
node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 746:47]
|
||
|
|
node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 746:45]
|
||
|
|
take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 746:28]
|
||
|
|
node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 748:46]
|
||
|
|
node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 748:70]
|
||
|
|
node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 748:94]
|
||
|
|
ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 748:24]
|
||
|
|
node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 749:67]
|
||
|
|
node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 749:49]
|
||
|
|
node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 749:47]
|
||
|
|
take_ext_int <= _T_686 @[dec_tlu_ctl.scala 749:22]
|
||
|
|
node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 750:49]
|
||
|
|
fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 750:26]
|
||
|
|
ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 751:41]
|
||
|
|
node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 764:35]
|
||
|
|
node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 764:33]
|
||
|
|
node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 764:52]
|
||
|
|
node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 764:50]
|
||
|
|
take_ce_int <= _T_691 @[dec_tlu_ctl.scala 764:17]
|
||
|
|
node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 765:38]
|
||
|
|
node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 765:36]
|
||
|
|
node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 765:55]
|
||
|
|
node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 765:53]
|
||
|
|
node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 765:71]
|
||
|
|
node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 765:69]
|
||
|
|
take_soft_int <= _T_697 @[dec_tlu_ctl.scala 765:18]
|
||
|
|
node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 766:40]
|
||
|
|
node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 766:38]
|
||
|
|
node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:58]
|
||
|
|
node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 766:56]
|
||
|
|
node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 766:75]
|
||
|
|
node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 766:73]
|
||
|
|
node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 766:91]
|
||
|
|
node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 766:89]
|
||
|
|
take_timer_int <= _T_705 @[dec_tlu_ctl.scala 766:19]
|
||
|
|
node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 767:49]
|
||
|
|
node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 767:74]
|
||
|
|
node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 767:102]
|
||
|
|
node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 767:100]
|
||
|
|
node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 767:129]
|
||
|
|
node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 767:127]
|
||
|
|
node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 767:148]
|
||
|
|
node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 767:146]
|
||
|
|
node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 767:166]
|
||
|
|
node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 767:164]
|
||
|
|
node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 767:183]
|
||
|
|
node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 767:181]
|
||
|
|
node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 767:199]
|
||
|
|
node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 767:197]
|
||
|
|
take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 767:24]
|
||
|
|
node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 768:49]
|
||
|
|
node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 768:74]
|
||
|
|
node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 768:102]
|
||
|
|
node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 768:100]
|
||
|
|
node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 768:152]
|
||
|
|
node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 768:129]
|
||
|
|
node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 768:127]
|
||
|
|
node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 768:179]
|
||
|
|
node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 768:177]
|
||
|
|
node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 768:198]
|
||
|
|
node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 768:196]
|
||
|
|
node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 768:216]
|
||
|
|
node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 768:214]
|
||
|
|
node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 768:233]
|
||
|
|
node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 768:231]
|
||
|
|
node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 768:249]
|
||
|
|
node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 768:247]
|
||
|
|
take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 768:24]
|
||
|
|
node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 769:32]
|
||
|
|
take_reset <= _T_737 @[dec_tlu_ctl.scala 769:15]
|
||
|
|
node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 770:35]
|
||
|
|
node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 770:33]
|
||
|
|
node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 770:65]
|
||
|
|
node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 770:125]
|
||
|
|
node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 770:119]
|
||
|
|
node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 770:141]
|
||
|
|
node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 770:139]
|
||
|
|
node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 770:166]
|
||
|
|
node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 770:164]
|
||
|
|
node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 770:89]
|
||
|
|
node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 770:62]
|
||
|
|
node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 770:195]
|
||
|
|
node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 770:193]
|
||
|
|
node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 770:218]
|
||
|
|
node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 770:216]
|
||
|
|
node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 770:228]
|
||
|
|
node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 770:226]
|
||
|
|
node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 770:242]
|
||
|
|
node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 770:240]
|
||
|
|
node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 770:269]
|
||
|
|
node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 770:332]
|
||
|
|
node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 770:313]
|
||
|
|
node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 770:288]
|
||
|
|
node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 770:266]
|
||
|
|
take_nmi <= _T_761 @[dec_tlu_ctl.scala 770:13]
|
||
|
|
node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 773:38]
|
||
|
|
node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 773:55]
|
||
|
|
node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 773:71]
|
||
|
|
node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 773:82]
|
||
|
|
node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 773:96]
|
||
|
|
node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 773:118]
|
||
|
|
interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 773:22]
|
||
|
|
node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 778:34]
|
||
|
|
node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58]
|
||
|
|
node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 778:51]
|
||
|
|
node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 778:51]
|
||
|
|
node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 779:38]
|
||
|
|
node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 779:67]
|
||
|
|
node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 779:71]
|
||
|
|
node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 779:104]
|
||
|
|
node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 779:61]
|
||
|
|
node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 779:28]
|
||
|
|
node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 780:36]
|
||
|
|
node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 780:48]
|
||
|
|
node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 780:96]
|
||
|
|
node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 780:94]
|
||
|
|
node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 780:74]
|
||
|
|
node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 780:131]
|
||
|
|
node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 780:129]
|
||
|
|
node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 780:116]
|
||
|
|
node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 781:43]
|
||
|
|
node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 781:66]
|
||
|
|
node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 782:65]
|
||
|
|
node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 782:47]
|
||
|
|
node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 782:45]
|
||
|
|
node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 783:49]
|
||
|
|
node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 783:61]
|
||
|
|
node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 783:79]
|
||
|
|
node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 783:91]
|
||
|
|
node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 783:108]
|
||
|
|
node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 783:135]
|
||
|
|
node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 783:157]
|
||
|
|
node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 783:175]
|
||
|
|
node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 783:201]
|
||
|
|
synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 783:25]
|
||
|
|
node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 784:43]
|
||
|
|
node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 784:52]
|
||
|
|
node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 784:74]
|
||
|
|
node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 784:86]
|
||
|
|
node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 784:99]
|
||
|
|
tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 784:22]
|
||
|
|
node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 786:42]
|
||
|
|
node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 787:72]
|
||
|
|
node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 788:66]
|
||
|
|
node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 788:84]
|
||
|
|
node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 788:73]
|
||
|
|
node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 789:66]
|
||
|
|
node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 789:84]
|
||
|
|
node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 789:73]
|
||
|
|
node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 789:114]
|
||
|
|
node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 789:91]
|
||
|
|
node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 789:132]
|
||
|
|
node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 789:121]
|
||
|
|
node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 790:75]
|
||
|
|
node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 790:96]
|
||
|
|
node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 790:82]
|
||
|
|
node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 791:80]
|
||
|
|
node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 791:120]
|
||
|
|
node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 791:118]
|
||
|
|
node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 791:98]
|
||
|
|
node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 791:145]
|
||
|
|
node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 791:143]
|
||
|
|
node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 791:166]
|
||
|
|
node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 791:164]
|
||
|
|
node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 791:181]
|
||
|
|
node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 791:205]
|
||
|
|
node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 792:58]
|
||
|
|
node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 792:68]
|
||
|
|
node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 792:78]
|
||
|
|
node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 793:58]
|
||
|
|
node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 793:68]
|
||
|
|
node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 793:90]
|
||
|
|
node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 794:58]
|
||
|
|
node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 794:68]
|
||
|
|
node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 794:86]
|
||
|
|
node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_841 = mux(_T_817, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_842 = mux(_T_826, _T_828, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_843 = mux(_T_831, mepc, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_844 = mux(_T_834, dpc, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_845 = mux(_T_837, npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_846 = or(_T_838, _T_839) @[Mux.scala 27:72]
|
||
|
|
node _T_847 = or(_T_846, _T_840) @[Mux.scala 27:72]
|
||
|
|
node _T_848 = or(_T_847, _T_841) @[Mux.scala 27:72]
|
||
|
|
node _T_849 = or(_T_848, _T_842) @[Mux.scala 27:72]
|
||
|
|
node _T_850 = or(_T_849, _T_843) @[Mux.scala 27:72]
|
||
|
|
node _T_851 = or(_T_850, _T_844) @[Mux.scala 27:72]
|
||
|
|
node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72]
|
||
|
|
wire _T_853 : UInt<31> @[Mux.scala 27:72]
|
||
|
|
_T_853 <= _T_852 @[Mux.scala 27:72]
|
||
|
|
node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 786:30]
|
||
|
|
reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 797:64]
|
||
|
|
tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 797:64]
|
||
|
|
io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 799:41]
|
||
|
|
io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 801:49]
|
||
|
|
io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 802:49]
|
||
|
|
node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 805:45]
|
||
|
|
node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 805:68]
|
||
|
|
node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 805:110]
|
||
|
|
node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 805:108]
|
||
|
|
node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 805:88]
|
||
|
|
reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 807:90]
|
||
|
|
_T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 807:90]
|
||
|
|
interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 807:57]
|
||
|
|
reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 808:89]
|
||
|
|
i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 808:89]
|
||
|
|
reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:90]
|
||
|
|
_T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 809:90]
|
||
|
|
exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 809:57]
|
||
|
|
reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:89]
|
||
|
|
exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 810:89]
|
||
|
|
node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 811:119]
|
||
|
|
node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 811:117]
|
||
|
|
reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:97]
|
||
|
|
i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 811:97]
|
||
|
|
reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 812:89]
|
||
|
|
trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 812:89]
|
||
|
|
reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 813:98]
|
||
|
|
_T_862 <= take_nmi @[dec_tlu_ctl.scala 813:98]
|
||
|
|
take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 813:65]
|
||
|
|
reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 814:90]
|
||
|
|
_T_863 <= pause_expired_r @[dec_tlu_ctl.scala 814:90]
|
||
|
|
pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 814:57]
|
||
|
|
inst csr of csr_tlu @[dec_tlu_ctl.scala 816:15]
|
||
|
|
csr.clock <= clock
|
||
|
|
csr.reset <= reset
|
||
|
|
csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 817:44]
|
||
|
|
csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 818:44]
|
||
|
|
csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 819:44]
|
||
|
|
csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 820:44]
|
||
|
|
csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 821:44]
|
||
|
|
csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 822:44]
|
||
|
|
csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 823:44]
|
||
|
|
csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 824:44]
|
||
|
|
csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 825:44]
|
||
|
|
csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 826:44]
|
||
|
|
csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 827:44]
|
||
|
|
csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 828:44]
|
||
|
|
csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 829:44]
|
||
|
|
csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 830:44]
|
||
|
|
csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 831:44]
|
||
|
|
csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 832:44]
|
||
|
|
csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 833:44]
|
||
|
|
csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 834:44]
|
||
|
|
csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 835:44]
|
||
|
|
csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 836:44]
|
||
|
|
csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 837:44]
|
||
|
|
csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 838:44]
|
||
|
|
csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 839:44]
|
||
|
|
csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 840:44]
|
||
|
|
csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 841:44]
|
||
|
|
csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 842:44]
|
||
|
|
csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 843:44]
|
||
|
|
csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 844:44]
|
||
|
|
csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 845:44]
|
||
|
|
csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 846:44]
|
||
|
|
csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 847:44]
|
||
|
|
csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 848:44]
|
||
|
|
csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 849:44]
|
||
|
|
csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 850:44]
|
||
|
|
csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 851:44]
|
||
|
|
csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 852:44]
|
||
|
|
csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 853:44]
|
||
|
|
csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 854:44]
|
||
|
|
csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 855:44]
|
||
|
|
csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 856:44]
|
||
|
|
csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 857:44]
|
||
|
|
csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 858:44]
|
||
|
|
csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 859:44]
|
||
|
|
csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 860:44]
|
||
|
|
csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 861:44]
|
||
|
|
csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 862:44]
|
||
|
|
csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 863:44]
|
||
|
|
csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 864:44]
|
||
|
|
csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 865:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 866:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 866:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 866:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 866:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 866:44]
|
||
|
|
csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 866:44]
|
||
|
|
csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 867:44]
|
||
|
|
csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 868:44]
|
||
|
|
csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 869:44]
|
||
|
|
csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 870:44]
|
||
|
|
csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 871:44]
|
||
|
|
csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 872:44]
|
||
|
|
csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 873:44]
|
||
|
|
io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 874:52]
|
||
|
|
io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 875:52]
|
||
|
|
io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 876:52]
|
||
|
|
io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 877:44]
|
||
|
|
io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 878:44]
|
||
|
|
io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 879:44]
|
||
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 880:52]
|
||
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 880:52]
|
||
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 880:52]
|
||
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 880:52]
|
||
|
|
io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 881:40]
|
||
|
|
io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 882:40]
|
||
|
|
io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 883:40]
|
||
|
|
io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 884:40]
|
||
|
|
io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 885:40]
|
||
|
|
io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 886:40]
|
||
|
|
io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 887:40]
|
||
|
|
io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 888:40]
|
||
|
|
io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 889:40]
|
||
|
|
io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 890:40]
|
||
|
|
io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 891:40]
|
||
|
|
io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 892:40]
|
||
|
|
io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 893:40]
|
||
|
|
io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 894:40]
|
||
|
|
io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 895:40]
|
||
|
|
io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 896:40]
|
||
|
|
io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 897:40]
|
||
|
|
io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 898:40]
|
||
|
|
io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 899:48]
|
||
|
|
io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 900:52]
|
||
|
|
io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 901:47]
|
||
|
|
io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 902:52]
|
||
|
|
io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 903:48]
|
||
|
|
io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 904:52]
|
||
|
|
io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 905:48]
|
||
|
|
csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 906:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 907:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 907:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 907:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 907:44]
|
||
|
|
csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 907:44]
|
||
|
|
csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 907:44]
|
||
|
|
csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 908:44]
|
||
|
|
csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 909:44]
|
||
|
|
csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 910:44]
|
||
|
|
csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 911:44]
|
||
|
|
csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 912:44]
|
||
|
|
csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 913:44]
|
||
|
|
csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 914:44]
|
||
|
|
csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 917:39]
|
||
|
|
csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 918:39]
|
||
|
|
csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 919:39]
|
||
|
|
csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 920:39]
|
||
|
|
csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 921:39]
|
||
|
|
csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 922:39]
|
||
|
|
csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 923:39]
|
||
|
|
csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 924:39]
|
||
|
|
csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 925:39]
|
||
|
|
csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 926:39]
|
||
|
|
csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 927:39]
|
||
|
|
csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 928:39]
|
||
|
|
csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 929:39]
|
||
|
|
csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 930:39]
|
||
|
|
csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 931:39]
|
||
|
|
csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 932:39]
|
||
|
|
csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 933:39]
|
||
|
|
csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 934:39]
|
||
|
|
csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 935:39]
|
||
|
|
csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 936:39]
|
||
|
|
csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 937:39]
|
||
|
|
csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 938:39]
|
||
|
|
csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 939:39]
|
||
|
|
csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 940:39]
|
||
|
|
csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 941:39]
|
||
|
|
csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 942:39]
|
||
|
|
csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 943:39]
|
||
|
|
csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 944:39]
|
||
|
|
csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 945:39]
|
||
|
|
csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 946:39]
|
||
|
|
csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 947:39]
|
||
|
|
csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 948:39]
|
||
|
|
csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 949:39]
|
||
|
|
csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 950:39]
|
||
|
|
csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 951:39]
|
||
|
|
csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 952:39]
|
||
|
|
csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 953:39]
|
||
|
|
csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 954:39]
|
||
|
|
csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 955:39]
|
||
|
|
csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 956:39]
|
||
|
|
csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 957:39]
|
||
|
|
csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 958:39]
|
||
|
|
csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 959:39]
|
||
|
|
csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 960:39]
|
||
|
|
csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 961:39]
|
||
|
|
csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 962:39]
|
||
|
|
csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 963:39]
|
||
|
|
csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 964:39]
|
||
|
|
csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 965:39]
|
||
|
|
csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 966:39]
|
||
|
|
csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 967:39]
|
||
|
|
csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 968:39]
|
||
|
|
csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 969:51]
|
||
|
|
csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 970:47]
|
||
|
|
csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 971:43]
|
||
|
|
csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 972:43]
|
||
|
|
csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 973:43]
|
||
|
|
csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 974:39]
|
||
|
|
csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 975:51]
|
||
|
|
csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 976:39]
|
||
|
|
csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 977:39]
|
||
|
|
csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 978:39]
|
||
|
|
csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 979:39]
|
||
|
|
csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 980:39]
|
||
|
|
csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 981:39]
|
||
|
|
csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 982:39]
|
||
|
|
csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 983:39]
|
||
|
|
csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 984:39]
|
||
|
|
csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 985:39]
|
||
|
|
csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 986:39]
|
||
|
|
csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 987:39]
|
||
|
|
csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 988:39]
|
||
|
|
csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 989:39]
|
||
|
|
csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 990:39]
|
||
|
|
csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 991:39]
|
||
|
|
csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 992:39]
|
||
|
|
csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 992:39]
|
||
|
|
npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 994:31]
|
||
|
|
npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 995:31]
|
||
|
|
mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 996:31]
|
||
|
|
mepc <= csr.io.mepc @[dec_tlu_ctl.scala 997:31]
|
||
|
|
mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 998:31]
|
||
|
|
force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 999:31]
|
||
|
|
dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1000:31]
|
||
|
|
mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1001:31]
|
||
|
|
dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1002:31]
|
||
|
|
fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1003:31]
|
||
|
|
mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1004:31]
|
||
|
|
dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1005:31]
|
||
|
|
mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1006:31]
|
||
|
|
mip <= csr.io.mip @[dec_tlu_ctl.scala 1007:31]
|
||
|
|
mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1008:33]
|
||
|
|
mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1008:33]
|
||
|
|
mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1008:33]
|
||
|
|
mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1008:33]
|
||
|
|
inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1009:22]
|
||
|
|
csr_read.clock <= clock
|
||
|
|
csr_read.reset <= reset
|
||
|
|
csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1010:37]
|
||
|
|
csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1011:16]
|
||
|
|
node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1013:42]
|
||
|
|
node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1013:67]
|
||
|
|
node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1013:65]
|
||
|
|
io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1013:23]
|
||
|
|
node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1014:43]
|
||
|
|
io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1014:23]
|
||
|
|
node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1017:50]
|
||
|
|
node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1017:72]
|
||
|
|
node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1017:92]
|
||
|
|
node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1017:112]
|
||
|
|
node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1017:134]
|
||
|
|
node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1017:159]
|
||
|
|
node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1017:157]
|
||
|
|
node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1018:55]
|
||
|
|
node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1018:73]
|
||
|
|
node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1018:92]
|
||
|
|
node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1018:115]
|
||
|
|
node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1018:136]
|
||
|
|
node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1018:158]
|
||
|
|
node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1018:179]
|
||
|
|
node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1018:36]
|
||
|
|
node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1018:201]
|
||
|
|
node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1018:33]
|
||
|
|
node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1018:223]
|
||
|
|
node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1018:221]
|
||
|
|
node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1018:243]
|
||
|
|
node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1018:241]
|
||
|
|
node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1020:46]
|
||
|
|
node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1020:107]
|
||
|
|
node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1020:129]
|
||
|
|
node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1020:150]
|
||
|
|
node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1020:172]
|
||
|
|
node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1020:193]
|
||
|
|
node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1020:82]
|
||
|
|
node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1020:59]
|
||
|
|
node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1020:57]
|
||
|
|
io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1020:20]
|
||
|
|
|
||
|
|
module dec_trigger :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>}
|
||
|
|
|
||
|
|
node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
|
||
|
|
node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[dec_trigger.scala 14:93]
|
||
|
|
wire _T_2 : UInt<1>[32] @[lib.scala 12:48]
|
||
|
|
_T_2[0] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[1] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[2] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[3] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[4] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[5] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[6] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[7] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[8] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[9] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[10] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[11] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[12] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[13] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[14] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[15] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[16] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[17] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[18] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[19] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[20] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[21] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[22] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[23] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[24] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[25] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[26] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[27] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[28] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[29] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[30] <= _T_1 @[lib.scala 12:48]
|
||
|
|
_T_2[31] <= _T_1 @[lib.scala 12:48]
|
||
|
|
node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_6 = cat(_T_5, _T_2[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_7 = cat(_T_6, _T_2[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_8 = cat(_T_7, _T_2[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_9 = cat(_T_8, _T_2[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_10 = cat(_T_9, _T_2[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_11 = cat(_T_10, _T_2[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_12 = cat(_T_11, _T_2[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_13 = cat(_T_12, _T_2[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_14 = cat(_T_13, _T_2[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_15 = cat(_T_14, _T_2[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_16 = cat(_T_15, _T_2[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_17 = cat(_T_16, _T_2[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_18 = cat(_T_17, _T_2[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_19 = cat(_T_18, _T_2[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_20 = cat(_T_19, _T_2[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_21 = cat(_T_20, _T_2[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_22 = cat(_T_21, _T_2[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_23 = cat(_T_22, _T_2[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_24 = cat(_T_23, _T_2[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_25 = cat(_T_24, _T_2[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_26 = cat(_T_25, _T_2[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_27 = cat(_T_26, _T_2[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_28 = cat(_T_27, _T_2[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_29 = cat(_T_28, _T_2[27]) @[Cat.scala 29:58]
|
||
|
|
node _T_30 = cat(_T_29, _T_2[28]) @[Cat.scala 29:58]
|
||
|
|
node _T_31 = cat(_T_30, _T_2[29]) @[Cat.scala 29:58]
|
||
|
|
node _T_32 = cat(_T_31, _T_2[30]) @[Cat.scala 29:58]
|
||
|
|
node _T_33 = cat(_T_32, _T_2[31]) @[Cat.scala 29:58]
|
||
|
|
node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
||
|
|
node _T_35 = cat(io.dec_i0_pc_d, _T_34) @[Cat.scala 29:58]
|
||
|
|
node _T_36 = and(_T_33, _T_35) @[dec_trigger.scala 14:127]
|
||
|
|
node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
|
||
|
|
node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[dec_trigger.scala 14:93]
|
||
|
|
wire _T_39 : UInt<1>[32] @[lib.scala 12:48]
|
||
|
|
_T_39[0] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[1] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[2] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[3] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[4] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[5] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[6] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[7] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[8] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[9] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[10] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[11] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[12] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[13] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[14] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[15] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[16] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[17] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[18] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[19] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[20] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[21] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[22] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[23] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[24] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[25] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[26] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[27] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[28] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[29] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[30] <= _T_38 @[lib.scala 12:48]
|
||
|
|
_T_39[31] <= _T_38 @[lib.scala 12:48]
|
||
|
|
node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_43 = cat(_T_42, _T_39[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_44 = cat(_T_43, _T_39[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_45 = cat(_T_44, _T_39[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_46 = cat(_T_45, _T_39[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_47 = cat(_T_46, _T_39[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_48 = cat(_T_47, _T_39[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_49 = cat(_T_48, _T_39[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_50 = cat(_T_49, _T_39[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_51 = cat(_T_50, _T_39[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_52 = cat(_T_51, _T_39[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_53 = cat(_T_52, _T_39[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_54 = cat(_T_53, _T_39[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_55 = cat(_T_54, _T_39[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_56 = cat(_T_55, _T_39[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_57 = cat(_T_56, _T_39[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_58 = cat(_T_57, _T_39[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_59 = cat(_T_58, _T_39[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_60 = cat(_T_59, _T_39[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_61 = cat(_T_60, _T_39[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_62 = cat(_T_61, _T_39[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_63 = cat(_T_62, _T_39[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_64 = cat(_T_63, _T_39[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_65 = cat(_T_64, _T_39[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_66 = cat(_T_65, _T_39[27]) @[Cat.scala 29:58]
|
||
|
|
node _T_67 = cat(_T_66, _T_39[28]) @[Cat.scala 29:58]
|
||
|
|
node _T_68 = cat(_T_67, _T_39[29]) @[Cat.scala 29:58]
|
||
|
|
node _T_69 = cat(_T_68, _T_39[30]) @[Cat.scala 29:58]
|
||
|
|
node _T_70 = cat(_T_69, _T_39[31]) @[Cat.scala 29:58]
|
||
|
|
node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
||
|
|
node _T_72 = cat(io.dec_i0_pc_d, _T_71) @[Cat.scala 29:58]
|
||
|
|
node _T_73 = and(_T_70, _T_72) @[dec_trigger.scala 14:127]
|
||
|
|
node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
|
||
|
|
node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[dec_trigger.scala 14:93]
|
||
|
|
wire _T_76 : UInt<1>[32] @[lib.scala 12:48]
|
||
|
|
_T_76[0] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[1] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[2] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[3] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[4] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[5] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[6] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[7] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[8] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[9] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[10] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[11] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[12] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[13] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[14] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[15] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[16] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[17] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[18] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[19] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[20] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[21] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[22] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[23] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[24] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[25] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[26] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[27] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[28] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[29] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[30] <= _T_75 @[lib.scala 12:48]
|
||
|
|
_T_76[31] <= _T_75 @[lib.scala 12:48]
|
||
|
|
node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_80 = cat(_T_79, _T_76[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_81 = cat(_T_80, _T_76[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_82 = cat(_T_81, _T_76[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_83 = cat(_T_82, _T_76[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_84 = cat(_T_83, _T_76[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_85 = cat(_T_84, _T_76[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_86 = cat(_T_85, _T_76[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_87 = cat(_T_86, _T_76[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_88 = cat(_T_87, _T_76[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_89 = cat(_T_88, _T_76[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_90 = cat(_T_89, _T_76[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_91 = cat(_T_90, _T_76[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_92 = cat(_T_91, _T_76[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_93 = cat(_T_92, _T_76[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_94 = cat(_T_93, _T_76[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_95 = cat(_T_94, _T_76[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_96 = cat(_T_95, _T_76[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_97 = cat(_T_96, _T_76[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_98 = cat(_T_97, _T_76[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_99 = cat(_T_98, _T_76[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_100 = cat(_T_99, _T_76[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_101 = cat(_T_100, _T_76[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_102 = cat(_T_101, _T_76[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_103 = cat(_T_102, _T_76[27]) @[Cat.scala 29:58]
|
||
|
|
node _T_104 = cat(_T_103, _T_76[28]) @[Cat.scala 29:58]
|
||
|
|
node _T_105 = cat(_T_104, _T_76[29]) @[Cat.scala 29:58]
|
||
|
|
node _T_106 = cat(_T_105, _T_76[30]) @[Cat.scala 29:58]
|
||
|
|
node _T_107 = cat(_T_106, _T_76[31]) @[Cat.scala 29:58]
|
||
|
|
node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
||
|
|
node _T_109 = cat(io.dec_i0_pc_d, _T_108) @[Cat.scala 29:58]
|
||
|
|
node _T_110 = and(_T_107, _T_109) @[dec_trigger.scala 14:127]
|
||
|
|
node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
|
||
|
|
node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[dec_trigger.scala 14:93]
|
||
|
|
wire _T_113 : UInt<1>[32] @[lib.scala 12:48]
|
||
|
|
_T_113[0] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[1] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[2] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[3] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[4] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[5] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[6] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[7] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[8] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[9] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[10] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[11] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[12] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[13] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[14] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[15] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[16] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[17] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[18] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[19] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[20] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[21] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[22] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[23] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[24] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[25] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[26] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[27] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[28] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[29] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[30] <= _T_112 @[lib.scala 12:48]
|
||
|
|
_T_113[31] <= _T_112 @[lib.scala 12:48]
|
||
|
|
node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_117 = cat(_T_116, _T_113[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_118 = cat(_T_117, _T_113[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_119 = cat(_T_118, _T_113[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_120 = cat(_T_119, _T_113[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_121 = cat(_T_120, _T_113[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_122 = cat(_T_121, _T_113[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_123 = cat(_T_122, _T_113[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_124 = cat(_T_123, _T_113[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_125 = cat(_T_124, _T_113[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_126 = cat(_T_125, _T_113[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_127 = cat(_T_126, _T_113[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_128 = cat(_T_127, _T_113[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_129 = cat(_T_128, _T_113[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_130 = cat(_T_129, _T_113[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_131 = cat(_T_130, _T_113[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_132 = cat(_T_131, _T_113[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_133 = cat(_T_132, _T_113[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_134 = cat(_T_133, _T_113[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_135 = cat(_T_134, _T_113[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_136 = cat(_T_135, _T_113[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_137 = cat(_T_136, _T_113[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_138 = cat(_T_137, _T_113[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_139 = cat(_T_138, _T_113[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_140 = cat(_T_139, _T_113[27]) @[Cat.scala 29:58]
|
||
|
|
node _T_141 = cat(_T_140, _T_113[28]) @[Cat.scala 29:58]
|
||
|
|
node _T_142 = cat(_T_141, _T_113[29]) @[Cat.scala 29:58]
|
||
|
|
node _T_143 = cat(_T_142, _T_113[30]) @[Cat.scala 29:58]
|
||
|
|
node _T_144 = cat(_T_143, _T_113[31]) @[Cat.scala 29:58]
|
||
|
|
node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
||
|
|
node _T_146 = cat(io.dec_i0_pc_d, _T_145) @[Cat.scala 29:58]
|
||
|
|
node _T_147 = and(_T_144, _T_146) @[dec_trigger.scala 14:127]
|
||
|
|
wire dec_i0_match_data : UInt<32>[4] @[dec_trigger.scala 14:46]
|
||
|
|
dec_i0_match_data[0] <= _T_36 @[dec_trigger.scala 14:46]
|
||
|
|
dec_i0_match_data[1] <= _T_73 @[dec_trigger.scala 14:46]
|
||
|
|
dec_i0_match_data[2] <= _T_110 @[dec_trigger.scala 14:46]
|
||
|
|
dec_i0_match_data[3] <= _T_147 @[dec_trigger.scala 14:46]
|
||
|
|
node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[dec_trigger.scala 15:83]
|
||
|
|
node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
||
|
|
wire _T_150 : UInt<1>[32] @[lib.scala 100:24]
|
||
|
|
node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45]
|
||
|
|
node _T_152 = not(_T_151) @[lib.scala 101:39]
|
||
|
|
node _T_153 = and(_T_149, _T_152) @[lib.scala 101:37]
|
||
|
|
node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48]
|
||
|
|
node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[lib.scala 102:60]
|
||
|
|
node _T_156 = eq(_T_154, _T_155) @[lib.scala 102:52]
|
||
|
|
node _T_157 = or(_T_153, _T_156) @[lib.scala 102:41]
|
||
|
|
_T_150[0] <= _T_157 @[lib.scala 102:18]
|
||
|
|
node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28]
|
||
|
|
node _T_159 = andr(_T_158) @[lib.scala 104:36]
|
||
|
|
node _T_160 = and(_T_159, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74]
|
||
|
|
node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[lib.scala 104:86]
|
||
|
|
node _T_163 = eq(_T_161, _T_162) @[lib.scala 104:78]
|
||
|
|
node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[lib.scala 104:23]
|
||
|
|
_T_150[1] <= _T_164 @[lib.scala 104:17]
|
||
|
|
node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28]
|
||
|
|
node _T_166 = andr(_T_165) @[lib.scala 104:36]
|
||
|
|
node _T_167 = and(_T_166, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74]
|
||
|
|
node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[lib.scala 104:86]
|
||
|
|
node _T_170 = eq(_T_168, _T_169) @[lib.scala 104:78]
|
||
|
|
node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[lib.scala 104:23]
|
||
|
|
_T_150[2] <= _T_171 @[lib.scala 104:17]
|
||
|
|
node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28]
|
||
|
|
node _T_173 = andr(_T_172) @[lib.scala 104:36]
|
||
|
|
node _T_174 = and(_T_173, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74]
|
||
|
|
node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[lib.scala 104:86]
|
||
|
|
node _T_177 = eq(_T_175, _T_176) @[lib.scala 104:78]
|
||
|
|
node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[lib.scala 104:23]
|
||
|
|
_T_150[3] <= _T_178 @[lib.scala 104:17]
|
||
|
|
node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28]
|
||
|
|
node _T_180 = andr(_T_179) @[lib.scala 104:36]
|
||
|
|
node _T_181 = and(_T_180, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74]
|
||
|
|
node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[lib.scala 104:86]
|
||
|
|
node _T_184 = eq(_T_182, _T_183) @[lib.scala 104:78]
|
||
|
|
node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[lib.scala 104:23]
|
||
|
|
_T_150[4] <= _T_185 @[lib.scala 104:17]
|
||
|
|
node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28]
|
||
|
|
node _T_187 = andr(_T_186) @[lib.scala 104:36]
|
||
|
|
node _T_188 = and(_T_187, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74]
|
||
|
|
node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[lib.scala 104:86]
|
||
|
|
node _T_191 = eq(_T_189, _T_190) @[lib.scala 104:78]
|
||
|
|
node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[lib.scala 104:23]
|
||
|
|
_T_150[5] <= _T_192 @[lib.scala 104:17]
|
||
|
|
node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28]
|
||
|
|
node _T_194 = andr(_T_193) @[lib.scala 104:36]
|
||
|
|
node _T_195 = and(_T_194, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74]
|
||
|
|
node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[lib.scala 104:86]
|
||
|
|
node _T_198 = eq(_T_196, _T_197) @[lib.scala 104:78]
|
||
|
|
node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[lib.scala 104:23]
|
||
|
|
_T_150[6] <= _T_199 @[lib.scala 104:17]
|
||
|
|
node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28]
|
||
|
|
node _T_201 = andr(_T_200) @[lib.scala 104:36]
|
||
|
|
node _T_202 = and(_T_201, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74]
|
||
|
|
node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[lib.scala 104:86]
|
||
|
|
node _T_205 = eq(_T_203, _T_204) @[lib.scala 104:78]
|
||
|
|
node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[lib.scala 104:23]
|
||
|
|
_T_150[7] <= _T_206 @[lib.scala 104:17]
|
||
|
|
node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28]
|
||
|
|
node _T_208 = andr(_T_207) @[lib.scala 104:36]
|
||
|
|
node _T_209 = and(_T_208, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74]
|
||
|
|
node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[lib.scala 104:86]
|
||
|
|
node _T_212 = eq(_T_210, _T_211) @[lib.scala 104:78]
|
||
|
|
node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[lib.scala 104:23]
|
||
|
|
_T_150[8] <= _T_213 @[lib.scala 104:17]
|
||
|
|
node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28]
|
||
|
|
node _T_215 = andr(_T_214) @[lib.scala 104:36]
|
||
|
|
node _T_216 = and(_T_215, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74]
|
||
|
|
node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[lib.scala 104:86]
|
||
|
|
node _T_219 = eq(_T_217, _T_218) @[lib.scala 104:78]
|
||
|
|
node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[lib.scala 104:23]
|
||
|
|
_T_150[9] <= _T_220 @[lib.scala 104:17]
|
||
|
|
node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28]
|
||
|
|
node _T_222 = andr(_T_221) @[lib.scala 104:36]
|
||
|
|
node _T_223 = and(_T_222, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74]
|
||
|
|
node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[lib.scala 104:86]
|
||
|
|
node _T_226 = eq(_T_224, _T_225) @[lib.scala 104:78]
|
||
|
|
node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[lib.scala 104:23]
|
||
|
|
_T_150[10] <= _T_227 @[lib.scala 104:17]
|
||
|
|
node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28]
|
||
|
|
node _T_229 = andr(_T_228) @[lib.scala 104:36]
|
||
|
|
node _T_230 = and(_T_229, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74]
|
||
|
|
node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[lib.scala 104:86]
|
||
|
|
node _T_233 = eq(_T_231, _T_232) @[lib.scala 104:78]
|
||
|
|
node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[lib.scala 104:23]
|
||
|
|
_T_150[11] <= _T_234 @[lib.scala 104:17]
|
||
|
|
node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28]
|
||
|
|
node _T_236 = andr(_T_235) @[lib.scala 104:36]
|
||
|
|
node _T_237 = and(_T_236, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74]
|
||
|
|
node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[lib.scala 104:86]
|
||
|
|
node _T_240 = eq(_T_238, _T_239) @[lib.scala 104:78]
|
||
|
|
node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[lib.scala 104:23]
|
||
|
|
_T_150[12] <= _T_241 @[lib.scala 104:17]
|
||
|
|
node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28]
|
||
|
|
node _T_243 = andr(_T_242) @[lib.scala 104:36]
|
||
|
|
node _T_244 = and(_T_243, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74]
|
||
|
|
node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[lib.scala 104:86]
|
||
|
|
node _T_247 = eq(_T_245, _T_246) @[lib.scala 104:78]
|
||
|
|
node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[lib.scala 104:23]
|
||
|
|
_T_150[13] <= _T_248 @[lib.scala 104:17]
|
||
|
|
node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28]
|
||
|
|
node _T_250 = andr(_T_249) @[lib.scala 104:36]
|
||
|
|
node _T_251 = and(_T_250, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74]
|
||
|
|
node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[lib.scala 104:86]
|
||
|
|
node _T_254 = eq(_T_252, _T_253) @[lib.scala 104:78]
|
||
|
|
node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[lib.scala 104:23]
|
||
|
|
_T_150[14] <= _T_255 @[lib.scala 104:17]
|
||
|
|
node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28]
|
||
|
|
node _T_257 = andr(_T_256) @[lib.scala 104:36]
|
||
|
|
node _T_258 = and(_T_257, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74]
|
||
|
|
node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[lib.scala 104:86]
|
||
|
|
node _T_261 = eq(_T_259, _T_260) @[lib.scala 104:78]
|
||
|
|
node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[lib.scala 104:23]
|
||
|
|
_T_150[15] <= _T_262 @[lib.scala 104:17]
|
||
|
|
node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28]
|
||
|
|
node _T_264 = andr(_T_263) @[lib.scala 104:36]
|
||
|
|
node _T_265 = and(_T_264, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74]
|
||
|
|
node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[lib.scala 104:86]
|
||
|
|
node _T_268 = eq(_T_266, _T_267) @[lib.scala 104:78]
|
||
|
|
node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[lib.scala 104:23]
|
||
|
|
_T_150[16] <= _T_269 @[lib.scala 104:17]
|
||
|
|
node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28]
|
||
|
|
node _T_271 = andr(_T_270) @[lib.scala 104:36]
|
||
|
|
node _T_272 = and(_T_271, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74]
|
||
|
|
node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[lib.scala 104:86]
|
||
|
|
node _T_275 = eq(_T_273, _T_274) @[lib.scala 104:78]
|
||
|
|
node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[lib.scala 104:23]
|
||
|
|
_T_150[17] <= _T_276 @[lib.scala 104:17]
|
||
|
|
node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28]
|
||
|
|
node _T_278 = andr(_T_277) @[lib.scala 104:36]
|
||
|
|
node _T_279 = and(_T_278, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74]
|
||
|
|
node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[lib.scala 104:86]
|
||
|
|
node _T_282 = eq(_T_280, _T_281) @[lib.scala 104:78]
|
||
|
|
node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[lib.scala 104:23]
|
||
|
|
_T_150[18] <= _T_283 @[lib.scala 104:17]
|
||
|
|
node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28]
|
||
|
|
node _T_285 = andr(_T_284) @[lib.scala 104:36]
|
||
|
|
node _T_286 = and(_T_285, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74]
|
||
|
|
node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[lib.scala 104:86]
|
||
|
|
node _T_289 = eq(_T_287, _T_288) @[lib.scala 104:78]
|
||
|
|
node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[lib.scala 104:23]
|
||
|
|
_T_150[19] <= _T_290 @[lib.scala 104:17]
|
||
|
|
node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28]
|
||
|
|
node _T_292 = andr(_T_291) @[lib.scala 104:36]
|
||
|
|
node _T_293 = and(_T_292, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74]
|
||
|
|
node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[lib.scala 104:86]
|
||
|
|
node _T_296 = eq(_T_294, _T_295) @[lib.scala 104:78]
|
||
|
|
node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[lib.scala 104:23]
|
||
|
|
_T_150[20] <= _T_297 @[lib.scala 104:17]
|
||
|
|
node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28]
|
||
|
|
node _T_299 = andr(_T_298) @[lib.scala 104:36]
|
||
|
|
node _T_300 = and(_T_299, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74]
|
||
|
|
node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[lib.scala 104:86]
|
||
|
|
node _T_303 = eq(_T_301, _T_302) @[lib.scala 104:78]
|
||
|
|
node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[lib.scala 104:23]
|
||
|
|
_T_150[21] <= _T_304 @[lib.scala 104:17]
|
||
|
|
node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28]
|
||
|
|
node _T_306 = andr(_T_305) @[lib.scala 104:36]
|
||
|
|
node _T_307 = and(_T_306, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74]
|
||
|
|
node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[lib.scala 104:86]
|
||
|
|
node _T_310 = eq(_T_308, _T_309) @[lib.scala 104:78]
|
||
|
|
node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[lib.scala 104:23]
|
||
|
|
_T_150[22] <= _T_311 @[lib.scala 104:17]
|
||
|
|
node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28]
|
||
|
|
node _T_313 = andr(_T_312) @[lib.scala 104:36]
|
||
|
|
node _T_314 = and(_T_313, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74]
|
||
|
|
node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[lib.scala 104:86]
|
||
|
|
node _T_317 = eq(_T_315, _T_316) @[lib.scala 104:78]
|
||
|
|
node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[lib.scala 104:23]
|
||
|
|
_T_150[23] <= _T_318 @[lib.scala 104:17]
|
||
|
|
node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28]
|
||
|
|
node _T_320 = andr(_T_319) @[lib.scala 104:36]
|
||
|
|
node _T_321 = and(_T_320, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74]
|
||
|
|
node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[lib.scala 104:86]
|
||
|
|
node _T_324 = eq(_T_322, _T_323) @[lib.scala 104:78]
|
||
|
|
node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[lib.scala 104:23]
|
||
|
|
_T_150[24] <= _T_325 @[lib.scala 104:17]
|
||
|
|
node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28]
|
||
|
|
node _T_327 = andr(_T_326) @[lib.scala 104:36]
|
||
|
|
node _T_328 = and(_T_327, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74]
|
||
|
|
node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[lib.scala 104:86]
|
||
|
|
node _T_331 = eq(_T_329, _T_330) @[lib.scala 104:78]
|
||
|
|
node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[lib.scala 104:23]
|
||
|
|
_T_150[25] <= _T_332 @[lib.scala 104:17]
|
||
|
|
node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28]
|
||
|
|
node _T_334 = andr(_T_333) @[lib.scala 104:36]
|
||
|
|
node _T_335 = and(_T_334, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74]
|
||
|
|
node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[lib.scala 104:86]
|
||
|
|
node _T_338 = eq(_T_336, _T_337) @[lib.scala 104:78]
|
||
|
|
node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[lib.scala 104:23]
|
||
|
|
_T_150[26] <= _T_339 @[lib.scala 104:17]
|
||
|
|
node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28]
|
||
|
|
node _T_341 = andr(_T_340) @[lib.scala 104:36]
|
||
|
|
node _T_342 = and(_T_341, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74]
|
||
|
|
node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[lib.scala 104:86]
|
||
|
|
node _T_345 = eq(_T_343, _T_344) @[lib.scala 104:78]
|
||
|
|
node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[lib.scala 104:23]
|
||
|
|
_T_150[27] <= _T_346 @[lib.scala 104:17]
|
||
|
|
node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28]
|
||
|
|
node _T_348 = andr(_T_347) @[lib.scala 104:36]
|
||
|
|
node _T_349 = and(_T_348, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74]
|
||
|
|
node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[lib.scala 104:86]
|
||
|
|
node _T_352 = eq(_T_350, _T_351) @[lib.scala 104:78]
|
||
|
|
node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[lib.scala 104:23]
|
||
|
|
_T_150[28] <= _T_353 @[lib.scala 104:17]
|
||
|
|
node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28]
|
||
|
|
node _T_355 = andr(_T_354) @[lib.scala 104:36]
|
||
|
|
node _T_356 = and(_T_355, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74]
|
||
|
|
node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[lib.scala 104:86]
|
||
|
|
node _T_359 = eq(_T_357, _T_358) @[lib.scala 104:78]
|
||
|
|
node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[lib.scala 104:23]
|
||
|
|
_T_150[29] <= _T_360 @[lib.scala 104:17]
|
||
|
|
node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28]
|
||
|
|
node _T_362 = andr(_T_361) @[lib.scala 104:36]
|
||
|
|
node _T_363 = and(_T_362, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74]
|
||
|
|
node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[lib.scala 104:86]
|
||
|
|
node _T_366 = eq(_T_364, _T_365) @[lib.scala 104:78]
|
||
|
|
node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[lib.scala 104:23]
|
||
|
|
_T_150[30] <= _T_367 @[lib.scala 104:17]
|
||
|
|
node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28]
|
||
|
|
node _T_369 = andr(_T_368) @[lib.scala 104:36]
|
||
|
|
node _T_370 = and(_T_369, _T_153) @[lib.scala 104:41]
|
||
|
|
node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74]
|
||
|
|
node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[lib.scala 104:86]
|
||
|
|
node _T_373 = eq(_T_371, _T_372) @[lib.scala 104:78]
|
||
|
|
node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[lib.scala 104:23]
|
||
|
|
_T_150[31] <= _T_374 @[lib.scala 104:17]
|
||
|
|
node _T_375 = cat(_T_150[1], _T_150[0]) @[lib.scala 105:14]
|
||
|
|
node _T_376 = cat(_T_150[3], _T_150[2]) @[lib.scala 105:14]
|
||
|
|
node _T_377 = cat(_T_376, _T_375) @[lib.scala 105:14]
|
||
|
|
node _T_378 = cat(_T_150[5], _T_150[4]) @[lib.scala 105:14]
|
||
|
|
node _T_379 = cat(_T_150[7], _T_150[6]) @[lib.scala 105:14]
|
||
|
|
node _T_380 = cat(_T_379, _T_378) @[lib.scala 105:14]
|
||
|
|
node _T_381 = cat(_T_380, _T_377) @[lib.scala 105:14]
|
||
|
|
node _T_382 = cat(_T_150[9], _T_150[8]) @[lib.scala 105:14]
|
||
|
|
node _T_383 = cat(_T_150[11], _T_150[10]) @[lib.scala 105:14]
|
||
|
|
node _T_384 = cat(_T_383, _T_382) @[lib.scala 105:14]
|
||
|
|
node _T_385 = cat(_T_150[13], _T_150[12]) @[lib.scala 105:14]
|
||
|
|
node _T_386 = cat(_T_150[15], _T_150[14]) @[lib.scala 105:14]
|
||
|
|
node _T_387 = cat(_T_386, _T_385) @[lib.scala 105:14]
|
||
|
|
node _T_388 = cat(_T_387, _T_384) @[lib.scala 105:14]
|
||
|
|
node _T_389 = cat(_T_388, _T_381) @[lib.scala 105:14]
|
||
|
|
node _T_390 = cat(_T_150[17], _T_150[16]) @[lib.scala 105:14]
|
||
|
|
node _T_391 = cat(_T_150[19], _T_150[18]) @[lib.scala 105:14]
|
||
|
|
node _T_392 = cat(_T_391, _T_390) @[lib.scala 105:14]
|
||
|
|
node _T_393 = cat(_T_150[21], _T_150[20]) @[lib.scala 105:14]
|
||
|
|
node _T_394 = cat(_T_150[23], _T_150[22]) @[lib.scala 105:14]
|
||
|
|
node _T_395 = cat(_T_394, _T_393) @[lib.scala 105:14]
|
||
|
|
node _T_396 = cat(_T_395, _T_392) @[lib.scala 105:14]
|
||
|
|
node _T_397 = cat(_T_150[25], _T_150[24]) @[lib.scala 105:14]
|
||
|
|
node _T_398 = cat(_T_150[27], _T_150[26]) @[lib.scala 105:14]
|
||
|
|
node _T_399 = cat(_T_398, _T_397) @[lib.scala 105:14]
|
||
|
|
node _T_400 = cat(_T_150[29], _T_150[28]) @[lib.scala 105:14]
|
||
|
|
node _T_401 = cat(_T_150[31], _T_150[30]) @[lib.scala 105:14]
|
||
|
|
node _T_402 = cat(_T_401, _T_400) @[lib.scala 105:14]
|
||
|
|
node _T_403 = cat(_T_402, _T_399) @[lib.scala 105:14]
|
||
|
|
node _T_404 = cat(_T_403, _T_396) @[lib.scala 105:14]
|
||
|
|
node _T_405 = cat(_T_404, _T_389) @[lib.scala 105:14]
|
||
|
|
node _T_406 = andr(_T_405) @[lib.scala 105:25]
|
||
|
|
node _T_407 = and(_T_148, _T_406) @[dec_trigger.scala 15:109]
|
||
|
|
node _T_408 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83]
|
||
|
|
node _T_409 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
||
|
|
wire _T_410 : UInt<1>[32] @[lib.scala 100:24]
|
||
|
|
node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45]
|
||
|
|
node _T_412 = not(_T_411) @[lib.scala 101:39]
|
||
|
|
node _T_413 = and(_T_409, _T_412) @[lib.scala 101:37]
|
||
|
|
node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48]
|
||
|
|
node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 102:60]
|
||
|
|
node _T_416 = eq(_T_414, _T_415) @[lib.scala 102:52]
|
||
|
|
node _T_417 = or(_T_413, _T_416) @[lib.scala 102:41]
|
||
|
|
_T_410[0] <= _T_417 @[lib.scala 102:18]
|
||
|
|
node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28]
|
||
|
|
node _T_419 = andr(_T_418) @[lib.scala 104:36]
|
||
|
|
node _T_420 = and(_T_419, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74]
|
||
|
|
node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 104:86]
|
||
|
|
node _T_423 = eq(_T_421, _T_422) @[lib.scala 104:78]
|
||
|
|
node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[lib.scala 104:23]
|
||
|
|
_T_410[1] <= _T_424 @[lib.scala 104:17]
|
||
|
|
node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28]
|
||
|
|
node _T_426 = andr(_T_425) @[lib.scala 104:36]
|
||
|
|
node _T_427 = and(_T_426, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74]
|
||
|
|
node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 104:86]
|
||
|
|
node _T_430 = eq(_T_428, _T_429) @[lib.scala 104:78]
|
||
|
|
node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[lib.scala 104:23]
|
||
|
|
_T_410[2] <= _T_431 @[lib.scala 104:17]
|
||
|
|
node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28]
|
||
|
|
node _T_433 = andr(_T_432) @[lib.scala 104:36]
|
||
|
|
node _T_434 = and(_T_433, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74]
|
||
|
|
node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 104:86]
|
||
|
|
node _T_437 = eq(_T_435, _T_436) @[lib.scala 104:78]
|
||
|
|
node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[lib.scala 104:23]
|
||
|
|
_T_410[3] <= _T_438 @[lib.scala 104:17]
|
||
|
|
node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28]
|
||
|
|
node _T_440 = andr(_T_439) @[lib.scala 104:36]
|
||
|
|
node _T_441 = and(_T_440, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74]
|
||
|
|
node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 104:86]
|
||
|
|
node _T_444 = eq(_T_442, _T_443) @[lib.scala 104:78]
|
||
|
|
node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[lib.scala 104:23]
|
||
|
|
_T_410[4] <= _T_445 @[lib.scala 104:17]
|
||
|
|
node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28]
|
||
|
|
node _T_447 = andr(_T_446) @[lib.scala 104:36]
|
||
|
|
node _T_448 = and(_T_447, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74]
|
||
|
|
node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 104:86]
|
||
|
|
node _T_451 = eq(_T_449, _T_450) @[lib.scala 104:78]
|
||
|
|
node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[lib.scala 104:23]
|
||
|
|
_T_410[5] <= _T_452 @[lib.scala 104:17]
|
||
|
|
node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28]
|
||
|
|
node _T_454 = andr(_T_453) @[lib.scala 104:36]
|
||
|
|
node _T_455 = and(_T_454, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74]
|
||
|
|
node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 104:86]
|
||
|
|
node _T_458 = eq(_T_456, _T_457) @[lib.scala 104:78]
|
||
|
|
node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[lib.scala 104:23]
|
||
|
|
_T_410[6] <= _T_459 @[lib.scala 104:17]
|
||
|
|
node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28]
|
||
|
|
node _T_461 = andr(_T_460) @[lib.scala 104:36]
|
||
|
|
node _T_462 = and(_T_461, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74]
|
||
|
|
node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 104:86]
|
||
|
|
node _T_465 = eq(_T_463, _T_464) @[lib.scala 104:78]
|
||
|
|
node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[lib.scala 104:23]
|
||
|
|
_T_410[7] <= _T_466 @[lib.scala 104:17]
|
||
|
|
node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28]
|
||
|
|
node _T_468 = andr(_T_467) @[lib.scala 104:36]
|
||
|
|
node _T_469 = and(_T_468, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74]
|
||
|
|
node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 104:86]
|
||
|
|
node _T_472 = eq(_T_470, _T_471) @[lib.scala 104:78]
|
||
|
|
node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[lib.scala 104:23]
|
||
|
|
_T_410[8] <= _T_473 @[lib.scala 104:17]
|
||
|
|
node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28]
|
||
|
|
node _T_475 = andr(_T_474) @[lib.scala 104:36]
|
||
|
|
node _T_476 = and(_T_475, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74]
|
||
|
|
node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 104:86]
|
||
|
|
node _T_479 = eq(_T_477, _T_478) @[lib.scala 104:78]
|
||
|
|
node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[lib.scala 104:23]
|
||
|
|
_T_410[9] <= _T_480 @[lib.scala 104:17]
|
||
|
|
node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28]
|
||
|
|
node _T_482 = andr(_T_481) @[lib.scala 104:36]
|
||
|
|
node _T_483 = and(_T_482, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74]
|
||
|
|
node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 104:86]
|
||
|
|
node _T_486 = eq(_T_484, _T_485) @[lib.scala 104:78]
|
||
|
|
node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[lib.scala 104:23]
|
||
|
|
_T_410[10] <= _T_487 @[lib.scala 104:17]
|
||
|
|
node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28]
|
||
|
|
node _T_489 = andr(_T_488) @[lib.scala 104:36]
|
||
|
|
node _T_490 = and(_T_489, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74]
|
||
|
|
node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 104:86]
|
||
|
|
node _T_493 = eq(_T_491, _T_492) @[lib.scala 104:78]
|
||
|
|
node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[lib.scala 104:23]
|
||
|
|
_T_410[11] <= _T_494 @[lib.scala 104:17]
|
||
|
|
node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28]
|
||
|
|
node _T_496 = andr(_T_495) @[lib.scala 104:36]
|
||
|
|
node _T_497 = and(_T_496, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74]
|
||
|
|
node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 104:86]
|
||
|
|
node _T_500 = eq(_T_498, _T_499) @[lib.scala 104:78]
|
||
|
|
node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[lib.scala 104:23]
|
||
|
|
_T_410[12] <= _T_501 @[lib.scala 104:17]
|
||
|
|
node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28]
|
||
|
|
node _T_503 = andr(_T_502) @[lib.scala 104:36]
|
||
|
|
node _T_504 = and(_T_503, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74]
|
||
|
|
node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 104:86]
|
||
|
|
node _T_507 = eq(_T_505, _T_506) @[lib.scala 104:78]
|
||
|
|
node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[lib.scala 104:23]
|
||
|
|
_T_410[13] <= _T_508 @[lib.scala 104:17]
|
||
|
|
node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28]
|
||
|
|
node _T_510 = andr(_T_509) @[lib.scala 104:36]
|
||
|
|
node _T_511 = and(_T_510, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74]
|
||
|
|
node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 104:86]
|
||
|
|
node _T_514 = eq(_T_512, _T_513) @[lib.scala 104:78]
|
||
|
|
node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[lib.scala 104:23]
|
||
|
|
_T_410[14] <= _T_515 @[lib.scala 104:17]
|
||
|
|
node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28]
|
||
|
|
node _T_517 = andr(_T_516) @[lib.scala 104:36]
|
||
|
|
node _T_518 = and(_T_517, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74]
|
||
|
|
node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 104:86]
|
||
|
|
node _T_521 = eq(_T_519, _T_520) @[lib.scala 104:78]
|
||
|
|
node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[lib.scala 104:23]
|
||
|
|
_T_410[15] <= _T_522 @[lib.scala 104:17]
|
||
|
|
node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28]
|
||
|
|
node _T_524 = andr(_T_523) @[lib.scala 104:36]
|
||
|
|
node _T_525 = and(_T_524, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74]
|
||
|
|
node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 104:86]
|
||
|
|
node _T_528 = eq(_T_526, _T_527) @[lib.scala 104:78]
|
||
|
|
node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[lib.scala 104:23]
|
||
|
|
_T_410[16] <= _T_529 @[lib.scala 104:17]
|
||
|
|
node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28]
|
||
|
|
node _T_531 = andr(_T_530) @[lib.scala 104:36]
|
||
|
|
node _T_532 = and(_T_531, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74]
|
||
|
|
node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 104:86]
|
||
|
|
node _T_535 = eq(_T_533, _T_534) @[lib.scala 104:78]
|
||
|
|
node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[lib.scala 104:23]
|
||
|
|
_T_410[17] <= _T_536 @[lib.scala 104:17]
|
||
|
|
node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28]
|
||
|
|
node _T_538 = andr(_T_537) @[lib.scala 104:36]
|
||
|
|
node _T_539 = and(_T_538, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74]
|
||
|
|
node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 104:86]
|
||
|
|
node _T_542 = eq(_T_540, _T_541) @[lib.scala 104:78]
|
||
|
|
node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[lib.scala 104:23]
|
||
|
|
_T_410[18] <= _T_543 @[lib.scala 104:17]
|
||
|
|
node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28]
|
||
|
|
node _T_545 = andr(_T_544) @[lib.scala 104:36]
|
||
|
|
node _T_546 = and(_T_545, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74]
|
||
|
|
node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 104:86]
|
||
|
|
node _T_549 = eq(_T_547, _T_548) @[lib.scala 104:78]
|
||
|
|
node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[lib.scala 104:23]
|
||
|
|
_T_410[19] <= _T_550 @[lib.scala 104:17]
|
||
|
|
node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28]
|
||
|
|
node _T_552 = andr(_T_551) @[lib.scala 104:36]
|
||
|
|
node _T_553 = and(_T_552, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74]
|
||
|
|
node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 104:86]
|
||
|
|
node _T_556 = eq(_T_554, _T_555) @[lib.scala 104:78]
|
||
|
|
node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[lib.scala 104:23]
|
||
|
|
_T_410[20] <= _T_557 @[lib.scala 104:17]
|
||
|
|
node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28]
|
||
|
|
node _T_559 = andr(_T_558) @[lib.scala 104:36]
|
||
|
|
node _T_560 = and(_T_559, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74]
|
||
|
|
node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 104:86]
|
||
|
|
node _T_563 = eq(_T_561, _T_562) @[lib.scala 104:78]
|
||
|
|
node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[lib.scala 104:23]
|
||
|
|
_T_410[21] <= _T_564 @[lib.scala 104:17]
|
||
|
|
node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28]
|
||
|
|
node _T_566 = andr(_T_565) @[lib.scala 104:36]
|
||
|
|
node _T_567 = and(_T_566, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74]
|
||
|
|
node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 104:86]
|
||
|
|
node _T_570 = eq(_T_568, _T_569) @[lib.scala 104:78]
|
||
|
|
node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[lib.scala 104:23]
|
||
|
|
_T_410[22] <= _T_571 @[lib.scala 104:17]
|
||
|
|
node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28]
|
||
|
|
node _T_573 = andr(_T_572) @[lib.scala 104:36]
|
||
|
|
node _T_574 = and(_T_573, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74]
|
||
|
|
node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 104:86]
|
||
|
|
node _T_577 = eq(_T_575, _T_576) @[lib.scala 104:78]
|
||
|
|
node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[lib.scala 104:23]
|
||
|
|
_T_410[23] <= _T_578 @[lib.scala 104:17]
|
||
|
|
node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28]
|
||
|
|
node _T_580 = andr(_T_579) @[lib.scala 104:36]
|
||
|
|
node _T_581 = and(_T_580, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74]
|
||
|
|
node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 104:86]
|
||
|
|
node _T_584 = eq(_T_582, _T_583) @[lib.scala 104:78]
|
||
|
|
node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[lib.scala 104:23]
|
||
|
|
_T_410[24] <= _T_585 @[lib.scala 104:17]
|
||
|
|
node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28]
|
||
|
|
node _T_587 = andr(_T_586) @[lib.scala 104:36]
|
||
|
|
node _T_588 = and(_T_587, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74]
|
||
|
|
node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 104:86]
|
||
|
|
node _T_591 = eq(_T_589, _T_590) @[lib.scala 104:78]
|
||
|
|
node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[lib.scala 104:23]
|
||
|
|
_T_410[25] <= _T_592 @[lib.scala 104:17]
|
||
|
|
node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28]
|
||
|
|
node _T_594 = andr(_T_593) @[lib.scala 104:36]
|
||
|
|
node _T_595 = and(_T_594, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74]
|
||
|
|
node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 104:86]
|
||
|
|
node _T_598 = eq(_T_596, _T_597) @[lib.scala 104:78]
|
||
|
|
node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[lib.scala 104:23]
|
||
|
|
_T_410[26] <= _T_599 @[lib.scala 104:17]
|
||
|
|
node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28]
|
||
|
|
node _T_601 = andr(_T_600) @[lib.scala 104:36]
|
||
|
|
node _T_602 = and(_T_601, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74]
|
||
|
|
node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 104:86]
|
||
|
|
node _T_605 = eq(_T_603, _T_604) @[lib.scala 104:78]
|
||
|
|
node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[lib.scala 104:23]
|
||
|
|
_T_410[27] <= _T_606 @[lib.scala 104:17]
|
||
|
|
node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28]
|
||
|
|
node _T_608 = andr(_T_607) @[lib.scala 104:36]
|
||
|
|
node _T_609 = and(_T_608, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74]
|
||
|
|
node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 104:86]
|
||
|
|
node _T_612 = eq(_T_610, _T_611) @[lib.scala 104:78]
|
||
|
|
node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[lib.scala 104:23]
|
||
|
|
_T_410[28] <= _T_613 @[lib.scala 104:17]
|
||
|
|
node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28]
|
||
|
|
node _T_615 = andr(_T_614) @[lib.scala 104:36]
|
||
|
|
node _T_616 = and(_T_615, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74]
|
||
|
|
node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 104:86]
|
||
|
|
node _T_619 = eq(_T_617, _T_618) @[lib.scala 104:78]
|
||
|
|
node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[lib.scala 104:23]
|
||
|
|
_T_410[29] <= _T_620 @[lib.scala 104:17]
|
||
|
|
node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28]
|
||
|
|
node _T_622 = andr(_T_621) @[lib.scala 104:36]
|
||
|
|
node _T_623 = and(_T_622, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74]
|
||
|
|
node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 104:86]
|
||
|
|
node _T_626 = eq(_T_624, _T_625) @[lib.scala 104:78]
|
||
|
|
node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[lib.scala 104:23]
|
||
|
|
_T_410[30] <= _T_627 @[lib.scala 104:17]
|
||
|
|
node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28]
|
||
|
|
node _T_629 = andr(_T_628) @[lib.scala 104:36]
|
||
|
|
node _T_630 = and(_T_629, _T_413) @[lib.scala 104:41]
|
||
|
|
node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74]
|
||
|
|
node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 104:86]
|
||
|
|
node _T_633 = eq(_T_631, _T_632) @[lib.scala 104:78]
|
||
|
|
node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[lib.scala 104:23]
|
||
|
|
_T_410[31] <= _T_634 @[lib.scala 104:17]
|
||
|
|
node _T_635 = cat(_T_410[1], _T_410[0]) @[lib.scala 105:14]
|
||
|
|
node _T_636 = cat(_T_410[3], _T_410[2]) @[lib.scala 105:14]
|
||
|
|
node _T_637 = cat(_T_636, _T_635) @[lib.scala 105:14]
|
||
|
|
node _T_638 = cat(_T_410[5], _T_410[4]) @[lib.scala 105:14]
|
||
|
|
node _T_639 = cat(_T_410[7], _T_410[6]) @[lib.scala 105:14]
|
||
|
|
node _T_640 = cat(_T_639, _T_638) @[lib.scala 105:14]
|
||
|
|
node _T_641 = cat(_T_640, _T_637) @[lib.scala 105:14]
|
||
|
|
node _T_642 = cat(_T_410[9], _T_410[8]) @[lib.scala 105:14]
|
||
|
|
node _T_643 = cat(_T_410[11], _T_410[10]) @[lib.scala 105:14]
|
||
|
|
node _T_644 = cat(_T_643, _T_642) @[lib.scala 105:14]
|
||
|
|
node _T_645 = cat(_T_410[13], _T_410[12]) @[lib.scala 105:14]
|
||
|
|
node _T_646 = cat(_T_410[15], _T_410[14]) @[lib.scala 105:14]
|
||
|
|
node _T_647 = cat(_T_646, _T_645) @[lib.scala 105:14]
|
||
|
|
node _T_648 = cat(_T_647, _T_644) @[lib.scala 105:14]
|
||
|
|
node _T_649 = cat(_T_648, _T_641) @[lib.scala 105:14]
|
||
|
|
node _T_650 = cat(_T_410[17], _T_410[16]) @[lib.scala 105:14]
|
||
|
|
node _T_651 = cat(_T_410[19], _T_410[18]) @[lib.scala 105:14]
|
||
|
|
node _T_652 = cat(_T_651, _T_650) @[lib.scala 105:14]
|
||
|
|
node _T_653 = cat(_T_410[21], _T_410[20]) @[lib.scala 105:14]
|
||
|
|
node _T_654 = cat(_T_410[23], _T_410[22]) @[lib.scala 105:14]
|
||
|
|
node _T_655 = cat(_T_654, _T_653) @[lib.scala 105:14]
|
||
|
|
node _T_656 = cat(_T_655, _T_652) @[lib.scala 105:14]
|
||
|
|
node _T_657 = cat(_T_410[25], _T_410[24]) @[lib.scala 105:14]
|
||
|
|
node _T_658 = cat(_T_410[27], _T_410[26]) @[lib.scala 105:14]
|
||
|
|
node _T_659 = cat(_T_658, _T_657) @[lib.scala 105:14]
|
||
|
|
node _T_660 = cat(_T_410[29], _T_410[28]) @[lib.scala 105:14]
|
||
|
|
node _T_661 = cat(_T_410[31], _T_410[30]) @[lib.scala 105:14]
|
||
|
|
node _T_662 = cat(_T_661, _T_660) @[lib.scala 105:14]
|
||
|
|
node _T_663 = cat(_T_662, _T_659) @[lib.scala 105:14]
|
||
|
|
node _T_664 = cat(_T_663, _T_656) @[lib.scala 105:14]
|
||
|
|
node _T_665 = cat(_T_664, _T_649) @[lib.scala 105:14]
|
||
|
|
node _T_666 = andr(_T_665) @[lib.scala 105:25]
|
||
|
|
node _T_667 = and(_T_408, _T_666) @[dec_trigger.scala 15:109]
|
||
|
|
node _T_668 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83]
|
||
|
|
node _T_669 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
||
|
|
wire _T_670 : UInt<1>[32] @[lib.scala 100:24]
|
||
|
|
node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45]
|
||
|
|
node _T_672 = not(_T_671) @[lib.scala 101:39]
|
||
|
|
node _T_673 = and(_T_669, _T_672) @[lib.scala 101:37]
|
||
|
|
node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48]
|
||
|
|
node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 102:60]
|
||
|
|
node _T_676 = eq(_T_674, _T_675) @[lib.scala 102:52]
|
||
|
|
node _T_677 = or(_T_673, _T_676) @[lib.scala 102:41]
|
||
|
|
_T_670[0] <= _T_677 @[lib.scala 102:18]
|
||
|
|
node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28]
|
||
|
|
node _T_679 = andr(_T_678) @[lib.scala 104:36]
|
||
|
|
node _T_680 = and(_T_679, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74]
|
||
|
|
node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 104:86]
|
||
|
|
node _T_683 = eq(_T_681, _T_682) @[lib.scala 104:78]
|
||
|
|
node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[lib.scala 104:23]
|
||
|
|
_T_670[1] <= _T_684 @[lib.scala 104:17]
|
||
|
|
node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28]
|
||
|
|
node _T_686 = andr(_T_685) @[lib.scala 104:36]
|
||
|
|
node _T_687 = and(_T_686, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74]
|
||
|
|
node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 104:86]
|
||
|
|
node _T_690 = eq(_T_688, _T_689) @[lib.scala 104:78]
|
||
|
|
node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[lib.scala 104:23]
|
||
|
|
_T_670[2] <= _T_691 @[lib.scala 104:17]
|
||
|
|
node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28]
|
||
|
|
node _T_693 = andr(_T_692) @[lib.scala 104:36]
|
||
|
|
node _T_694 = and(_T_693, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74]
|
||
|
|
node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 104:86]
|
||
|
|
node _T_697 = eq(_T_695, _T_696) @[lib.scala 104:78]
|
||
|
|
node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[lib.scala 104:23]
|
||
|
|
_T_670[3] <= _T_698 @[lib.scala 104:17]
|
||
|
|
node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28]
|
||
|
|
node _T_700 = andr(_T_699) @[lib.scala 104:36]
|
||
|
|
node _T_701 = and(_T_700, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74]
|
||
|
|
node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 104:86]
|
||
|
|
node _T_704 = eq(_T_702, _T_703) @[lib.scala 104:78]
|
||
|
|
node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[lib.scala 104:23]
|
||
|
|
_T_670[4] <= _T_705 @[lib.scala 104:17]
|
||
|
|
node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28]
|
||
|
|
node _T_707 = andr(_T_706) @[lib.scala 104:36]
|
||
|
|
node _T_708 = and(_T_707, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74]
|
||
|
|
node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 104:86]
|
||
|
|
node _T_711 = eq(_T_709, _T_710) @[lib.scala 104:78]
|
||
|
|
node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[lib.scala 104:23]
|
||
|
|
_T_670[5] <= _T_712 @[lib.scala 104:17]
|
||
|
|
node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28]
|
||
|
|
node _T_714 = andr(_T_713) @[lib.scala 104:36]
|
||
|
|
node _T_715 = and(_T_714, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74]
|
||
|
|
node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 104:86]
|
||
|
|
node _T_718 = eq(_T_716, _T_717) @[lib.scala 104:78]
|
||
|
|
node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[lib.scala 104:23]
|
||
|
|
_T_670[6] <= _T_719 @[lib.scala 104:17]
|
||
|
|
node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28]
|
||
|
|
node _T_721 = andr(_T_720) @[lib.scala 104:36]
|
||
|
|
node _T_722 = and(_T_721, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74]
|
||
|
|
node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 104:86]
|
||
|
|
node _T_725 = eq(_T_723, _T_724) @[lib.scala 104:78]
|
||
|
|
node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[lib.scala 104:23]
|
||
|
|
_T_670[7] <= _T_726 @[lib.scala 104:17]
|
||
|
|
node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28]
|
||
|
|
node _T_728 = andr(_T_727) @[lib.scala 104:36]
|
||
|
|
node _T_729 = and(_T_728, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74]
|
||
|
|
node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 104:86]
|
||
|
|
node _T_732 = eq(_T_730, _T_731) @[lib.scala 104:78]
|
||
|
|
node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[lib.scala 104:23]
|
||
|
|
_T_670[8] <= _T_733 @[lib.scala 104:17]
|
||
|
|
node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28]
|
||
|
|
node _T_735 = andr(_T_734) @[lib.scala 104:36]
|
||
|
|
node _T_736 = and(_T_735, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74]
|
||
|
|
node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 104:86]
|
||
|
|
node _T_739 = eq(_T_737, _T_738) @[lib.scala 104:78]
|
||
|
|
node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[lib.scala 104:23]
|
||
|
|
_T_670[9] <= _T_740 @[lib.scala 104:17]
|
||
|
|
node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28]
|
||
|
|
node _T_742 = andr(_T_741) @[lib.scala 104:36]
|
||
|
|
node _T_743 = and(_T_742, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74]
|
||
|
|
node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 104:86]
|
||
|
|
node _T_746 = eq(_T_744, _T_745) @[lib.scala 104:78]
|
||
|
|
node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[lib.scala 104:23]
|
||
|
|
_T_670[10] <= _T_747 @[lib.scala 104:17]
|
||
|
|
node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28]
|
||
|
|
node _T_749 = andr(_T_748) @[lib.scala 104:36]
|
||
|
|
node _T_750 = and(_T_749, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74]
|
||
|
|
node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 104:86]
|
||
|
|
node _T_753 = eq(_T_751, _T_752) @[lib.scala 104:78]
|
||
|
|
node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[lib.scala 104:23]
|
||
|
|
_T_670[11] <= _T_754 @[lib.scala 104:17]
|
||
|
|
node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28]
|
||
|
|
node _T_756 = andr(_T_755) @[lib.scala 104:36]
|
||
|
|
node _T_757 = and(_T_756, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74]
|
||
|
|
node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 104:86]
|
||
|
|
node _T_760 = eq(_T_758, _T_759) @[lib.scala 104:78]
|
||
|
|
node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[lib.scala 104:23]
|
||
|
|
_T_670[12] <= _T_761 @[lib.scala 104:17]
|
||
|
|
node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28]
|
||
|
|
node _T_763 = andr(_T_762) @[lib.scala 104:36]
|
||
|
|
node _T_764 = and(_T_763, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74]
|
||
|
|
node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 104:86]
|
||
|
|
node _T_767 = eq(_T_765, _T_766) @[lib.scala 104:78]
|
||
|
|
node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[lib.scala 104:23]
|
||
|
|
_T_670[13] <= _T_768 @[lib.scala 104:17]
|
||
|
|
node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28]
|
||
|
|
node _T_770 = andr(_T_769) @[lib.scala 104:36]
|
||
|
|
node _T_771 = and(_T_770, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74]
|
||
|
|
node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 104:86]
|
||
|
|
node _T_774 = eq(_T_772, _T_773) @[lib.scala 104:78]
|
||
|
|
node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[lib.scala 104:23]
|
||
|
|
_T_670[14] <= _T_775 @[lib.scala 104:17]
|
||
|
|
node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28]
|
||
|
|
node _T_777 = andr(_T_776) @[lib.scala 104:36]
|
||
|
|
node _T_778 = and(_T_777, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74]
|
||
|
|
node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 104:86]
|
||
|
|
node _T_781 = eq(_T_779, _T_780) @[lib.scala 104:78]
|
||
|
|
node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[lib.scala 104:23]
|
||
|
|
_T_670[15] <= _T_782 @[lib.scala 104:17]
|
||
|
|
node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28]
|
||
|
|
node _T_784 = andr(_T_783) @[lib.scala 104:36]
|
||
|
|
node _T_785 = and(_T_784, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74]
|
||
|
|
node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 104:86]
|
||
|
|
node _T_788 = eq(_T_786, _T_787) @[lib.scala 104:78]
|
||
|
|
node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[lib.scala 104:23]
|
||
|
|
_T_670[16] <= _T_789 @[lib.scala 104:17]
|
||
|
|
node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28]
|
||
|
|
node _T_791 = andr(_T_790) @[lib.scala 104:36]
|
||
|
|
node _T_792 = and(_T_791, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74]
|
||
|
|
node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 104:86]
|
||
|
|
node _T_795 = eq(_T_793, _T_794) @[lib.scala 104:78]
|
||
|
|
node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[lib.scala 104:23]
|
||
|
|
_T_670[17] <= _T_796 @[lib.scala 104:17]
|
||
|
|
node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28]
|
||
|
|
node _T_798 = andr(_T_797) @[lib.scala 104:36]
|
||
|
|
node _T_799 = and(_T_798, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74]
|
||
|
|
node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 104:86]
|
||
|
|
node _T_802 = eq(_T_800, _T_801) @[lib.scala 104:78]
|
||
|
|
node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[lib.scala 104:23]
|
||
|
|
_T_670[18] <= _T_803 @[lib.scala 104:17]
|
||
|
|
node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28]
|
||
|
|
node _T_805 = andr(_T_804) @[lib.scala 104:36]
|
||
|
|
node _T_806 = and(_T_805, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74]
|
||
|
|
node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 104:86]
|
||
|
|
node _T_809 = eq(_T_807, _T_808) @[lib.scala 104:78]
|
||
|
|
node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[lib.scala 104:23]
|
||
|
|
_T_670[19] <= _T_810 @[lib.scala 104:17]
|
||
|
|
node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28]
|
||
|
|
node _T_812 = andr(_T_811) @[lib.scala 104:36]
|
||
|
|
node _T_813 = and(_T_812, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74]
|
||
|
|
node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 104:86]
|
||
|
|
node _T_816 = eq(_T_814, _T_815) @[lib.scala 104:78]
|
||
|
|
node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[lib.scala 104:23]
|
||
|
|
_T_670[20] <= _T_817 @[lib.scala 104:17]
|
||
|
|
node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28]
|
||
|
|
node _T_819 = andr(_T_818) @[lib.scala 104:36]
|
||
|
|
node _T_820 = and(_T_819, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74]
|
||
|
|
node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 104:86]
|
||
|
|
node _T_823 = eq(_T_821, _T_822) @[lib.scala 104:78]
|
||
|
|
node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[lib.scala 104:23]
|
||
|
|
_T_670[21] <= _T_824 @[lib.scala 104:17]
|
||
|
|
node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28]
|
||
|
|
node _T_826 = andr(_T_825) @[lib.scala 104:36]
|
||
|
|
node _T_827 = and(_T_826, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74]
|
||
|
|
node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 104:86]
|
||
|
|
node _T_830 = eq(_T_828, _T_829) @[lib.scala 104:78]
|
||
|
|
node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[lib.scala 104:23]
|
||
|
|
_T_670[22] <= _T_831 @[lib.scala 104:17]
|
||
|
|
node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28]
|
||
|
|
node _T_833 = andr(_T_832) @[lib.scala 104:36]
|
||
|
|
node _T_834 = and(_T_833, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74]
|
||
|
|
node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 104:86]
|
||
|
|
node _T_837 = eq(_T_835, _T_836) @[lib.scala 104:78]
|
||
|
|
node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[lib.scala 104:23]
|
||
|
|
_T_670[23] <= _T_838 @[lib.scala 104:17]
|
||
|
|
node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28]
|
||
|
|
node _T_840 = andr(_T_839) @[lib.scala 104:36]
|
||
|
|
node _T_841 = and(_T_840, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74]
|
||
|
|
node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 104:86]
|
||
|
|
node _T_844 = eq(_T_842, _T_843) @[lib.scala 104:78]
|
||
|
|
node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[lib.scala 104:23]
|
||
|
|
_T_670[24] <= _T_845 @[lib.scala 104:17]
|
||
|
|
node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28]
|
||
|
|
node _T_847 = andr(_T_846) @[lib.scala 104:36]
|
||
|
|
node _T_848 = and(_T_847, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74]
|
||
|
|
node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 104:86]
|
||
|
|
node _T_851 = eq(_T_849, _T_850) @[lib.scala 104:78]
|
||
|
|
node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[lib.scala 104:23]
|
||
|
|
_T_670[25] <= _T_852 @[lib.scala 104:17]
|
||
|
|
node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28]
|
||
|
|
node _T_854 = andr(_T_853) @[lib.scala 104:36]
|
||
|
|
node _T_855 = and(_T_854, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74]
|
||
|
|
node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 104:86]
|
||
|
|
node _T_858 = eq(_T_856, _T_857) @[lib.scala 104:78]
|
||
|
|
node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[lib.scala 104:23]
|
||
|
|
_T_670[26] <= _T_859 @[lib.scala 104:17]
|
||
|
|
node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28]
|
||
|
|
node _T_861 = andr(_T_860) @[lib.scala 104:36]
|
||
|
|
node _T_862 = and(_T_861, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74]
|
||
|
|
node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 104:86]
|
||
|
|
node _T_865 = eq(_T_863, _T_864) @[lib.scala 104:78]
|
||
|
|
node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[lib.scala 104:23]
|
||
|
|
_T_670[27] <= _T_866 @[lib.scala 104:17]
|
||
|
|
node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28]
|
||
|
|
node _T_868 = andr(_T_867) @[lib.scala 104:36]
|
||
|
|
node _T_869 = and(_T_868, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74]
|
||
|
|
node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 104:86]
|
||
|
|
node _T_872 = eq(_T_870, _T_871) @[lib.scala 104:78]
|
||
|
|
node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[lib.scala 104:23]
|
||
|
|
_T_670[28] <= _T_873 @[lib.scala 104:17]
|
||
|
|
node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28]
|
||
|
|
node _T_875 = andr(_T_874) @[lib.scala 104:36]
|
||
|
|
node _T_876 = and(_T_875, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74]
|
||
|
|
node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 104:86]
|
||
|
|
node _T_879 = eq(_T_877, _T_878) @[lib.scala 104:78]
|
||
|
|
node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[lib.scala 104:23]
|
||
|
|
_T_670[29] <= _T_880 @[lib.scala 104:17]
|
||
|
|
node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28]
|
||
|
|
node _T_882 = andr(_T_881) @[lib.scala 104:36]
|
||
|
|
node _T_883 = and(_T_882, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74]
|
||
|
|
node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 104:86]
|
||
|
|
node _T_886 = eq(_T_884, _T_885) @[lib.scala 104:78]
|
||
|
|
node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[lib.scala 104:23]
|
||
|
|
_T_670[30] <= _T_887 @[lib.scala 104:17]
|
||
|
|
node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28]
|
||
|
|
node _T_889 = andr(_T_888) @[lib.scala 104:36]
|
||
|
|
node _T_890 = and(_T_889, _T_673) @[lib.scala 104:41]
|
||
|
|
node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74]
|
||
|
|
node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 104:86]
|
||
|
|
node _T_893 = eq(_T_891, _T_892) @[lib.scala 104:78]
|
||
|
|
node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[lib.scala 104:23]
|
||
|
|
_T_670[31] <= _T_894 @[lib.scala 104:17]
|
||
|
|
node _T_895 = cat(_T_670[1], _T_670[0]) @[lib.scala 105:14]
|
||
|
|
node _T_896 = cat(_T_670[3], _T_670[2]) @[lib.scala 105:14]
|
||
|
|
node _T_897 = cat(_T_896, _T_895) @[lib.scala 105:14]
|
||
|
|
node _T_898 = cat(_T_670[5], _T_670[4]) @[lib.scala 105:14]
|
||
|
|
node _T_899 = cat(_T_670[7], _T_670[6]) @[lib.scala 105:14]
|
||
|
|
node _T_900 = cat(_T_899, _T_898) @[lib.scala 105:14]
|
||
|
|
node _T_901 = cat(_T_900, _T_897) @[lib.scala 105:14]
|
||
|
|
node _T_902 = cat(_T_670[9], _T_670[8]) @[lib.scala 105:14]
|
||
|
|
node _T_903 = cat(_T_670[11], _T_670[10]) @[lib.scala 105:14]
|
||
|
|
node _T_904 = cat(_T_903, _T_902) @[lib.scala 105:14]
|
||
|
|
node _T_905 = cat(_T_670[13], _T_670[12]) @[lib.scala 105:14]
|
||
|
|
node _T_906 = cat(_T_670[15], _T_670[14]) @[lib.scala 105:14]
|
||
|
|
node _T_907 = cat(_T_906, _T_905) @[lib.scala 105:14]
|
||
|
|
node _T_908 = cat(_T_907, _T_904) @[lib.scala 105:14]
|
||
|
|
node _T_909 = cat(_T_908, _T_901) @[lib.scala 105:14]
|
||
|
|
node _T_910 = cat(_T_670[17], _T_670[16]) @[lib.scala 105:14]
|
||
|
|
node _T_911 = cat(_T_670[19], _T_670[18]) @[lib.scala 105:14]
|
||
|
|
node _T_912 = cat(_T_911, _T_910) @[lib.scala 105:14]
|
||
|
|
node _T_913 = cat(_T_670[21], _T_670[20]) @[lib.scala 105:14]
|
||
|
|
node _T_914 = cat(_T_670[23], _T_670[22]) @[lib.scala 105:14]
|
||
|
|
node _T_915 = cat(_T_914, _T_913) @[lib.scala 105:14]
|
||
|
|
node _T_916 = cat(_T_915, _T_912) @[lib.scala 105:14]
|
||
|
|
node _T_917 = cat(_T_670[25], _T_670[24]) @[lib.scala 105:14]
|
||
|
|
node _T_918 = cat(_T_670[27], _T_670[26]) @[lib.scala 105:14]
|
||
|
|
node _T_919 = cat(_T_918, _T_917) @[lib.scala 105:14]
|
||
|
|
node _T_920 = cat(_T_670[29], _T_670[28]) @[lib.scala 105:14]
|
||
|
|
node _T_921 = cat(_T_670[31], _T_670[30]) @[lib.scala 105:14]
|
||
|
|
node _T_922 = cat(_T_921, _T_920) @[lib.scala 105:14]
|
||
|
|
node _T_923 = cat(_T_922, _T_919) @[lib.scala 105:14]
|
||
|
|
node _T_924 = cat(_T_923, _T_916) @[lib.scala 105:14]
|
||
|
|
node _T_925 = cat(_T_924, _T_909) @[lib.scala 105:14]
|
||
|
|
node _T_926 = andr(_T_925) @[lib.scala 105:25]
|
||
|
|
node _T_927 = and(_T_668, _T_926) @[dec_trigger.scala 15:109]
|
||
|
|
node _T_928 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83]
|
||
|
|
node _T_929 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
||
|
|
wire _T_930 : UInt<1>[32] @[lib.scala 100:24]
|
||
|
|
node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45]
|
||
|
|
node _T_932 = not(_T_931) @[lib.scala 101:39]
|
||
|
|
node _T_933 = and(_T_929, _T_932) @[lib.scala 101:37]
|
||
|
|
node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48]
|
||
|
|
node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 102:60]
|
||
|
|
node _T_936 = eq(_T_934, _T_935) @[lib.scala 102:52]
|
||
|
|
node _T_937 = or(_T_933, _T_936) @[lib.scala 102:41]
|
||
|
|
_T_930[0] <= _T_937 @[lib.scala 102:18]
|
||
|
|
node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28]
|
||
|
|
node _T_939 = andr(_T_938) @[lib.scala 104:36]
|
||
|
|
node _T_940 = and(_T_939, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74]
|
||
|
|
node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 104:86]
|
||
|
|
node _T_943 = eq(_T_941, _T_942) @[lib.scala 104:78]
|
||
|
|
node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 104:23]
|
||
|
|
_T_930[1] <= _T_944 @[lib.scala 104:17]
|
||
|
|
node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28]
|
||
|
|
node _T_946 = andr(_T_945) @[lib.scala 104:36]
|
||
|
|
node _T_947 = and(_T_946, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74]
|
||
|
|
node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 104:86]
|
||
|
|
node _T_950 = eq(_T_948, _T_949) @[lib.scala 104:78]
|
||
|
|
node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 104:23]
|
||
|
|
_T_930[2] <= _T_951 @[lib.scala 104:17]
|
||
|
|
node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28]
|
||
|
|
node _T_953 = andr(_T_952) @[lib.scala 104:36]
|
||
|
|
node _T_954 = and(_T_953, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74]
|
||
|
|
node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 104:86]
|
||
|
|
node _T_957 = eq(_T_955, _T_956) @[lib.scala 104:78]
|
||
|
|
node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 104:23]
|
||
|
|
_T_930[3] <= _T_958 @[lib.scala 104:17]
|
||
|
|
node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28]
|
||
|
|
node _T_960 = andr(_T_959) @[lib.scala 104:36]
|
||
|
|
node _T_961 = and(_T_960, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74]
|
||
|
|
node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 104:86]
|
||
|
|
node _T_964 = eq(_T_962, _T_963) @[lib.scala 104:78]
|
||
|
|
node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 104:23]
|
||
|
|
_T_930[4] <= _T_965 @[lib.scala 104:17]
|
||
|
|
node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28]
|
||
|
|
node _T_967 = andr(_T_966) @[lib.scala 104:36]
|
||
|
|
node _T_968 = and(_T_967, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74]
|
||
|
|
node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 104:86]
|
||
|
|
node _T_971 = eq(_T_969, _T_970) @[lib.scala 104:78]
|
||
|
|
node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 104:23]
|
||
|
|
_T_930[5] <= _T_972 @[lib.scala 104:17]
|
||
|
|
node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28]
|
||
|
|
node _T_974 = andr(_T_973) @[lib.scala 104:36]
|
||
|
|
node _T_975 = and(_T_974, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74]
|
||
|
|
node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 104:86]
|
||
|
|
node _T_978 = eq(_T_976, _T_977) @[lib.scala 104:78]
|
||
|
|
node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 104:23]
|
||
|
|
_T_930[6] <= _T_979 @[lib.scala 104:17]
|
||
|
|
node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28]
|
||
|
|
node _T_981 = andr(_T_980) @[lib.scala 104:36]
|
||
|
|
node _T_982 = and(_T_981, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74]
|
||
|
|
node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 104:86]
|
||
|
|
node _T_985 = eq(_T_983, _T_984) @[lib.scala 104:78]
|
||
|
|
node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 104:23]
|
||
|
|
_T_930[7] <= _T_986 @[lib.scala 104:17]
|
||
|
|
node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28]
|
||
|
|
node _T_988 = andr(_T_987) @[lib.scala 104:36]
|
||
|
|
node _T_989 = and(_T_988, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74]
|
||
|
|
node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 104:86]
|
||
|
|
node _T_992 = eq(_T_990, _T_991) @[lib.scala 104:78]
|
||
|
|
node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 104:23]
|
||
|
|
_T_930[8] <= _T_993 @[lib.scala 104:17]
|
||
|
|
node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28]
|
||
|
|
node _T_995 = andr(_T_994) @[lib.scala 104:36]
|
||
|
|
node _T_996 = and(_T_995, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74]
|
||
|
|
node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 104:86]
|
||
|
|
node _T_999 = eq(_T_997, _T_998) @[lib.scala 104:78]
|
||
|
|
node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 104:23]
|
||
|
|
_T_930[9] <= _T_1000 @[lib.scala 104:17]
|
||
|
|
node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1002 = andr(_T_1001) @[lib.scala 104:36]
|
||
|
|
node _T_1003 = and(_T_1002, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74]
|
||
|
|
node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 104:86]
|
||
|
|
node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 104:78]
|
||
|
|
node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 104:23]
|
||
|
|
_T_930[10] <= _T_1007 @[lib.scala 104:17]
|
||
|
|
node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1009 = andr(_T_1008) @[lib.scala 104:36]
|
||
|
|
node _T_1010 = and(_T_1009, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74]
|
||
|
|
node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 104:86]
|
||
|
|
node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 104:78]
|
||
|
|
node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 104:23]
|
||
|
|
_T_930[11] <= _T_1014 @[lib.scala 104:17]
|
||
|
|
node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1016 = andr(_T_1015) @[lib.scala 104:36]
|
||
|
|
node _T_1017 = and(_T_1016, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74]
|
||
|
|
node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 104:86]
|
||
|
|
node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 104:78]
|
||
|
|
node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 104:23]
|
||
|
|
_T_930[12] <= _T_1021 @[lib.scala 104:17]
|
||
|
|
node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1023 = andr(_T_1022) @[lib.scala 104:36]
|
||
|
|
node _T_1024 = and(_T_1023, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74]
|
||
|
|
node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 104:86]
|
||
|
|
node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 104:78]
|
||
|
|
node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 104:23]
|
||
|
|
_T_930[13] <= _T_1028 @[lib.scala 104:17]
|
||
|
|
node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1030 = andr(_T_1029) @[lib.scala 104:36]
|
||
|
|
node _T_1031 = and(_T_1030, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74]
|
||
|
|
node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 104:86]
|
||
|
|
node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 104:78]
|
||
|
|
node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 104:23]
|
||
|
|
_T_930[14] <= _T_1035 @[lib.scala 104:17]
|
||
|
|
node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1037 = andr(_T_1036) @[lib.scala 104:36]
|
||
|
|
node _T_1038 = and(_T_1037, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74]
|
||
|
|
node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 104:86]
|
||
|
|
node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 104:78]
|
||
|
|
node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 104:23]
|
||
|
|
_T_930[15] <= _T_1042 @[lib.scala 104:17]
|
||
|
|
node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1044 = andr(_T_1043) @[lib.scala 104:36]
|
||
|
|
node _T_1045 = and(_T_1044, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74]
|
||
|
|
node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 104:86]
|
||
|
|
node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 104:78]
|
||
|
|
node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 104:23]
|
||
|
|
_T_930[16] <= _T_1049 @[lib.scala 104:17]
|
||
|
|
node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1051 = andr(_T_1050) @[lib.scala 104:36]
|
||
|
|
node _T_1052 = and(_T_1051, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74]
|
||
|
|
node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 104:86]
|
||
|
|
node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 104:78]
|
||
|
|
node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 104:23]
|
||
|
|
_T_930[17] <= _T_1056 @[lib.scala 104:17]
|
||
|
|
node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1058 = andr(_T_1057) @[lib.scala 104:36]
|
||
|
|
node _T_1059 = and(_T_1058, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74]
|
||
|
|
node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 104:86]
|
||
|
|
node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 104:78]
|
||
|
|
node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 104:23]
|
||
|
|
_T_930[18] <= _T_1063 @[lib.scala 104:17]
|
||
|
|
node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1065 = andr(_T_1064) @[lib.scala 104:36]
|
||
|
|
node _T_1066 = and(_T_1065, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74]
|
||
|
|
node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 104:86]
|
||
|
|
node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 104:78]
|
||
|
|
node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 104:23]
|
||
|
|
_T_930[19] <= _T_1070 @[lib.scala 104:17]
|
||
|
|
node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1072 = andr(_T_1071) @[lib.scala 104:36]
|
||
|
|
node _T_1073 = and(_T_1072, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74]
|
||
|
|
node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 104:86]
|
||
|
|
node _T_1076 = eq(_T_1074, _T_1075) @[lib.scala 104:78]
|
||
|
|
node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[lib.scala 104:23]
|
||
|
|
_T_930[20] <= _T_1077 @[lib.scala 104:17]
|
||
|
|
node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1079 = andr(_T_1078) @[lib.scala 104:36]
|
||
|
|
node _T_1080 = and(_T_1079, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74]
|
||
|
|
node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 104:86]
|
||
|
|
node _T_1083 = eq(_T_1081, _T_1082) @[lib.scala 104:78]
|
||
|
|
node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[lib.scala 104:23]
|
||
|
|
_T_930[21] <= _T_1084 @[lib.scala 104:17]
|
||
|
|
node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1086 = andr(_T_1085) @[lib.scala 104:36]
|
||
|
|
node _T_1087 = and(_T_1086, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74]
|
||
|
|
node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 104:86]
|
||
|
|
node _T_1090 = eq(_T_1088, _T_1089) @[lib.scala 104:78]
|
||
|
|
node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[lib.scala 104:23]
|
||
|
|
_T_930[22] <= _T_1091 @[lib.scala 104:17]
|
||
|
|
node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1093 = andr(_T_1092) @[lib.scala 104:36]
|
||
|
|
node _T_1094 = and(_T_1093, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74]
|
||
|
|
node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 104:86]
|
||
|
|
node _T_1097 = eq(_T_1095, _T_1096) @[lib.scala 104:78]
|
||
|
|
node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[lib.scala 104:23]
|
||
|
|
_T_930[23] <= _T_1098 @[lib.scala 104:17]
|
||
|
|
node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1100 = andr(_T_1099) @[lib.scala 104:36]
|
||
|
|
node _T_1101 = and(_T_1100, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74]
|
||
|
|
node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 104:86]
|
||
|
|
node _T_1104 = eq(_T_1102, _T_1103) @[lib.scala 104:78]
|
||
|
|
node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[lib.scala 104:23]
|
||
|
|
_T_930[24] <= _T_1105 @[lib.scala 104:17]
|
||
|
|
node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1107 = andr(_T_1106) @[lib.scala 104:36]
|
||
|
|
node _T_1108 = and(_T_1107, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74]
|
||
|
|
node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 104:86]
|
||
|
|
node _T_1111 = eq(_T_1109, _T_1110) @[lib.scala 104:78]
|
||
|
|
node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[lib.scala 104:23]
|
||
|
|
_T_930[25] <= _T_1112 @[lib.scala 104:17]
|
||
|
|
node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1114 = andr(_T_1113) @[lib.scala 104:36]
|
||
|
|
node _T_1115 = and(_T_1114, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74]
|
||
|
|
node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 104:86]
|
||
|
|
node _T_1118 = eq(_T_1116, _T_1117) @[lib.scala 104:78]
|
||
|
|
node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[lib.scala 104:23]
|
||
|
|
_T_930[26] <= _T_1119 @[lib.scala 104:17]
|
||
|
|
node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1121 = andr(_T_1120) @[lib.scala 104:36]
|
||
|
|
node _T_1122 = and(_T_1121, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74]
|
||
|
|
node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 104:86]
|
||
|
|
node _T_1125 = eq(_T_1123, _T_1124) @[lib.scala 104:78]
|
||
|
|
node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[lib.scala 104:23]
|
||
|
|
_T_930[27] <= _T_1126 @[lib.scala 104:17]
|
||
|
|
node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1128 = andr(_T_1127) @[lib.scala 104:36]
|
||
|
|
node _T_1129 = and(_T_1128, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74]
|
||
|
|
node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 104:86]
|
||
|
|
node _T_1132 = eq(_T_1130, _T_1131) @[lib.scala 104:78]
|
||
|
|
node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[lib.scala 104:23]
|
||
|
|
_T_930[28] <= _T_1133 @[lib.scala 104:17]
|
||
|
|
node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1135 = andr(_T_1134) @[lib.scala 104:36]
|
||
|
|
node _T_1136 = and(_T_1135, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74]
|
||
|
|
node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 104:86]
|
||
|
|
node _T_1139 = eq(_T_1137, _T_1138) @[lib.scala 104:78]
|
||
|
|
node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[lib.scala 104:23]
|
||
|
|
_T_930[29] <= _T_1140 @[lib.scala 104:17]
|
||
|
|
node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1142 = andr(_T_1141) @[lib.scala 104:36]
|
||
|
|
node _T_1143 = and(_T_1142, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74]
|
||
|
|
node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 104:86]
|
||
|
|
node _T_1146 = eq(_T_1144, _T_1145) @[lib.scala 104:78]
|
||
|
|
node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[lib.scala 104:23]
|
||
|
|
_T_930[30] <= _T_1147 @[lib.scala 104:17]
|
||
|
|
node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28]
|
||
|
|
node _T_1149 = andr(_T_1148) @[lib.scala 104:36]
|
||
|
|
node _T_1150 = and(_T_1149, _T_933) @[lib.scala 104:41]
|
||
|
|
node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74]
|
||
|
|
node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 104:86]
|
||
|
|
node _T_1153 = eq(_T_1151, _T_1152) @[lib.scala 104:78]
|
||
|
|
node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[lib.scala 104:23]
|
||
|
|
_T_930[31] <= _T_1154 @[lib.scala 104:17]
|
||
|
|
node _T_1155 = cat(_T_930[1], _T_930[0]) @[lib.scala 105:14]
|
||
|
|
node _T_1156 = cat(_T_930[3], _T_930[2]) @[lib.scala 105:14]
|
||
|
|
node _T_1157 = cat(_T_1156, _T_1155) @[lib.scala 105:14]
|
||
|
|
node _T_1158 = cat(_T_930[5], _T_930[4]) @[lib.scala 105:14]
|
||
|
|
node _T_1159 = cat(_T_930[7], _T_930[6]) @[lib.scala 105:14]
|
||
|
|
node _T_1160 = cat(_T_1159, _T_1158) @[lib.scala 105:14]
|
||
|
|
node _T_1161 = cat(_T_1160, _T_1157) @[lib.scala 105:14]
|
||
|
|
node _T_1162 = cat(_T_930[9], _T_930[8]) @[lib.scala 105:14]
|
||
|
|
node _T_1163 = cat(_T_930[11], _T_930[10]) @[lib.scala 105:14]
|
||
|
|
node _T_1164 = cat(_T_1163, _T_1162) @[lib.scala 105:14]
|
||
|
|
node _T_1165 = cat(_T_930[13], _T_930[12]) @[lib.scala 105:14]
|
||
|
|
node _T_1166 = cat(_T_930[15], _T_930[14]) @[lib.scala 105:14]
|
||
|
|
node _T_1167 = cat(_T_1166, _T_1165) @[lib.scala 105:14]
|
||
|
|
node _T_1168 = cat(_T_1167, _T_1164) @[lib.scala 105:14]
|
||
|
|
node _T_1169 = cat(_T_1168, _T_1161) @[lib.scala 105:14]
|
||
|
|
node _T_1170 = cat(_T_930[17], _T_930[16]) @[lib.scala 105:14]
|
||
|
|
node _T_1171 = cat(_T_930[19], _T_930[18]) @[lib.scala 105:14]
|
||
|
|
node _T_1172 = cat(_T_1171, _T_1170) @[lib.scala 105:14]
|
||
|
|
node _T_1173 = cat(_T_930[21], _T_930[20]) @[lib.scala 105:14]
|
||
|
|
node _T_1174 = cat(_T_930[23], _T_930[22]) @[lib.scala 105:14]
|
||
|
|
node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 105:14]
|
||
|
|
node _T_1176 = cat(_T_1175, _T_1172) @[lib.scala 105:14]
|
||
|
|
node _T_1177 = cat(_T_930[25], _T_930[24]) @[lib.scala 105:14]
|
||
|
|
node _T_1178 = cat(_T_930[27], _T_930[26]) @[lib.scala 105:14]
|
||
|
|
node _T_1179 = cat(_T_1178, _T_1177) @[lib.scala 105:14]
|
||
|
|
node _T_1180 = cat(_T_930[29], _T_930[28]) @[lib.scala 105:14]
|
||
|
|
node _T_1181 = cat(_T_930[31], _T_930[30]) @[lib.scala 105:14]
|
||
|
|
node _T_1182 = cat(_T_1181, _T_1180) @[lib.scala 105:14]
|
||
|
|
node _T_1183 = cat(_T_1182, _T_1179) @[lib.scala 105:14]
|
||
|
|
node _T_1184 = cat(_T_1183, _T_1176) @[lib.scala 105:14]
|
||
|
|
node _T_1185 = cat(_T_1184, _T_1169) @[lib.scala 105:14]
|
||
|
|
node _T_1186 = andr(_T_1185) @[lib.scala 105:25]
|
||
|
|
node _T_1187 = and(_T_928, _T_1186) @[dec_trigger.scala 15:109]
|
||
|
|
node _T_1188 = cat(_T_1187, _T_927) @[Cat.scala 29:58]
|
||
|
|
node _T_1189 = cat(_T_1188, _T_667) @[Cat.scala 29:58]
|
||
|
|
node _T_1190 = cat(_T_1189, _T_407) @[Cat.scala 29:58]
|
||
|
|
io.dec_i0_trigger_match_d <= _T_1190 @[dec_trigger.scala 15:29]
|
||
|
|
|
||
|
|
module dec :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt
|
||
|
|
|
||
|
|
wire dec_i0_inst_wb1 : UInt<32>
|
||
|
|
dec_i0_inst_wb1 <= UInt<1>("h00")
|
||
|
|
wire dec_i0_pc_wb1 : UInt<32>
|
||
|
|
dec_i0_pc_wb1 <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_i0_valid_wb1 : UInt<1>
|
||
|
|
dec_tlu_i0_valid_wb1 <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_int_valid_wb1 : UInt<1>
|
||
|
|
dec_tlu_int_valid_wb1 <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_exc_cause_wb1 : UInt<5>
|
||
|
|
dec_tlu_exc_cause_wb1 <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_mtval_wb1 : UInt<32>
|
||
|
|
dec_tlu_mtval_wb1 <= UInt<1>("h00")
|
||
|
|
wire dec_tlu_i0_exc_valid_wb1 : UInt<1>
|
||
|
|
dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00")
|
||
|
|
inst instbuff of dec_ib_ctl @[dec.scala 117:24]
|
||
|
|
instbuff.clock <= clock
|
||
|
|
instbuff.reset <= reset
|
||
|
|
inst decode of dec_decode_ctl @[dec.scala 118:22]
|
||
|
|
decode.clock <= clock
|
||
|
|
decode.reset <= reset
|
||
|
|
inst gpr of dec_gpr_ctl @[dec.scala 119:19]
|
||
|
|
gpr.clock <= clock
|
||
|
|
gpr.reset <= reset
|
||
|
|
inst tlu of dec_tlu_ctl @[dec.scala 120:19]
|
||
|
|
tlu.clock <= clock
|
||
|
|
tlu.reset <= reset
|
||
|
|
inst dec_trigger of dec_trigger @[dec.scala 121:27]
|
||
|
|
dec_trigger.clock <= clock
|
||
|
|
dec_trigger.reset <= reset
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_icaf_f1 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 125:22]
|
||
|
|
instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 125:22]
|
||
|
|
io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 126:22]
|
||
|
|
io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 126:22]
|
||
|
|
instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 127:22]
|
||
|
|
instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 127:22]
|
||
|
|
instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 127:22]
|
||
|
|
instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 127:22]
|
||
|
|
dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 128:30]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 129:34]
|
||
|
|
dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 129:34]
|
||
|
|
decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 133:21]
|
||
|
|
io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 133:21]
|
||
|
|
decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 135:23]
|
||
|
|
decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= decode.io.decode_exu.dec_i0_rs2_bypass_data_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= decode.io.decode_exu.dec_i0_rs1_bypass_data_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 135:23]
|
||
|
|
io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 135:23]
|
||
|
|
decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 136:20]
|
||
|
|
io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 136:20]
|
||
|
|
io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 136:20]
|
||
|
|
io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 136:20]
|
||
|
|
io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 137:20]
|
||
|
|
io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 137:20]
|
||
|
|
io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 137:20]
|
||
|
|
io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 137:20]
|
||
|
|
decode.io.dctl_dma.dma_dccm_stall_any <= io.dec_dma.dctl_dma.dma_dccm_stall_any @[dec.scala 138:22]
|
||
|
|
decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 139:48]
|
||
|
|
decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 140:48]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_data <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 141:26]
|
||
|
|
decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 141:26]
|
||
|
|
decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 142:48]
|
||
|
|
decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 143:48]
|
||
|
|
decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 144:48]
|
||
|
|
decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 145:48]
|
||
|
|
decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 146:48]
|
||
|
|
decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 147:48]
|
||
|
|
decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 148:48]
|
||
|
|
decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 149:48]
|
||
|
|
decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 150:22]
|
||
|
|
decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 151:48]
|
||
|
|
decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[dec.scala 152:48]
|
||
|
|
decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 153:48]
|
||
|
|
decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 154:48]
|
||
|
|
decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 155:48]
|
||
|
|
decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 156:48]
|
||
|
|
decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 157:48]
|
||
|
|
decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 158:48]
|
||
|
|
decode.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 159:48]
|
||
|
|
decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 160:48]
|
||
|
|
decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 161:48]
|
||
|
|
decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 162:48]
|
||
|
|
decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 163:48]
|
||
|
|
decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 164:48]
|
||
|
|
decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 165:48]
|
||
|
|
decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 166:48]
|
||
|
|
decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 167:48]
|
||
|
|
decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 168:48]
|
||
|
|
decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 169:48]
|
||
|
|
decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 170:48]
|
||
|
|
decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 171:48]
|
||
|
|
decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 172:48]
|
||
|
|
decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 173:48]
|
||
|
|
decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 174:48]
|
||
|
|
decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 175:48]
|
||
|
|
decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 176:48]
|
||
|
|
decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 177:48]
|
||
|
|
decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 178:48]
|
||
|
|
decode.io.free_clk <= io.free_clk @[dec.scala 179:48]
|
||
|
|
decode.io.active_clk <= io.active_clk @[dec.scala 180:48]
|
||
|
|
decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 181:48]
|
||
|
|
decode.io.scan_mode <= io.scan_mode @[dec.scala 182:48]
|
||
|
|
dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[dec.scala 183:40]
|
||
|
|
dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[dec.scala 184:40]
|
||
|
|
io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 185:40]
|
||
|
|
io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 185:40]
|
||
|
|
io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 185:40]
|
||
|
|
io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 186:40]
|
||
|
|
io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 187:40]
|
||
|
|
io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 188:40]
|
||
|
|
gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 189:23]
|
||
|
|
gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 190:23]
|
||
|
|
gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 191:23]
|
||
|
|
gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 192:23]
|
||
|
|
gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 193:23]
|
||
|
|
gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 194:23]
|
||
|
|
gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 195:23]
|
||
|
|
gpr.io.wd1 <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[dec.scala 196:23]
|
||
|
|
gpr.io.wen2 <= io.exu_div_wren @[dec.scala 197:23]
|
||
|
|
gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 198:23]
|
||
|
|
gpr.io.wd2 <= io.exu_div_result @[dec.scala 199:23]
|
||
|
|
gpr.io.scan_mode <= io.scan_mode @[dec.scala 200:23]
|
||
|
|
io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 201:22]
|
||
|
|
io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 201:22]
|
||
|
|
tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 202:18]
|
||
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 202:18]
|
||
|
|
tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 203:18]
|
||
|
|
io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 203:18]
|
||
|
|
io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 203:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 204:18]
|
||
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 204:18]
|
||
|
|
tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 205:18]
|
||
|
|
io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 205:18]
|
||
|
|
io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 205:18]
|
||
|
|
io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 205:18]
|
||
|
|
tlu.io.tlu_dma.dma_iccm_stall_any <= io.dec_dma.tlu_dma.dma_iccm_stall_any @[dec.scala 206:18]
|
||
|
|
tlu.io.tlu_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dec.scala 206:18]
|
||
|
|
io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= tlu.io.tlu_dma.dec_tlu_dma_qos_prty @[dec.scala 206:18]
|
||
|
|
tlu.io.tlu_dma.dma_pmu_any_write <= io.dec_dma.tlu_dma.dma_pmu_any_write @[dec.scala 206:18]
|
||
|
|
tlu.io.tlu_dma.dma_pmu_any_read <= io.dec_dma.tlu_dma.dma_pmu_any_read @[dec.scala 206:18]
|
||
|
|
tlu.io.tlu_dma.dma_pmu_dccm_write <= io.dec_dma.tlu_dma.dma_pmu_dccm_write @[dec.scala 206:18]
|
||
|
|
tlu.io.tlu_dma.dma_pmu_dccm_read <= io.dec_dma.tlu_dma.dma_pmu_dccm_read @[dec.scala 206:18]
|
||
|
|
tlu.io.active_clk <= io.active_clk @[dec.scala 207:45]
|
||
|
|
tlu.io.free_clk <= io.free_clk @[dec.scala 208:45]
|
||
|
|
tlu.io.scan_mode <= io.scan_mode @[dec.scala 209:45]
|
||
|
|
tlu.io.rst_vec <= io.rst_vec @[dec.scala 210:45]
|
||
|
|
tlu.io.nmi_int <= io.nmi_int @[dec.scala 211:45]
|
||
|
|
tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 212:45]
|
||
|
|
tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 213:45]
|
||
|
|
tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 214:45]
|
||
|
|
tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 215:45]
|
||
|
|
tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 216:45]
|
||
|
|
tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 217:45]
|
||
|
|
tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 218:45]
|
||
|
|
tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 219:45]
|
||
|
|
tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 220:45]
|
||
|
|
tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 221:45]
|
||
|
|
tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 222:26]
|
||
|
|
tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 222:26]
|
||
|
|
tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 222:26]
|
||
|
|
io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 222:26]
|
||
|
|
io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 222:26]
|
||
|
|
io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 222:26]
|
||
|
|
tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 222:26]
|
||
|
|
tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 222:26]
|
||
|
|
tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 222:26]
|
||
|
|
tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 222:26]
|
||
|
|
tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 223:14]
|
||
|
|
tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 223:14]
|
||
|
|
tlu.io.dec_pic.mexintpend <= io.dec_pic.mexintpend @[dec.scala 224:14]
|
||
|
|
io.dec_pic.dec_tlu_meipt <= tlu.io.dec_pic.dec_tlu_meipt @[dec.scala 224:14]
|
||
|
|
io.dec_pic.dec_tlu_meicurpl <= tlu.io.dec_pic.dec_tlu_meicurpl @[dec.scala 224:14]
|
||
|
|
tlu.io.dec_pic.mhwakeup <= io.dec_pic.mhwakeup @[dec.scala 224:14]
|
||
|
|
tlu.io.dec_pic.pic_pl <= io.dec_pic.pic_pl @[dec.scala 224:14]
|
||
|
|
tlu.io.dec_pic.pic_claimid <= io.dec_pic.pic_claimid @[dec.scala 224:14]
|
||
|
|
tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 225:45]
|
||
|
|
tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 226:45]
|
||
|
|
tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 227:45]
|
||
|
|
tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 228:45]
|
||
|
|
tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 228:45]
|
||
|
|
tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 228:45]
|
||
|
|
tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 228:45]
|
||
|
|
tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 228:45]
|
||
|
|
tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 228:45]
|
||
|
|
tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 229:45]
|
||
|
|
tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 230:45]
|
||
|
|
tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 231:45]
|
||
|
|
tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 232:45]
|
||
|
|
tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 233:45]
|
||
|
|
tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 234:45]
|
||
|
|
tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 235:45]
|
||
|
|
tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 236:45]
|
||
|
|
tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 237:45]
|
||
|
|
tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 238:45]
|
||
|
|
tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 239:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 240:45]
|
||
|
|
tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 241:45]
|
||
|
|
tlu.io.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 242:45]
|
||
|
|
tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 243:45]
|
||
|
|
tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 244:45]
|
||
|
|
tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 245:45]
|
||
|
|
tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 246:45]
|
||
|
|
tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 247:45]
|
||
|
|
tlu.io.timer_int <= io.timer_int @[dec.scala 252:45]
|
||
|
|
tlu.io.soft_int <= io.soft_int @[dec.scala 253:45]
|
||
|
|
tlu.io.core_id <= io.core_id @[dec.scala 254:45]
|
||
|
|
tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 255:45]
|
||
|
|
tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 256:45]
|
||
|
|
tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 257:45]
|
||
|
|
io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 258:28]
|
||
|
|
io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 259:28]
|
||
|
|
io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 260:28]
|
||
|
|
io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 261:28]
|
||
|
|
io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 262:28]
|
||
|
|
io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 263:51]
|
||
|
|
io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 264:29]
|
||
|
|
io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 264:29]
|
||
|
|
io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 265:29]
|
||
|
|
io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 266:29]
|
||
|
|
io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 267:29]
|
||
|
|
io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 268:29]
|
||
|
|
io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 269:29]
|
||
|
|
io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 270:29]
|
||
|
|
io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 271:29]
|
||
|
|
io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 274:34]
|
||
|
|
io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 275:29]
|
||
|
|
io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 276:29]
|
||
|
|
io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 277:29]
|
||
|
|
io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 278:29]
|
||
|
|
dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 279:32]
|
||
|
|
dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 280:32]
|
||
|
|
dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 281:32]
|
||
|
|
dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 282:32]
|
||
|
|
dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 283:32]
|
||
|
|
io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 284:35]
|
||
|
|
io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 285:36]
|
||
|
|
io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 286:36]
|
||
|
|
io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 287:36]
|
||
|
|
io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 288:36]
|
||
|
|
io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 289:36]
|
||
|
|
io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 290:36]
|
||
|
|
io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[dec.scala 294:32]
|
||
|
|
node _T = cat(decode.io.dec_i0_pc_wb1, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
io.rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 295:35]
|
||
|
|
node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 296:98]
|
||
|
|
node _T_2 = cat(tlu.io.dec_tlu_int_valid_wb1, _T_1) @[Cat.scala 29:58]
|
||
|
|
io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 296:33]
|
||
|
|
node _T_3 = cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[Cat.scala 29:58]
|
||
|
|
io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 297:37]
|
||
|
|
node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 298:65]
|
||
|
|
io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 298:34]
|
||
|
|
node _T_5 = cat(tlu.io.dec_tlu_int_valid_wb1, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[dec.scala 299:37]
|
||
|
|
io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 300:32]
|
||
|
|
io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 304:21]
|
||
|
|
|