2020-09-08 22:00:03 +08:00
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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2020-10-02 13:14:08 +08:00
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test",
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2020-09-08 22:00:03 +08:00
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"sources":[
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2020-10-02 13:14:08 +08:00
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr"
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2020-09-08 22:00:03 +08:00
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"EL2_IC_TAG"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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