5033 lines
337 KiB
Plaintext
5033 lines
337 KiB
Plaintext
|
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||
|
|
circuit el2_dec_decode_ctl :
|
||
|
|
extmodule gated_latch :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
module el2_dec_dec_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}}
|
||
|
|
|
||
|
|
node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23]
|
||
|
|
node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35]
|
||
|
|
node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27]
|
||
|
|
node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49]
|
||
|
|
node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42]
|
||
|
|
node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60]
|
||
|
|
node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53]
|
||
|
|
node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39]
|
||
|
|
node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75]
|
||
|
|
node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68]
|
||
|
|
node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85]
|
||
|
|
node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78]
|
||
|
|
node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65]
|
||
|
|
io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14]
|
||
|
|
node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51]
|
||
|
|
node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51]
|
||
|
|
node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90]
|
||
|
|
node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90]
|
||
|
|
node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55]
|
||
|
|
node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37]
|
||
|
|
node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37]
|
||
|
|
node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94]
|
||
|
|
node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76]
|
||
|
|
node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76]
|
||
|
|
node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41]
|
||
|
|
node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38]
|
||
|
|
node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38]
|
||
|
|
node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80]
|
||
|
|
node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76]
|
||
|
|
node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76]
|
||
|
|
node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42]
|
||
|
|
node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37]
|
||
|
|
node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37]
|
||
|
|
node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80]
|
||
|
|
node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75]
|
||
|
|
node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75]
|
||
|
|
node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41]
|
||
|
|
node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37]
|
||
|
|
node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37]
|
||
|
|
node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79]
|
||
|
|
node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75]
|
||
|
|
node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75]
|
||
|
|
node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41]
|
||
|
|
node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37]
|
||
|
|
node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37]
|
||
|
|
node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79]
|
||
|
|
node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71]
|
||
|
|
node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41]
|
||
|
|
node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106]
|
||
|
|
node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75]
|
||
|
|
io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14]
|
||
|
|
node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48]
|
||
|
|
node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48]
|
||
|
|
node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85]
|
||
|
|
node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85]
|
||
|
|
node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52]
|
||
|
|
io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14]
|
||
|
|
node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50]
|
||
|
|
node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50]
|
||
|
|
node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90]
|
||
|
|
node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90]
|
||
|
|
node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90]
|
||
|
|
node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54]
|
||
|
|
node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40]
|
||
|
|
node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40]
|
||
|
|
node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40]
|
||
|
|
node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94]
|
||
|
|
node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81]
|
||
|
|
node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81]
|
||
|
|
node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81]
|
||
|
|
node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44]
|
||
|
|
io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16]
|
||
|
|
node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24]
|
||
|
|
node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17]
|
||
|
|
node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37]
|
||
|
|
node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30]
|
||
|
|
node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28]
|
||
|
|
node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51]
|
||
|
|
node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63]
|
||
|
|
node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55]
|
||
|
|
node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42]
|
||
|
|
node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76]
|
||
|
|
node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68]
|
||
|
|
io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13]
|
||
|
|
node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58]
|
||
|
|
node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58]
|
||
|
|
node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58]
|
||
|
|
node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58]
|
||
|
|
io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17]
|
||
|
|
node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26]
|
||
|
|
node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36]
|
||
|
|
node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29]
|
||
|
|
node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50]
|
||
|
|
node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60]
|
||
|
|
node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53]
|
||
|
|
node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41]
|
||
|
|
io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16]
|
||
|
|
node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24]
|
||
|
|
node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17]
|
||
|
|
node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37]
|
||
|
|
node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30]
|
||
|
|
node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28]
|
||
|
|
node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49]
|
||
|
|
node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41]
|
||
|
|
node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63]
|
||
|
|
node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75]
|
||
|
|
node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67]
|
||
|
|
node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54]
|
||
|
|
io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13]
|
||
|
|
node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50]
|
||
|
|
node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50]
|
||
|
|
io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15]
|
||
|
|
node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50]
|
||
|
|
node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50]
|
||
|
|
io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16]
|
||
|
|
node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49]
|
||
|
|
node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49]
|
||
|
|
io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14]
|
||
|
|
node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57]
|
||
|
|
node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57]
|
||
|
|
node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57]
|
||
|
|
node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57]
|
||
|
|
node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94]
|
||
|
|
node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94]
|
||
|
|
node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61]
|
||
|
|
node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56]
|
||
|
|
node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98]
|
||
|
|
io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14]
|
||
|
|
node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57]
|
||
|
|
node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57]
|
||
|
|
node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57]
|
||
|
|
node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57]
|
||
|
|
node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57]
|
||
|
|
node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105]
|
||
|
|
node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105]
|
||
|
|
node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105]
|
||
|
|
node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105]
|
||
|
|
node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105]
|
||
|
|
node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61]
|
||
|
|
node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43]
|
||
|
|
node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43]
|
||
|
|
node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43]
|
||
|
|
node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43]
|
||
|
|
node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109]
|
||
|
|
node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80]
|
||
|
|
node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80]
|
||
|
|
node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47]
|
||
|
|
io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14]
|
||
|
|
node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56]
|
||
|
|
node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56]
|
||
|
|
node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56]
|
||
|
|
node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56]
|
||
|
|
node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104]
|
||
|
|
node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104]
|
||
|
|
node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104]
|
||
|
|
node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104]
|
||
|
|
node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104]
|
||
|
|
node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60]
|
||
|
|
io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15]
|
||
|
|
node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45]
|
||
|
|
node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94]
|
||
|
|
node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94]
|
||
|
|
node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94]
|
||
|
|
node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94]
|
||
|
|
node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94]
|
||
|
|
node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49]
|
||
|
|
node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34]
|
||
|
|
node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34]
|
||
|
|
node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98]
|
||
|
|
node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75]
|
||
|
|
node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75]
|
||
|
|
node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75]
|
||
|
|
node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38]
|
||
|
|
node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44]
|
||
|
|
node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44]
|
||
|
|
node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44]
|
||
|
|
node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44]
|
||
|
|
node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79]
|
||
|
|
io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14]
|
||
|
|
node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61]
|
||
|
|
node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61]
|
||
|
|
node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61]
|
||
|
|
node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61]
|
||
|
|
node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61]
|
||
|
|
node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109]
|
||
|
|
node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109]
|
||
|
|
node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109]
|
||
|
|
node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109]
|
||
|
|
node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109]
|
||
|
|
node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65]
|
||
|
|
io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15]
|
||
|
|
node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63]
|
||
|
|
node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63]
|
||
|
|
node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63]
|
||
|
|
node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63]
|
||
|
|
node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63]
|
||
|
|
node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63]
|
||
|
|
io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14]
|
||
|
|
node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58]
|
||
|
|
node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58]
|
||
|
|
node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58]
|
||
|
|
node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58]
|
||
|
|
node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58]
|
||
|
|
io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14]
|
||
|
|
node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66]
|
||
|
|
io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14]
|
||
|
|
node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62]
|
||
|
|
node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62]
|
||
|
|
node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62]
|
||
|
|
node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62]
|
||
|
|
node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62]
|
||
|
|
node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62]
|
||
|
|
node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106]
|
||
|
|
node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106]
|
||
|
|
node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106]
|
||
|
|
node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106]
|
||
|
|
node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66]
|
||
|
|
io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14]
|
||
|
|
node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59]
|
||
|
|
node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59]
|
||
|
|
node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59]
|
||
|
|
node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59]
|
||
|
|
node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99]
|
||
|
|
node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99]
|
||
|
|
node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99]
|
||
|
|
node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63]
|
||
|
|
node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37]
|
||
|
|
node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37]
|
||
|
|
node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103]
|
||
|
|
node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86]
|
||
|
|
node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86]
|
||
|
|
node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86]
|
||
|
|
node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86]
|
||
|
|
node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86]
|
||
|
|
node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41]
|
||
|
|
node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45]
|
||
|
|
node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45]
|
||
|
|
node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45]
|
||
|
|
node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45]
|
||
|
|
node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45]
|
||
|
|
node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90]
|
||
|
|
io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17]
|
||
|
|
node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51]
|
||
|
|
node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51]
|
||
|
|
io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17]
|
||
|
|
node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56]
|
||
|
|
node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56]
|
||
|
|
node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56]
|
||
|
|
node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56]
|
||
|
|
io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14]
|
||
|
|
node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55]
|
||
|
|
node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55]
|
||
|
|
node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55]
|
||
|
|
node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55]
|
||
|
|
io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14]
|
||
|
|
node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54]
|
||
|
|
node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54]
|
||
|
|
node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54]
|
||
|
|
node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54]
|
||
|
|
io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14]
|
||
|
|
node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55]
|
||
|
|
node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55]
|
||
|
|
node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55]
|
||
|
|
node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55]
|
||
|
|
io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14]
|
||
|
|
node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44]
|
||
|
|
io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14]
|
||
|
|
node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56]
|
||
|
|
node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56]
|
||
|
|
node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56]
|
||
|
|
node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56]
|
||
|
|
io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13]
|
||
|
|
node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53]
|
||
|
|
node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53]
|
||
|
|
node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53]
|
||
|
|
io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15]
|
||
|
|
node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50]
|
||
|
|
node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50]
|
||
|
|
io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15]
|
||
|
|
node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52]
|
||
|
|
node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52]
|
||
|
|
node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87]
|
||
|
|
node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87]
|
||
|
|
node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56]
|
||
|
|
node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34]
|
||
|
|
node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34]
|
||
|
|
node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91]
|
||
|
|
node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69]
|
||
|
|
node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69]
|
||
|
|
node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38]
|
||
|
|
node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105]
|
||
|
|
node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105]
|
||
|
|
node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73]
|
||
|
|
node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35]
|
||
|
|
node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35]
|
||
|
|
node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109]
|
||
|
|
io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19]
|
||
|
|
node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57]
|
||
|
|
node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57]
|
||
|
|
node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57]
|
||
|
|
node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57]
|
||
|
|
node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99]
|
||
|
|
node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99]
|
||
|
|
node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99]
|
||
|
|
node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99]
|
||
|
|
node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61]
|
||
|
|
node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41]
|
||
|
|
node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41]
|
||
|
|
node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41]
|
||
|
|
node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41]
|
||
|
|
node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103]
|
||
|
|
node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81]
|
||
|
|
node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81]
|
||
|
|
node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81]
|
||
|
|
node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45]
|
||
|
|
node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39]
|
||
|
|
node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39]
|
||
|
|
node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39]
|
||
|
|
node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85]
|
||
|
|
io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18]
|
||
|
|
node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57]
|
||
|
|
node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57]
|
||
|
|
node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57]
|
||
|
|
io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20]
|
||
|
|
node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55]
|
||
|
|
node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55]
|
||
|
|
node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55]
|
||
|
|
node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94]
|
||
|
|
node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94]
|
||
|
|
node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94]
|
||
|
|
node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59]
|
||
|
|
node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38]
|
||
|
|
node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38]
|
||
|
|
node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38]
|
||
|
|
node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98]
|
||
|
|
node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77]
|
||
|
|
node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77]
|
||
|
|
node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77]
|
||
|
|
node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42]
|
||
|
|
node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38]
|
||
|
|
node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38]
|
||
|
|
node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38]
|
||
|
|
node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81]
|
||
|
|
node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77]
|
||
|
|
node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77]
|
||
|
|
node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77]
|
||
|
|
node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42]
|
||
|
|
io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18]
|
||
|
|
node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55]
|
||
|
|
node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55]
|
||
|
|
node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55]
|
||
|
|
node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95]
|
||
|
|
node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95]
|
||
|
|
node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95]
|
||
|
|
node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59]
|
||
|
|
node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39]
|
||
|
|
node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39]
|
||
|
|
node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39]
|
||
|
|
node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99]
|
||
|
|
node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79]
|
||
|
|
node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79]
|
||
|
|
node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79]
|
||
|
|
node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43]
|
||
|
|
node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39]
|
||
|
|
node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39]
|
||
|
|
node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39]
|
||
|
|
node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83]
|
||
|
|
io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18]
|
||
|
|
node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62]
|
||
|
|
node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62]
|
||
|
|
node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62]
|
||
|
|
node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62]
|
||
|
|
node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62]
|
||
|
|
io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17]
|
||
|
|
node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62]
|
||
|
|
node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62]
|
||
|
|
node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62]
|
||
|
|
node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62]
|
||
|
|
node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62]
|
||
|
|
io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16]
|
||
|
|
node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56]
|
||
|
|
node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56]
|
||
|
|
node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56]
|
||
|
|
node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56]
|
||
|
|
io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15]
|
||
|
|
node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57]
|
||
|
|
node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57]
|
||
|
|
node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57]
|
||
|
|
node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57]
|
||
|
|
node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57]
|
||
|
|
io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14]
|
||
|
|
node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69]
|
||
|
|
node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50]
|
||
|
|
node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50]
|
||
|
|
node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50]
|
||
|
|
node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50]
|
||
|
|
node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50]
|
||
|
|
node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50]
|
||
|
|
node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73]
|
||
|
|
io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19]
|
||
|
|
node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67]
|
||
|
|
node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67]
|
||
|
|
node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67]
|
||
|
|
node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67]
|
||
|
|
node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67]
|
||
|
|
node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67]
|
||
|
|
io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19]
|
||
|
|
node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62]
|
||
|
|
node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62]
|
||
|
|
node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62]
|
||
|
|
node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62]
|
||
|
|
node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62]
|
||
|
|
node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62]
|
||
|
|
io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14]
|
||
|
|
node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54]
|
||
|
|
node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54]
|
||
|
|
node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54]
|
||
|
|
node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54]
|
||
|
|
io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14]
|
||
|
|
node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57]
|
||
|
|
node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57]
|
||
|
|
node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57]
|
||
|
|
node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57]
|
||
|
|
node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57]
|
||
|
|
io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14]
|
||
|
|
node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47]
|
||
|
|
io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16]
|
||
|
|
node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52]
|
||
|
|
node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52]
|
||
|
|
io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18]
|
||
|
|
node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59]
|
||
|
|
node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59]
|
||
|
|
node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59]
|
||
|
|
node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59]
|
||
|
|
node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92]
|
||
|
|
node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63]
|
||
|
|
node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37]
|
||
|
|
node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37]
|
||
|
|
node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96]
|
||
|
|
node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71]
|
||
|
|
node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41]
|
||
|
|
io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17]
|
||
|
|
node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49]
|
||
|
|
node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88]
|
||
|
|
node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88]
|
||
|
|
node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88]
|
||
|
|
node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53]
|
||
|
|
node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38]
|
||
|
|
node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38]
|
||
|
|
node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38]
|
||
|
|
node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92]
|
||
|
|
node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77]
|
||
|
|
node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77]
|
||
|
|
node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77]
|
||
|
|
node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42]
|
||
|
|
node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38]
|
||
|
|
node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38]
|
||
|
|
node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38]
|
||
|
|
node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81]
|
||
|
|
node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78]
|
||
|
|
node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78]
|
||
|
|
node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78]
|
||
|
|
node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42]
|
||
|
|
node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39]
|
||
|
|
node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39]
|
||
|
|
node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39]
|
||
|
|
node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82]
|
||
|
|
node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78]
|
||
|
|
node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78]
|
||
|
|
node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78]
|
||
|
|
node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43]
|
||
|
|
node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38]
|
||
|
|
node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38]
|
||
|
|
node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38]
|
||
|
|
node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82]
|
||
|
|
node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77]
|
||
|
|
node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77]
|
||
|
|
node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77]
|
||
|
|
node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42]
|
||
|
|
node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38]
|
||
|
|
node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38]
|
||
|
|
node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38]
|
||
|
|
node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81]
|
||
|
|
node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77]
|
||
|
|
node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77]
|
||
|
|
node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77]
|
||
|
|
node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42]
|
||
|
|
io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18]
|
||
|
|
node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53]
|
||
|
|
node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53]
|
||
|
|
node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98]
|
||
|
|
node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98]
|
||
|
|
node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98]
|
||
|
|
node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98]
|
||
|
|
node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57]
|
||
|
|
node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38]
|
||
|
|
node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38]
|
||
|
|
node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38]
|
||
|
|
node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102]
|
||
|
|
node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77]
|
||
|
|
node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77]
|
||
|
|
node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77]
|
||
|
|
node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42]
|
||
|
|
node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38]
|
||
|
|
node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38]
|
||
|
|
node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38]
|
||
|
|
node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81]
|
||
|
|
node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78]
|
||
|
|
node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78]
|
||
|
|
node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78]
|
||
|
|
node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42]
|
||
|
|
node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39]
|
||
|
|
node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39]
|
||
|
|
node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39]
|
||
|
|
node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82]
|
||
|
|
node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78]
|
||
|
|
node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78]
|
||
|
|
node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78]
|
||
|
|
node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43]
|
||
|
|
node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38]
|
||
|
|
node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38]
|
||
|
|
node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38]
|
||
|
|
node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82]
|
||
|
|
node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77]
|
||
|
|
node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77]
|
||
|
|
node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77]
|
||
|
|
node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42]
|
||
|
|
node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38]
|
||
|
|
node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38]
|
||
|
|
node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38]
|
||
|
|
node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81]
|
||
|
|
node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77]
|
||
|
|
node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77]
|
||
|
|
node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77]
|
||
|
|
node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42]
|
||
|
|
io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19]
|
||
|
|
node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144]
|
||
|
|
node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130]
|
||
|
|
node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148]
|
||
|
|
node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127]
|
||
|
|
node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134]
|
||
|
|
node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68]
|
||
|
|
node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131]
|
||
|
|
node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77]
|
||
|
|
node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72]
|
||
|
|
node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74]
|
||
|
|
node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81]
|
||
|
|
node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66]
|
||
|
|
node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78]
|
||
|
|
node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54]
|
||
|
|
node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70]
|
||
|
|
node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48]
|
||
|
|
node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58]
|
||
|
|
node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47]
|
||
|
|
node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47]
|
||
|
|
node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47]
|
||
|
|
node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47]
|
||
|
|
node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47]
|
||
|
|
node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47]
|
||
|
|
node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52]
|
||
|
|
node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99]
|
||
|
|
node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51]
|
||
|
|
node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47]
|
||
|
|
node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103]
|
||
|
|
node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142]
|
||
|
|
node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51]
|
||
|
|
node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110]
|
||
|
|
node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146]
|
||
|
|
node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51]
|
||
|
|
node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114]
|
||
|
|
node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95]
|
||
|
|
node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95]
|
||
|
|
node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95]
|
||
|
|
node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95]
|
||
|
|
node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95]
|
||
|
|
node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95]
|
||
|
|
node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55]
|
||
|
|
node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46]
|
||
|
|
node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46]
|
||
|
|
node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46]
|
||
|
|
node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46]
|
||
|
|
node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46]
|
||
|
|
node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46]
|
||
|
|
node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99]
|
||
|
|
node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99]
|
||
|
|
node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50]
|
||
|
|
node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
|
||
|
|
node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
|
||
|
|
node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
|
||
|
|
node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43]
|
||
|
|
node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43]
|
||
|
|
node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43]
|
||
|
|
node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43]
|
||
|
|
node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43]
|
||
|
|
node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103]
|
||
|
|
io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16]
|
||
|
|
|
||
|
|
extmodule gated_latch_1 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_1 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_2 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_2 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_3 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_3 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_4 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_4 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_5 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_5 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_6 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_6 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_7 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_7 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_8 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_8 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_9 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_9 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_10 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_10 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_11 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_11 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_12 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_12 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_13 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_13 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_14 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_14 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_15 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_15 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_16 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_16 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_17 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_17 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_18 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_18 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_19 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_19 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
module el2_dec_decode_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence
|
||
|
|
|
||
|
|
wire _T : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>} @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.crc32c_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.crc32c_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.crc32c_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.crc32_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.crc32_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.crc32_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.unshfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.shfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.grev <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.clmulr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.clmulh <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.clmul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.bdep <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.bext <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
_T.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
|
||
|
|
io.mul_p.bfp <= _T.bfp @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.crc32c_w <= _T.crc32c_w @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.crc32c_h <= _T.crc32c_h @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.crc32c_b <= _T.crc32c_b @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.crc32_w <= _T.crc32_w @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.crc32_h <= _T.crc32_h @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.crc32_b <= _T.crc32_b @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.unshfl <= _T.unshfl @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.shfl <= _T.shfl @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.grev <= _T.grev @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.clmulr <= _T.clmulr @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.clmulh <= _T.clmulh @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.clmul <= _T.clmul @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.bdep <= _T.bdep @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.bext <= _T.bext @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.low <= _T.low @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.rs2_sign <= _T.rs2_sign @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.rs1_sign <= _T.rs1_sign @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
io.mul_p.valid <= _T.valid @[el2_dec_decode_ctl.scala 126:12]
|
||
|
|
wire leak1_i1_stall_in : UInt<1>
|
||
|
|
leak1_i1_stall_in <= UInt<1>("h00")
|
||
|
|
wire leak1_i0_stall_in : UInt<1>
|
||
|
|
leak1_i0_stall_in <= UInt<1>("h00")
|
||
|
|
wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 130:17]
|
||
|
|
wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 131:17]
|
||
|
|
wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 132:17]
|
||
|
|
wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20]
|
||
|
|
wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17]
|
||
|
|
wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23]
|
||
|
|
wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17]
|
||
|
|
wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17]
|
||
|
|
wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17]
|
||
|
|
wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20]
|
||
|
|
wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17]
|
||
|
|
wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20]
|
||
|
|
wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28]
|
||
|
|
wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28]
|
||
|
|
wire i0_rs1_depth_d : UInt<2>
|
||
|
|
i0_rs1_depth_d <= UInt<1>("h00")
|
||
|
|
wire i0_rs2_depth_d : UInt<2>
|
||
|
|
i0_rs2_depth_d <= UInt<1>("h00")
|
||
|
|
wire cam_wen : UInt<4>
|
||
|
|
cam_wen <= UInt<1>("h00")
|
||
|
|
wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17]
|
||
|
|
wire cam_write : UInt<1>
|
||
|
|
cam_write <= UInt<1>("h00")
|
||
|
|
wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29]
|
||
|
|
wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30]
|
||
|
|
wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31]
|
||
|
|
wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20]
|
||
|
|
wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20]
|
||
|
|
wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18]
|
||
|
|
wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22]
|
||
|
|
wire i0_rs1bypass : UInt<3>
|
||
|
|
i0_rs1bypass <= UInt<1>("h00")
|
||
|
|
wire i0_rs2bypass : UInt<3>
|
||
|
|
i0_rs2bypass <= UInt<1>("h00")
|
||
|
|
wire illegal_lockout : UInt<1>
|
||
|
|
illegal_lockout <= UInt<1>("h00")
|
||
|
|
wire postsync_stall : UInt<1>
|
||
|
|
postsync_stall <= UInt<1>("h00")
|
||
|
|
wire ps_stall_in : UInt<1>
|
||
|
|
ps_stall_in <= UInt<1>("h00")
|
||
|
|
wire i0_pipe_en : UInt<4>
|
||
|
|
i0_pipe_en <= UInt<1>("h00")
|
||
|
|
wire i0_load_block_d : UInt<1>
|
||
|
|
i0_load_block_d <= UInt<1>("h00")
|
||
|
|
wire load_ldst_bypass_d : UInt<1>
|
||
|
|
load_ldst_bypass_d <= UInt<1>("h00")
|
||
|
|
wire store_data_bypass_d : UInt<1>
|
||
|
|
store_data_bypass_d <= UInt<1>("h00")
|
||
|
|
wire store_data_bypass_m : UInt<1>
|
||
|
|
store_data_bypass_m <= UInt<1>("h00")
|
||
|
|
wire tlu_wr_pause_r1 : UInt<1>
|
||
|
|
tlu_wr_pause_r1 <= UInt<1>("h00")
|
||
|
|
wire tlu_wr_pause_r2 : UInt<1>
|
||
|
|
tlu_wr_pause_r2 <= UInt<1>("h00")
|
||
|
|
wire leak1_i1_stall : UInt<1>
|
||
|
|
leak1_i1_stall <= UInt<1>("h00")
|
||
|
|
wire leak1_i0_stall : UInt<1>
|
||
|
|
leak1_i0_stall <= UInt<1>("h00")
|
||
|
|
wire pause_stall : UInt<1>
|
||
|
|
pause_stall <= UInt<1>("h00")
|
||
|
|
wire flush_final_r : UInt<1>
|
||
|
|
flush_final_r <= UInt<1>("h00")
|
||
|
|
wire illegal_lockout_in : UInt<1>
|
||
|
|
illegal_lockout_in <= UInt<1>("h00")
|
||
|
|
wire lsu_idle : UInt<1>
|
||
|
|
lsu_idle <= UInt<1>("h00")
|
||
|
|
wire pause_state_in : UInt<1>
|
||
|
|
pause_state_in <= UInt<1>("h00")
|
||
|
|
wire leak1_mode : UInt<1>
|
||
|
|
leak1_mode <= UInt<1>("h00")
|
||
|
|
wire i0_pcall : UInt<1>
|
||
|
|
i0_pcall <= UInt<1>("h00")
|
||
|
|
wire i0_pja : UInt<1>
|
||
|
|
i0_pja <= UInt<1>("h00")
|
||
|
|
wire i0_pret : UInt<1>
|
||
|
|
i0_pret <= UInt<1>("h00")
|
||
|
|
wire i0_legal_decode_d : UInt<1>
|
||
|
|
i0_legal_decode_d <= UInt<1>("h00")
|
||
|
|
wire i0_pcall_raw : UInt<1>
|
||
|
|
i0_pcall_raw <= UInt<1>("h00")
|
||
|
|
wire i0_pja_raw : UInt<1>
|
||
|
|
i0_pja_raw <= UInt<1>("h00")
|
||
|
|
wire i0_pret_raw : UInt<1>
|
||
|
|
i0_pret_raw <= UInt<1>("h00")
|
||
|
|
wire i0_br_offset : UInt<12>
|
||
|
|
i0_br_offset <= UInt<1>("h00")
|
||
|
|
wire i0_csr_write_only_d : UInt<1>
|
||
|
|
i0_csr_write_only_d <= UInt<1>("h00")
|
||
|
|
wire i0_jal : UInt<1>
|
||
|
|
i0_jal <= UInt<1>("h00")
|
||
|
|
wire i0_wen_r : UInt<1>
|
||
|
|
i0_wen_r <= UInt<1>("h00")
|
||
|
|
wire i0_x_ctl_en : UInt<1>
|
||
|
|
i0_x_ctl_en <= UInt<1>("h00")
|
||
|
|
wire i0_r_ctl_en : UInt<1>
|
||
|
|
i0_r_ctl_en <= UInt<1>("h00")
|
||
|
|
wire i0_wb_ctl_en : UInt<1>
|
||
|
|
i0_wb_ctl_en <= UInt<1>("h00")
|
||
|
|
wire i0_x_data_en : UInt<1>
|
||
|
|
i0_x_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_r_data_en : UInt<1>
|
||
|
|
i0_r_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_wb_data_en : UInt<1>
|
||
|
|
i0_wb_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_wb1_data_en : UInt<1>
|
||
|
|
i0_wb1_data_en <= UInt<1>("h00")
|
||
|
|
wire i0_nonblock_load_stall : UInt<1>
|
||
|
|
i0_nonblock_load_stall <= UInt<1>("h00")
|
||
|
|
wire csr_read : UInt<1>
|
||
|
|
csr_read <= UInt<1>("h00")
|
||
|
|
wire lsu_decode_d : UInt<1>
|
||
|
|
lsu_decode_d <= UInt<1>("h00")
|
||
|
|
wire mul_decode_d : UInt<1>
|
||
|
|
mul_decode_d <= UInt<1>("h00")
|
||
|
|
wire div_decode_d : UInt<1>
|
||
|
|
div_decode_d <= UInt<1>("h00")
|
||
|
|
wire write_csr_data : UInt<32>
|
||
|
|
write_csr_data <= UInt<1>("h00")
|
||
|
|
wire i0_result_corr_r : UInt<32>
|
||
|
|
i0_result_corr_r <= UInt<1>("h00")
|
||
|
|
wire presync_stall : UInt<1>
|
||
|
|
presync_stall <= UInt<1>("h00")
|
||
|
|
wire i0_nonblock_div_stall : UInt<1>
|
||
|
|
i0_nonblock_div_stall <= UInt<1>("h00")
|
||
|
|
wire debug_fence : UInt<1>
|
||
|
|
debug_fence <= UInt<1>("h00")
|
||
|
|
wire i0_immed_d : UInt<32>
|
||
|
|
i0_immed_d <= UInt<1>("h00")
|
||
|
|
wire i0_result_x : UInt<32>
|
||
|
|
i0_result_x <= UInt<1>("h00")
|
||
|
|
wire i0_result_r : UInt<32>
|
||
|
|
i0_result_r <= UInt<1>("h00")
|
||
|
|
node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[el2_dec_decode_ctl.scala 211:51]
|
||
|
|
node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[el2_dec_decode_ctl.scala 212:32]
|
||
|
|
node _T_3 = or(_T_1, _T_2) @[el2_dec_decode_ctl.scala 211:73]
|
||
|
|
node _T_4 = xor(io.dec_tlu_flush_extint, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 213:32]
|
||
|
|
node _T_5 = or(_T_3, _T_4) @[el2_dec_decode_ctl.scala 212:56]
|
||
|
|
node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[el2_dec_decode_ctl.scala 214:32]
|
||
|
|
node _T_7 = or(_T_5, _T_6) @[el2_dec_decode_ctl.scala 213:56]
|
||
|
|
node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[el2_dec_decode_ctl.scala 215:32]
|
||
|
|
node _T_9 = or(_T_7, _T_8) @[el2_dec_decode_ctl.scala 214:56]
|
||
|
|
node _T_10 = xor(pause_state_in, pause_stall) @[el2_dec_decode_ctl.scala 216:32]
|
||
|
|
node _T_11 = or(_T_9, _T_10) @[el2_dec_decode_ctl.scala 215:56]
|
||
|
|
node _T_12 = xor(ps_stall_in, postsync_stall) @[el2_dec_decode_ctl.scala 217:32]
|
||
|
|
node _T_13 = or(_T_11, _T_12) @[el2_dec_decode_ctl.scala 216:56]
|
||
|
|
node _T_14 = xor(io.exu_flush_final, flush_final_r) @[el2_dec_decode_ctl.scala 218:32]
|
||
|
|
node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56]
|
||
|
|
node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32]
|
||
|
|
node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56]
|
||
|
|
inst data_gated_cgc of rvclkhdr @[el2_dec_decode_ctl.scala 222:29]
|
||
|
|
data_gated_cgc.clock <= clock
|
||
|
|
data_gated_cgc.reset <= reset
|
||
|
|
data_gated_cgc.io.en <= data_gate_en @[el2_dec_decode_ctl.scala 223:31]
|
||
|
|
data_gated_cgc.io.scan_mode <= io.scan_mode @[el2_dec_decode_ctl.scala 224:31]
|
||
|
|
data_gated_cgc.io.clk <= clock @[el2_dec_decode_ctl.scala 225:31]
|
||
|
|
node _T_17 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 230:62]
|
||
|
|
node i0_brp_valid = and(io.dec_i0_brp.valid, _T_17) @[el2_dec_decode_ctl.scala 230:60]
|
||
|
|
io.dec_i0_predict_p_d.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 231:38]
|
||
|
|
io.dec_i0_predict_p_d.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 232:38]
|
||
|
|
io.dec_i0_predict_p_d.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 233:38]
|
||
|
|
io.dec_i0_predict_p_d.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 234:38]
|
||
|
|
io.dec_i0_predict_p_d.pja <= i0_pja @[el2_dec_decode_ctl.scala 235:38]
|
||
|
|
io.dec_i0_predict_p_d.pret <= i0_pret @[el2_dec_decode_ctl.scala 236:38]
|
||
|
|
io.dec_i0_predict_p_d.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 237:38]
|
||
|
|
io.dec_i0_predict_p_d.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 238:38]
|
||
|
|
io.dec_i0_predict_p_d.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 239:38]
|
||
|
|
node _T_18 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 240:55]
|
||
|
|
io.dec_i0_predict_p_d.valid <= _T_18 @[el2_dec_decode_ctl.scala 240:38]
|
||
|
|
node _T_19 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 241:75]
|
||
|
|
node _T_20 = or(_T_19, i0_pja_raw) @[el2_dec_decode_ctl.scala 241:90]
|
||
|
|
node _T_21 = or(_T_20, i0_pret_raw) @[el2_dec_decode_ctl.scala 241:103]
|
||
|
|
node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:56]
|
||
|
|
node i0_notbr_error = and(i0_brp_valid, _T_22) @[el2_dec_decode_ctl.scala 241:54]
|
||
|
|
node _T_23 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 244:67]
|
||
|
|
node _T_24 = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 244:47]
|
||
|
|
node _T_25 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 244:96]
|
||
|
|
node _T_26 = and(_T_24, _T_25) @[el2_dec_decode_ctl.scala 244:71]
|
||
|
|
node _T_27 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116]
|
||
|
|
node i0_br_toffset_error = and(_T_26, _T_27) @[el2_dec_decode_ctl.scala 244:114]
|
||
|
|
node _T_28 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 245:47]
|
||
|
|
node _T_29 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 245:69]
|
||
|
|
node i0_ret_error = and(_T_28, _T_29) @[el2_dec_decode_ctl.scala 245:67]
|
||
|
|
node _T_30 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 246:57]
|
||
|
|
node _T_31 = or(_T_30, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 246:74]
|
||
|
|
node i0_br_error = or(_T_31, i0_ret_error) @[el2_dec_decode_ctl.scala 246:96]
|
||
|
|
node _T_32 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 247:67]
|
||
|
|
node _T_33 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:89]
|
||
|
|
node _T_34 = and(_T_32, _T_33) @[el2_dec_decode_ctl.scala 247:87]
|
||
|
|
io.dec_i0_predict_p_d.br_error <= _T_34 @[el2_dec_decode_ctl.scala 247:51]
|
||
|
|
node _T_35 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 248:84]
|
||
|
|
node _T_36 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 248:106]
|
||
|
|
node _T_37 = and(_T_35, _T_36) @[el2_dec_decode_ctl.scala 248:104]
|
||
|
|
io.dec_i0_predict_p_d.br_start_error <= _T_37 @[el2_dec_decode_ctl.scala 248:51]
|
||
|
|
io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 249:32]
|
||
|
|
io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 250:32]
|
||
|
|
node _T_38 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 251:47]
|
||
|
|
node _T_39 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 251:81]
|
||
|
|
node i0_br_error_all = and(_T_38, _T_39) @[el2_dec_decode_ctl.scala 251:79]
|
||
|
|
io.dec_i0_predict_p_d.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 252:44]
|
||
|
|
io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 253:32]
|
||
|
|
io.dec_i0_predict_p_d.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 254:51]
|
||
|
|
node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 260:36]
|
||
|
|
i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 263:9]
|
||
|
|
node _T_40 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 264:25]
|
||
|
|
node _T_41 = bits(_T_40, 0, 0) @[el2_dec_decode_ctl.scala 264:43]
|
||
|
|
when _T_41 : @[el2_dec_decode_ctl.scala 264:50]
|
||
|
|
wire _T_42 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
_T_42.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35]
|
||
|
|
i0_dp.legal <= _T_42.legal @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.pm_alu <= _T_42.pm_alu @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.fence_i <= _T_42.fence_i @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.fence <= _T_42.fence @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.rem <= _T_42.rem @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.div <= _T_42.div @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.low <= _T_42.low @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.rs2_sign <= _T_42.rs2_sign @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.rs1_sign <= _T_42.rs1_sign @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.mul <= _T_42.mul @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.mret <= _T_42.mret @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.ecall <= _T_42.ecall @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.ebreak <= _T_42.ebreak @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.postsync <= _T_42.postsync @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.presync <= _T_42.presync @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.csr_imm <= _T_42.csr_imm @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.csr_write <= _T_42.csr_write @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.csr_set <= _T_42.csr_set @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.csr_clr <= _T_42.csr_clr @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.csr_read <= _T_42.csr_read @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.word <= _T_42.word @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.half <= _T_42.half @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.by <= _T_42.by @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.jal <= _T_42.jal @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.blt <= _T_42.blt @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.bge <= _T_42.bge @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.bne <= _T_42.bne @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.beq <= _T_42.beq @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.condbr <= _T_42.condbr @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.unsign <= _T_42.unsign @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.slt <= _T_42.slt @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.srl <= _T_42.srl @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.sra <= _T_42.sra @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.sll <= _T_42.sll @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.lxor <= _T_42.lxor @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.lor <= _T_42.lor @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.land <= _T_42.land @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.sub <= _T_42.sub @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.add <= _T_42.add @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.lsu <= _T_42.lsu @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.store <= _T_42.store @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.load <= _T_42.load @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.pc <= _T_42.pc @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.imm20 <= _T_42.imm20 @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.shimm5 <= _T_42.shimm5 @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.rd <= _T_42.rd @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.imm12 <= _T_42.imm12 @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.rs2 <= _T_42.rs2 @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.rs1 <= _T_42.rs1 @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.alu <= _T_42.alu @[el2_dec_decode_ctl.scala 265:20]
|
||
|
|
i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20]
|
||
|
|
i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20]
|
||
|
|
i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 268:20]
|
||
|
|
i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 269:20]
|
||
|
|
i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 270:20]
|
||
|
|
i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 271:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 264:50]
|
||
|
|
io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 275:25]
|
||
|
|
node _T_43 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 278:38]
|
||
|
|
node _T_44 = or(_T_43, i0_pja) @[el2_dec_decode_ctl.scala 278:49]
|
||
|
|
node i0_predict_br = or(_T_44, i0_pret) @[el2_dec_decode_ctl.scala 278:58]
|
||
|
|
node _T_45 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 280:46]
|
||
|
|
node _T_46 = and(_T_45, i0_brp_valid) @[el2_dec_decode_ctl.scala 280:50]
|
||
|
|
node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 280:26]
|
||
|
|
node i0_predict_nt = and(_T_47, i0_predict_br) @[el2_dec_decode_ctl.scala 280:66]
|
||
|
|
node _T_48 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 281:46]
|
||
|
|
node _T_49 = and(_T_48, i0_brp_valid) @[el2_dec_decode_ctl.scala 281:50]
|
||
|
|
node i0_predict_t = and(_T_49, i0_predict_br) @[el2_dec_decode_ctl.scala 281:66]
|
||
|
|
node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 282:20]
|
||
|
|
io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 284:26]
|
||
|
|
io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 285:26]
|
||
|
|
io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 287:20]
|
||
|
|
io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 288:20]
|
||
|
|
io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 289:20]
|
||
|
|
io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 290:20]
|
||
|
|
io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 291:20]
|
||
|
|
io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 292:20]
|
||
|
|
io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 293:20]
|
||
|
|
io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 294:20]
|
||
|
|
io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 295:20]
|
||
|
|
io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 296:20]
|
||
|
|
io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 297:20]
|
||
|
|
io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 298:20]
|
||
|
|
io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 299:20]
|
||
|
|
io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 300:20]
|
||
|
|
io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 301:22]
|
||
|
|
io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 302:22]
|
||
|
|
io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 303:22]
|
||
|
|
node _T_50 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78]
|
||
|
|
node _T_51 = bits(_T_50, 0, 0) @[el2_dec_decode_ctl.scala 307:137]
|
||
|
|
node _T_52 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 307:158]
|
||
|
|
node _T_53 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78]
|
||
|
|
node _T_54 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120]
|
||
|
|
node _T_55 = bits(_T_53, 0, 0) @[el2_dec_decode_ctl.scala 307:129]
|
||
|
|
node _T_56 = and(_T_54, _T_55) @[el2_dec_decode_ctl.scala 307:126]
|
||
|
|
node _T_57 = bits(_T_56, 0, 0) @[el2_dec_decode_ctl.scala 307:137]
|
||
|
|
node _T_58 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 307:158]
|
||
|
|
node _T_59 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78]
|
||
|
|
node _T_60 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120]
|
||
|
|
node _T_61 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129]
|
||
|
|
node _T_62 = and(_T_60, _T_61) @[el2_dec_decode_ctl.scala 307:126]
|
||
|
|
node _T_63 = bits(_T_62, 0, 0) @[el2_dec_decode_ctl.scala 307:120]
|
||
|
|
node _T_64 = bits(_T_59, 0, 0) @[el2_dec_decode_ctl.scala 307:129]
|
||
|
|
node _T_65 = and(_T_63, _T_64) @[el2_dec_decode_ctl.scala 307:126]
|
||
|
|
node _T_66 = bits(_T_65, 0, 0) @[el2_dec_decode_ctl.scala 307:137]
|
||
|
|
node _T_67 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 307:158]
|
||
|
|
node _T_68 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78]
|
||
|
|
node _T_69 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120]
|
||
|
|
node _T_70 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129]
|
||
|
|
node _T_71 = and(_T_69, _T_70) @[el2_dec_decode_ctl.scala 307:126]
|
||
|
|
node _T_72 = bits(_T_71, 0, 0) @[el2_dec_decode_ctl.scala 307:120]
|
||
|
|
node _T_73 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129]
|
||
|
|
node _T_74 = and(_T_72, _T_73) @[el2_dec_decode_ctl.scala 307:126]
|
||
|
|
node _T_75 = bits(_T_74, 0, 0) @[el2_dec_decode_ctl.scala 307:120]
|
||
|
|
node _T_76 = bits(_T_68, 0, 0) @[el2_dec_decode_ctl.scala 307:129]
|
||
|
|
node _T_77 = and(_T_75, _T_76) @[el2_dec_decode_ctl.scala 307:126]
|
||
|
|
node _T_78 = bits(_T_77, 0, 0) @[el2_dec_decode_ctl.scala 307:137]
|
||
|
|
node _T_79 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 307:158]
|
||
|
|
node _T_80 = mux(_T_51, _T_52, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_81 = mux(_T_57, _T_58, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_82 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_83 = mux(_T_78, _T_79, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_84 = or(_T_80, _T_81) @[Mux.scala 27:72]
|
||
|
|
node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72]
|
||
|
|
node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72]
|
||
|
|
wire _T_87 : UInt<4> @[Mux.scala 27:72]
|
||
|
|
_T_87 <= _T_86 @[Mux.scala 27:72]
|
||
|
|
cam_wen <= _T_87 @[el2_dec_decode_ctl.scala 307:11]
|
||
|
|
cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 309:25]
|
||
|
|
node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 310:54]
|
||
|
|
node cam_inv_reset_tag = bits(io.lsu_nonblock_load_inv_tag_r, 1, 0) @[el2_dec_decode_ctl.scala 313:59]
|
||
|
|
node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 315:63]
|
||
|
|
node cam_data_reset_tag = bits(io.lsu_nonblock_load_data_tag, 1, 0) @[el2_dec_decode_ctl.scala 316:60]
|
||
|
|
node _T_88 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 318:43]
|
||
|
|
node nonblock_load_rd = mux(_T_88, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 318:31]
|
||
|
|
node _T_89 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 322:116]
|
||
|
|
reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_89 : @[Reg.scala 28:19]
|
||
|
|
nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 323:56]
|
||
|
|
node _T_90 = eq(cam_inv_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 325:66]
|
||
|
|
node _T_91 = and(io.lsu_nonblock_load_inv_r, _T_90) @[el2_dec_decode_ctl.scala 325:45]
|
||
|
|
node _T_92 = and(_T_91, cam[0].valid) @[el2_dec_decode_ctl.scala 325:82]
|
||
|
|
cam_inv_reset_val[0] <= _T_92 @[el2_dec_decode_ctl.scala 325:26]
|
||
|
|
node _T_93 = eq(cam_data_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 326:67]
|
||
|
|
node _T_94 = and(cam_data_reset, _T_93) @[el2_dec_decode_ctl.scala 326:45]
|
||
|
|
node _T_95 = and(_T_94, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 326:83]
|
||
|
|
cam_data_reset_val[0] <= _T_95 @[el2_dec_decode_ctl.scala 326:27]
|
||
|
|
wire _T_96 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_96.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_96.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_96.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_96.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
cam_in[0].rd <= _T_96.rd @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[0].tag <= _T_96.tag @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[0].wb <= _T_96.wb @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[0].valid <= _T_96.valid @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
node _T_97 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 330:32]
|
||
|
|
when _T_97 : @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
node _T_98 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 333:17]
|
||
|
|
node _T_99 = bits(_T_98, 0, 0) @[el2_dec_decode_ctl.scala 333:21]
|
||
|
|
when _T_99 : @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27]
|
||
|
|
cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27]
|
||
|
|
cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27]
|
||
|
|
cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
node _T_100 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 338:37]
|
||
|
|
node _T_101 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57]
|
||
|
|
node _T_102 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 338:80]
|
||
|
|
node _T_103 = and(_T_101, _T_102) @[el2_dec_decode_ctl.scala 338:64]
|
||
|
|
node _T_104 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108]
|
||
|
|
node _T_105 = and(_T_103, _T_104) @[el2_dec_decode_ctl.scala 338:95]
|
||
|
|
node _T_106 = or(_T_100, _T_105) @[el2_dec_decode_ctl.scala 338:44]
|
||
|
|
when _T_106 : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
node _T_107 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37]
|
||
|
|
node _T_108 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 343:79]
|
||
|
|
node _T_109 = and(_T_107, _T_108) @[el2_dec_decode_ctl.scala 343:44]
|
||
|
|
node _T_110 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110]
|
||
|
|
node _T_111 = and(_T_109, _T_110) @[el2_dec_decode_ctl.scala 343:95]
|
||
|
|
when _T_111 : @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
wire _T_112 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_112.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_112.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_112.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_112.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
reg _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_112)) @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_113.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_113.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_113.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_113.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
cam_raw[0].rd <= _T_113.rd @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[0].tag <= _T_113.tag @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[0].wb <= _T_113.wb @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[0].valid <= _T_113.valid @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
node _T_114 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 352:46]
|
||
|
|
node _T_115 = and(_T_114, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 352:66]
|
||
|
|
nonblock_load_write[0] <= _T_115 @[el2_dec_decode_ctl.scala 352:28]
|
||
|
|
node _T_116 = eq(cam_inv_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 325:66]
|
||
|
|
node _T_117 = and(io.lsu_nonblock_load_inv_r, _T_116) @[el2_dec_decode_ctl.scala 325:45]
|
||
|
|
node _T_118 = and(_T_117, cam[1].valid) @[el2_dec_decode_ctl.scala 325:82]
|
||
|
|
cam_inv_reset_val[1] <= _T_118 @[el2_dec_decode_ctl.scala 325:26]
|
||
|
|
node _T_119 = eq(cam_data_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 326:67]
|
||
|
|
node _T_120 = and(cam_data_reset, _T_119) @[el2_dec_decode_ctl.scala 326:45]
|
||
|
|
node _T_121 = and(_T_120, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 326:83]
|
||
|
|
cam_data_reset_val[1] <= _T_121 @[el2_dec_decode_ctl.scala 326:27]
|
||
|
|
wire _T_122 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_122.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_122.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_122.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_122.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
cam_in[1].rd <= _T_122.rd @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[1].tag <= _T_122.tag @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[1].wb <= _T_122.wb @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[1].valid <= _T_122.valid @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
node _T_123 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 330:32]
|
||
|
|
when _T_123 : @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
node _T_124 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 333:17]
|
||
|
|
node _T_125 = bits(_T_124, 0, 0) @[el2_dec_decode_ctl.scala 333:21]
|
||
|
|
when _T_125 : @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27]
|
||
|
|
cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27]
|
||
|
|
cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27]
|
||
|
|
cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
node _T_126 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 338:37]
|
||
|
|
node _T_127 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57]
|
||
|
|
node _T_128 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 338:80]
|
||
|
|
node _T_129 = and(_T_127, _T_128) @[el2_dec_decode_ctl.scala 338:64]
|
||
|
|
node _T_130 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108]
|
||
|
|
node _T_131 = and(_T_129, _T_130) @[el2_dec_decode_ctl.scala 338:95]
|
||
|
|
node _T_132 = or(_T_126, _T_131) @[el2_dec_decode_ctl.scala 338:44]
|
||
|
|
when _T_132 : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
node _T_133 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37]
|
||
|
|
node _T_134 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 343:79]
|
||
|
|
node _T_135 = and(_T_133, _T_134) @[el2_dec_decode_ctl.scala 343:44]
|
||
|
|
node _T_136 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110]
|
||
|
|
node _T_137 = and(_T_135, _T_136) @[el2_dec_decode_ctl.scala 343:95]
|
||
|
|
when _T_137 : @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
wire _T_138 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_138.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_138.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_138.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_138.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
reg _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_138)) @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_139.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_139.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_139.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_139.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
cam_raw[1].rd <= _T_139.rd @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[1].tag <= _T_139.tag @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[1].wb <= _T_139.wb @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[1].valid <= _T_139.valid @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
node _T_140 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 352:46]
|
||
|
|
node _T_141 = and(_T_140, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 352:66]
|
||
|
|
nonblock_load_write[1] <= _T_141 @[el2_dec_decode_ctl.scala 352:28]
|
||
|
|
node _T_142 = eq(cam_inv_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 325:66]
|
||
|
|
node _T_143 = and(io.lsu_nonblock_load_inv_r, _T_142) @[el2_dec_decode_ctl.scala 325:45]
|
||
|
|
node _T_144 = and(_T_143, cam[2].valid) @[el2_dec_decode_ctl.scala 325:82]
|
||
|
|
cam_inv_reset_val[2] <= _T_144 @[el2_dec_decode_ctl.scala 325:26]
|
||
|
|
node _T_145 = eq(cam_data_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 326:67]
|
||
|
|
node _T_146 = and(cam_data_reset, _T_145) @[el2_dec_decode_ctl.scala 326:45]
|
||
|
|
node _T_147 = and(_T_146, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 326:83]
|
||
|
|
cam_data_reset_val[2] <= _T_147 @[el2_dec_decode_ctl.scala 326:27]
|
||
|
|
wire _T_148 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_148.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_148.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_148.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_148.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
cam_in[2].rd <= _T_148.rd @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[2].tag <= _T_148.tag @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[2].wb <= _T_148.wb @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[2].valid <= _T_148.valid @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
node _T_149 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 330:32]
|
||
|
|
when _T_149 : @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
node _T_150 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 333:17]
|
||
|
|
node _T_151 = bits(_T_150, 0, 0) @[el2_dec_decode_ctl.scala 333:21]
|
||
|
|
when _T_151 : @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27]
|
||
|
|
cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27]
|
||
|
|
cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27]
|
||
|
|
cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
node _T_152 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 338:37]
|
||
|
|
node _T_153 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57]
|
||
|
|
node _T_154 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 338:80]
|
||
|
|
node _T_155 = and(_T_153, _T_154) @[el2_dec_decode_ctl.scala 338:64]
|
||
|
|
node _T_156 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108]
|
||
|
|
node _T_157 = and(_T_155, _T_156) @[el2_dec_decode_ctl.scala 338:95]
|
||
|
|
node _T_158 = or(_T_152, _T_157) @[el2_dec_decode_ctl.scala 338:44]
|
||
|
|
when _T_158 : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
node _T_159 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37]
|
||
|
|
node _T_160 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 343:79]
|
||
|
|
node _T_161 = and(_T_159, _T_160) @[el2_dec_decode_ctl.scala 343:44]
|
||
|
|
node _T_162 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110]
|
||
|
|
node _T_163 = and(_T_161, _T_162) @[el2_dec_decode_ctl.scala 343:95]
|
||
|
|
when _T_163 : @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
wire _T_164 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_164.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_164.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_164.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_164.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
reg _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_164)) @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_165.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_165.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_165.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_165.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
cam_raw[2].rd <= _T_165.rd @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[2].tag <= _T_165.tag @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[2].wb <= _T_165.wb @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[2].valid <= _T_165.valid @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
node _T_166 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 352:46]
|
||
|
|
node _T_167 = and(_T_166, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 352:66]
|
||
|
|
nonblock_load_write[2] <= _T_167 @[el2_dec_decode_ctl.scala 352:28]
|
||
|
|
node _T_168 = eq(cam_inv_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 325:66]
|
||
|
|
node _T_169 = and(io.lsu_nonblock_load_inv_r, _T_168) @[el2_dec_decode_ctl.scala 325:45]
|
||
|
|
node _T_170 = and(_T_169, cam[3].valid) @[el2_dec_decode_ctl.scala 325:82]
|
||
|
|
cam_inv_reset_val[3] <= _T_170 @[el2_dec_decode_ctl.scala 325:26]
|
||
|
|
node _T_171 = eq(cam_data_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 326:67]
|
||
|
|
node _T_172 = and(cam_data_reset, _T_171) @[el2_dec_decode_ctl.scala 326:45]
|
||
|
|
node _T_173 = and(_T_172, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 326:83]
|
||
|
|
cam_data_reset_val[3] <= _T_173 @[el2_dec_decode_ctl.scala 326:27]
|
||
|
|
wire _T_174 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_174.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_174.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_174.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
_T_174.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28]
|
||
|
|
cam_in[3].rd <= _T_174.rd @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[3].tag <= _T_174.tag @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[3].wb <= _T_174.wb @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam_in[3].valid <= _T_174.valid @[el2_dec_decode_ctl.scala 327:14]
|
||
|
|
cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 328:11]
|
||
|
|
node _T_175 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 330:32]
|
||
|
|
when _T_175 : @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 330:39]
|
||
|
|
node _T_176 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 333:17]
|
||
|
|
node _T_177 = bits(_T_176, 0, 0) @[el2_dec_decode_ctl.scala 333:21]
|
||
|
|
when _T_177 : @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27]
|
||
|
|
cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27]
|
||
|
|
cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27]
|
||
|
|
cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 333:28]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
node _T_178 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 338:37]
|
||
|
|
node _T_179 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57]
|
||
|
|
node _T_180 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 338:80]
|
||
|
|
node _T_181 = and(_T_179, _T_180) @[el2_dec_decode_ctl.scala 338:64]
|
||
|
|
node _T_182 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108]
|
||
|
|
node _T_183 = and(_T_181, _T_182) @[el2_dec_decode_ctl.scala 338:95]
|
||
|
|
node _T_184 = or(_T_178, _T_183) @[el2_dec_decode_ctl.scala 338:44]
|
||
|
|
when _T_184 : @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 338:116]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 341:22]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 340:16]
|
||
|
|
node _T_185 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37]
|
||
|
|
node _T_186 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 343:79]
|
||
|
|
node _T_187 = and(_T_185, _T_186) @[el2_dec_decode_ctl.scala 343:44]
|
||
|
|
node _T_188 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110]
|
||
|
|
node _T_189 = and(_T_187, _T_188) @[el2_dec_decode_ctl.scala 343:95]
|
||
|
|
when _T_189 : @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 343:117]
|
||
|
|
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 347:32]
|
||
|
|
wire _T_190 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_190.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_190.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_190.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
_T_190.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70]
|
||
|
|
reg _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_190)) @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_191.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_191.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_191.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
_T_191.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 351:47]
|
||
|
|
cam_raw[3].rd <= _T_191.rd @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[3].tag <= _T_191.tag @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[3].wb <= _T_191.wb @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
cam_raw[3].valid <= _T_191.valid @[el2_dec_decode_ctl.scala 351:15]
|
||
|
|
node _T_192 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 352:46]
|
||
|
|
node _T_193 = and(_T_192, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 352:66]
|
||
|
|
nonblock_load_write[3] <= _T_193 @[el2_dec_decode_ctl.scala 352:28]
|
||
|
|
io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 355:29]
|
||
|
|
node _T_194 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 357:44]
|
||
|
|
node nonblock_load_cancel = and(_T_194, i0_wen_r) @[el2_dec_decode_ctl.scala 357:76]
|
||
|
|
node _T_195 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 358:95]
|
||
|
|
node _T_196 = or(_T_195, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 358:95]
|
||
|
|
node _T_197 = or(_T_196, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 358:95]
|
||
|
|
node _T_198 = bits(_T_197, 0, 0) @[el2_dec_decode_ctl.scala 358:99]
|
||
|
|
node _T_199 = and(io.lsu_nonblock_load_data_valid, _T_198) @[el2_dec_decode_ctl.scala 358:64]
|
||
|
|
node _T_200 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 358:109]
|
||
|
|
node _T_201 = and(_T_199, _T_200) @[el2_dec_decode_ctl.scala 358:106]
|
||
|
|
io.dec_nonblock_load_wen <= _T_201 @[el2_dec_decode_ctl.scala 358:28]
|
||
|
|
node _T_202 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:54]
|
||
|
|
node _T_203 = and(_T_202, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:66]
|
||
|
|
node _T_204 = and(_T_203, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 359:97]
|
||
|
|
node _T_205 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:137]
|
||
|
|
node _T_206 = and(_T_205, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:149]
|
||
|
|
node _T_207 = and(_T_206, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 359:180]
|
||
|
|
node i0_nonblock_boundary_stall = or(_T_204, _T_207) @[el2_dec_decode_ctl.scala 359:118]
|
||
|
|
i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 361:26]
|
||
|
|
node _T_208 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_209 = mux(_T_208, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_210 = and(_T_209, cam[0].rd) @[el2_dec_decode_ctl.scala 363:88]
|
||
|
|
node _T_211 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:121]
|
||
|
|
node _T_212 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149]
|
||
|
|
node _T_213 = and(_T_211, _T_212) @[el2_dec_decode_ctl.scala 363:136]
|
||
|
|
node _T_214 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:182]
|
||
|
|
node _T_215 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210]
|
||
|
|
node _T_216 = and(_T_214, _T_215) @[el2_dec_decode_ctl.scala 363:197]
|
||
|
|
node _T_217 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_218 = mux(_T_217, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_219 = and(_T_218, cam[1].rd) @[el2_dec_decode_ctl.scala 363:88]
|
||
|
|
node _T_220 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:121]
|
||
|
|
node _T_221 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149]
|
||
|
|
node _T_222 = and(_T_220, _T_221) @[el2_dec_decode_ctl.scala 363:136]
|
||
|
|
node _T_223 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:182]
|
||
|
|
node _T_224 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210]
|
||
|
|
node _T_225 = and(_T_223, _T_224) @[el2_dec_decode_ctl.scala 363:197]
|
||
|
|
node _T_226 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_227 = mux(_T_226, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_228 = and(_T_227, cam[2].rd) @[el2_dec_decode_ctl.scala 363:88]
|
||
|
|
node _T_229 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:121]
|
||
|
|
node _T_230 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149]
|
||
|
|
node _T_231 = and(_T_229, _T_230) @[el2_dec_decode_ctl.scala 363:136]
|
||
|
|
node _T_232 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:182]
|
||
|
|
node _T_233 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210]
|
||
|
|
node _T_234 = and(_T_232, _T_233) @[el2_dec_decode_ctl.scala 363:197]
|
||
|
|
node _T_235 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_236 = mux(_T_235, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_237 = and(_T_236, cam[3].rd) @[el2_dec_decode_ctl.scala 363:88]
|
||
|
|
node _T_238 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:121]
|
||
|
|
node _T_239 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149]
|
||
|
|
node _T_240 = and(_T_238, _T_239) @[el2_dec_decode_ctl.scala 363:136]
|
||
|
|
node _T_241 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:182]
|
||
|
|
node _T_242 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210]
|
||
|
|
node _T_243 = and(_T_241, _T_242) @[el2_dec_decode_ctl.scala 363:197]
|
||
|
|
node _T_244 = or(_T_210, _T_219) @[el2_dec_decode_ctl.scala 364:69]
|
||
|
|
node _T_245 = or(_T_244, _T_228) @[el2_dec_decode_ctl.scala 364:69]
|
||
|
|
node waddr = or(_T_245, _T_237) @[el2_dec_decode_ctl.scala 364:69]
|
||
|
|
node _T_246 = or(_T_213, _T_222) @[el2_dec_decode_ctl.scala 364:102]
|
||
|
|
node _T_247 = or(_T_246, _T_231) @[el2_dec_decode_ctl.scala 364:102]
|
||
|
|
node ld_stall_1 = or(_T_247, _T_240) @[el2_dec_decode_ctl.scala 364:102]
|
||
|
|
node _T_248 = or(_T_216, _T_225) @[el2_dec_decode_ctl.scala 364:134]
|
||
|
|
node _T_249 = or(_T_248, _T_234) @[el2_dec_decode_ctl.scala 364:134]
|
||
|
|
node ld_stall_2 = or(_T_249, _T_243) @[el2_dec_decode_ctl.scala 364:134]
|
||
|
|
io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 365:29]
|
||
|
|
node _T_250 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 366:38]
|
||
|
|
node _T_251 = or(_T_250, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 366:51]
|
||
|
|
i0_nonblock_load_stall <= _T_251 @[el2_dec_decode_ctl.scala 366:25]
|
||
|
|
node _T_252 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 375:34]
|
||
|
|
node i0_br_unpred = and(i0_dp.jal, _T_252) @[el2_dec_decode_ctl.scala 375:32]
|
||
|
|
node _T_253 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_254 = mux(_T_253, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_255 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 387:16]
|
||
|
|
node _T_256 = bits(_T_255, 0, 0) @[el2_dec_decode_ctl.scala 387:30]
|
||
|
|
node _T_257 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 388:6]
|
||
|
|
node _T_258 = and(_T_257, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 388:16]
|
||
|
|
node _T_259 = bits(_T_258, 0, 0) @[el2_dec_decode_ctl.scala 388:30]
|
||
|
|
node _T_260 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 389:18]
|
||
|
|
node _T_261 = and(csr_read, _T_260) @[el2_dec_decode_ctl.scala 389:16]
|
||
|
|
node _T_262 = bits(_T_261, 0, 0) @[el2_dec_decode_ctl.scala 389:30]
|
||
|
|
node _T_263 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16]
|
||
|
|
node _T_264 = mux(i0_dp.load, UInt<4>("h02"), _T_263) @[Mux.scala 98:16]
|
||
|
|
node _T_265 = mux(i0_dp.store, UInt<4>("h03"), _T_264) @[Mux.scala 98:16]
|
||
|
|
node _T_266 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_265) @[Mux.scala 98:16]
|
||
|
|
node _T_267 = mux(_T_262, UInt<4>("h05"), _T_266) @[Mux.scala 98:16]
|
||
|
|
node _T_268 = mux(_T_259, UInt<4>("h06"), _T_267) @[Mux.scala 98:16]
|
||
|
|
node _T_269 = mux(_T_256, UInt<4>("h07"), _T_268) @[Mux.scala 98:16]
|
||
|
|
node _T_270 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_269) @[Mux.scala 98:16]
|
||
|
|
node _T_271 = mux(i0_dp.ecall, UInt<4>("h09"), _T_270) @[Mux.scala 98:16]
|
||
|
|
node _T_272 = mux(i0_dp.fence, UInt<4>("h0a"), _T_271) @[Mux.scala 98:16]
|
||
|
|
node _T_273 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_272) @[Mux.scala 98:16]
|
||
|
|
node _T_274 = mux(i0_dp.mret, UInt<4>("h0c"), _T_273) @[Mux.scala 98:16]
|
||
|
|
node _T_275 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_274) @[Mux.scala 98:16]
|
||
|
|
node _T_276 = mux(i0_dp.jal, UInt<4>("h0e"), _T_275) @[Mux.scala 98:16]
|
||
|
|
node _T_277 = and(_T_254, _T_276) @[el2_dec_decode_ctl.scala 379:49]
|
||
|
|
d_t.pmu_i0_itype <= _T_277 @[el2_dec_decode_ctl.scala 379:21]
|
||
|
|
inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 396:22]
|
||
|
|
i0_dec.clock <= clock
|
||
|
|
i0_dec.reset <= reset
|
||
|
|
i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 397:16]
|
||
|
|
i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 398:12]
|
||
|
|
reg _T_278 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:45]
|
||
|
|
_T_278 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 400:45]
|
||
|
|
lsu_idle <= _T_278 @[el2_dec_decode_ctl.scala 400:11]
|
||
|
|
node _T_279 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 403:73]
|
||
|
|
node _T_280 = and(leak1_i1_stall, _T_279) @[el2_dec_decode_ctl.scala 403:71]
|
||
|
|
node _T_281 = or(io.dec_tlu_flush_leak_one_r, _T_280) @[el2_dec_decode_ctl.scala 403:53]
|
||
|
|
leak1_i1_stall_in <= _T_281 @[el2_dec_decode_ctl.scala 403:21]
|
||
|
|
reg _T_282 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 404:56]
|
||
|
|
_T_282 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 404:56]
|
||
|
|
leak1_i1_stall <= _T_282 @[el2_dec_decode_ctl.scala 404:21]
|
||
|
|
leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 405:14]
|
||
|
|
node _T_283 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 406:45]
|
||
|
|
node _T_284 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 406:83]
|
||
|
|
node _T_285 = and(leak1_i0_stall, _T_284) @[el2_dec_decode_ctl.scala 406:81]
|
||
|
|
node _T_286 = or(_T_283, _T_285) @[el2_dec_decode_ctl.scala 406:63]
|
||
|
|
leak1_i0_stall_in <= _T_286 @[el2_dec_decode_ctl.scala 406:21]
|
||
|
|
reg _T_287 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 407:56]
|
||
|
|
_T_287 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 407:56]
|
||
|
|
leak1_i0_stall <= _T_287 @[el2_dec_decode_ctl.scala 407:21]
|
||
|
|
node _T_288 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 411:29]
|
||
|
|
node _T_289 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 411:36]
|
||
|
|
node _T_290 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 411:46]
|
||
|
|
node _T_291 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 411:53]
|
||
|
|
node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_293 = cat(_T_288, _T_289) @[Cat.scala 29:58]
|
||
|
|
node _T_294 = cat(_T_293, _T_290) @[Cat.scala 29:58]
|
||
|
|
node i0_pcall_imm = cat(_T_294, _T_292) @[Cat.scala 29:58]
|
||
|
|
node _T_295 = bits(i0_pcall_imm, 12, 12) @[el2_dec_decode_ctl.scala 412:46]
|
||
|
|
node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 412:51]
|
||
|
|
node _T_297 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:71]
|
||
|
|
node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 412:79]
|
||
|
|
node _T_299 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:104]
|
||
|
|
node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 412:112]
|
||
|
|
node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 412:33]
|
||
|
|
node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 413:47]
|
||
|
|
node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 413:76]
|
||
|
|
node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 413:98]
|
||
|
|
node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 413:89]
|
||
|
|
node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 413:65]
|
||
|
|
node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 414:47]
|
||
|
|
node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 414:76]
|
||
|
|
node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 414:98]
|
||
|
|
node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 414:89]
|
||
|
|
node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 414:67]
|
||
|
|
node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 414:65]
|
||
|
|
node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 415:38]
|
||
|
|
i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 415:20]
|
||
|
|
node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 416:38]
|
||
|
|
i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 416:20]
|
||
|
|
node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 417:38]
|
||
|
|
i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 417:20]
|
||
|
|
node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 418:38]
|
||
|
|
i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 418:20]
|
||
|
|
node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 419:41]
|
||
|
|
node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 419:55]
|
||
|
|
node _T_316 = bits(i0_pcall_imm, 12, 1) @[el2_dec_decode_ctl.scala 419:75]
|
||
|
|
node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 419:90]
|
||
|
|
node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 419:97]
|
||
|
|
node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 419:103]
|
||
|
|
node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 419:113]
|
||
|
|
node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58]
|
||
|
|
node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58]
|
||
|
|
node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58]
|
||
|
|
node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 419:26]
|
||
|
|
i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 419:20]
|
||
|
|
node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 421:37]
|
||
|
|
node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 421:65]
|
||
|
|
node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 421:55]
|
||
|
|
node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 421:89]
|
||
|
|
node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 421:111]
|
||
|
|
node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 421:101]
|
||
|
|
node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 421:79]
|
||
|
|
node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 422:32]
|
||
|
|
i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 422:15]
|
||
|
|
node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 423:32]
|
||
|
|
i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 423:15]
|
||
|
|
node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:35]
|
||
|
|
node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 424:32]
|
||
|
|
node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:52]
|
||
|
|
node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 424:50]
|
||
|
|
node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:67]
|
||
|
|
node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 424:65]
|
||
|
|
i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 424:15]
|
||
|
|
io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 427:21]
|
||
|
|
io.div_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 428:21]
|
||
|
|
io.div_p.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 429:21]
|
||
|
|
io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 431:21]
|
||
|
|
io.mul_p.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 432:21]
|
||
|
|
io.mul_p.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 433:21]
|
||
|
|
io.mul_p.low <= i0_dp.low @[el2_dec_decode_ctl.scala 434:21]
|
||
|
|
reg _T_339 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 436:58]
|
||
|
|
_T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 436:58]
|
||
|
|
io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 436:23]
|
||
|
|
wire _T_340 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
_T_340.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27]
|
||
|
|
io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.store_data_bypass_m <= _T_340.store_data_bypass_m @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.load_ldst_bypass_d <= _T_340.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.store_data_bypass_d <= _T_340.store_data_bypass_d @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.dma <= _T_340.dma @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.unsign <= _T_340.unsign @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.store <= _T_340.store @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.load <= _T_340.load @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.dword <= _T_340.dword @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.word <= _T_340.word @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.half <= _T_340.half @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.by <= _T_340.by @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
io.lsu_p.fast_int <= _T_340.fast_int @[el2_dec_decode_ctl.scala 438:12]
|
||
|
|
when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 439:29]
|
||
|
|
io.lsu_p.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 440:24]
|
||
|
|
io.lsu_p.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 441:24]
|
||
|
|
io.lsu_p.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 442:24]
|
||
|
|
io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 443:24]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 439:29]
|
||
|
|
else : @[el2_dec_decode_ctl.scala 444:15]
|
||
|
|
io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 445:35]
|
||
|
|
io.lsu_p.load <= i0_dp.load @[el2_dec_decode_ctl.scala 446:35]
|
||
|
|
io.lsu_p.store <= i0_dp.store @[el2_dec_decode_ctl.scala 447:35]
|
||
|
|
io.lsu_p.by <= i0_dp.by @[el2_dec_decode_ctl.scala 448:35]
|
||
|
|
io.lsu_p.half <= i0_dp.half @[el2_dec_decode_ctl.scala 449:35]
|
||
|
|
io.lsu_p.word <= i0_dp.word @[el2_dec_decode_ctl.scala 450:35]
|
||
|
|
io.lsu_p.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 451:35]
|
||
|
|
io.lsu_p.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 452:35]
|
||
|
|
io.lsu_p.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 453:35]
|
||
|
|
io.lsu_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 454:35]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 444:15]
|
||
|
|
io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 458:21]
|
||
|
|
node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:56]
|
||
|
|
node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 459:36]
|
||
|
|
csr_read <= _T_342 @[el2_dec_decode_ctl.scala 459:18]
|
||
|
|
node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 461:42]
|
||
|
|
node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 461:40]
|
||
|
|
node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 462:61]
|
||
|
|
node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 462:41]
|
||
|
|
node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 463:59]
|
||
|
|
node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 463:39]
|
||
|
|
node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 464:59]
|
||
|
|
node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 464:39]
|
||
|
|
node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 466:41]
|
||
|
|
node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 466:39]
|
||
|
|
i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 466:23]
|
||
|
|
node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 467:42]
|
||
|
|
node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 467:58]
|
||
|
|
io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 467:24]
|
||
|
|
node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 470:30]
|
||
|
|
io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 470:24]
|
||
|
|
io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 471:23]
|
||
|
|
node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 475:34]
|
||
|
|
node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 475:50]
|
||
|
|
node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 475:48]
|
||
|
|
io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 475:20]
|
||
|
|
node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 478:45]
|
||
|
|
node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 478:75]
|
||
|
|
node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 478:59]
|
||
|
|
node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 478:90]
|
||
|
|
node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 478:103]
|
||
|
|
node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 478:119]
|
||
|
|
node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 478:117]
|
||
|
|
io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 478:27]
|
||
|
|
reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:52]
|
||
|
|
csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 480:52]
|
||
|
|
reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 481:51]
|
||
|
|
csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 481:51]
|
||
|
|
reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 482:51]
|
||
|
|
csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 482:51]
|
||
|
|
reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 483:53]
|
||
|
|
csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 483:53]
|
||
|
|
reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 484:51]
|
||
|
|
csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 484:51]
|
||
|
|
node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 487:27]
|
||
|
|
node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 487:48]
|
||
|
|
inst rvclkhdr of rvclkhdr_1 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr.io.en <= _T_363 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg csrimm_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
csrimm_x <= _T_362 @[el2_lib.scala 514:16]
|
||
|
|
node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 488:62]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_2 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_1.io.en <= _T_364 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg csr_rddata_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 514:16]
|
||
|
|
node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 491:15]
|
||
|
|
wire _T_366 : UInt<1>[27] @[el2_lib.scala 161:48]
|
||
|
|
_T_366[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[10] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[11] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[12] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[13] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[14] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[15] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[16] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[17] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[18] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[19] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[20] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[21] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[22] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[23] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[24] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[25] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_366[26] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_370 = cat(_T_369, _T_366[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_371 = cat(_T_370, _T_366[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_372 = cat(_T_371, _T_366[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_373 = cat(_T_372, _T_366[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_374 = cat(_T_373, _T_366[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_375 = cat(_T_374, _T_366[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_376 = cat(_T_375, _T_366[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_377 = cat(_T_376, _T_366[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_378 = cat(_T_377, _T_366[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_379 = cat(_T_378, _T_366[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_380 = cat(_T_379, _T_366[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_381 = cat(_T_380, _T_366[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_382 = cat(_T_381, _T_366[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_383 = cat(_T_382, _T_366[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_384 = cat(_T_383, _T_366[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_385 = cat(_T_384, _T_366[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_386 = cat(_T_385, _T_366[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_387 = cat(_T_386, _T_366[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_388 = cat(_T_387, _T_366[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_389 = cat(_T_388, _T_366[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 491:53]
|
||
|
|
node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58]
|
||
|
|
node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 492:16]
|
||
|
|
node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 492:5]
|
||
|
|
node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72]
|
||
|
|
wire csr_mask_x : UInt<32> @[Mux.scala 27:72]
|
||
|
|
csr_mask_x <= _T_399 @[Mux.scala 27:72]
|
||
|
|
node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 495:38]
|
||
|
|
node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 495:35]
|
||
|
|
node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 496:35]
|
||
|
|
node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_406 = or(_T_403, _T_404) @[Mux.scala 27:72]
|
||
|
|
node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72]
|
||
|
|
wire write_csr_data_x : UInt @[Mux.scala 27:72]
|
||
|
|
write_csr_data_x <= _T_407 @[Mux.scala 27:72]
|
||
|
|
node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 499:49]
|
||
|
|
node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 499:47]
|
||
|
|
node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 499:109]
|
||
|
|
node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 499:91]
|
||
|
|
node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 499:76]
|
||
|
|
node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 500:44]
|
||
|
|
node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 500:61]
|
||
|
|
node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 500:59]
|
||
|
|
pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 500:18]
|
||
|
|
reg _T_415 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 501:50]
|
||
|
|
_T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 501:50]
|
||
|
|
pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 501:15]
|
||
|
|
io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 502:22]
|
||
|
|
reg _T_416 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 503:29]
|
||
|
|
_T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 503:29]
|
||
|
|
tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 503:19]
|
||
|
|
reg _T_417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 504:29]
|
||
|
|
_T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 504:29]
|
||
|
|
tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 504:19]
|
||
|
|
node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:44]
|
||
|
|
node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:64]
|
||
|
|
node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 506:61]
|
||
|
|
node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 506:41]
|
||
|
|
io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 506:25]
|
||
|
|
node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 509:59]
|
||
|
|
node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 509:59]
|
||
|
|
node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 510:8]
|
||
|
|
node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 509:30]
|
||
|
|
node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 511:34]
|
||
|
|
node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 511:46]
|
||
|
|
node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 511:61]
|
||
|
|
node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 511:75]
|
||
|
|
node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 511:99]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_3 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_2.io.en <= csr_data_wen @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_429 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_429 <= write_csr_data_in @[el2_lib.scala 514:16]
|
||
|
|
write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 512:18]
|
||
|
|
node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 518:44]
|
||
|
|
node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 518:30]
|
||
|
|
io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 518:24]
|
||
|
|
node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 520:38]
|
||
|
|
node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 520:53]
|
||
|
|
node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 522:67]
|
||
|
|
node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 522:48]
|
||
|
|
node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 523:67]
|
||
|
|
node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 523:48]
|
||
|
|
node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 524:40]
|
||
|
|
debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 524:21]
|
||
|
|
node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 527:34]
|
||
|
|
node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 527:57]
|
||
|
|
node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 527:73]
|
||
|
|
node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 527:91]
|
||
|
|
node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 530:36]
|
||
|
|
node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 530:60]
|
||
|
|
node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 530:104]
|
||
|
|
node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 530:112]
|
||
|
|
node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 530:99]
|
||
|
|
node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 530:76]
|
||
|
|
node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 532:34]
|
||
|
|
io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 533:24]
|
||
|
|
node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:40]
|
||
|
|
node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 534:51]
|
||
|
|
node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 534:37]
|
||
|
|
wire _T_446 : UInt<1>[16] @[el2_lib.scala 161:48]
|
||
|
|
_T_446[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[10] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[11] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[12] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[13] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[14] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_446[15] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_447 = cat(_T_446[0], _T_446[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_448 = cat(_T_447, _T_446[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_449 = cat(_T_448, _T_446[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_450 = cat(_T_449, _T_446[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_451 = cat(_T_450, _T_446[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_452 = cat(_T_451, _T_446[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_453 = cat(_T_452, _T_446[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_454 = cat(_T_453, _T_446[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_455 = cat(_T_454, _T_446[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_456 = cat(_T_455, _T_446[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_457 = cat(_T_456, _T_446[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_458 = cat(_T_457, _T_446[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_459 = cat(_T_458, _T_446[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58]
|
||
|
|
node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 535:27]
|
||
|
|
node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 538:49]
|
||
|
|
node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 538:47]
|
||
|
|
node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 539:44]
|
||
|
|
node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 539:42]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_4 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_3.io.en <= illegal_inst_en @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_465 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_465 <= i0_inst_d @[el2_lib.scala 514:16]
|
||
|
|
io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 540:23]
|
||
|
|
node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 541:40]
|
||
|
|
node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 541:61]
|
||
|
|
node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 541:59]
|
||
|
|
illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 541:22]
|
||
|
|
reg _T_469 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 542:54]
|
||
|
|
_T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 542:54]
|
||
|
|
illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 542:19]
|
||
|
|
node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 543:42]
|
||
|
|
node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 545:40]
|
||
|
|
node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 545:59]
|
||
|
|
node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 545:81]
|
||
|
|
node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 545:95]
|
||
|
|
node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 546:20]
|
||
|
|
node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 546:45]
|
||
|
|
node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 546:62]
|
||
|
|
node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 547:19]
|
||
|
|
node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 547:36]
|
||
|
|
node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 547:34]
|
||
|
|
node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 546:79]
|
||
|
|
node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 547:47]
|
||
|
|
node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 547:72]
|
||
|
|
node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 548:21]
|
||
|
|
node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 548:45]
|
||
|
|
node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 550:65]
|
||
|
|
node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 550:39]
|
||
|
|
node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 551:63]
|
||
|
|
node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 551:38]
|
||
|
|
node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 552:38]
|
||
|
|
node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 552:57]
|
||
|
|
node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:46]
|
||
|
|
node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 556:44]
|
||
|
|
node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:63]
|
||
|
|
node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 556:61]
|
||
|
|
node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:91]
|
||
|
|
node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 556:89]
|
||
|
|
io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 556:22]
|
||
|
|
node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:46]
|
||
|
|
node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 557:44]
|
||
|
|
node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:63]
|
||
|
|
node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 557:61]
|
||
|
|
node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:91]
|
||
|
|
node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 557:89]
|
||
|
|
node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 558:46]
|
||
|
|
io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 561:28]
|
||
|
|
node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 562:51]
|
||
|
|
node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 562:49]
|
||
|
|
io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 562:27]
|
||
|
|
node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 563:47]
|
||
|
|
io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 563:29]
|
||
|
|
node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 564:46]
|
||
|
|
io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 564:29]
|
||
|
|
node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 568:41]
|
||
|
|
node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 569:31]
|
||
|
|
node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 571:37]
|
||
|
|
presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 571:22]
|
||
|
|
reg _T_503 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 572:53]
|
||
|
|
_T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 572:53]
|
||
|
|
postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 572:18]
|
||
|
|
node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 574:56]
|
||
|
|
node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 574:54]
|
||
|
|
node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 574:39]
|
||
|
|
node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 574:88]
|
||
|
|
node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 574:69]
|
||
|
|
ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 574:15]
|
||
|
|
node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 576:50]
|
||
|
|
io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 576:26]
|
||
|
|
node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 578:40]
|
||
|
|
lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 578:16]
|
||
|
|
node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 579:40]
|
||
|
|
mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 579:16]
|
||
|
|
node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 580:40]
|
||
|
|
div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 580:16]
|
||
|
|
node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 582:47]
|
||
|
|
node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 582:45]
|
||
|
|
io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 582:29]
|
||
|
|
d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 585:26]
|
||
|
|
node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:40]
|
||
|
|
d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 586:26]
|
||
|
|
node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 587:50]
|
||
|
|
d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 587:26]
|
||
|
|
d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 588:26]
|
||
|
|
node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 590:44]
|
||
|
|
node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 590:61]
|
||
|
|
d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 590:26]
|
||
|
|
d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 593:26]
|
||
|
|
d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 594:26]
|
||
|
|
d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 595:26]
|
||
|
|
wire _T_519 : UInt<1>[4] @[el2_lib.scala 161:48]
|
||
|
|
_T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 161:48]
|
||
|
|
_T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 161:48]
|
||
|
|
_T_519[2] <= io.dec_i0_decode_d @[el2_lib.scala 161:48]
|
||
|
|
_T_519[3] <= io.dec_i0_decode_d @[el2_lib.scala 161:48]
|
||
|
|
node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 597:56]
|
||
|
|
d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 597:26]
|
||
|
|
node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 600:33]
|
||
|
|
inst rvclkhdr_4 of rvclkhdr_5 @[el2_lib.scala 518:23]
|
||
|
|
rvclkhdr_4.clock <= clock
|
||
|
|
rvclkhdr_4.reset <= reset
|
||
|
|
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 520:18]
|
||
|
|
rvclkhdr_4.io.en <= _T_524 @[el2_lib.scala 521:17]
|
||
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
|
||
|
|
wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33]
|
||
|
|
_T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_525.legal <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_4.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16]
|
||
|
|
_T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 524:16]
|
||
|
|
_T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 524:16]
|
||
|
|
_T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 524:16]
|
||
|
|
_T_526.pmu_i0_itype <= d_t.pmu_i0_itype @[el2_lib.scala 524:16]
|
||
|
|
_T_526.i0trigger <= d_t.i0trigger @[el2_lib.scala 524:16]
|
||
|
|
_T_526.fence_i <= d_t.fence_i @[el2_lib.scala 524:16]
|
||
|
|
_T_526.icaf_type <= d_t.icaf_type @[el2_lib.scala 524:16]
|
||
|
|
_T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 524:16]
|
||
|
|
_T_526.icaf <= d_t.icaf @[el2_lib.scala 524:16]
|
||
|
|
_T_526.legal <= d_t.legal @[el2_lib.scala 524:16]
|
||
|
|
x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 600:7]
|
||
|
|
x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 602:10]
|
||
|
|
wire _T_527 : UInt<1>[4] @[el2_lib.scala 161:48]
|
||
|
|
_T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48]
|
||
|
|
_T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48]
|
||
|
|
_T_527[2] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48]
|
||
|
|
_T_527[3] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48]
|
||
|
|
node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 603:39]
|
||
|
|
node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 603:37]
|
||
|
|
x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 603:20]
|
||
|
|
node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 605:36]
|
||
|
|
inst rvclkhdr_5 of rvclkhdr_6 @[el2_lib.scala 518:23]
|
||
|
|
rvclkhdr_5.clock <= clock
|
||
|
|
rvclkhdr_5.reset <= reset
|
||
|
|
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18]
|
||
|
|
rvclkhdr_5.io.en <= _T_533 @[el2_lib.scala 521:17]
|
||
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
|
||
|
|
wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33]
|
||
|
|
_T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_534.legal <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16]
|
||
|
|
_T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 524:16]
|
||
|
|
_T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 524:16]
|
||
|
|
_T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 524:16]
|
||
|
|
_T_535.pmu_i0_itype <= x_t_in.pmu_i0_itype @[el2_lib.scala 524:16]
|
||
|
|
_T_535.i0trigger <= x_t_in.i0trigger @[el2_lib.scala 524:16]
|
||
|
|
_T_535.fence_i <= x_t_in.fence_i @[el2_lib.scala 524:16]
|
||
|
|
_T_535.icaf_type <= x_t_in.icaf_type @[el2_lib.scala 524:16]
|
||
|
|
_T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 524:16]
|
||
|
|
_T_535.icaf <= x_t_in.icaf @[el2_lib.scala 524:16]
|
||
|
|
_T_535.legal <= x_t_in.legal @[el2_lib.scala 524:16]
|
||
|
|
r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 605:7]
|
||
|
|
reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 606:36]
|
||
|
|
lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 606:36]
|
||
|
|
reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 607:37]
|
||
|
|
lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 607:37]
|
||
|
|
r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 609:10]
|
||
|
|
node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 611:56]
|
||
|
|
wire _T_537 : UInt<1>[4] @[el2_lib.scala 161:48]
|
||
|
|
_T_537[0] <= _T_536 @[el2_lib.scala 161:48]
|
||
|
|
_T_537[1] <= _T_536 @[el2_lib.scala 161:48]
|
||
|
|
_T_537[2] <= _T_536 @[el2_lib.scala 161:48]
|
||
|
|
_T_537[3] <= _T_536 @[el2_lib.scala 161:48]
|
||
|
|
node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 611:72]
|
||
|
|
node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 611:95]
|
||
|
|
r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 611:33]
|
||
|
|
r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 612:33]
|
||
|
|
node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 614:35]
|
||
|
|
when _T_543 : @[el2_dec_decode_ctl.scala 614:43]
|
||
|
|
wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
_T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66]
|
||
|
|
r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 614:51]
|
||
|
|
skip @[el2_dec_decode_ctl.scala 614:43]
|
||
|
|
io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 616:39]
|
||
|
|
node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 617:53]
|
||
|
|
io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 617:39]
|
||
|
|
reg _T_546 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 620:52]
|
||
|
|
_T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 620:52]
|
||
|
|
flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 620:17]
|
||
|
|
node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:46]
|
||
|
|
node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 622:44]
|
||
|
|
node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:60]
|
||
|
|
node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 622:58]
|
||
|
|
node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:88]
|
||
|
|
node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 622:86]
|
||
|
|
io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 622:22]
|
||
|
|
node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 624:16]
|
||
|
|
i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 624:11]
|
||
|
|
node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 625:16]
|
||
|
|
i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 625:11]
|
||
|
|
node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 626:16]
|
||
|
|
i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 626:11]
|
||
|
|
node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 628:49]
|
||
|
|
node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 628:38]
|
||
|
|
io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 628:24]
|
||
|
|
node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 629:49]
|
||
|
|
node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 629:38]
|
||
|
|
io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 629:24]
|
||
|
|
node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 630:48]
|
||
|
|
node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 630:37]
|
||
|
|
io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 631:19]
|
||
|
|
io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 632:19]
|
||
|
|
node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 634:38]
|
||
|
|
node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:27]
|
||
|
|
node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 635:38]
|
||
|
|
node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 639:5]
|
||
|
|
node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72]
|
||
|
|
wire _T_566 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_566 <= _T_565 @[Mux.scala 27:72]
|
||
|
|
io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 637:21]
|
||
|
|
node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 642:38]
|
||
|
|
wire _T_568 : UInt<1>[20] @[el2_lib.scala 161:48]
|
||
|
|
_T_568[0] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[1] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[2] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[3] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[4] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[5] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[6] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[7] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[8] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[9] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[10] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[11] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[12] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[13] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[14] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[15] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[16] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[17] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[18] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
_T_568[19] <= _T_567 @[el2_lib.scala 161:48]
|
||
|
|
node _T_569 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_570 = cat(_T_569, _T_568[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_571 = cat(_T_570, _T_568[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_572 = cat(_T_571, _T_568[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_573 = cat(_T_572, _T_568[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_574 = cat(_T_573, _T_568[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_575 = cat(_T_574, _T_568[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_576 = cat(_T_575, _T_568[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_577 = cat(_T_576, _T_568[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_578 = cat(_T_577, _T_568[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_579 = cat(_T_578, _T_568[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_580 = cat(_T_579, _T_568[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_581 = cat(_T_580, _T_568[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_582 = cat(_T_581, _T_568[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_583 = cat(_T_582, _T_568[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_584 = cat(_T_583, _T_568[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 642:46]
|
||
|
|
node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58]
|
||
|
|
wire _T_590 : UInt<1>[27] @[el2_lib.scala 161:48]
|
||
|
|
_T_590[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[10] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[11] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[12] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[13] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[14] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[15] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[16] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[17] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[18] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[19] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[20] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[21] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[22] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[23] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[24] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[25] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_590[26] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_591 = cat(_T_590[0], _T_590[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_592 = cat(_T_591, _T_590[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_593 = cat(_T_592, _T_590[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_594 = cat(_T_593, _T_590[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_595 = cat(_T_594, _T_590[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_596 = cat(_T_595, _T_590[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_597 = cat(_T_596, _T_590[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_598 = cat(_T_597, _T_590[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_599 = cat(_T_598, _T_590[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_600 = cat(_T_599, _T_590[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_601 = cat(_T_600, _T_590[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_602 = cat(_T_601, _T_590[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_603 = cat(_T_602, _T_590[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_604 = cat(_T_603, _T_590[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_605 = cat(_T_604, _T_590[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_606 = cat(_T_605, _T_590[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_607 = cat(_T_606, _T_590[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_608 = cat(_T_607, _T_590[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_609 = cat(_T_608, _T_590[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_610 = cat(_T_609, _T_590[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_611 = cat(_T_610, _T_590[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_612 = cat(_T_611, _T_590[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_613 = cat(_T_612, _T_590[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 643:43]
|
||
|
|
node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58]
|
||
|
|
node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 644:38]
|
||
|
|
wire _T_620 : UInt<1>[12] @[el2_lib.scala 161:48]
|
||
|
|
_T_620[0] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[1] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[2] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[3] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[4] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[5] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[6] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[7] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[8] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[9] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[10] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
_T_620[11] <= _T_619 @[el2_lib.scala 161:48]
|
||
|
|
node _T_621 = cat(_T_620[0], _T_620[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_622 = cat(_T_621, _T_620[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_623 = cat(_T_622, _T_620[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_624 = cat(_T_623, _T_620[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_625 = cat(_T_624, _T_620[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_626 = cat(_T_625, _T_620[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_627 = cat(_T_626, _T_620[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_628 = cat(_T_627, _T_620[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 644:46]
|
||
|
|
node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 644:56]
|
||
|
|
node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 644:63]
|
||
|
|
node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58]
|
||
|
|
node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58]
|
||
|
|
node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58]
|
||
|
|
node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 645:30]
|
||
|
|
wire _T_640 : UInt<1>[12] @[el2_lib.scala 161:48]
|
||
|
|
_T_640[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[10] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_640[11] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_644 = cat(_T_643, _T_640[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_645 = cat(_T_644, _T_640[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_646 = cat(_T_645, _T_640[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_647 = cat(_T_646, _T_640[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_648 = cat(_T_647, _T_640[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_649 = cat(_T_648, _T_640[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58]
|
||
|
|
node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 646:26]
|
||
|
|
node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 646:43]
|
||
|
|
wire _T_655 : UInt<1>[27] @[el2_lib.scala 161:48]
|
||
|
|
_T_655[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[10] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[11] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[12] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[13] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[14] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[15] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[16] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[17] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[18] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[19] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[20] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[21] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[22] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[23] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[24] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[25] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_655[26] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_656 = cat(_T_655[0], _T_655[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_657 = cat(_T_656, _T_655[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_658 = cat(_T_657, _T_655[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_659 = cat(_T_658, _T_655[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_660 = cat(_T_659, _T_655[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_661 = cat(_T_660, _T_655[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_662 = cat(_T_661, _T_655[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_663 = cat(_T_662, _T_655[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_664 = cat(_T_663, _T_655[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_665 = cat(_T_664, _T_655[10]) @[Cat.scala 29:58]
|
||
|
|
node _T_666 = cat(_T_665, _T_655[11]) @[Cat.scala 29:58]
|
||
|
|
node _T_667 = cat(_T_666, _T_655[12]) @[Cat.scala 29:58]
|
||
|
|
node _T_668 = cat(_T_667, _T_655[13]) @[Cat.scala 29:58]
|
||
|
|
node _T_669 = cat(_T_668, _T_655[14]) @[Cat.scala 29:58]
|
||
|
|
node _T_670 = cat(_T_669, _T_655[15]) @[Cat.scala 29:58]
|
||
|
|
node _T_671 = cat(_T_670, _T_655[16]) @[Cat.scala 29:58]
|
||
|
|
node _T_672 = cat(_T_671, _T_655[17]) @[Cat.scala 29:58]
|
||
|
|
node _T_673 = cat(_T_672, _T_655[18]) @[Cat.scala 29:58]
|
||
|
|
node _T_674 = cat(_T_673, _T_655[19]) @[Cat.scala 29:58]
|
||
|
|
node _T_675 = cat(_T_674, _T_655[20]) @[Cat.scala 29:58]
|
||
|
|
node _T_676 = cat(_T_675, _T_655[21]) @[Cat.scala 29:58]
|
||
|
|
node _T_677 = cat(_T_676, _T_655[22]) @[Cat.scala 29:58]
|
||
|
|
node _T_678 = cat(_T_677, _T_655[23]) @[Cat.scala 29:58]
|
||
|
|
node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58]
|
||
|
|
node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58]
|
||
|
|
node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58]
|
||
|
|
node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 646:72]
|
||
|
|
node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58]
|
||
|
|
node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_686 = mux(i0_jalimm20, _T_638, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_687 = mux(i0_uiimm20, _T_652, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_688 = mux(_T_654, _T_683, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_689 = or(_T_684, _T_685) @[Mux.scala 27:72]
|
||
|
|
node _T_690 = or(_T_689, _T_686) @[Mux.scala 27:72]
|
||
|
|
node _T_691 = or(_T_690, _T_687) @[Mux.scala 27:72]
|
||
|
|
node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72]
|
||
|
|
wire _T_693 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_693 <= _T_692 @[Mux.scala 27:72]
|
||
|
|
i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 641:14]
|
||
|
|
node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 648:46]
|
||
|
|
i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 648:24]
|
||
|
|
node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 650:44]
|
||
|
|
i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 650:29]
|
||
|
|
node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 651:44]
|
||
|
|
i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 651:29]
|
||
|
|
node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 652:44]
|
||
|
|
i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 652:29]
|
||
|
|
node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 654:71]
|
||
|
|
reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16]
|
||
|
|
when _T_698 : @[Reg.scala 16:19]
|
||
|
|
i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23]
|
||
|
|
i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23]
|
||
|
|
i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23]
|
||
|
|
skip @[Reg.scala 16:19]
|
||
|
|
node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 655:71]
|
||
|
|
reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16]
|
||
|
|
when _T_699 : @[Reg.scala 16:19]
|
||
|
|
i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23]
|
||
|
|
i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23]
|
||
|
|
i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23]
|
||
|
|
skip @[Reg.scala 16:19]
|
||
|
|
node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 656:83]
|
||
|
|
reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 656:72]
|
||
|
|
_T_701 <= _T_700 @[el2_dec_decode_ctl.scala 656:72]
|
||
|
|
node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58]
|
||
|
|
i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 656:14]
|
||
|
|
node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 658:43]
|
||
|
|
node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 658:49]
|
||
|
|
node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 658:53]
|
||
|
|
i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 658:29]
|
||
|
|
node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 659:43]
|
||
|
|
node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 659:49]
|
||
|
|
node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 659:53]
|
||
|
|
i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 659:29]
|
||
|
|
node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 660:43]
|
||
|
|
node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 660:49]
|
||
|
|
node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 660:53]
|
||
|
|
i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 660:29]
|
||
|
|
node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 661:44]
|
||
|
|
node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 661:50]
|
||
|
|
i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 661:29]
|
||
|
|
node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 662:44]
|
||
|
|
node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 662:50]
|
||
|
|
i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 662:29]
|
||
|
|
node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 663:44]
|
||
|
|
node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 663:50]
|
||
|
|
i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 663:29]
|
||
|
|
node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 664:44]
|
||
|
|
node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 664:50]
|
||
|
|
i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 664:29]
|
||
|
|
node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
|
||
|
|
io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 666:27]
|
||
|
|
node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
|
||
|
|
io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 667:27]
|
||
|
|
d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 669:29]
|
||
|
|
node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45]
|
||
|
|
d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 670:29]
|
||
|
|
d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 671:29]
|
||
|
|
node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:45]
|
||
|
|
d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 673:29]
|
||
|
|
node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 674:45]
|
||
|
|
d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 674:29]
|
||
|
|
node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 675:45]
|
||
|
|
d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 675:29]
|
||
|
|
node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 677:56]
|
||
|
|
d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 677:29]
|
||
|
|
node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 678:53]
|
||
|
|
d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 678:29]
|
||
|
|
node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 679:35]
|
||
|
|
d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 679:29]
|
||
|
|
node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 681:34]
|
||
|
|
inst rvclkhdr_6 of rvclkhdr_7 @[el2_lib.scala 518:23]
|
||
|
|
rvclkhdr_6.clock <= clock
|
||
|
|
rvclkhdr_6.reset <= reset
|
||
|
|
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18]
|
||
|
|
rvclkhdr_6.io.en <= _T_729 @[el2_lib.scala 521:17]
|
||
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
|
||
|
|
wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33]
|
||
|
|
_T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
|
||
|
|
reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16]
|
||
|
|
_T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16]
|
||
|
|
_T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16]
|
||
|
|
_T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16]
|
||
|
|
_T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16]
|
||
|
|
_T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16]
|
||
|
|
_T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16]
|
||
|
|
_T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16]
|
||
|
|
_T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16]
|
||
|
|
_T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16]
|
||
|
|
x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 681:7]
|
||
|
|
wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 682:20]
|
||
|
|
x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 683:10]
|
||
|
|
node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:39]
|
||
|
|
node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 684:37]
|
||
|
|
node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:68]
|
||
|
|
node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 684:66]
|
||
|
|
x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 684:22]
|
||
|
|
node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:39]
|
||
|
|
node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 685:37]
|
||
|
|
node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:68]
|
||
|
|
node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 685:66]
|
||
|
|
x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 685:22]
|
||
|
|
node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 687:36]
|
||
|
|
inst rvclkhdr_7 of rvclkhdr_8 @[el2_lib.scala 518:23]
|
||
|
|
rvclkhdr_7.clock <= clock
|
||
|
|
rvclkhdr_7.reset <= reset
|
||
|
|
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18]
|
||
|
|
rvclkhdr_7.io.en <= _T_740 @[el2_lib.scala 521:17]
|
||
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
|
||
|
|
wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33]
|
||
|
|
_T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
|
||
|
|
reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16]
|
||
|
|
_T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16]
|
||
|
|
_T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16]
|
||
|
|
_T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16]
|
||
|
|
_T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16]
|
||
|
|
_T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16]
|
||
|
|
_T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16]
|
||
|
|
_T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16]
|
||
|
|
_T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16]
|
||
|
|
_T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16]
|
||
|
|
r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 687:7]
|
||
|
|
r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 688:10]
|
||
|
|
r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 689:17]
|
||
|
|
node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 691:41]
|
||
|
|
node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 691:39]
|
||
|
|
r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 691:22]
|
||
|
|
node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 692:41]
|
||
|
|
node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 692:39]
|
||
|
|
r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 692:22]
|
||
|
|
node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 693:41]
|
||
|
|
node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 693:39]
|
||
|
|
r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 693:22]
|
||
|
|
node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 694:41]
|
||
|
|
node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 694:39]
|
||
|
|
r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 694:22]
|
||
|
|
node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 696:37]
|
||
|
|
inst rvclkhdr_8 of rvclkhdr_9 @[el2_lib.scala 518:23]
|
||
|
|
rvclkhdr_8.clock <= clock
|
||
|
|
rvclkhdr_8.reset <= reset
|
||
|
|
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18]
|
||
|
|
rvclkhdr_8.io.en <= _T_751 @[el2_lib.scala 521:17]
|
||
|
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
|
||
|
|
wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33]
|
||
|
|
_T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
|
||
|
|
_T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
|
||
|
|
reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16]
|
||
|
|
_T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16]
|
||
|
|
_T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16]
|
||
|
|
_T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16]
|
||
|
|
_T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16]
|
||
|
|
_T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16]
|
||
|
|
_T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16]
|
||
|
|
_T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16]
|
||
|
|
_T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16]
|
||
|
|
_T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16]
|
||
|
|
wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 696:7]
|
||
|
|
io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 698:27]
|
||
|
|
node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:42]
|
||
|
|
node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 699:40]
|
||
|
|
i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 699:25]
|
||
|
|
node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:49]
|
||
|
|
node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 700:47]
|
||
|
|
node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:65]
|
||
|
|
node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 700:63]
|
||
|
|
io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 700:32]
|
||
|
|
io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 701:26]
|
||
|
|
node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 703:57]
|
||
|
|
inst rvclkhdr_9 of rvclkhdr_10 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_9.clock <= clock
|
||
|
|
rvclkhdr_9.reset <= reset
|
||
|
|
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_9.io.en <= _T_760 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg i0_result_r_raw : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16]
|
||
|
|
node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 709:42]
|
||
|
|
node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 709:56]
|
||
|
|
node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 709:32]
|
||
|
|
i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 709:26]
|
||
|
|
i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 710:26]
|
||
|
|
node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 714:37]
|
||
|
|
node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 714:51]
|
||
|
|
node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 714:27]
|
||
|
|
i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 714:21]
|
||
|
|
node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 715:54]
|
||
|
|
node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 715:52]
|
||
|
|
node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 715:66]
|
||
|
|
wire _T_770 : UInt<1>[10] @[el2_lib.scala 161:48]
|
||
|
|
_T_770[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_770[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_771 = cat(_T_770[0], _T_770[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_772 = cat(_T_771, _T_770[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_773 = cat(_T_772, _T_770[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_774 = cat(_T_773, _T_770[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_775 = cat(_T_774, _T_770[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_776 = cat(_T_775, _T_770[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_777 = cat(_T_776, _T_770[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_778 = cat(_T_777, _T_770[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58]
|
||
|
|
node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58]
|
||
|
|
node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 715:30]
|
||
|
|
io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 715:24]
|
||
|
|
wire last_br_immed_d : UInt<12>
|
||
|
|
last_br_immed_d <= UInt<1>("h00")
|
||
|
|
node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 717:48]
|
||
|
|
wire _T_784 : UInt<1>[10] @[el2_lib.scala 161:48]
|
||
|
|
_T_784[0] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[1] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[2] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[3] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[4] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[5] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[6] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[7] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[8] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
_T_784[9] <= UInt<1>("h00") @[el2_lib.scala 161:48]
|
||
|
|
node _T_785 = cat(_T_784[0], _T_784[1]) @[Cat.scala 29:58]
|
||
|
|
node _T_786 = cat(_T_785, _T_784[2]) @[Cat.scala 29:58]
|
||
|
|
node _T_787 = cat(_T_786, _T_784[3]) @[Cat.scala 29:58]
|
||
|
|
node _T_788 = cat(_T_787, _T_784[4]) @[Cat.scala 29:58]
|
||
|
|
node _T_789 = cat(_T_788, _T_784[5]) @[Cat.scala 29:58]
|
||
|
|
node _T_790 = cat(_T_789, _T_784[6]) @[Cat.scala 29:58]
|
||
|
|
node _T_791 = cat(_T_790, _T_784[7]) @[Cat.scala 29:58]
|
||
|
|
node _T_792 = cat(_T_791, _T_784[8]) @[Cat.scala 29:58]
|
||
|
|
node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58]
|
||
|
|
node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58]
|
||
|
|
node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58]
|
||
|
|
node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 717:25]
|
||
|
|
last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 717:19]
|
||
|
|
wire last_br_immed_x : UInt<12>
|
||
|
|
last_br_immed_x <= UInt<1>("h00")
|
||
|
|
node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 719:58]
|
||
|
|
inst rvclkhdr_10 of rvclkhdr_11 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_10.clock <= clock
|
||
|
|
rvclkhdr_10.reset <= reset
|
||
|
|
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_10.io.en <= _T_797 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_798 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_798 <= last_br_immed_d @[el2_lib.scala 514:16]
|
||
|
|
last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 719:19]
|
||
|
|
node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 723:40]
|
||
|
|
node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:68]
|
||
|
|
node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 723:55]
|
||
|
|
node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 725:43]
|
||
|
|
node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 725:69]
|
||
|
|
node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 725:57]
|
||
|
|
node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 726:16]
|
||
|
|
node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 726:30]
|
||
|
|
node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 725:86]
|
||
|
|
node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 727:16]
|
||
|
|
node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 727:30]
|
||
|
|
node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 727:57]
|
||
|
|
node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 726:59]
|
||
|
|
node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 731:51]
|
||
|
|
node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 732:26]
|
||
|
|
node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 732:24]
|
||
|
|
node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 732:51]
|
||
|
|
node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 732:39]
|
||
|
|
node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 732:72]
|
||
|
|
node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 731:65]
|
||
|
|
node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 734:53]
|
||
|
|
io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 734:29]
|
||
|
|
node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 735:55]
|
||
|
|
node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:62]
|
||
|
|
node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 737:60]
|
||
|
|
node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:81]
|
||
|
|
node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 737:79]
|
||
|
|
node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 737:39]
|
||
|
|
reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 739:54]
|
||
|
|
_T_821 <= div_active_in @[el2_dec_decode_ctl.scala 739:54]
|
||
|
|
io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 739:21]
|
||
|
|
node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 742:49]
|
||
|
|
node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 742:88]
|
||
|
|
node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 742:69]
|
||
|
|
node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 743:25]
|
||
|
|
node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 743:64]
|
||
|
|
node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 743:45]
|
||
|
|
node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 742:102]
|
||
|
|
i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 742:26]
|
||
|
|
node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 745:59]
|
||
|
|
reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_829 : @[Reg.scala 28:19]
|
||
|
|
_T_830 <= i0r.rd @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 745:19]
|
||
|
|
node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 752:34]
|
||
|
|
node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 752:57]
|
||
|
|
inst rvclkhdr_11 of rvclkhdr_12 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_11.clock <= clock
|
||
|
|
rvclkhdr_11.reset <= reset
|
||
|
|
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_11.io.en <= _T_832 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg div_inst : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
div_inst <= _T_831 @[el2_lib.scala 514:16]
|
||
|
|
node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:49]
|
||
|
|
inst rvclkhdr_12 of rvclkhdr_13 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_12.clock <= clock
|
||
|
|
rvclkhdr_12.reset <= reset
|
||
|
|
rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_12.io.en <= _T_833 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg i0_inst_x : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16]
|
||
|
|
node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:49]
|
||
|
|
inst rvclkhdr_13 of rvclkhdr_14 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_13.clock <= clock
|
||
|
|
rvclkhdr_13.reset <= reset
|
||
|
|
rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_13.io.en <= _T_834 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg i0_inst_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16]
|
||
|
|
node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:50]
|
||
|
|
inst rvclkhdr_14 of rvclkhdr_15 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_14.clock <= clock
|
||
|
|
rvclkhdr_14.reset <= reset
|
||
|
|
rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_14.io.en <= _T_835 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg i0_inst_wb : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16]
|
||
|
|
node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:53]
|
||
|
|
inst rvclkhdr_15 of rvclkhdr_16 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_15.clock <= clock
|
||
|
|
rvclkhdr_15.reset <= reset
|
||
|
|
rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_15.io.en <= _T_836 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_837 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_837 <= i0_inst_wb @[el2_lib.scala 514:16]
|
||
|
|
io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 757:22]
|
||
|
|
node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 758:53]
|
||
|
|
inst rvclkhdr_16 of rvclkhdr_17 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_16.clock <= clock
|
||
|
|
rvclkhdr_16.reset <= reset
|
||
|
|
rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_16.io.en <= _T_838 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg i0_pc_wb : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16]
|
||
|
|
node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 760:49]
|
||
|
|
inst rvclkhdr_17 of rvclkhdr_18 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_17.clock <= clock
|
||
|
|
rvclkhdr_17.reset <= reset
|
||
|
|
rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_17.io.en <= _T_839 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_840 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_840 <= i0_pc_wb @[el2_lib.scala 514:16]
|
||
|
|
io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 760:20]
|
||
|
|
node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 761:56]
|
||
|
|
inst rvclkhdr_18 of rvclkhdr_19 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_18.clock <= clock
|
||
|
|
rvclkhdr_18.reset <= reset
|
||
|
|
rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_18.io.en <= _T_841 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg dec_i0_pc_r : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 514:16]
|
||
|
|
io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 763:27]
|
||
|
|
node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 208:24]
|
||
|
|
node _T_845 = bits(_T_843, 12, 1) @[el2_lib.scala 208:40]
|
||
|
|
node _T_846 = add(_T_844, _T_845) @[el2_lib.scala 208:31]
|
||
|
|
node _T_847 = bits(_T_842, 31, 13) @[el2_lib.scala 209:20]
|
||
|
|
node _T_848 = add(_T_847, UInt<1>("h01")) @[el2_lib.scala 209:27]
|
||
|
|
node _T_849 = tail(_T_848, 1) @[el2_lib.scala 209:27]
|
||
|
|
node _T_850 = bits(_T_842, 31, 13) @[el2_lib.scala 210:20]
|
||
|
|
node _T_851 = sub(_T_850, UInt<1>("h01")) @[el2_lib.scala 210:27]
|
||
|
|
node _T_852 = tail(_T_851, 1) @[el2_lib.scala 210:27]
|
||
|
|
node _T_853 = bits(_T_843, 12, 12) @[el2_lib.scala 211:22]
|
||
|
|
node _T_854 = bits(_T_846, 12, 12) @[el2_lib.scala 212:39]
|
||
|
|
node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_lib.scala 212:28]
|
||
|
|
node _T_856 = xor(_T_853, _T_855) @[el2_lib.scala 212:26]
|
||
|
|
node _T_857 = bits(_T_856, 0, 0) @[el2_lib.scala 212:64]
|
||
|
|
node _T_858 = bits(_T_842, 31, 13) @[el2_lib.scala 212:76]
|
||
|
|
node _T_859 = eq(_T_853, UInt<1>("h00")) @[el2_lib.scala 213:8]
|
||
|
|
node _T_860 = bits(_T_846, 12, 12) @[el2_lib.scala 213:27]
|
||
|
|
node _T_861 = and(_T_859, _T_860) @[el2_lib.scala 213:14]
|
||
|
|
node _T_862 = bits(_T_861, 0, 0) @[el2_lib.scala 213:52]
|
||
|
|
node _T_863 = bits(_T_846, 12, 12) @[el2_lib.scala 214:27]
|
||
|
|
node _T_864 = eq(_T_863, UInt<1>("h00")) @[el2_lib.scala 214:16]
|
||
|
|
node _T_865 = and(_T_853, _T_864) @[el2_lib.scala 214:14]
|
||
|
|
node _T_866 = bits(_T_865, 0, 0) @[el2_lib.scala 214:52]
|
||
|
|
node _T_867 = mux(_T_857, _T_858, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_868 = mux(_T_862, _T_849, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_869 = mux(_T_866, _T_852, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_870 = or(_T_867, _T_868) @[Mux.scala 27:72]
|
||
|
|
node _T_871 = or(_T_870, _T_869) @[Mux.scala 27:72]
|
||
|
|
wire _T_872 : UInt<19> @[Mux.scala 27:72]
|
||
|
|
_T_872 <= _T_871 @[Mux.scala 27:72]
|
||
|
|
node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 214:82]
|
||
|
|
node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58]
|
||
|
|
node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 768:51]
|
||
|
|
io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 768:25]
|
||
|
|
node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 772:48]
|
||
|
|
node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 772:70]
|
||
|
|
node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 772:58]
|
||
|
|
node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 773:48]
|
||
|
|
node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 773:70]
|
||
|
|
node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 773:58]
|
||
|
|
node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 775:48]
|
||
|
|
node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 775:70]
|
||
|
|
node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 775:58]
|
||
|
|
node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 776:48]
|
||
|
|
node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 776:70]
|
||
|
|
node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 776:58]
|
||
|
|
node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 778:44]
|
||
|
|
node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 778:81]
|
||
|
|
wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 778:109]
|
||
|
|
_T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109]
|
||
|
|
_T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109]
|
||
|
|
_T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109]
|
||
|
|
node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 778:61]
|
||
|
|
node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 778:24]
|
||
|
|
i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 778:18]
|
||
|
|
i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 778:18]
|
||
|
|
i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 778:18]
|
||
|
|
node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 779:44]
|
||
|
|
node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 779:83]
|
||
|
|
node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 779:63]
|
||
|
|
node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 779:24]
|
||
|
|
i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 779:18]
|
||
|
|
node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 780:44]
|
||
|
|
node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 780:81]
|
||
|
|
wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 780:109]
|
||
|
|
_T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109]
|
||
|
|
_T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109]
|
||
|
|
_T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109]
|
||
|
|
node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 780:61]
|
||
|
|
node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 780:24]
|
||
|
|
i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 780:18]
|
||
|
|
i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 780:18]
|
||
|
|
i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 780:18]
|
||
|
|
node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 781:44]
|
||
|
|
node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 781:83]
|
||
|
|
node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 781:63]
|
||
|
|
node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 781:24]
|
||
|
|
i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 781:18]
|
||
|
|
i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 791:21]
|
||
|
|
node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 792:43]
|
||
|
|
node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 792:74]
|
||
|
|
node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 792:58]
|
||
|
|
node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 792:78]
|
||
|
|
load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 792:27]
|
||
|
|
node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 793:59]
|
||
|
|
node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 793:43]
|
||
|
|
node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 793:63]
|
||
|
|
store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 793:25]
|
||
|
|
store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 794:25]
|
||
|
|
node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 798:62]
|
||
|
|
node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 798:119]
|
||
|
|
node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 798:89]
|
||
|
|
node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 800:62]
|
||
|
|
node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 800:119]
|
||
|
|
node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 800:89]
|
||
|
|
node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:41]
|
||
|
|
node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:66]
|
||
|
|
node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 803:45]
|
||
|
|
node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:104]
|
||
|
|
node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:108]
|
||
|
|
node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 803:149]
|
||
|
|
node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:175]
|
||
|
|
node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:196]
|
||
|
|
node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 803:153]
|
||
|
|
node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58]
|
||
|
|
node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58]
|
||
|
|
i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 803:18]
|
||
|
|
node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:41]
|
||
|
|
node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:67]
|
||
|
|
node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 805:45]
|
||
|
|
node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:105]
|
||
|
|
node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:109]
|
||
|
|
node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 805:149]
|
||
|
|
node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:175]
|
||
|
|
node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:196]
|
||
|
|
node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 805:153]
|
||
|
|
node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58]
|
||
|
|
node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58]
|
||
|
|
i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 805:18]
|
||
|
|
node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:54]
|
||
|
|
node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 807:71]
|
||
|
|
node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 807:89]
|
||
|
|
node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 807:75]
|
||
|
|
node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:109]
|
||
|
|
node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 807:96]
|
||
|
|
node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 807:113]
|
||
|
|
node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 807:93]
|
||
|
|
node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58]
|
||
|
|
io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 807:34]
|
||
|
|
node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:54]
|
||
|
|
node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:71]
|
||
|
|
node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 808:89]
|
||
|
|
node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 808:75]
|
||
|
|
node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:109]
|
||
|
|
node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 808:96]
|
||
|
|
node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 808:113]
|
||
|
|
node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 808:93]
|
||
|
|
node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58]
|
||
|
|
io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 808:34]
|
||
|
|
node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 811:17]
|
||
|
|
node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 811:21]
|
||
|
|
node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 812:17]
|
||
|
|
node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 812:21]
|
||
|
|
node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:19]
|
||
|
|
node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:6]
|
||
|
|
node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 813:38]
|
||
|
|
node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:25]
|
||
|
|
node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 813:23]
|
||
|
|
node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 813:42]
|
||
|
|
node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 813:78]
|
||
|
|
node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_967 = or(_T_964, _T_965) @[Mux.scala 27:72]
|
||
|
|
node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72]
|
||
|
|
wire _T_969 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_969 <= _T_968 @[Mux.scala 27:72]
|
||
|
|
io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 810:31]
|
||
|
|
node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 816:17]
|
||
|
|
node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 816:21]
|
||
|
|
node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 817:17]
|
||
|
|
node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 817:21]
|
||
|
|
node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 818:19]
|
||
|
|
node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:6]
|
||
|
|
node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 818:38]
|
||
|
|
node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:25]
|
||
|
|
node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 818:23]
|
||
|
|
node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 818:42]
|
||
|
|
node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 818:78]
|
||
|
|
node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_984 = or(_T_981, _T_982) @[Mux.scala 27:72]
|
||
|
|
node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72]
|
||
|
|
wire _T_986 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_986 <= _T_985 @[Mux.scala 27:72]
|
||
|
|
io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 815:31]
|
||
|
|
node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 820:68]
|
||
|
|
node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 820:50]
|
||
|
|
node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:89]
|
||
|
|
node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 820:87]
|
||
|
|
node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:114]
|
||
|
|
node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 820:112]
|
||
|
|
node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 820:131]
|
||
|
|
io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 820:26]
|
||
|
|
node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 822:6]
|
||
|
|
node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 822:27]
|
||
|
|
node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 822:39]
|
||
|
|
node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 822:53]
|
||
|
|
node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 822:70]
|
||
|
|
node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 823:6]
|
||
|
|
node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 823:27]
|
||
|
|
node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 823:39]
|
||
|
|
node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 823:54]
|
||
|
|
node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 823:74]
|
||
|
|
node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 823:84]
|
||
|
|
node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58]
|
||
|
|
node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72]
|
||
|
|
wire _T_1009 : UInt<12> @[Mux.scala 27:72]
|
||
|
|
_T_1009 <= _T_1008 @[Mux.scala 27:72]
|
||
|
|
io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 821:23]
|
||
|
|
|