2020-11-18 18:42:14 +08:00
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module gated_latch
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2020-09-22 13:35:24 +08:00
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(
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2020-12-09 12:34:03 +08:00
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input wire SE, EN, CK,
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2020-09-22 13:35:24 +08:00
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output Q
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);
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2020-12-09 12:34:03 +08:00
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reg en_ff;
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wire enable;
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2020-09-22 13:35:24 +08:00
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assign enable = EN | SE;
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always @(CK, enable) begin
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if(!CK)
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en_ff = enable;
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end
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assign Q = CK & en_ff;
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endmodule
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