2236 lines
116 KiB
Plaintext
2236 lines
116 KiB
Plaintext
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_dec_gpr_ctl :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_6 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_6 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_7 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_7 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_8 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_8 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_9 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_9 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_10 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_10 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_11 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_11 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_12 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_12 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_13 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_13 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_14 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_14 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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|
||
|
|
inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_15 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_15 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_16 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_16 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_17 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_17 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_18 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_18 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_19 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_19 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_20 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_20 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_21 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_21 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_22 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_22 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_23 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_23 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_24 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_24 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_25 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_25 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_26 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_26 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_27 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_27 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_28 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_28 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_29 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_29 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
extmodule gated_latch_30 :
|
||
|
|
output Q : Clock
|
||
|
|
input CK : Clock
|
||
|
|
input EN : UInt<1>
|
||
|
|
input SE : UInt<1>
|
||
|
|
|
||
|
|
defname = gated_latch
|
||
|
|
|
||
|
|
|
||
|
|
module rvclkhdr_30 :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : Reset
|
||
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26]
|
||
|
|
clkhdr.SE is invalid
|
||
|
|
clkhdr.EN is invalid
|
||
|
|
clkhdr.CK is invalid
|
||
|
|
clkhdr.Q is invalid
|
||
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||
|
|
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||
|
|
|
||
|
|
module el2_dec_gpr_ctl :
|
||
|
|
input clock : Clock
|
||
|
|
input reset : AsyncReset
|
||
|
|
output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>}
|
||
|
|
|
||
|
|
wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30]
|
||
|
|
w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
w0v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7]
|
||
|
|
wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 13:30]
|
||
|
|
w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
w1v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7]
|
||
|
|
wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 16:30]
|
||
|
|
w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
w2v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7]
|
||
|
|
wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 19:22]
|
||
|
|
gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
gpr_in[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10]
|
||
|
|
wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 22:22]
|
||
|
|
gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
gpr_out[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11]
|
||
|
|
wire gpr_wr_en : UInt<32>
|
||
|
|
gpr_wr_en <= UInt<1>("h00")
|
||
|
|
w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 26:9]
|
||
|
|
w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 27:9]
|
||
|
|
w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 28:9]
|
||
|
|
gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 29:13]
|
||
|
|
gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 30:12]
|
||
|
|
io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 31:9]
|
||
|
|
io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 32:9]
|
||
|
|
node _T = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_1 = and(io.wen0, _T) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[1] <= _T_1 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_3 = and(io.wen1, _T_2) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[1] <= _T_3 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_5 = and(io.wen2, _T_4) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[1] <= _T_5 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_8 = and(_T_7, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_11 = and(_T_10, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_12 = or(_T_8, _T_11) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_15 = and(_T_14, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_16 = or(_T_12, _T_15) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[1] <= _T_16 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_18 = and(io.wen0, _T_17) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[2] <= _T_18 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_20 = and(io.wen1, _T_19) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[2] <= _T_20 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_22 = and(io.wen2, _T_21) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[2] <= _T_22 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_25 = and(_T_24, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_28 = and(_T_27, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_29 = or(_T_25, _T_28) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_32 = and(_T_31, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_33 = or(_T_29, _T_32) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[2] <= _T_33 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_35 = and(io.wen0, _T_34) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[3] <= _T_35 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_37 = and(io.wen1, _T_36) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[3] <= _T_37 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_39 = and(io.wen2, _T_38) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[3] <= _T_39 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_42 = and(_T_41, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_45 = and(_T_44, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_46 = or(_T_42, _T_45) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_49 = and(_T_48, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_50 = or(_T_46, _T_49) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[3] <= _T_50 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_52 = and(io.wen0, _T_51) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[4] <= _T_52 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_54 = and(io.wen1, _T_53) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[4] <= _T_54 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_56 = and(io.wen2, _T_55) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[4] <= _T_56 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_59 = and(_T_58, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_62 = and(_T_61, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_63 = or(_T_59, _T_62) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_66 = and(_T_65, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_67 = or(_T_63, _T_66) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[4] <= _T_67 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_69 = and(io.wen0, _T_68) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[5] <= _T_69 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_71 = and(io.wen1, _T_70) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[5] <= _T_71 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_73 = and(io.wen2, _T_72) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[5] <= _T_73 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_76 = and(_T_75, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_79 = and(_T_78, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_80 = or(_T_76, _T_79) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_83 = and(_T_82, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_84 = or(_T_80, _T_83) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[5] <= _T_84 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_86 = and(io.wen0, _T_85) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[6] <= _T_86 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_88 = and(io.wen1, _T_87) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[6] <= _T_88 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_90 = and(io.wen2, _T_89) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[6] <= _T_90 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_93 = and(_T_92, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_96 = and(_T_95, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_97 = or(_T_93, _T_96) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_100 = and(_T_99, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_101 = or(_T_97, _T_100) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[6] <= _T_101 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_103 = and(io.wen0, _T_102) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[7] <= _T_103 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_105 = and(io.wen1, _T_104) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[7] <= _T_105 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_107 = and(io.wen2, _T_106) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[7] <= _T_107 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_110 = and(_T_109, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_113 = and(_T_112, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_114 = or(_T_110, _T_113) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_117 = and(_T_116, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_118 = or(_T_114, _T_117) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[7] <= _T_118 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_120 = and(io.wen0, _T_119) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[8] <= _T_120 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_122 = and(io.wen1, _T_121) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[8] <= _T_122 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_124 = and(io.wen2, _T_123) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[8] <= _T_124 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_127 = and(_T_126, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_130 = and(_T_129, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_131 = or(_T_127, _T_130) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_134 = and(_T_133, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_135 = or(_T_131, _T_134) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[8] <= _T_135 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_137 = and(io.wen0, _T_136) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[9] <= _T_137 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_139 = and(io.wen1, _T_138) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[9] <= _T_139 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_141 = and(io.wen2, _T_140) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[9] <= _T_141 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_144 = and(_T_143, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_147 = and(_T_146, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_148 = or(_T_144, _T_147) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_151 = and(_T_150, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_152 = or(_T_148, _T_151) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[9] <= _T_152 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_154 = and(io.wen0, _T_153) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[10] <= _T_154 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_156 = and(io.wen1, _T_155) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[10] <= _T_156 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_158 = and(io.wen2, _T_157) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[10] <= _T_158 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_161 = and(_T_160, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_164 = and(_T_163, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_165 = or(_T_161, _T_164) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_168 = and(_T_167, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_169 = or(_T_165, _T_168) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[10] <= _T_169 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_171 = and(io.wen0, _T_170) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[11] <= _T_171 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_173 = and(io.wen1, _T_172) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[11] <= _T_173 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_175 = and(io.wen2, _T_174) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[11] <= _T_175 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_178 = and(_T_177, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_181 = and(_T_180, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_182 = or(_T_178, _T_181) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_185 = and(_T_184, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_186 = or(_T_182, _T_185) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[11] <= _T_186 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_188 = and(io.wen0, _T_187) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[12] <= _T_188 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_190 = and(io.wen1, _T_189) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[12] <= _T_190 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_192 = and(io.wen2, _T_191) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[12] <= _T_192 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_195 = and(_T_194, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_198 = and(_T_197, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_199 = or(_T_195, _T_198) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_202 = and(_T_201, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_203 = or(_T_199, _T_202) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[12] <= _T_203 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_205 = and(io.wen0, _T_204) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[13] <= _T_205 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_207 = and(io.wen1, _T_206) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[13] <= _T_207 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_209 = and(io.wen2, _T_208) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[13] <= _T_209 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_212 = and(_T_211, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_215 = and(_T_214, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_216 = or(_T_212, _T_215) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_219 = and(_T_218, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_220 = or(_T_216, _T_219) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[13] <= _T_220 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_222 = and(io.wen0, _T_221) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[14] <= _T_222 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_224 = and(io.wen1, _T_223) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[14] <= _T_224 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_226 = and(io.wen2, _T_225) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[14] <= _T_226 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_229 = and(_T_228, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_232 = and(_T_231, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_233 = or(_T_229, _T_232) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_236 = and(_T_235, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_237 = or(_T_233, _T_236) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[14] <= _T_237 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_239 = and(io.wen0, _T_238) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[15] <= _T_239 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_241 = and(io.wen1, _T_240) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[15] <= _T_241 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_243 = and(io.wen2, _T_242) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[15] <= _T_243 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_246 = and(_T_245, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_249 = and(_T_248, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_250 = or(_T_246, _T_249) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_253 = and(_T_252, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_254 = or(_T_250, _T_253) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[15] <= _T_254 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_256 = and(io.wen0, _T_255) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[16] <= _T_256 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_258 = and(io.wen1, _T_257) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[16] <= _T_258 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_260 = and(io.wen2, _T_259) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[16] <= _T_260 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_263 = and(_T_262, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_266 = and(_T_265, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_267 = or(_T_263, _T_266) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_270 = and(_T_269, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_271 = or(_T_267, _T_270) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[16] <= _T_271 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_273 = and(io.wen0, _T_272) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[17] <= _T_273 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_275 = and(io.wen1, _T_274) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[17] <= _T_275 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_277 = and(io.wen2, _T_276) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[17] <= _T_277 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_280 = and(_T_279, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_283 = and(_T_282, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_284 = or(_T_280, _T_283) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_287 = and(_T_286, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_288 = or(_T_284, _T_287) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[17] <= _T_288 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_290 = and(io.wen0, _T_289) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[18] <= _T_290 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_292 = and(io.wen1, _T_291) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[18] <= _T_292 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_294 = and(io.wen2, _T_293) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[18] <= _T_294 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_297 = and(_T_296, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_300 = and(_T_299, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_301 = or(_T_297, _T_300) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_304 = and(_T_303, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_305 = or(_T_301, _T_304) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[18] <= _T_305 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_307 = and(io.wen0, _T_306) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[19] <= _T_307 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_309 = and(io.wen1, _T_308) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[19] <= _T_309 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_311 = and(io.wen2, _T_310) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[19] <= _T_311 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_314 = and(_T_313, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_317 = and(_T_316, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_318 = or(_T_314, _T_317) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_321 = and(_T_320, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_322 = or(_T_318, _T_321) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[19] <= _T_322 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_324 = and(io.wen0, _T_323) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[20] <= _T_324 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_326 = and(io.wen1, _T_325) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[20] <= _T_326 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_328 = and(io.wen2, _T_327) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[20] <= _T_328 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_331 = and(_T_330, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_334 = and(_T_333, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_335 = or(_T_331, _T_334) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_338 = and(_T_337, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_339 = or(_T_335, _T_338) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[20] <= _T_339 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_341 = and(io.wen0, _T_340) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[21] <= _T_341 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_343 = and(io.wen1, _T_342) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[21] <= _T_343 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_345 = and(io.wen2, _T_344) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[21] <= _T_345 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_348 = and(_T_347, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_351 = and(_T_350, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_352 = or(_T_348, _T_351) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_355 = and(_T_354, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_356 = or(_T_352, _T_355) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[21] <= _T_356 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_358 = and(io.wen0, _T_357) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[22] <= _T_358 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_360 = and(io.wen1, _T_359) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[22] <= _T_360 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_362 = and(io.wen2, _T_361) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[22] <= _T_362 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_365 = and(_T_364, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_368 = and(_T_367, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_369 = or(_T_365, _T_368) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_372 = and(_T_371, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_373 = or(_T_369, _T_372) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[22] <= _T_373 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_375 = and(io.wen0, _T_374) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[23] <= _T_375 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_377 = and(io.wen1, _T_376) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[23] <= _T_377 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_379 = and(io.wen2, _T_378) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[23] <= _T_379 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_382 = and(_T_381, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_385 = and(_T_384, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_386 = or(_T_382, _T_385) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_389 = and(_T_388, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_390 = or(_T_386, _T_389) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[23] <= _T_390 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_392 = and(io.wen0, _T_391) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[24] <= _T_392 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_394 = and(io.wen1, _T_393) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[24] <= _T_394 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_396 = and(io.wen2, _T_395) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[24] <= _T_396 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_399 = and(_T_398, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_402 = and(_T_401, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_403 = or(_T_399, _T_402) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_406 = and(_T_405, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_407 = or(_T_403, _T_406) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[24] <= _T_407 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_409 = and(io.wen0, _T_408) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[25] <= _T_409 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_411 = and(io.wen1, _T_410) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[25] <= _T_411 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_413 = and(io.wen2, _T_412) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[25] <= _T_413 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_416 = and(_T_415, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_419 = and(_T_418, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_420 = or(_T_416, _T_419) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_423 = and(_T_422, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_424 = or(_T_420, _T_423) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[25] <= _T_424 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_426 = and(io.wen0, _T_425) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[26] <= _T_426 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_428 = and(io.wen1, _T_427) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[26] <= _T_428 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_430 = and(io.wen2, _T_429) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[26] <= _T_430 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_433 = and(_T_432, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_436 = and(_T_435, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_437 = or(_T_433, _T_436) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_440 = and(_T_439, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_441 = or(_T_437, _T_440) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[26] <= _T_441 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_443 = and(io.wen0, _T_442) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[27] <= _T_443 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_445 = and(io.wen1, _T_444) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[27] <= _T_445 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_447 = and(io.wen2, _T_446) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[27] <= _T_447 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_450 = and(_T_449, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_453 = and(_T_452, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_454 = or(_T_450, _T_453) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_457 = and(_T_456, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_458 = or(_T_454, _T_457) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[27] <= _T_458 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_460 = and(io.wen0, _T_459) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[28] <= _T_460 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_462 = and(io.wen1, _T_461) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[28] <= _T_462 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_464 = and(io.wen2, _T_463) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[28] <= _T_464 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_467 = and(_T_466, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_470 = and(_T_469, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_471 = or(_T_467, _T_470) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_474 = and(_T_473, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_475 = or(_T_471, _T_474) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[28] <= _T_475 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_477 = and(io.wen0, _T_476) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[29] <= _T_477 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_479 = and(io.wen1, _T_478) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[29] <= _T_479 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_481 = and(io.wen2, _T_480) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[29] <= _T_481 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_484 = and(_T_483, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_487 = and(_T_486, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_488 = or(_T_484, _T_487) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_491 = and(_T_490, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_492 = or(_T_488, _T_491) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[29] <= _T_492 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_494 = and(io.wen0, _T_493) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[30] <= _T_494 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_496 = and(io.wen1, _T_495) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[30] <= _T_496 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_498 = and(io.wen2, _T_497) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[30] <= _T_498 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_501 = and(_T_500, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_504 = and(_T_503, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_505 = or(_T_501, _T_504) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_508 = and(_T_507, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_509 = or(_T_505, _T_508) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[30] <= _T_509 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 35:40]
|
||
|
|
node _T_511 = and(io.wen0, _T_510) @[el2_dec_gpr_ctl.scala 35:28]
|
||
|
|
w0v[31] <= _T_511 @[el2_dec_gpr_ctl.scala 35:16]
|
||
|
|
node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:40]
|
||
|
|
node _T_513 = and(io.wen1, _T_512) @[el2_dec_gpr_ctl.scala 36:28]
|
||
|
|
w1v[31] <= _T_513 @[el2_dec_gpr_ctl.scala 36:16]
|
||
|
|
node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:40]
|
||
|
|
node _T_515 = and(io.wen2, _T_514) @[el2_dec_gpr_ctl.scala 37:28]
|
||
|
|
w2v[31] <= _T_515 @[el2_dec_gpr_ctl.scala 37:16]
|
||
|
|
node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_518 = and(_T_517, io.wd0) @[el2_dec_gpr_ctl.scala 38:37]
|
||
|
|
node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_521 = and(_T_520, io.wd1) @[el2_dec_gpr_ctl.scala 38:66]
|
||
|
|
node _T_522 = or(_T_518, _T_521) @[el2_dec_gpr_ctl.scala 38:47]
|
||
|
|
node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_525 = and(_T_524, io.wd2) @[el2_dec_gpr_ctl.scala 38:95]
|
||
|
|
node _T_526 = or(_T_522, _T_525) @[el2_dec_gpr_ctl.scala 38:76]
|
||
|
|
gpr_in[31] <= _T_526 @[el2_dec_gpr_ctl.scala 38:16]
|
||
|
|
node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58]
|
||
|
|
node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58]
|
||
|
|
node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58]
|
||
|
|
node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58]
|
||
|
|
node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58]
|
||
|
|
node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58]
|
||
|
|
node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58]
|
||
|
|
node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58]
|
||
|
|
node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58]
|
||
|
|
node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58]
|
||
|
|
node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58]
|
||
|
|
node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58]
|
||
|
|
node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58]
|
||
|
|
node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58]
|
||
|
|
node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58]
|
||
|
|
node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58]
|
||
|
|
node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58]
|
||
|
|
node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58]
|
||
|
|
node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58]
|
||
|
|
node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58]
|
||
|
|
node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58]
|
||
|
|
node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58]
|
||
|
|
node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58]
|
||
|
|
node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58]
|
||
|
|
node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58]
|
||
|
|
node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58]
|
||
|
|
node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58]
|
||
|
|
node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58]
|
||
|
|
node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58]
|
||
|
|
node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58]
|
||
|
|
node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58]
|
||
|
|
node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58]
|
||
|
|
node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58]
|
||
|
|
node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58]
|
||
|
|
node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58]
|
||
|
|
node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58]
|
||
|
|
node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58]
|
||
|
|
node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58]
|
||
|
|
node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58]
|
||
|
|
node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58]
|
||
|
|
node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58]
|
||
|
|
node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58]
|
||
|
|
node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58]
|
||
|
|
node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58]
|
||
|
|
node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58]
|
||
|
|
node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58]
|
||
|
|
node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58]
|
||
|
|
node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58]
|
||
|
|
node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58]
|
||
|
|
node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58]
|
||
|
|
node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58]
|
||
|
|
node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58]
|
||
|
|
node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58]
|
||
|
|
node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58]
|
||
|
|
node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58]
|
||
|
|
node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58]
|
||
|
|
node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58]
|
||
|
|
node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58]
|
||
|
|
node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58]
|
||
|
|
node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58]
|
||
|
|
node _T_589 = or(_T_557, _T_588) @[el2_dec_gpr_ctl.scala 40:51]
|
||
|
|
node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58]
|
||
|
|
node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58]
|
||
|
|
node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58]
|
||
|
|
node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58]
|
||
|
|
node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58]
|
||
|
|
node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58]
|
||
|
|
node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58]
|
||
|
|
node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58]
|
||
|
|
node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58]
|
||
|
|
node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58]
|
||
|
|
node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58]
|
||
|
|
node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58]
|
||
|
|
node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58]
|
||
|
|
node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58]
|
||
|
|
node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58]
|
||
|
|
node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58]
|
||
|
|
node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58]
|
||
|
|
node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58]
|
||
|
|
node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58]
|
||
|
|
node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58]
|
||
|
|
node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58]
|
||
|
|
node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58]
|
||
|
|
node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58]
|
||
|
|
node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58]
|
||
|
|
node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58]
|
||
|
|
node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58]
|
||
|
|
node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58]
|
||
|
|
node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58]
|
||
|
|
node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58]
|
||
|
|
node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58]
|
||
|
|
node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58]
|
||
|
|
node _T_621 = or(_T_589, _T_620) @[el2_dec_gpr_ctl.scala 40:89]
|
||
|
|
gpr_wr_en <= _T_621 @[el2_dec_gpr_ctl.scala 40:12]
|
||
|
|
node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr.io.en <= _T_622 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_623 <= gpr_in[1] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_1.io.en <= _T_624 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_625 <= gpr_in[2] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= reset
|
||
|
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_2.io.en <= _T_626 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_627 <= gpr_in[3] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= reset
|
||
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_3.io.en <= _T_628 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_629 <= gpr_in[4] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_4.clock <= clock
|
||
|
|
rvclkhdr_4.reset <= reset
|
||
|
|
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_4.io.en <= _T_630 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_631 <= gpr_in[5] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_5.clock <= clock
|
||
|
|
rvclkhdr_5.reset <= reset
|
||
|
|
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_5.io.en <= _T_632 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_633 <= gpr_in[6] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_6.clock <= clock
|
||
|
|
rvclkhdr_6.reset <= reset
|
||
|
|
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_6.io.en <= _T_634 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_635 <= gpr_in[7] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_7.clock <= clock
|
||
|
|
rvclkhdr_7.reset <= reset
|
||
|
|
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_7.io.en <= _T_636 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_637 <= gpr_in[8] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_8.clock <= clock
|
||
|
|
rvclkhdr_8.reset <= reset
|
||
|
|
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_8.io.en <= _T_638 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_639 <= gpr_in[9] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_9.clock <= clock
|
||
|
|
rvclkhdr_9.reset <= reset
|
||
|
|
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_9.io.en <= _T_640 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_641 <= gpr_in[10] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_10.clock <= clock
|
||
|
|
rvclkhdr_10.reset <= reset
|
||
|
|
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_10.io.en <= _T_642 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_643 <= gpr_in[11] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_11.clock <= clock
|
||
|
|
rvclkhdr_11.reset <= reset
|
||
|
|
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_11.io.en <= _T_644 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_645 <= gpr_in[12] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_12.clock <= clock
|
||
|
|
rvclkhdr_12.reset <= reset
|
||
|
|
rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_12.io.en <= _T_646 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_647 <= gpr_in[13] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_13.clock <= clock
|
||
|
|
rvclkhdr_13.reset <= reset
|
||
|
|
rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_13.io.en <= _T_648 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_649 <= gpr_in[14] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_14.clock <= clock
|
||
|
|
rvclkhdr_14.reset <= reset
|
||
|
|
rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_14.io.en <= _T_650 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_651 <= gpr_in[15] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_15.clock <= clock
|
||
|
|
rvclkhdr_15.reset <= reset
|
||
|
|
rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_15.io.en <= _T_652 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_653 <= gpr_in[16] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_16.clock <= clock
|
||
|
|
rvclkhdr_16.reset <= reset
|
||
|
|
rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_16.io.en <= _T_654 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_655 <= gpr_in[17] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_17.clock <= clock
|
||
|
|
rvclkhdr_17.reset <= reset
|
||
|
|
rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_17.io.en <= _T_656 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_657 <= gpr_in[18] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_18.clock <= clock
|
||
|
|
rvclkhdr_18.reset <= reset
|
||
|
|
rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_18.io.en <= _T_658 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_659 <= gpr_in[19] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_19.clock <= clock
|
||
|
|
rvclkhdr_19.reset <= reset
|
||
|
|
rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_19.io.en <= _T_660 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_661 <= gpr_in[20] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_20.clock <= clock
|
||
|
|
rvclkhdr_20.reset <= reset
|
||
|
|
rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_20.io.en <= _T_662 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_663 <= gpr_in[21] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_21.clock <= clock
|
||
|
|
rvclkhdr_21.reset <= reset
|
||
|
|
rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_21.io.en <= _T_664 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_665 <= gpr_in[22] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_22.clock <= clock
|
||
|
|
rvclkhdr_22.reset <= reset
|
||
|
|
rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_22.io.en <= _T_666 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_667 <= gpr_in[23] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_23.clock <= clock
|
||
|
|
rvclkhdr_23.reset <= reset
|
||
|
|
rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_23.io.en <= _T_668 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_669 <= gpr_in[24] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_24.clock <= clock
|
||
|
|
rvclkhdr_24.reset <= reset
|
||
|
|
rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_24.io.en <= _T_670 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_671 <= gpr_in[25] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_25.clock <= clock
|
||
|
|
rvclkhdr_25.reset <= reset
|
||
|
|
rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_25.io.en <= _T_672 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_673 <= gpr_in[26] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_26 of rvclkhdr_26 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_26.clock <= clock
|
||
|
|
rvclkhdr_26.reset <= reset
|
||
|
|
rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_26.io.en <= _T_674 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_675 <= gpr_in[27] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_27 of rvclkhdr_27 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_27.clock <= clock
|
||
|
|
rvclkhdr_27.reset <= reset
|
||
|
|
rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_27.io.en <= _T_676 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_677 <= gpr_in[28] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_28 of rvclkhdr_28 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_28.clock <= clock
|
||
|
|
rvclkhdr_28.reset <= reset
|
||
|
|
rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_28.io.en <= _T_678 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_679 <= gpr_in[29] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_29 of rvclkhdr_29 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_29.clock <= clock
|
||
|
|
rvclkhdr_29.reset <= reset
|
||
|
|
rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_29.io.en <= _T_680 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_681 <= gpr_in[30] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 44:43]
|
||
|
|
inst rvclkhdr_30 of rvclkhdr_30 @[el2_lib.scala 508:23]
|
||
|
|
rvclkhdr_30.clock <= clock
|
||
|
|
rvclkhdr_30.reset <= reset
|
||
|
|
rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18]
|
||
|
|
rvclkhdr_30.io.en <= _T_682 @[el2_lib.scala 511:17]
|
||
|
|
rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||
|
|
reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||
|
|
_T_683 <= gpr_in[31] @[el2_lib.scala 514:16]
|
||
|
|
gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 44:15]
|
||
|
|
node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 47:49]
|
||
|
|
node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 47:57]
|
||
|
|
node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72]
|
||
|
|
node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72]
|
||
|
|
node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72]
|
||
|
|
node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72]
|
||
|
|
node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72]
|
||
|
|
node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72]
|
||
|
|
node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72]
|
||
|
|
node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72]
|
||
|
|
node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72]
|
||
|
|
node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72]
|
||
|
|
node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72]
|
||
|
|
node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72]
|
||
|
|
node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72]
|
||
|
|
node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72]
|
||
|
|
node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72]
|
||
|
|
node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72]
|
||
|
|
node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72]
|
||
|
|
node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72]
|
||
|
|
node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72]
|
||
|
|
node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72]
|
||
|
|
node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72]
|
||
|
|
node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72]
|
||
|
|
node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72]
|
||
|
|
node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72]
|
||
|
|
node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72]
|
||
|
|
node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72]
|
||
|
|
node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72]
|
||
|
|
node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72]
|
||
|
|
node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72]
|
||
|
|
node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72]
|
||
|
|
wire _T_807 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_807 <= _T_806 @[Mux.scala 27:72]
|
||
|
|
io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 47:9]
|
||
|
|
node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 48:49]
|
||
|
|
node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 48:57]
|
||
|
|
node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
|
||
|
|
node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72]
|
||
|
|
node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72]
|
||
|
|
node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72]
|
||
|
|
node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72]
|
||
|
|
node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72]
|
||
|
|
node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72]
|
||
|
|
node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72]
|
||
|
|
node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72]
|
||
|
|
node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72]
|
||
|
|
node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72]
|
||
|
|
node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72]
|
||
|
|
node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72]
|
||
|
|
node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72]
|
||
|
|
node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72]
|
||
|
|
node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72]
|
||
|
|
node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72]
|
||
|
|
node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72]
|
||
|
|
node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72]
|
||
|
|
node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72]
|
||
|
|
node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72]
|
||
|
|
node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72]
|
||
|
|
node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72]
|
||
|
|
node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72]
|
||
|
|
node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72]
|
||
|
|
node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72]
|
||
|
|
node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72]
|
||
|
|
node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72]
|
||
|
|
node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72]
|
||
|
|
node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72]
|
||
|
|
node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72]
|
||
|
|
wire _T_931 : UInt<32> @[Mux.scala 27:72]
|
||
|
|
_T_931 <= _T_930 @[Mux.scala 27:72]
|
||
|
|
io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 48:9]
|
||
|
|
|