21 lines
562 B
Plaintext
21 lines
562 B
Plaintext
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit caller :
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module rvdff :
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input clock : Clock
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input reset : Reset
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output io : {flip in : UInt<32>, out : UInt}
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io.out <= io.in @[GCD.scala 12:10]
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module caller :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip in : UInt<32>, out : UInt}
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inst u0 of rvdff @[GCD.scala 21:18]
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u0.clock <= clock
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u0.reset <= reset
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io.out <= u0.io.out @[GCD.scala 22:6]
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u0.io.in <= io.in @[GCD.scala 22:6]
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