19 lines
770 B
Plaintext
19 lines
770 B
Plaintext
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_bp_ctl :
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module el2_ifu_bp_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip in : UInt<32>, out : UInt}
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node _T = bits(io.in, 14, 10) @[el2_lib.scala 18:33]
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node _T_1 = bits(io.in, 19, 15) @[el2_lib.scala 18:33]
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node _T_2 = bits(io.in, 24, 20) @[el2_lib.scala 18:33]
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wire _T_3 : UInt<5>[3] @[el2_lib.scala 18:25]
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_T_3[0] <= _T @[el2_lib.scala 18:25]
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_T_3[1] <= _T_1 @[el2_lib.scala 18:25]
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_T_3[2] <= _T_2 @[el2_lib.scala 18:25]
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node _T_4 = xor(_T_3[0], _T_3[1]) @[el2_lib.scala 18:113]
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node _T_5 = xor(_T_4, _T_3[2]) @[el2_lib.scala 18:113]
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io.out <= _T_5 @[el2_ifu_bp_ctl.scala 12:10]
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