396 lines
14 KiB
Systemverilog
396 lines
14 KiB
Systemverilog
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typedef struct packed {
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logic trace_rv_i_valid_ip;
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logic [31:0] trace_rv_i_insn_ip;
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logic [31:0] trace_rv_i_address_ip;
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logic trace_rv_i_exception_ip;
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logic [4:0] trace_rv_i_ecause_ip;
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logic trace_rv_i_interrupt_ip;
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logic [31:0] trace_rv_i_tval_ip;
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} trace_pkt_t;
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typedef enum logic [3:0] {
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NULL = 4'b0000,
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MUL = 4'b0001,
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LOAD = 4'b0010,
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STORE = 4'b0011,
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ALU = 4'b0100,
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CSRREAD = 4'b0101,
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CSRWRITE = 4'b0110,
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CSRRW = 4'b0111,
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EBREAK = 4'b1000,
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ECALL = 4'b1001,
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FENCE = 4'b1010,
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FENCEI = 4'b1011,
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MRET = 4'b1100,
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CONDBR = 4'b1101,
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JAL = 4'b1110,
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BITMANIPU = 4'b1111
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} inst_pkt_t;
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typedef struct packed {
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logic valid;
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logic wb;
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logic [2:0] tag;
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logic [4:0] rd;
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} load_cam_pkt_t;
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typedef struct packed {
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logic pc0_call;
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logic pc0_ret;
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logic pc0_pc4;
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} rets_pkt_t;
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typedef struct packed {
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logic valid;
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logic [11:0] toffset;
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logic [1:0] hist;
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logic br_error;
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logic br_start_error;
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logic bank;
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logic [31:1] prett; // predicted ret target
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logic way;
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logic ret;
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} br_pkt_t;
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typedef struct packed {
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logic valid;
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logic [1:0] hist;
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logic br_error;
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logic br_start_error;
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logic way;
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logic middle;
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} br_tlu_pkt_t;
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typedef struct packed {
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logic misp;
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logic ataken;
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logic boffset;
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logic pc4;
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logic [1:0] hist;
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logic [11:0] toffset;
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logic valid;
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logic br_error;
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logic br_start_error;
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logic pcall;
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logic pja;
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logic way;
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logic pret;
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// for power use the pret bit to clock the prett field
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logic [31:1] prett;
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} predict_pkt_t;
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typedef struct packed {
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// unlikely to change
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logic icaf;
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logic icaf_second;
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logic [1:0] icaf_type;
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logic fence_i;
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logic [3:0] i0trigger;
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logic pmu_i0_br_unpred; // pmu
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logic pmu_divide;
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// likely to change
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logic legal;
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logic pmu_lsu_misaligned;
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inst_pkt_t pmu_i0_itype; // pmu - instruction type
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} trap_pkt_t;
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typedef struct packed {
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// unlikely to change
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logic i0div;
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logic csrwen;
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logic csrwonly;
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logic [11:0] csrwaddr;
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// likely to change
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logic [4:0] i0rd;
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logic i0load;
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logic i0store;
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logic i0v;
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logic i0valid;
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} dest_pkt_t;
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typedef struct packed {
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logic mul;
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logic load;
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logic alu;
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} class_pkt_t;
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typedef struct packed {
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logic [4:0] rs1;
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logic [4:0] rs2;
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logic [4:0] rd;
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} reg_pkt_t;
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typedef struct packed {
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logic clz;
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logic ctz;
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logic pcnt;
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logic sext_b;
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logic sext_h;
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logic slo;
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logic sro;
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logic min;
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logic max;
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logic pack;
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logic packu;
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logic packh;
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logic rol;
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logic ror;
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logic grev;
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logic gorc;
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logic zbb;
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logic sbset;
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logic sbclr;
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logic sbinv;
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logic sbext;
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logic sh1add;
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logic sh2add;
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logic sh3add;
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logic zba;
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logic land;
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logic lor;
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logic lxor;
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logic sll;
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logic srl;
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logic sra;
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logic beq;
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logic bne;
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logic blt;
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logic bge;
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logic add;
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logic sub;
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logic slt;
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logic unsign;
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logic jal;
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logic predict_t;
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logic predict_nt;
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logic csr_write;
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logic csr_imm;
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} alu_pkt_t;
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typedef struct packed {
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logic fast_int;
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/* verilator lint_off SYMRSVDWORD */
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logic stack;
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/* verilator lint_on SYMRSVDWORD */
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logic by;
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logic half;
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logic word;
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logic dword; // for dma
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logic load;
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logic store;
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logic unsign;
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logic dma; // dma pkt
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logic store_data_bypass_d;
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logic load_ldst_bypass_d;
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logic store_data_bypass_m;
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logic valid;
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} lsu_pkt_t;
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typedef struct packed {
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logic inst_type; //0: Load, 1: Store
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//logic dma_valid;
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logic exc_type; //0: MisAligned, 1: Access Fault
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logic [3:0] mscause;
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logic [31:0] addr;
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logic single_ecc_error;
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logic exc_valid;
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} lsu_error_pkt_t;
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typedef struct packed {
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logic clz;
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logic ctz;
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logic pcnt;
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logic sext_b;
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logic sext_h;
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logic slo;
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logic sro;
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logic min;
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logic max;
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logic pack;
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logic packu;
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logic packh;
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logic rol;
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logic ror;
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logic grev;
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logic gorc;
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logic zbb;
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logic sbset;
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logic sbclr;
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logic sbinv;
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logic sbext;
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logic zbs;
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logic bext;
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logic bdep;
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logic zbe;
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logic clmul;
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logic clmulh;
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logic clmulr;
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logic zbc;
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logic shfl;
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logic unshfl;
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logic zbp;
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logic crc32_b;
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logic crc32_h;
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logic crc32_w;
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logic crc32c_b;
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logic crc32c_h;
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logic crc32c_w;
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logic zbr;
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logic bfp;
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logic zbf;
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logic sh1add;
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logic sh2add;
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logic sh3add;
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logic zba;
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logic alu;
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logic rs1;
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logic rs2;
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logic imm12;
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logic rd;
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logic shimm5;
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logic imm20;
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logic pc;
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logic load;
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logic store;
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logic lsu;
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logic add;
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logic sub;
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logic land;
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logic lor;
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logic lxor;
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logic sll;
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logic sra;
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logic srl;
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logic slt;
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logic unsign;
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logic condbr;
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logic beq;
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logic bne;
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logic bge;
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logic blt;
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logic jal;
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logic by;
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logic half;
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logic word;
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logic csr_read;
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logic csr_clr;
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logic csr_set;
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logic csr_write;
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logic csr_imm;
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logic presync;
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logic postsync;
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logic ebreak;
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logic ecall;
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logic mret;
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logic mul;
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logic rs1_sign;
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logic rs2_sign;
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logic low;
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logic div;
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logic rem;
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logic fence;
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logic fence_i;
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logic pm_alu;
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logic legal;
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} dec_pkt_t;
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typedef struct packed {
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logic valid;
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logic rs1_sign;
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logic rs2_sign;
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logic low;
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logic bext;
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logic bdep;
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logic clmul;
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logic clmulh;
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logic clmulr;
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logic grev;
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logic gorc;
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logic shfl;
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logic unshfl;
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logic crc32_b;
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logic crc32_h;
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logic crc32_w;
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logic crc32c_b;
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logic crc32c_h;
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logic crc32c_w;
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logic bfp;
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} mul_pkt_t;
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typedef struct packed {
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logic valid;
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logic unsign;
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logic rem;
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} div_pkt_t;
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typedef struct packed {
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logic TEST1;
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logic RME;
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logic [3:0] RM;
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logic LS;
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logic DS;
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logic SD;
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logic TEST_RNM;
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logic BC1;
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logic BC2;
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} iccm_ext_in_pkt_t;
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typedef struct packed {
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logic TEST1;
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logic RME;
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logic [3:0] RM;
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logic LS;
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logic DS;
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logic SD;
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logic TEST_RNM;
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logic BC1;
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logic BC2;
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} dccm_ext_in_pkt_t;
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typedef struct packed {
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logic TEST1;
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logic RME;
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logic [3:0] RM;
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logic LS;
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logic DS;
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logic SD;
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logic TEST_RNM;
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logic BC1;
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logic BC2;
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} ic_data_ext_in_pkt_t;
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typedef struct packed {
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logic TEST1;
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logic RME;
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logic [3:0] RM;
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logic LS;
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logic DS;
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logic SD;
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logic TEST_RNM;
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logic BC1;
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logic BC2;
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} ic_tag_ext_in_pkt_t;
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typedef struct packed {
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logic select;
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logic match;
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logic store;
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logic load;
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logic execute;
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logic m;
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logic [31:0] tdata2;
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} trigger_pkt_t;
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typedef struct packed {
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logic [70:0] icache_wrdata; // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}
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logic [16:0] icache_dicawics; // Arraysel:24, Waysel:21:20, Index:16:3
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logic icache_rd_valid;
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logic icache_wr_valid;
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} cache_debug_pkt_t;
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